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Description:- Verilog FSM level 2

Developer :- Shah Henisha
Date:- 23/02/2025
email :- [email protected]
Version :- 1.0
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**************************************************************************************************
Question:1
**************************************************************************************************
a) Develop Verilog code for the FSM given that is below and also
make testbench to verify it: Where “w” is input signal and “z”
is output signal and A,B,C are states
******************************************************************************************
Code:
******************************************************************************************
module fsm_L2_q1(
input clk, reset,
input w,
output reg z
);
reg [1:0] state, next_state;
parameter A = 2'b00, B = 2'b01, C = 2'b10;
// State transition
always @(posedge clk or posedge reset) begin
if (reset)
state <= A;
else
state <= next_state;
end
// Next state logic and output logic
always @(*) begin
case (state)
A: begin
z = 0;
if (w) next_state = B;
else next_state = A;
end
B: begin
z = 0;
if (w) next_state = C;
else next_state = A;

1
 end
C: begin
z = 1;
if (w) next_state = C;
else next_state = A;
end
default: begin
z = 0;
next_state = A;
end
endcase
end
endmodule

Testbench:
module fsm_L2_q1_tb;
reg clk, reset, w;
wire z
fsm_L2_q1 uut (.clk(clk), .reset(reset), .w(w), .z(z));
// Clock generation
always #5 clk = ~clk;
initial begin
clk = 0; reset = 1; w = 0;
#10 reset = 0;
#10 w = 1; // Move to B
#10 w = 1; // Move to C
#10 w = 0; // Move back to A
#10 w = 0; // Stay in A
#10 w = 1; // Move to B
#10 w = 0; // Move back to A
#10 w = 1; // Move to B
#10 w = 1; // Move to C
#10 w = 1; // Stay in C
#10 w = 0; // Move back to A
#20 $stop;
end
initial begin
$dumpfile("fsm_L2_q1_tb.vcd");
$dumpvars(0, fsm_L2_q1_tb);
end
endmodule

*****************************************************************************************

2
 Output:
******************************************************************************************
Time = 0 | clk = 0 | reset = 1 | w = 0 | z = 0
Time = 5 | clk = 1 | reset = 1 | w = 0 | z = 0
Time = 10 | clk = 0 | reset = 0 | w = 0 | z = 0
Time = 15 | clk = 1 | reset = 0 | w = 0 | z = 0
Time = 20 | clk = 0 | reset = 0 | w = 1 | z = 0
Time = 25 | clk = 1 | reset = 0 | w = 1 | z = 0
Time = 30 | clk = 0 | reset = 0 | w = 1 | z = 0
Time = 35 | clk = 1 | reset = 0 | w = 1 | z = 1
Time = 40 | clk = 0 | reset = 0 | w = 0 | z = 1
Time = 45 | clk = 1 | reset = 0 | w = 0 | z = 0
Time = 50 | clk = 0 | reset = 0 | w = 0 | z = 0
Time = 55 | clk = 1 | reset = 0 | w = 0 | z = 0
Time = 60 | clk = 0 | reset = 0 | w = 1 | z = 0
Time = 65 | clk = 1 | reset = 0 | w = 1 | z = 0
Time = 70 | clk = 0 | reset = 0 | w = 0 | z = 0
Time = 75 | clk = 1 | reset = 0 | w = 0 | z = 0
Time = 80 | clk = 0 | reset = 0 | w = 1 | z = 0
Time = 85 | clk = 1 | reset = 0 | w = 1 | z = 0
Time = 90 | clk = 0 | reset = 0 | w = 1 | z = 0
Time = 95 | clk = 1 | reset = 0 | w = 1 | z = 1
Time = 100 | clk = 0 | reset = 0 | w = 1 | z = 1
Time = 105 | clk = 1 | reset = 0 | w = 1 | z = 1
Time = 110 | clk = 0 | reset = 0 | w = 0 | z = 1
Time = 115 | clk = 1 | reset = 0 | w = 0 | z = 0
Time = 120 | clk = 0 | reset = 0 | w = 0 | z = 0
Time = 125 | clk = 1 | reset = 0 | w = 0 | z = 0

******************************************************************************************

3
 Question :2
******************************************************************************************
Q2) Develop Verilog code for the FSM given that is below and make
testbench to verify it: Where “w” is input signal and “R2out,
R3in, R1out, R3out, R1in, done” are output signals and A,B,C,D
are states

******************************************************************************************
Code
******************************************************************************************
module fsm_q2 (
input wire clk, rst, w,
output reg R2out, R3in, R1out, R2in, R3out, R1in, done
);
// State Encoding
parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;

reg [1:0] state, next_state;

// State transition logic (sequential)

always @(posedge clk or posedge rst) begin
if (rst)
state <= A;
else
state <= next_state;
end

// Next state and output logic (combinational)

always @(*) begin
// Default values for outputs

4
 R2out = 0;
R3in = 0;
R1out = 0;
R2in = 0;
R3out = 0;
R1in = 0;
done = 0;

case (state)
A: begin
next_state = (w) ? B : A;
end
B: begin
R2out = 1;
R3in = 1;
next_state = (w) ? C : A;
end
C: begin
R1out = 1;
R2in = 1;
next_state = (w) ? D : A;
end
D: begin
R3out = 1;
R1in = 1;
done = 1;
next_state = A; // Goes back to A after execution
end
default: begin
next_state = A;
end
endcase
end
endmodule

Testbench:

module fsm_q2_tb;
reg clk, rst, w;

5
wire R2out, R3in, R1out, R2in, R3out, R1in, done;
wire [1:0] state;

// Instantiate the FSM module

fsm_q2 uut (
.clk(clk),
.rst(rst),
.w(w),
.R2out(R2out),
.R3in(R3in),
.R1out(R1out),
.R2in(R2in),
.R3out(R3out),
.R1in(R1in),
.done(done)
);

assign state = uut.state; // Capture FSM state for debugging

// Clock generation
always #5 clk = ~clk;

initial begin
// Initialize inputs
clk = 0;
rst = 1;
w = 0;

// Reset FSM
#10 rst = 0;

// Test sequence
repeat(20) begin
#10 w = $random;
end

#20 $finish;
end

6
 // Monitor signals
initial begin
$monitor("Time=%0t | w=%b | R2out=%b | R3in=%b | R1out=%b | R2in=%b | R3out=%b
| R1in=%b | Done=%b",
$time, w, R2out, R3in, R1out, R2in, R3out, R1in, done);
end

// Dump waveform
initial begin
$dumpfile("fsm_q2_tb.vcd");
$dumpvars(1, fsm_q2_tb);
end
endmodule
******************************************************************************************

OUTPUT:
******************************************************************************************
Time=0 | w=0 | R2out=0 | R3in=0 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=30 | w=1 | R2out=0 | R3in=0 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=35 | w=1 | R2out=1 | R3in=1 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=45 | w=1 | R2out=0 | R3in=0 | R1out=1 | R2in=1 | R3out=0 | R1in=0 | Done=0
Time=55 | w=1 | R2out=0 | R3in=0 | R1out=0 | R2in=0 | R3out=1 | R1in=1 | Done=1
Time=65 | w=1 | R2out=0 | R3in=0 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=75 | w=1 | R2out=1 | R3in=1 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=85 | w=1 | R2out=0 | R3in=0 | R1out=1 | R2in=1 | R3out=0 | R1in=0 | Done=0
Time=90 | w=0 | R2out=0 | R3in=0 | R1out=1 | R2in=1 | R3out=0 | R1in=0 | Done=0
Time=95 | w=0 | R2out=0 | R3in=0 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=100 | w=1 | R2out=0 | R3in=0 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=105 | w=1 | R2out=1 | R3in=1 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=115 | w=1 | R2out=0 | R3in=0 | R1out=1 | R2in=1 | R3out=0 | R1in=0 | Done=0
Time=120 | w=0 | R2out=0 | R3in=0 | R1out=1 | R2in=1 | R3out=0 | R1in=0 | Done=0
Time=125 | w=0 | R2out=0 | R3in=0 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=130 | w=1 | R2out=0 | R3in=0 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=135 | w=1 | R2out=1 | R3in=1 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=145 | w=1 | R2out=0 | R3in=0 | R1out=1 | R2in=1 | R3out=0 | R1in=0 | Done=0
Time=150 | w=0 | R2out=0 | R3in=0 | R1out=1 | R2in=1 | R3out=0 | R1in=0 | Done=0
Time=155 | w=0 | R2out=0 | R3in=0 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=160 | w=1 | R2out=0 | R3in=0 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0

7
Time=165 | w=1 | R2out=1 | R3in=1 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=170 | w=0 | R2out=1 | R3in=1 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=175 | w=0 | R2out=0 | R3in=0 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=180 | w=1 | R2out=0 | R3in=0 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=185 | w=1 | R2out=1 | R3in=1 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=190 | w=0 | R2out=1 | R3in=1 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=195 | w=0 | R2out=0 | R3in=0 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=200 | w=1 | R2out=0 | R3in=0 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=205 | w=1 | R2out=1 | R3in=1 | R1out=0 | R2in=0 | R3out=0 | R1in=0 | Done=0
Time=215 | w=1 | R2out=0 | R3in=0 | R1out=1 | R2in=1 | R3out=0 | R1in=0 | Done=0
Time=225 | w=1 | R2out=0 | R3in=0 | R1out=0 | R2in=0 | R3out=1 | R1in=1 | Done=1

******************************************************************************************

Question:3
**************************************************************************************************
Q3) Write Verilog code for the FSM given that is below and also
make testbench to verify it : Where “w, Reset” are input signal
and “z” is output signals and A,B are states

******************************************************************************************
Code:
******************************************************************************************
module fsm_q3 (
input wire clk, Reset, w,
output reg z
);

parameter A = 1'b0, B = 1'b1;

reg state, next_state;

8
 always @(posedge clk or posedge Reset) begin
if (Reset)
state <= A;
else
state <= next_state;
end

always @(*) begin

z = 0;
case (state)
A: begin
next_state = (w) ? B : A;
z = 0;
end
B: begin
next_state = (w) ? B : A;
z = 1;
end
default: begin
next_state = A;
z = 0;
end
endcase
end
endmodule

Testbench:
// Testbench for FSM
module fsm_q3_tb;
reg clk, Reset, w;
wire z;
wire state;

// Instantiate the FSM module

fsm_q3 uut (
.clk(clk),
.Reset(Reset),
.w(w),
.z(z)
);

assign state = uut.state; // Capture FSM state for debugging

9
 // Clock generation
always #10 clk = ~clk;

initial begin
// Initialize inputs
clk = 0;
Reset = 1;
w = 0;

// Reset FSM
#10 Reset = 0;

// Test sequence
repeat(20) begin
#10 w = $random;
end

#200 $finish;
end

// Monitor signals
initial begin
$monitor("Time=%0t | w=%b | z=%b", $time, w, z);
end

// Dump waveform
initial begin
$dumpfile("fsm_q3_tb.vcd");
$dumpvars(1, fsm_q3_tb);
end
endmodule
*****************************************************************************************
Output:
******************************************************************************************
Time=0 | w=0 | z=0
Time=30 | w=1 | z=0
Time=50 | w=1 | z=1
Time=90 | w=0 | z=1
Time=100 | w=1 | z=1
Time=120 | w=0 | z=1
Time=130 | w=1 | z=0
Time=150 | w=0 | z=1

10
Time=160 | w=1 | z=1
Time=170 | w=0 | z=1
Time=180 | w=1 | z=1
Time=190 | w=0 | z=1
Time=200 | w=1 | z=1

******************************************************************************************

Question:5
**************************************************************************************************
Q5) a) Design an FSM that has an input w and an output z. The
machine is a sequence detector that produces z = 1 when the
previous two values of w were 00 or 11; otherwise z=0. And
implement the testbench to verify the design
b) Implement the sequence detector mentioned in part (a) by
using two FSMs. One FSM detects the occurrence of consecutive
1s, while the other detects consecutive 0s. And implement the
testbench to verify the design
c) Derive a Mealy Type FSM that can act as a sequence detector
described in part (a) And implement the testbench to verify the
design
******************************************************************************************
Code:
******************************************************************************************

11
module sequence_detector (
input clk,
input reset,
input w,
output reg z
);
parameter S0 = 2'b00, // Initial state
S1 = 2'b01, // Last input was 0
S2 = 2'b10, // Last input was 1
S3 = 2'b11; // Detected two consecutive 0s or 1s

reg [1:0] state, next_state;

// State transition logic

always @(posedge clk or posedge reset) begin
if (reset)
state <= S0;
else
state <= next_state;
end

// Next state logic

always @(*) begin
case (state)
S0: next_state = (w) ? S2 : S1;
S1: next_state = (w) ? S2 : S3; // Detects '00'
S2: next_state = (w) ? S3 : S1; // Detects '11'
S3: next_state = (w) ? S2 : S1;
default: next_state = S0;
endcase
end

// Output logic
always @(state) begin
z = (state == S3) ? 1'b1 : 1'b0;
end
endmodule

Testbench:
`timescale 1ns / 1ps
module tb_sequence_detector;
reg clk, reset, w;
wire z;

12
 // Instantiate the FSM
sequence_detector uut (
.clk(clk),
.reset(reset),
.w(w),
.z(z)
);

// Clock Generation
always #5 clk = ~clk;

initial begin
clk = 0;
reset = 1;
w = 0;

#10 reset = 0;

// Test cases: 00, 11 detection

#10 w = 0;
#10 w = 0; // z should be 1
#10 w = 1;
#10 w = 1; // z should be 1
#10 w = 0;
#10 w = 1;
#10 w = 0;
#10 w = 0; // z should be 1

#50 $finish;
end

initial begin
$monitor("Time=%0t | w=%b | z=%b", $time, w, z);
end

initial begin
$dumpfile("sequence_detector.vcd");
$dumpvars(1, tb_sequence_detector);
end

endmodule
*****************************************************************************************

13
 Output:
******************************************************************************************
Time=0 | w=0 | z=0
Time=25000 | w=0 | z=1
Time=35000 | w=0 | z=0
Time=40000 | w=1 | z=0
Time=55000 | w=1 | z=1
Time=60000 | w=0 | z=1
Time=65000 | w=0 | z=0
Time=70000 | w=1 | z=0
Time=80000 | w=0 | z=0
Time=95000 | w=0 | z=1
Time=105000 | w=0 | z=0
Time=115000 | w=0 | z=1
Time=125000 | w=0 | z=0
Time=135000 | w=0 | z=1

******************************************************************************************
Code:
******************************************************************************************
b)
module fsm_00_detector (
input clk,
input reset,
input w,
output reg z
);
parameter IDLE = 1'b0, DETECTED = 1'b1;
reg state;

always @(posedge clk or posedge reset) begin

if (reset)
state <= IDLE;
else

14
 state <= (w == 0) ? DETECTED : IDLE;
end

always @(state) begin

z = (state == DETECTED) ? 1'b1 : 1'b0;
end
endmodule

module fsm_11_detector (
input clk,
input reset,
input w,
output reg z
);
parameter IDLE = 1'b0, DETECTED = 1'b1;
reg state;

always @(posedge clk or posedge reset) begin

if (reset)
state <= IDLE;
else
state <= (w == 1) ? DETECTED : IDLE;
end

always @(state) begin

z = (state == DETECTED) ? 1'b1 : 1'b0;
end
endmodule

module combined_fsm (
input clk,
input reset,
input w,
output z
);
wire z_00, z_11;

fsm_00_detector u1 (.clk(clk), .reset(reset), .w(w), .z(z_00));

fsm_11_detector u2 (.clk(clk), .reset(reset), .w(w), .z(z_11));

assign z = z_00 | z_11; // Output is 1 when either FSM detects 00 or 11

endmodule

15
Testbench:
`timescale 1ns / 1ps
module tb_combined_fsm;
reg clk, reset, w;
wire z;

// Instantiate the FSM

combined_fsm uut (
.clk(clk),
.reset(reset),
.w(w),
.z(z)
);
always #5 clk = ~clk;
initial begin
clk = 0;
reset = 1;
w = 0;
#10 reset = 0;
#10 w = 0;
#10 w = 0; // Should detect 00
#10 w = 1;
#10 w = 1; // Should detect 11
#10 w = 0;
#10 w = 1;
#10 w = 0;
#10 w = 0; // Should detect 00 again
#50 $finish;
end
initial begin
$monitor("Time=%0t | w=%b | z=%b", $time, w, z);
end
initial begin
$dumpfile("combined_fsm.vcd");
$dumpvars(1, tb_combined_fsm);
end
endmodule
*****************************************************************************************
Output:
******************************************************************************************
Time=0 | w=0 | z=0
Time=15000 | w=0 | z=1
Time=40000 | w=1 | z=1

16
Time=60000 | w=0 | z=1
Time=70000 | w=1 | z=1
Time=80000 | w=0 | z=1

******************************************************************************************
Code:
******************************************************************************************

module mealy_sequence_detector (
input clk,
input reset,
input w,
output reg z
);
parameter S0 = 1'b0, S1 = 1'b1;

reg state, next_state;

always @(posedge clk or posedge reset) begin

if (reset)
state <= S0;
else
state <= next_state;
end

always @(*) begin

case (state)
S0: begin

17
 z = 0;
next_state = (w == 0) ? S1 : S0;
end
S1: begin
z = (w == state) ? 1 : 0; // Output depends on input
next_state = (w == 0) ? S1 : S0;
end
default: begin
z = 0;
next_state = S0;
end
endcase
end
endmodule

Testbench:
`timescale 1ns / 1ps
module tb_mealy_sequence_detector;
reg clk, reset, w;
wire z;

mealy_sequence_detector uut (
.clk(clk),
.reset(reset),
.w(w),
.z(z)
);

always #5 clk = ~clk;

initial begin
clk = 0;
reset = 1;
w = 0;

#10 reset = 0;

#10 w = 0;
#10 w = 0; // z should be 1
#10 w = 1;
#10 w = 1; // z should be 1

#50 $finish;

18
 end

initial begin
$monitor("Time=%0t | w=%b | z=%b", $time, w, z);
end

initial begin
$dumpfile("mealy_sequence_detector.vcd");
$dumpvars(1, tb_mealy_sequence_detector);
end
endmodule
*****************************************************************************************
Output:
******************************************************************************************
Time=0 | w=0 | z=0
Time=40000 | w=1 | z=1
Time=45000 | w=1 | z=0

******************************************************************************************
Question:6
**************************************************************************************************
Q6) In computer systems it is often desirable to transmit data
serially, namely, one bit at a time, to save on the cost of
interconnecting cables. This means that parallel data at one end
must be transmitted serially, and at the other end the received
serial data has to be turned back into parallel form. Suppose
that we wish to transmit ASCII characters in this manner. As
explained in Chapter 1, the standard ASCII code uses seven bits
to define each character. Usually, a character occupies one
byte, in which case the eighth bit can either be set to 0 or it
can be used to indicate the parity of the other bits to ensure a
more reliable transmission. Parallel-to-serial conversion can be
done by means of a shift register. Assume that a circuit accepts
parallel data, B = b7, b6, . . . , b0, representing ASCII
characters. Assume also that bit b7 is set to 0. The circuit is
supposed to generate a parity bit, p, and send it instead of b7
as a part of the serial transfer. Figure 6.97 gives a possible
circuit. An FSM is used to generate the parity bit, which is
included in the output stream by using a multiplexer. A

19
three bit counter is used to determine when the p bit is
transmitted, which happens when the count reaches 7. Design the
desired FSM. And implement the testbench to verify the design

******************************************************************************************
Code:
******************************************************************************************
module parity_fsm (
input clk,
input reset,
input w,
input counter_done,
output reg p,
output reg reset_counter
);
reg parity_bit;

always @(posedge clk or posedge reset) begin

if (reset) begin
parity_bit <= 0;
reset_counter <= 1;
end else begin
reset_counter <= 0;
parity_bit <= parity_bit ^ w; // XOR for parity calculation
end
end

always @(posedge clk) begin

if (counter_done) begin
p <= parity_bit; // Transmit the calculated parity bit

20
 end
end
endmodule

Testbench:
`timescale 1ns / 1ps
module tb_parity_fsm;
reg clk, reset, w, counter_done;
wire p, reset_counter;

// Instantiate the FSM

parity_fsm uut (
.clk(clk),
.reset(reset),
.w(w),
.counter_done(counter_done),
.p(p),
.reset_counter(reset_counter)
);

// Clock Generation
always #5 clk = ~clk;

initial begin
clk = 0;
reset = 1;
w = 0;
counter_done = 0;

#10 reset = 0;

// Provide input sequence (7-bit ASCII, example: 0110001)

#10 w = 0;
#10 w = 1;
#10 w = 1;
#10 w = 0;
#10 w = 0;
#10 w = 0;
#10 w = 1;

// Indicate end of transmission

#10 counter_done = 1;
#10 counter_done = 0;

21
 #50 $finish;
end

initial begin
$monitor("Time=%0t | w=%b | p=%b | reset_counter=%b", $time, w, p, reset_counter);
end

initial begin
$dumpfile("parity_fsm.vcd");
$dumpvars(1, tb_parity_fsm);
end
endmodule
*****************************************************************************************
Output:
******************************************************************************************
Time=0 | w=0 | p=x | reset_counter=1
Time=15000 | w=0 | p=x | reset_counter=0
Time=30000 | w=1 | p=x | reset_counter=0
Time=50000 | w=0 | p=x | reset_counter=0
Time=80000 | w=1 | p=x | reset_counter=0
Time=95000 | w=1 | p=1 | reset_counter=0

******************************************************************************************
Question:7
**************************************************************************************************
Q7) You have to develop a state diagram for a washing machine.
The machine starts when a coin is deposited. It then sequences
through the following steps : soak, wash, rinse and spin. There
is a switch called double wash, which if turned on, uses a 2
times rinse need to occur. There is one timer -you may assume
that each stage takes the same amount of time. The timer begins
ticking as soon as the coin is deposited, generates a signal T
at the end of the time period, and then resets itself and starts
again. If the lid (door of the washing machine) is raised during
the spin cycle, then the timer stops ticking and the machine
stops spinning. At the end of the time period, the machine goes
back to its initial state. implement the testbench to verify the
design also a) Identify your inputs and outputs and draw a state

22
machine to achieve the control function. b) Write verilog code
to simulate the state machine.
******************************************************************************************
Code:
******************************************************************************************
Inputs: coin ,double_wash ,lid_open ,T (timer signal)
Outputs: state ,start_timer ,machine_running
module washing_machine_fsm (
input clk,
input reset,
input coin,
input double_wash,
input lid_open,
input T, // Timer signal
output reg [2:0] state,
output reg start_timer,
output reg machine_running
);
// Define states
parameter IDLE = 3'b000, SOAK = 3'b001, WASH = 3'b010,
RINSE1 = 3'b011, RINSE2 = 3'b100, SPIN = 3'b101;

reg [2:0] next_state;

// State transition logic (Sequential)

always @(posedge clk or posedge reset) begin
if (reset)
state <= IDLE;
else
state <= next_state;
end

// Next state logic (Combinational)

always @(*) begin
next_state = state;
start_timer = 0;
machine_running = 1;

case (state)
IDLE: begin
machine_running = 0;
if (coin) begin
next_state = SOAK;

23
 start_timer = 1;
end
end

SOAK: if (T) begin

next_state = WASH;
start_timer = 1;
end

WASH: if (T) begin

next_state = RINSE1;
start_timer = 1;
end

RINSE1: if (T) begin

if (double_wash)
next_state = RINSE2;
else
next_state = SPIN;
start_timer = 1;
end

RINSE2: if (T) begin

next_state = SPIN;
start_timer = 1;
end

SPIN: begin
if (lid_open)
machine_running = 0; // Stop spinning if lid is open
else if (T)
next_state = IDLE;
end
endcase
end
endmodule

Testbench:
`timescale 1ns / 1ps

module tb_washing_machine_fsm;
reg clk, reset, coin, double_wash, lid_open, T;
wire [2:0] state;

24
wire start_timer, machine_running;

// Instantiate FSM
washing_machine_fsm uut (
.clk(clk),
.reset(reset),
.coin(coin),
.double_wash(double_wash),
.lid_open(lid_open),
.T(T),
.state(state),
.start_timer(start_timer),
.machine_running(machine_running)
);

// Clock Generation
always #5 clk = ~clk;

initial begin
// Initialize
clk = 0;
reset = 1;
coin = 0;
double_wash = 0;
lid_open = 0;
T = 0;

#10 reset = 0;

// Insert coin to start

#10 coin = 1;
#10 coin = 0;

// Timer progresses through states

repeat (5) begin
#10 T = 1;
#10 T = 0;
end

// Enable double wash

#10 double_wash = 1;
repeat (2) begin
#10 T = 1;

25
 #10 T = 0;
end

// Spin cycle, then open lid

#10 T = 1;
#10 lid_open = 1;
#10 lid_open = 0;
#10 T = 1;

#20 $finish;
end

initial begin
$monitor("Time: %0t | State: %b | Timer: %b | Lid Open: %b | Running: %b",
$time, state, T, lid_open, machine_running);
end

initial begin
$dumpfile("washing_machine_fsm.vcd");
$dumpvars(1, tb_washing_machine_fsm);
end
endmodule
*****************************************************************************************
Output:
******************************************************************************************
Time: 0 | State: 000 | Timer: 0 | Lid Open: 0 | Running: 0
Time: 25000 | State: 001 | Timer: 0 | Lid Open: 0 | Running: 1
Time: 40000 | State: 001 | Timer: 1 | Lid Open: 0 | Running: 1
Time: 45000 | State: 010 | Timer: 1 | Lid Open: 0 | Running: 1
Time: 50000 | State: 010 | Timer: 0 | Lid Open: 0 | Running: 1
Time: 60000 | State: 010 | Timer: 1 | Lid Open: 0 | Running: 1
Time: 65000 | State: 011 | Timer: 1 | Lid Open: 0 | Running: 1
Time: 70000 | State: 011 | Timer: 0 | Lid Open: 0 | Running: 1
Time: 80000 | State: 011 | Timer: 1 | Lid Open: 0 | Running: 1
Time: 85000 | State: 101 | Timer: 1 | Lid Open: 0 | Running: 1
Time: 90000 | State: 101 | Timer: 0 | Lid Open: 0 | Running: 1
Time: 100000 | State: 101 | Timer: 1 | Lid Open: 0 | Running: 1
Time: 105000 | State: 000 | Timer: 1 | Lid Open: 0 | Running: 0
Time: 110000 | State: 000 | Timer: 0 | Lid Open: 0 | Running: 0
Time: 120000 | State: 000 | Timer: 1 | Lid Open: 0 | Running: 0
Time: 130000 | State: 000 | Timer: 0 | Lid Open: 0 | Running: 0

26
Time: 150000 | State: 000 | Timer: 1 | Lid Open: 0 | Running: 0
Time: 160000 | State: 000 | Timer: 0 | Lid Open: 0 | Running: 0
Time: 170000 | State: 000 | Timer: 1 | Lid Open: 0 | Running: 0
Time: 180000 | State: 000 | Timer: 0 | Lid Open: 0 | Running: 0
Time: 190000 | State: 000 | Timer: 1 | Lid Open: 0 | Running: 0
Time: 200000 | State: 000 | Timer: 1 | Lid Open: 1 | Running: 0
Time: 210000 | State: 000 | Timer: 1 | Lid Open: 0 | Running: 0

******************************************************************************************
Question:8
**************************************************************************************************
Q8) You are to design a Mealy state diagram for a digital lock.
Assume that two debounced pushbuttons, A and B, are available to
enter the combination. An electromechanical interlock guarantees
that the buttons cannot be activated simultaneously. The lock
should have the following features: The combination is A-A-B-A-
B-A. If this sequence is correctly entered, an output signal is
asserted that causes the lock to open. For any state, three B
pulses in a row should guarantee to reset the control to its
initial state. When any out-of-sequence use of the A pushbutton
occurs, an output is asserted that rings a bell to warn that the
lock is being tampered with. Once the lock is open, pressing
either A or B will cause the lock to close without signaling an
error. Draw a Mealy state diagram for this finite state machine.
Indicate what each state represents and what input conditions
cause state and output changes. Everything may not have been
specified, so write down any assumptions you make
// PSSWORDS = AABABA // RING = AAA // INITIAL STATE = BBB or
passwords detect and after that press A or B
******************************************************************************************
Code:
******************************************************************************************
module digital_lock_fsm (
input clk,
input reset,
input A, B,

27
 output reg lock_open,
output reg ring_bell
);

// State Encoding
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010,
S3 = 3'b011, S4 = 3'b100, S5 = 3'b101, S6 = 3'b110;

reg [2:0] state, next_state;

reg [1:0] b_count; // Counts consecutive 'B' presses

// State Transition (Sequential Logic)

always @(posedge clk or posedge reset) begin
if (reset)
state <= S0;
else
state <= next_state;
end

// Next State Logic (Combinational Logic)

always @(*) begin
next_state = state;
lock_open = 0;
ring_bell = 0;

case (state)
S0: begin
if (A) next_state = S1;
else if (B) begin
b_count = b_count + 1;
if (b_count == 2) next_state = S0; // Reset after 3 B presses
end
end

S1: if (A) next_state = S2; else next_state = S0;

S2: begin
if (B) next_state = S3;
else begin
ring_bell = 1; // Tamper detected
next_state = S0;
end
end

28
 S3: if (A) next_state = S4; else next_state = S0;

S4: begin
if (B) next_state = S5;
else begin
ring_bell = 1; // Tamper detected
next_state = S0;
end
end

S5: if (A) next_state = S6; else next_state = S0;

S6: begin
lock_open = 1; // Lock is open
if (A || B) next_state = S0; // Close lock
end
endcase
end
endmodule

Testbench:
`timescale 1ns / 1ps

module tb_digital_lock_fsm;
reg clk, reset, A, B;
wire lock_open, ring_bell;

// Instantiate FSM
digital_lock_fsm uut (
.clk(clk),
.reset(reset),
.A(A),
.B(B),
.lock_open(lock_open),
.ring_bell(ring_bell)
);

// Clock Generation
always #5 clk = ~clk;

initial begin
// Initialize signals

29
 clk = 0; reset = 1; A = 0; B = 0;
#10 reset = 0;

// Correct Password: AABABA

#10 A = 1; #10 A = 0;
#10 A = 1; #10 A = 0;
#10 B = 1; #10 B = 0;
#10 A = 1; #10 A = 0;
#10 B = 1; #10 B = 0;
#10 A = 1; #10 A = 0;

// Lock is Open, Press A/B to Close

#10 A = 1; #10 A = 0;

// Incorrect sequence - Bell Rings

#10 A = 1; #10 A = 0;
#10 A = 1; #10 A = 0;
#10 A = 1; #10 A = 0; // Tamper alert

// Reset and try again

#10 reset = 1; #10 reset = 0;

// Three consecutive B presses to reset

#10 B = 1; #10 B = 0;
#10 B = 1; #10 B = 0;
#10 B = 1; #10 B = 0;

#20 $finish;
end

initial begin
$monitor("Time: %0t | State: %b | A: %b | B: %b | Lock Open: %b | Bell: %b",
$time, uut.state, A, B, lock_open, ring_bell);
end

initial begin
$dumpfile("digital_lock_fsm.vcd");
$dumpvars(1, tb_digital_lock_fsm);
end
endmodule
*****************************************************************************************

30
 Output:
******************************************************************************************
Time: 0 | State: 000 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 20000 | State: 000 | A: 1 | B: 0 | Lock Open: 0 | Bell: 0
Time: 25000 | State: 001 | A: 1 | B: 0 | Lock Open: 0 | Bell: 0
Time: 30000 | State: 001 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 35000 | State: 000 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 40000 | State: 000 | A: 1 | B: 0 | Lock Open: 0 | Bell: 0
Time: 45000 | State: 001 | A: 1 | B: 0 | Lock Open: 0 | Bell: 0
Time: 50000 | State: 001 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 55000 | State: 000 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 60000 | State: 000 | A: 0 | B: 1 | Lock Open: 0 | Bell: 0
Time: 70000 | State: 000 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 80000 | State: 000 | A: 1 | B: 0 | Lock Open: 0 | Bell: 0
Time: 85000 | State: 001 | A: 1 | B: 0 | Lock Open: 0 | Bell: 0
Time: 90000 | State: 001 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 95000 | State: 000 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 100000 | State: 000 | A: 0 | B: 1 | Lock Open: 0 | Bell: 0
Time: 110000 | State: 000 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 120000 | State: 000 | A: 1 | B: 0 | Lock Open: 0 | Bell: 0
Time: 125000 | State: 001 | A: 1 | B: 0 | Lock Open: 0 | Bell: 0
Time: 130000 | State: 001 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 135000 | State: 000 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 140000 | State: 000 | A: 1 | B: 0 | Lock Open: 0 | Bell: 0
Time: 145000 | State: 001 | A: 1 | B: 0 | Lock Open: 0 | Bell: 0
Time: 150000 | State: 001 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 155000 | State: 000 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 160000 | State: 000 | A: 1 | B: 0 | Lock Open: 0 | Bell: 0
Time: 165000 | State: 001 | A: 1 | B: 0 | Lock Open: 0 | Bell: 0
Time: 170000 | State: 001 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 175000 | State: 000 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 180000 | State: 000 | A: 1 | B: 0 | Lock Open: 0 | Bell: 0
Time: 185000 | State: 001 | A: 1 | B: 0 | Lock Open: 0 | Bell: 0
Time: 190000 | State: 001 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 195000 | State: 000 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 200000 | State: 000 | A: 1 | B: 0 | Lock Open: 0 | Bell: 0
Time: 205000 | State: 001 | A: 1 | B: 0 | Lock Open: 0 | Bell: 0
Time: 210000 | State: 001 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 215000 | State: 000 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0

31
Time: 240000 | State: 000 | A: 0 | B: 1 | Lock Open: 0 | Bell: 0
Time: 250000 | State: 000 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 260000 | State: 000 | A: 0 | B: 1 | Lock Open: 0 | Bell: 0
Time: 270000 | State: 000 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0
Time: 280000 | State: 000 | A: 0 | B: 1 | Lock Open: 0 | Bell: 0
Time: 290000 | State: 000 | A: 0 | B: 0 | Lock Open: 0 | Bell: 0

******************************************************************************************
Question:9
**************************************************************************************************
Q9) You have to design a Vending Machine. The machine takes
input in the form of Rs. 5, Rs 10, Rs.20, Rs. 50 and Rs. 100.
The outputs can be any one or combination of these:
1) Cold drink: Rs 10
2) Dairy Milk: Rs 45
3) Biscuits: Rs 5
4) Red-bull: Rs 75
5) Imported chocolate: Rs 135
If you want to buy more than one item, it is possible. You will
get the change if the price of the item is less than the amount
entered. Items should be released only when the entire purchase
procedure is completed
******************************************************************************************
Code:
******************************************************************************************
module vending_machine (
input clk,
input reset,
input [7:0] coin_input, // Denominations: 5, 10, 20, 50, 100
input [2:0] item_select, // 3-bit item selection
input confirm,
input cancel,
output reg [2:0] item_dispensed, // Item dispensed signal
output reg [7:0] change, // Change returned
output reg transaction_complete // Signals end of transaction
);

// Item price encoding

32
parameter COLD_DRINK = 10, DAIRY_MILK = 45, BISCUITS = 5,
RED_BULL = 75, IMPORTED_CHOCOLATE = 135;

// State Encoding
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010,
S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;

reg [2:0] state, next_state;

reg [7:0] balance, item_price;

// State Transition
always @(posedge clk or posedge reset) begin
if (reset)
state <= S0;
else
state <= next_state;
end

// Next State Logic

always @(*) begin
next_state = state;
transaction_complete = 0;
item_dispensed = 0;
change = 0;

case (state)
S0: begin
if (coin_input > 0)
next_state = S1; // Move to money-accepting state
end

S1: begin
if (cancel)
next_state = S5; // Cancel transaction
else if (confirm)
next_state = S2; // Proceed to selection
end

S2: begin
case (item_select)
3'b000: item_price = BISCUITS;
3'b001: item_price = COLD_DRINK;
3'b010: item_price = DAIRY_MILK;

33
 3'b011: item_price = RED_BULL;
3'b100: item_price = IMPORTED_CHOCOLATE;
default: item_price = 0;
endcase

next_state = S3;
end

S3: begin
if (balance >= item_price)
next_state = S4; // Proceed to dispense item
else
next_state = S1; // Wait for more money
end

S4: begin
item_dispensed = item_select;
change = balance - item_price;
next_state = S5;
end

S5: begin
transaction_complete = 1;
next_state = S0; // Reset to initial state
end
endcase
end

// Balance Update
always @(posedge clk) begin
if (reset)
balance <= 0;
else if (state == S1)
balance <= balance + coin_input;
else if (state == S4)
balance <= 0; // Reset after transaction
end
endmodule

Testbench:
`timescale 1ns / 1ps

module tb_vending_machine;

34
reg clk, reset, confirm, cancel;
reg [7:0] coin_input;
reg [2:0] item_select;
wire [2:0] item_dispensed;
wire [7:0] change;
wire transaction_complete;

// Instantiate vending machine

vending_machine uut (
.clk(clk),
.reset(reset),
.coin_input(coin_input),
.item_select(item_select),
.confirm(confirm),
.cancel(cancel),
.item_dispensed(item_dispensed),
.change(change),
.transaction_complete(transaction_complete)
);

// Clock Generation
always #5 clk = ~clk;

initial begin
// Initialize
clk = 0; reset = 1; coin_input = 0; item_select = 0; confirm = 0; cancel = 0;
#10 reset = 0;

// Insert Rs. 50
#10 coin_input = 50;
#10 coin_input = 0;

// Select Dairy Milk (Rs. 45)

#10 item_select = 3'b010; confirm = 1;
#10 confirm = 0;

// Transaction should complete, return Rs. 5 change

#20;

// New Transaction: Insert Rs. 100

#10 coin_input = 100;
#10 coin_input = 0;

35
 // Select Red Bull (Rs. 75)
#10 item_select = 3'b011; confirm = 1;
#10 confirm = 0;

// Transaction should complete, return Rs. 25 change

#20;

// Reset and Try to Buy Imported Chocolate with Rs. 50 (should wait for more money)
#10 reset = 1; #10 reset = 0;
#10 coin_input = 50;
#10 coin_input = 0;
#10 item_select = 3'b100; confirm = 1;
#10 confirm = 0;

// Insert Rs. 100 (Now total Rs. 150)

#10 coin_input = 100;
#10 coin_input = 0;

// Now confirm purchase (Rs. 135 used, Rs. 15 change)

#10 confirm = 1;
#10 confirm = 0;

#20 $finish;
end

initial begin
$monitor("Time: %0t | State: %b | Balance: %d | Item Selected: %b | Item Dispensed: %b |
Change: %d | Transaction Complete: %b",
$time, uut.state, uut.balance, item_select, item_dispensed, change,
transaction_complete);
end

initial begin
$dumpfile("vending_machine.vcd");
$dumpvars(1, tb_vending_machine);
end
endmodule
*****************************************************************************************
Output:
******************************************************************************************
Time: 0 | State: 000 | Balance: x | Item Selected: 000 | Item Dispensed: 000 | Change:
0 | Transaction Complete: 0
Time: 5000 | State: 000 | Balance: 0 | Item Selected: 000 | Item Dispensed: 000 |

36
Change: 0 | Transaction Complete: 0
Time: 25000 | State: 001 | Balance: 0 | Item Selected: 000 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0
Time: 40000 | State: 001 | Balance: 0 | Item Selected: 010 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0
Time: 45000 | State: 010 | Balance: 0 | Item Selected: 010 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0
Time: 55000 | State: 011 | Balance: 0 | Item Selected: 010 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0
Time: 65000 | State: 001 | Balance: 0 | Item Selected: 010 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0
Time: 85000 | State: 001 | Balance: 100 | Item Selected: 010 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0
Time: 100000 | State: 001 | Balance: 100 | Item Selected: 011 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0
Time: 105000 | State: 010 | Balance: 100 | Item Selected: 011 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0
Time: 115000 | State: 011 | Balance: 100 | Item Selected: 011 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0
Time: 125000 | State: 100 | Balance: 100 | Item Selected: 011 | Item Dispensed: 011 |
Change: 25 | Transaction Complete: 0
Time: 135000 | State: 101 | Balance: 0 | Item Selected: 011 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 1
Time: 140000 | State: 000 | Balance: 0 | Item Selected: 011 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0
Time: 165000 | State: 001 | Balance: 0 | Item Selected: 011 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0
Time: 180000 | State: 001 | Balance: 0 | Item Selected: 100 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0
Time: 185000 | State: 010 | Balance: 0 | Item Selected: 100 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0
Time: 195000 | State: 011 | Balance: 0 | Item Selected: 100 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0
Time: 205000 | State: 001 | Balance: 0 | Item Selected: 100 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0
Time: 225000 | State: 010 | Balance: 0 | Item Selected: 100 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0
Time: 235000 | State: 011 | Balance: 0 | Item Selected: 100 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0

37
Time: 245000 | State: 001 | Balance: 0 | Item Selected: 100 | Item Dispensed: 000 |
Change: 0 | Transaction Complete: 0

******************************************************************************************

38