Silicon (2023) 15:2385–2405

https://doi.org/10.1007/s12633-022-02189-2

REVIEW PAPER

A Comprehensive Review on the Single Gate, Double Gate, Tri‑Gate,

and Heterojunction Tunnel FET for Future Generation Devices
P. Hannah Blessy1 · A. Shenbagavalli1 · T. S. Arun Samuel1

Received: 17 August 2022 / Accepted: 19 October 2022 / Published online: 27 October 2022
© Springer Nature B.V. 2022

Abstract
Today’s generation of the technological world needs low-power application devices and low-cost transistors. Recently
researchers have developed a 3 nm MOSFET nanoelectronics device. Even though MOSFET reduces its size and power
consumption, it prompts a few issues due to SCEs such as Hot electron, leakage current, threshold voltage roll-off, Impact
Ionization, Drain Induced Barrier lowering (DIBL), and so on. The tunnel FET (TFET) structure is one of the best-proposed
structures instead of the MOSFET structure, and it overcomes the limits induced by the CMOS transistor. TFET structure
is very suitable for low-power applications. TFET structure breaks the limits of CMOS’s subthreshold swing and attains an
average subthreshold swing of 60 mv/decade at normal temperature. The investigation of various TFET structure designs is
the emphasis of this work. This study discusses the numerous suggested TFET architectures, such as Heterojunction TFET,
Double Gate TFET, Tri-Gate TFET, and Single Gate TFET, and their performance.

Keywords Tunnel FET · Heterojunction TFET · Band to band tunneling(BTBT) · ON current · OFF current

1 Introduction TFET was proposed as the alternative technology for

CMOS and offered better performance for low-power appli-
Everyone needs high-performance application devices with cation electronic devices. A Quantum tunneling mechanism
low power consumption in today's technological world. is used in the Tunnel Field-Effect transistor, and it has the
MOSFET is a frequently used device for building an inte- potential to conquer the subthreshold swing SS limits at
grated circuit. Many kinds of research are going under the ambient temperature, allowing considerably steeper switch-
minimization of the MOSFET dimension over the past four ing characteristics and lower supply voltages [2]. High ­ION
decades. By way of scaling, MOSFET reduces its size up current, low ­IOFF current, enhanced ­ION/IOFF, and suppres-
to nanometres. Due to the reduction of MOSFET size leads sion of the ambipolar behavior are the significant character-
to some critical issues like ambipolar behavior and short istics of various types of TFET. Certain structural and mate-
channel effects (SCE) such as velocity saturation, thresh- rial engineering methods have been developed to accomplish
old voltage roll-off, Impact Ionization, Hot electron, and a synchronous expansion in ON current, diminish OFF cur-
Drain induced Barrier Lowering (DIBL), and so on. As a rent, and precipitous SS [3–5]. In the TFET structure, all
result, the demand emerges from discovering an alternative three regions, source, channel, and Drain, are made of the
technology capable of overcoming the limitations of CMOS same material. As a result, it has a higher drain current than
technology [1]. a MOSFET Structure.
Researchers are developed various types of TFET struc-
* P. Hannah Blessy tures. Heterojunction TFET is more efficient than Si-based
[email protected] TFET. In Heterojunction TFET, low bandgap different mate-
A. Shenbagavalli rials are utilized in the channel and source region to boost
[email protected] ­ION current and suppress the ambipolar behavior by increas-
T. S. Arun Samuel ing the tunneling area. Heterojunction structures are InAs/
[email protected] si Heterojunction Tunnel FET, InAs/GaSb Heterojunction
Tunnel FET, GaSb/Si Vertical Heterojunction Tunnel FET,
1
Department of ECE, National Engineering College, GaAsSb/InGaAs Negative Capacitance Vertical Tunnel FET,
Kovilpatti, India

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2386 Silicon (2023) 15:2385–2405

n-OS/p-IV Heterojunction Tunnel FET, GaSb/AISb/InAs

Vertical Heterojunction TFET, Dielectric Material-Dual side
doping less Heterojunction Tunnel FET, Dual Material Gate
Heterojunction TFET. Source-pocked engineering GaSb/Si
Heterojunction vertical TFET, Ge/GeSn Heterojunction
Tunnel FET, Heterojunction Dopingless Tunnel FET.
This paper focuses on studying various TFET structure
designs in terms of gate engineering, source pocket TFET,
drain pocket TFET, dual material gates TFET, Triple mate-
rials gate TFET, and high-k stack dielectric. This paper
describes the device performance of numerous TFET archi-
tectures like Double gate Tunnel FET, Single gate Tunnel
FET, Heterojunction Tunnel FET, and Tri-gate Tunnel FET
and compares all parameter values of various TFET designs.
Section II describes the detailed review of various Single
Gate TFET structures. Section III describes the various Dou- Fig. 1  Schematic view of L-Shaped TFET[6]
ble Gate TFETs structure and analyzes the best performance
among the various structures by comparing various param-
eters. Section IV examines the gate engineering, source
pocket, and dual or triple materials gate of Tri-Gate TFETs.
Section V deals with Heterojunction and its characteristics.

2 Single Gate Tunnel FET

Many research articles have recently been published that

favor Tunnel FETs over MOSFET because of low I­ ON Cur-
rent and better device performance. TFET uses the BTBT
mechanism to achieve the smallest subthreshold swing pos-
sible [6]. Single Gate Tunnel FET has attained a minimum
SS of 60 mv/dec at the 300 k normal temperature [7].
LG-TFET Zhaonian yang. et al. [6] presented an
L-shaped gate TFET. The author designed a U-shaped
channel and an L-shaped gate region to reduce the device
tunneling area. N + pocket is introduced in the gap between
the channel and intrinsic region to enhance TFET charac-
teristics. By overlaying the gate and n + pocket regions, the
author boosts the TFET ON-State current. TCAD simulators
are used to analyze the device’s performance. The L-shaped
Fig. 2  L-Shaped channel TFET cross-sectional view[8]
TFET is shown schematically in Fig. 1. The author invents
silicon-based TFET using the parameters: the gate oxide
thickness of 2 nm, the thickness of n + pocket is 5 nm, the channel directions. An L-shaped N + pocket is introduced
gate’s work function is 4.17 eV, gate height is 40 nm, drain between gate and source oxide to allow Band-to-Band tun-
height is 10 nm, source height is 30 nm. L-shaped TFET neling, increasing the device's performance. The design and
has a doping concentration of n + drain (1 × ­1019 ­cm−3), p- simulation parameters and values for the device are Gate
substrate (1 × ­1017 ­cm−3), p + source (1 × ­1020 ­cm−3), and length 45 nm, Gate Oxide thickness 2 nm, Pocket thick-
n + pocket (1 × ­1019 ­cm−3). The device obtains an average ness 5 nm, Source Doping (1 × ­1020 ­cm−3), drain doping
subthreshold swing of 38.5 mv/dec at a 0.2 V threshold (1 × ­1018 ­cm−3), substrate doping(1 × ­1015 ­cm−3), and pocket
voltage. doping(1 × ­1019 ­cm−3). The cross-sectional view of the
LC-TFET Qianqiong wang. et al. [8] proposed a bur- L-Shaped channel TFET is depicted in Fig. 2, and the metal
ied oxide layer L-shaped channel TFET and simulated by gate work function is 4.45 eV. The results show that the
TCAD simulators. The tunneling junction was enhanced maximum range of drain current is attained a 2.59 × ­10−4A
by simulating the ion strike in both vertical and lateral at ­Vd = 05 V.

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Silicon (2023) 15:2385–2405 2387

AG-TFET Yi-Ruei-Jhan. et al. [9] presented an asymme- ETL-Tunnel FET Pei-yu-wang. et al. [11] presented
try Gate based Tunnel FET(AG-TFET) with all gates around an Epitaxial Tunnel Layer Tunnel FET for suppressing the
(GAA). The results show that the device attains a high ON cur- low electric field BTBT to boost the device performance,
rent (2.47 × 10-5A/µm) and a low OFF current (6.55 × 10-16A/ improving ­ION current and average subthreshold swing (SS).
µm) because the GAA nanowire structure screening length N channel ETL tunnel FET is designed with low bandgap
is half of the planar structure. The metal gate work function SiGe/Si hetero material to conquer electric field BTBT using
of AG-TFET is 4.72 eV, and the doping concentration of all band engineering. Figure 5 shows the design structure of
three regions of the source, drain, and channel is 1 × ­1020 ­cm−3, ETL TFET. The parameters used for the design are channel
1 × ­1019 ­cm−3, and 1 × ­1016 ­cm−3, respectively. TCAD simula- thickness, gate length, and high-k dielectric Effective Oxide
tion analysis obtains an excellent ION/IOFF ratio ­(1010) and Thickness (EOT), corresponding values of 20 nm, 50 nm,
minimum subthreshold swing (42 mv/dec). A schematic view and 1 nm, respectively. Both p + source and n + drain doping
of Asymmetry Gate-based Tunnel FETs is illustrated in Fig. 3. concentration has 1 × ­1020 ­cm−3. The Gate electrode work
CSC-TFET Sola woo. et al. [10] presented a trench gate-
based covered source channel Tunnel FET (CSC-TFET)
to enhance the tunneling area and increases the ON cur-
rent. The gate voltage controls band-to-band tunneling in
the CSC-TFET, which permits electrons to tunnel between
the channel and the source region. The author designs a
CSC-TFET structure with the following parameters: chan-
nel length of 30 nm, trench gate depth of 30 nm, silicon
thickness of 1.5 nm, the covered source length varies from
1 to 25 nm in the CSC-TFET, and gate oxide thickness
of 2 nm. The doping concentrations of the source region,
drain region, channel region, and silicon substrate are
1 × ­1020 ­cm−3 (p-type), 1 × ­1018 ­cm−3 (n-type), 1 × ­1015 ­cm−3
(p-type), and 1 × ­1015 ­cm−3 (p-type), respectively. The source
region, drain region, channel region, and silicon substrate
have doping concentrations of 1 × ­1020 ­cm−3, 1 × ­1018 ­cm−3,
1 × ­1015 ­cm−3, and 1 × ­1015 ­cm−3, respectively. The work
function of the metal gate is 4.0 eV. The result shows that
the CSC-TFET device achieves an ON/OFF current ratio
­1010 A/μm and improves ON current 1­ 0–5 A/µm at the 300 k
normal temperature. Figure 4 shows a schematic illustration
of the Covered source channel Tunnel FET. Fig. 4  Schematic View of CSC-TFET[10]

Fig. 3  Schematic view of AG-

TFET[9]

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Fig. 5  Design structure of ETL Tunnel FET[11]

Fig. 7  Schematic representation of HGD-TFET [7]

Fig. 6  Schematic structure of P channel ETL Tunnel FET[12]

function is 4 eV. Sentaurus–TCAD tool is used for structural

design analysis.
Fig. 8  Schematic diagram of TFET work function variation [13]
Bing-Yue Tsui et al. [12] developed a P channel with Ge
Epitaxial layer Tunnel FET structure by introducing gate-
to-source capacitance C ­ GS in p channel TFET. It implies device obtains a threshold voltage standard deviation of 1.4
that the BTBT process could develop minority carriers. The times larger than MOSFET and a subthreshold swing (SS)
author designed a structure with low bandgap material such standard deviation of 1.9 times larger than MOSFET. Fig-
as Ge and an epitaxial layer to enhance the ­ION current. The ure 8 depicts the schematic structure of the work function
Si layer and the buried oxide layer were 50 and 150 nm in variation of TFET. Figure 9 shows the drain current vs Gate
thickness. Figure 6 represents the schematic structure of p voltage characteristics of single gate TFET, and the figure
channel ETL TFET. indicates that the asymmetric Gate-based Single Gate TFET
HGD-TFET Woo-young Choi. et al. [7] introduced a (Yi-Ruei-Jhan. et al. 2013) structure yields a higher ON cur-
hetero-gate dielectric Tunnel FET. The major novelty of rent compared to other Single Gate TFET structures.
the design is replacing the source-side gate insulator with a
high-k dielectric material to boost the ON-Sate current and
conquer the ambipolar behavior. The gate length is 5 nm, the 3 Double Gate Tunnel Fet
silicon-on-insulator thickness is 30 nm, and the thickness of
the gate insulator is 2 nm, respectively. HG TFETs have an Si-based TFET has a low I­ ON Current, which induces ambi-
SS of 80% less and an ­Ion of two orders of magnitude higher polar behavior and increases the leakage current. Many
than SiO2-only TFETs. The schematic representation of an TFET structures were developed to overcome these limi-
HGD-TFET is shown in Fig. 7. tations based on low bandgap materials, high-k dielectric,
WFV-TFET A Tunnel Field Effect Transistor with Vari- and multiple gate TFET [14]. Many research papers have
able Work Function was proposed by Kyoung Min Choi recently been published comparing double-gate TFET to sin-
et al. [13]. The outcomes demonstrate that the work function gle-gate TFET for superior TFET performance [15, 16] and
variation of TFET is more efficient than MOSFET in terms improved ON-current [17, 18]. Due to the double gate in the
of subthreshold swing (SS) and threshold voltage ­(Vth). This TFET structure, it easily suppresses the ambipolar behavior

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Fig. 9  ID vs ­VGS Characteristics of Single Gate TFET

Fig. 10  Schematic view of DMGOSDG-TFET [21]

by increasing the tunneling area and attaining average sub-

threshold swing SS [17]. Realizing logic functions such as capacitance transfer characteristics, and transconductance
AND, OR, NAND, NOR, XOR, and XNOR are developed for DMGOSDG-TFET have been examined for comprehend-
using the double gate Tunnel FET [18–20]. ing the impact of various ITCs on the DC and Analog/per-
DMGOSDG-TFET Km. Sucheta Singh. et al. [21] formances. The device consists of a Dual gate oxide stack
developed a double gate Tunnel FET with a DMGOSDGT- of ­HfO2 and ­SiO2, three metal gates of the tunnel, a control,
FET-based bio-sensor. In DMGOSDG-TFET, a nanogap and an Auxillary gate. Three work functions Φ1 = 4.0 eV,
cavity is created between the gate dielectric region due to Φ2 = 4.6 eV, and Φ3 = 4.0 eV correspond to their metal gates.
the biomolecule sensing mechanism. To reduce gate chan- The results suggest that employing a high-k dielectric stack
nel length leakage and increase device channel interface gate-oxide material improves the reliability of DMGOSDG-
maintenance quality, this device is made using a gate oxide TFET performance. This device attains high I­ ON current
stack approach with asymmetrical doping in the p + and and low subthreshold swing compared to DMCG-TFET.
n + regions. This device is built utilizing a gate oxide stack Figure 11 depicts the dual material SOG double gate TFET
technique with asymmetrical doping to reduce gate channel schematic view.
length leakage and improve the quality of device channel GMEDG-TFET Gate metal engineered (GME) Ge
interface maintenance. The author created a DMGOSDG- source DG-TFET structure was developed by Jaya Madan.
TFET using the following parameters: Gate length (­ Lg) is et al. [23] to improve the device's reliability. Interface Trap
100 nm, cavity length ­(Lcavity) is 25 nm, cavity thickness Charges (ITC) are introduced in the dielectric semiconduc-
( ­tcavity) is 5.5 nm, ­SiO2 thickness ­(tSiO2) is 1.0 nm, Sili- tor and have an impact on device performance. The dop-
con thickness (­ tsi) is 10 nm. Tunnel gate WF (Φ1) = 4.0 eV, ing concentration of the proposed device has a p + source
control gate work function (Φ2) = 4.6 eV, and auxiliary ­(1020/cm3) and n + Drain (5 × ­1018/cm3). Gate metal engi-
gate work function (Φ3) = 4.0 eV are the work functions for neered DG-TFET introduced two different gate metals in
the three gate regions. Figure 10 represents the Schematic the gate region. The work function for the two metal gates
view of DMGOS-DG-TFET. The doping concentration has Φm1(4.1 eV) and Φm2(4.3 eV). The parameters used to
for proposed DMGOSDG-TFET design as source region design this structure has channel length ­(Lchannel) = 50 nm,
(1 × ­1020 ­cm−3), drain region (1 × ­1018 ­cm−3) and channel channel width = 10 nm, and doping density = ­1015/cm3.
region (1 × ­1017 ­cm−3). The author claimed that he could This design achieved a significant I­ ON current at 1 × ­10–5
achieve a least Subthreshold Swing (SS) of 11.05 mv/dec- A/µm for the least subthreshold swing of 30 mv/decade
ade, improve ­ION current ( 7.98 × ­10–6 A/µm) and reduce ­IOFF and attained a low I­ OFF current of 1 × ­10–11 A/µm using the
current is 2.1 × ­10–7 A/µm. TCAD simulator. Figure 12 shows the 3D schematic view
Satyendra Kumar et al. [22] proposed a dual material of GME-DG-TFET.
GOS double gate TFET and explored the impact of inter- DG-HJTFET SiO2/HfO2 stacked gate oxide (SGO)
face trap charges (ITC) by inserting localized charges structure in double gate heterojunction TFETs was developed
at the semiconductor interface. Electric field, parasitic by Sanjay Kumar. et al. [24]. The author utilizes the surface

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Fig. 11  Schematic representa-

tion of DM-SOG double gate
TFET [22]

Fig. 12  2D schematic view of GME-DG-TFET [23]

potential model to derive the BTBT generation rate and to

compute the drain current. The tangent line approximation
approach is used. A 2D schematic view of DG-HJTFET is
shown in Fig. 13. The doping concentration of DG-HJTFET
has source homo (1 × ­1020 ­cm−3), source hetero (5 × ­1019 ­cm−3),
channel (1 × ­1016 ­cm−3), and Drain (5 × ­1018 ­cm−3). Parameters
Fig. 13  2D schematic view of DG-HJTFET[24]
used for design have a channel length of 50 nm, an oxide layer
thickness of 1 nm, a high K gate thickness of 2 nm, and a work
function of gate region 4.2 eV. 4.0 eV, the auxiliary gate length of 18 nm, and the auxiliary
DMG-DG-TFET Vishwa et al. [14] invented the dual gate work function is 4.4 eV. Figure 14 represents the 2D
metal gate-double gate tunnel FET to enhance surface poten- analytical model of DMG-Double Gate Tunnel FET.
tial. The surface potential at both the source and drain junc- NTDGTFET Iman chahardah cherik. et al. [25] pre-
tions is used to compute tunneling width. This study involves sented the Si/Ge heterostructure nanotube-DG Tunnel FET.
band-to-band tunneling between the source and drains This device developed the two Germanium source regions
depletion regions. Doping concentration of three region covered by gate material to enhance the line tunneling. The
of DMG-DGTFET structure has p + source ­(1020 ­cm−3), system has two gate metal features. It involves control-
n + drain ­(1020 ­cm−3) and p-body 1­ 014 ­cm−3. Parameters ling the tunneling process on the source site. The source,
used to develop the design are t­ox of 2 nm, t­si of 10 nm, the drain, and channel doping concentration are 4 × ­1019 ­cm−3,
tunnel gate length of 12 nm, the tunnel gate work function is 3 × ­1018 ­cm−3, and 1 × ­1017 ­cm−3 respectively. Besides the

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Fig. 14  A 2D analytical model

of DMG-DGTFET [14]

Fig. 16  Schematic diagram of dual material gate heterodi-electric

TFET [26]

are investigated using dielectric materials' work function.

The performance of surface potential, energy-band pro-
Fig. 15  Schematic view of nanotube double gate TFET [25] file, and an electric field is analyzed using TCAD Simu-
lator. This design has two work functions for their cor-
responding dielectric materials, such as ­HfO2 and ­SiO2,
parameter value such as channel length (­ LC) = 20 nm, Effec- which are ­WF1 = 4.0 eV and ­WF2 = 4.4 eV, respectively.
tive Oxide Thickness (EOT) = 0.53 nm, source/Drain length Channel length = 50 nm, oxide thickness = 3 nm, channel
­(LSD) = 30 nm, channel thickness (­ TC) = 10 nm, Core Gate thickness = 10 nm, and charge density = + 1 × ­1016/m2 are
Radius ­(RCG) = 50 nm and Gate contact radius(RGC) = 5 nm the parameters used to design the proposed DMG-HD-
are used to design the NDGTFET. Figure 15 depicts the TFET structure. The drain-voltage characteristics result
schematic view representation of the nanotube Double Gate shows the I­ ON current attain ( 4.05 × ­1 0 –5 A/µm) at the
TFET. Calibrated simulators are used to analyze the device’s threshold voltage V ­ th = 0.38 V and achieve low I­ OFF cur-
performance. This device structure obtains a significant ­ION/ rent = 2.1 × ­10–12 A/µm. This design attains a good ­ION/
IOFF Current ratio (3.92 × ­107) with minimum subthreshold IOFF current (1.88 × ­107 A/µm) with a minimum subthresh-
swing (10 mv/dec) and achieves high ­ION (52.19µA/µm). old swing (SS) = 36.89 mv/decade. Figure 16 depicts the
DMG-HD-TFET Manoj Saxena et al. [26] examined Schematic view representation of dual material gate het-
a variety of DG-TFET configurations and defined the erodielectric TFET.
electrical characteristics of the Dual Material Gate Het- GME-SPDG-TFET Jayan Madan. et al. [27] proposed
erodi-electric (GMG-HD-TFET) to describe the dielec- a Gate Metal Engineered(GME) and source pocket(SP)
tric behavior. This result demonstrates how the proposed DG(Double Gate) TFET(GME-SPDG-TFET) for bet-
design's capacitive behavior and transient performance ter improvement of TFET ­ION current from ­1010 A/µm to

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­1012 A/µm. The result indicates a 27.71% threshold voltage

reduction. This system has two work functions, m1 = 4.1 eV
and m2 = 4.3 eV, for the tunneling and auxiliary gates,
respectively. ­N+ source pockets are introduced in the source
region with the doping concentration of 2 × ­1019 ­cm−3 and
their corresponding source pocket width of 4 nm. Besides,
parameter values such as Oxide layer thickness 2 nm, chan-
nel length 90 nm, the doping concentration of p­ + source (
1 × ­1020 ­cm−3), and n­ + drain (5 × ­1018 ­cm−3) are used in this
system. Significant ­ION/IOFF current ratio of 1 × ­1012 A/µm,
with a minimal subthreshold swing (SS) = 27.96 mv/decade,
this device achieves a good ION/IOFF current (1 × ­1012 A/
µm). Figure 17 shows the schematic representation of the Fig. 18  SSS-DG-TFET schematic design [15]
Gate Metal Engineered source pocket Double Gate TFET.
SSS-DG-TFET Mallikarjunarao. et al. [15] proposed detecting biomolecules. The Si-xGex source is buried over
the double gate symmetric spacer (SSS) Tunnel FET. This the Si channel to enhance the tunneling area, which is a
design structure improves better performance by using dif- massive breakthrough in this design. The work function for
ferent spacer materials. The novelty of the device structure different gate metals has Φm1 = 3.8 eV for gate over cavity
is to insert the optimal length of the 2 nm underlap region and Φm2 = 4.3 eV for ­HfO2 gate oxide. Silicon thickness
on both sides of the channels to increase the tunnel bar- of 18 nm, oxide thickness of 6 nm, nanogap cavity thick-
rier, which helps to reduce SCEs. Silicon dioxide acts as ness of 5 nm, cavity length of 20 nm, buried source Si-Ge
dielectric material and is inserted over a 0.9 nm channel length of 30 nm, and channel length of 40 nm are the param-
thickness. The Gate metal work function is 4.1 eV, the oxide eters used to design for the DMG-DMSDG-TFET. Source,
thickness is 0.9 nm, the channel length is 20 nm, the source drain, and channel doping concentration are 2 × ­1020 ­cm−3,
spacer length is 2 nm, and the drain spacer length is 2 nm. 1 × ­1020 ­cm−3 and 1 × ­1016 ­cm−3 respectively. 2D Silvaco
The doping concentration of the device: source has high ATLAS simulator is used in structural design development.
doped p + ­(1020 atoms/cm3), the channel has lightly doped The schematic structure of DMG-DMSDG-TFET is repre-
n-type(1017 atoms/cm3), and the Drain has moderately doped sented in Fig. 19. The drain current attains 2.6 × ­105, and
n-type(5 × ­1018 atoms/cm3). Figure 18 depicts the schematic ­ION/IOFF attains 4.96 × ­106 for the cavity length of 20 nm
structure of the symmetric spacer (SSS) Double Gate TFET. (10 nm source overlap). The Drain current and I­ON/IOFF
The results show better performance for the H ­ fO2 spacer response of 15 nm cavity length of 10 nm source overlap,
material compared to other spacer materials due to good 10 nm cavity length of source overlap, 5 nm cavity length
SCEs control. of 15 nm source overlap, and 10 nm cavity length of chan-
DMG-DMSDG-TFET The dual-gate material with nel overlap are 3.39 × ­102, 0.52 × ­101, 2.84 × ­105, 6.71 × ­104,
dielectric modulated symmetrical double gate TFET was 1.16 × ­102, 0.19 × ­101, 2.81 × ­102, and 1.46 × ­104 respec-
developed by aadil. et al. [28]. This device performs as a tively. The 20 nm cavity length has a high sensitivity of
biosensor, detecting biomolecules with minimum power drain current and ­ION/IOFF Current ratio.
consumption. The structure shows that a nanogap cav- LWLS-DG-TFET Satyendra Kumar et al. [16] present
ity is developed above the 1 nm gate oxide dielectric for a low work function live strip (LWLS) novel structure in
double gate Tunnel FET to improve the efficiency of device
performance. This structure's major novelty is implementing
a metal strip in the oxide layer at the source-channel contact.
LWSDG structure enhances the tunneling rate and achieves
an improved ­ION current. The results indicate the DC and
Analog/RF performance is analyzed and simulated by
using TCAD Simulator. A live metal strip length of 10 nm
and a thickness of 0.5 nm is inserted in the oxide layer at
source-channel contact. work function is divided into gate
work function, and the metal strip work function is listed
as Φg = 4.5 eV, and Φm = 4.75 eV respectively. The device
attains an ­ION current of 0.2 mA/µm at gate-to-source volt-
age ­VGS = 1.5 V. Figure 20 shows a cross-sectional view of
Fig. 17  GME-SPDG-TFET schematic structure[27] low work function lives strip Double Gate TFET.

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Fig. 19  Schematic structure of

DMG-DMSDG-TFET [28]

TMDG-TFET Sudipta Ghosh et al. [29] presented a

Graded channel Tri-Metal Double Gate TFET and developed
its analytical drain current model. The parabolic approxi-
mation approach is used to calculate Poisson's equation of
surface potential. The proposed model shows how a graded
channel can minimize leakage current in both the OFF and
ON states by acting as a potential barrier in the channel
area. Results indicate better performance of subthreshold
swing and ­ION and ­IOFF ratio by properly choosing gate
electrode work function. Dual gate oxide consists of three
work functions denoted as ΦM1 = 4.4 eV, ΦM2 = 5.08 ­eV, and
ΦM3 = 4.08eV respectively. Silicon thickness 5 nm, oxide
thickness 8 nm. Figure 21 shows the 2D representation
of Tri-metal Double Gate TFET. The device attains good
Fig. 20  A cross-sectional view of LWLSDG-TFET [16] ­ION = 0.1 mA at ­VGS = 0.5 V with a 40 mv/dec SS at 300 k
normal temperature.

Fig. 21  2D representation of

TMDG-TFET [29]

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Si-DG-TFET Zhijun Lyu et al. [30] proposed a silicon- Table 1 describes the different parameters of different
based(Si) Double Gate (DG) Tunnel Field-Effect Transis- structure architectures of double gate TFET. Si/Ge het-
tors and pseudo-2D Poisson equation that was examined erostructure Nanotube double gate TFET is more efficient
to develop the potential model. Drain tunneling current among the different Double Gate TFET structures. It attains
and modeling results are obtained from the TCAD simula- a higher ­ION current of 52.19 µA/µm and a low OFF current
tor. The author considers the source depletion region and of 1.33 × ­10–12 A/µm with the average subthreshold swing
channel inversion charges for the proposed model, which SS of 10 mv/decade. Figure 24 shows the drain current vs
is more reliable than ignoring the source depletion region. Gate voltage characteristics of Double Gate TFET. The fig-
The author describes the parameters used for the structure ure indicates that the Si/Ge heterostructure nanotube-DG
are: channel thickness t­si 20 nm, Gate length L ­ g 100 nm, Tunnel FET [25] structure yields a higher ON current than
and gate oxide thickness ­tox 2 nm. The doping concentration other Double Gate TFET structures.
of p + source highly doped(1020 ­cm−3), p- channel doped
­(1014 ­cm−3), and n + drain doped ­(1019 ­cm−3) respectively.
The gate electrode work function is configured as 4.2 eV. 4 Tri‑gate Tunnel FET
The cross-sectional depiction of Si-DG-TFET is shown in
Fig. 22. Tri-Gate TFET has a high ON-State current with better gate-
PE-DLTFET M.A.Raushan et al. [31] proposed a dop- to-channel electrostatic control than Double Gate TFET
ingless pocket engineering Double-Gate Tunnel FET (PE- [32]. A major hindrance in Si-TFET is low ON-State cur-
DLTFET). The author introduces three-pocket engineering, rent and high ambipolar current due to the band-to-band
namely, N-type pocket in the channel region, P-type pocket tunneling rate. Besides, Tri-gate TFET exhibits a high ­ION
in the source region, and N-type pocket in the drain region, current with average subthreshold swing SS and suppresses
to improve the device performance. The work function for the ambipolar behavior. Many researchers have recently pre-
three electrodes namely, source WF1 (5.93 eV), drain WF2 ferred Tri-Gate TFET over Double Gate TFET due to its
(4.4 eV), and gate electrode WF3 (4.5 eV) respectively. better efficiency.
The device parameters are a Gate length of 30 nm, a source GC-DMTG-SON-TFET Dinesh Kumar Dash et al. [33]
length of 20 nm, and a drain length of 20 nm. The gate and presented a Graded channel dual-material(DM) Tri-Gate
drain electrode oxide thickness is 3 nm, and the source elec- silicon on nothing (SON) Tunnel FET. The surface potential
trode oxide thickness is 0.37 nm. The doping concentration and electric field function were calculated using the appro-
is: N-type doped gate edge adjacent to the source pocket is priate boundary condition in 3D Poisson's equation. Using
4 × ­1019/cm3, P-type doped pocket 1 × ­1021/cm3 is placed at potential distribution drain current profile is calculated to
the source electrode edge, and N-type doped third pocket find the shortest tunneling path. The device structure con-
9 × ­1019/cm3 is placed to minimize ambipolarity in the chan- sists of two work functions of gate electrode Φm1 = 4.0Ev
nel close to the Drain at 5 nm from the edge of the gate and Φm2 = 4.4Ev, respectively, for the gate electrode. The
electrode. The suggested PE-DLTFET has a greater ION device doping concentration of two-channel length is
(2.4 × 10–5 A), a high ION/IOFF ratio of ­109, and a reduced ­Nch1 = ­1011 ­cm−3 and ­Nch2 = ­1013 ­cm−3, respectively. The
subthreshold slope (SS) of 42 mV/dec, as well as a higher parameters and their values used to design for GCDMTG-
ION/IOFF ratio of ­109. Figure 23 shows the schematic struc- SON-TFET such as channel thickness ­(tsi) are 10 nm, ­SiO2
ture of pocket engineering dopingless Double Gate TFET.

Fig. 22  Schematic representation of Silicon-based Double Gate(DG)- Fig. 23  Structure of pocket engineering dopingless Double Gate
TFET [30] TFET[31]

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Silicon (2023) 15:2385–2405 2395

Table 1  Comparison of various electrical parameters in Double Gate TFET

References Device architecture ION IOFF ION/IOFF Channel Length Vth Subthreshold
swing(SS)

[27] GME-SPDG-TFET 1 X ­10–4 A/µm 1 × ­10–17 A/µm 1 × ­1012 A/µm 90 nm 0.62Volts 27.96 mv/dec
[26] DMG-HD-TFET 4.05 × ­10–5 A/µm 2.1 × ­10–12 A/µm 1.88 × ­107 A/µm 50 nm 0.38Volts 36.89 mv/dec
[25] NTDG-TFET 52.19 µA/µm 1.33 × ­10–12 A/µm 3.92 × ­107 A/µm 20 nm 0.5 V 10 mv/dec
[21] DMGOSDG-TFET 7.98 × 10 −6 A/µm 2.1 × ­10–17 A/µm - 100 nm 1.0 V 11,05 mv/dec
[23] GME-DG-TFET 1 × ­10–5 A/µm 1 × ­10–12 A/µm 1 × ­107 A/µm 50 nm 0.8 V 28 mv/dec
[24] DG-HJTFET 1 × ­10–4 A/µm 1 × ­10–15 A/µm - 50 nm 0.5 V -
[14] DMG-DG-TFET 1 × ­10–11 A/µm 1 × ­10–19 A/µm - 30 nm 0.7 V -
[15] SSS-DG-TFET 1.35 µA 0.021 fA 6.0.4 × ­1010 20 nm 0.6 V 29.48 mv/dec
[28] DMG-DMSDG- 2.6 × ­105 A/µm - - 40 nm - -
TFET
[31] PE-DLTFET 2.4 X ­10−5A 1 × ­10–14 1 X ­109 30 nm - 42 mv/dec
[29] TMDG-TFET 0.1 mA - 1011 60 nm 0.5 V 40 mv/dec

Fig. 25  The schematic perspective of the 3D depiction of GC-

DMTG-SON-TFET[33]

Fig. 24  ID vs ­VGS Characteristics of Double Gate TFET metal is 4.1 eV, and the TCAD simulator is used to analyze
the performance. Figure 26 shows the Schematic represen-
tation of SHS-TG-SOI TFET. ION, IOFF, and subthreshold
layer thickness ­(t1) is 1 nm, and ­HfO2 layer thickness ­(t2) swing device characteristics are derived using the two dif-
is 2 nm, and the channel length is 40 nm. ALTAS device ferent Drain-to-Source voltages such as ­VDS = 0.35 V and
simulator is used to analyze the 3D analytical model of dual ­VDS = 1.1 V, respectively. Good ON-state current is attained
material(DM) Tri-Gate SON Tunnel FET. The schematic when ­VDS is 1.1 V.
perspective of the 3D depiction of GC-DMTG-SON-TFET TMTG-JL-TFET Monzurul Islam Dewan. et al. [35]
is shown in Fig. 25. proposed a triple material Tri-Gate Junction less Tunnel
SHS-TG-SOI TFET Rajeev Ranjan. et al. [34] proposed FET(TMTG-JL-TFET) with the contribution of quantum
the symmetric High-k spacer (SHS) TG SOI Tunnel FET tunneling. To elevate the better gate control, high-k H ­ fO2
to enhance the better performance in terms of subthreshold and a low-k spacer are used. The device has three work
swing (SS) and I­ OFF current. It indicates significant ON- functions corresponding to three gate electrodes, such as
current due to N-TFET source doping. Subthreshold swing 4.5 eV, 4.26 eV, and 4.2 eV, respectively. The source, Drain,
attains minimum values beneath 60mv/dec at 300 k room and channel regions have 1­ 020 ­cm−3 doping concentrations.
temperature. This design presented a low-k gate dielectric Parameter and their values used for design include chan-
and a High-k spacer to improve the I­ ON current. It utilized nel length 152 nm, gate length 50 nm, channel thickness
the two spacers with a dielectric constant of 22 on both sides 20 nm, oxide thickness 3 nm, and spacer gap 1 nm. Drain
of the source and drain region. The work function of gate current attains ­10−4A by varying ­VGS ranges from -1 V to

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2396 Silicon (2023) 15:2385–2405

Fig. 28  Schematic representa-

tion of Tri-Metal Gate Tunnel
FET[36]

Fig. 26  Schematic representation of SHS Trigate SOI TFET[34]

Fig. 27  2D schematic view of TMTG-JL-TFET with high-k H

­ fO2 and Fig. 29  3D schematic view of TMDG-Silicon On Nothing TFET [37]
low-k spacer [35]

proposed device performance, such as ON current, surface

3 V and keeping the ­VDS at a constant value of 0.4 V. Fig- potential, ambipolar conduction, and an electric field, is
ure 27 shows the 2D schematic view of TMTG-JL-TFET compared with the SMTG-TFET for better performance.
with high-k ­HfO2 and low-k spacer. Figure 29 shows the3D schematic view of TMDG-Silicon
TMG-TFET Eunah Ko.et.al [36] proposed a Triple metal On Nothing TFET The device structure is described as chan-
gate vertical TFET to suppress the ambipolar current and nel length is taken on X-axis for Lnm, the channel width
improve device performance by adjusting gate work function is taken on Y-axis and is denoted as W, and ­tsi is taken on
and gate length through the TCAD simulator. ­L1, ­L2, and Z-axis. A 3D ALTAS simulator is used to analyze the ana-
­L3 are the length of Metal Gate layers with corresponding lytical results.
values of 7 nm, 14 nm, and 7 nm. Work function of three Ti-TFET Hao Ye.et.al [32] presented a new-type TFET
gate electrode are WF1 (4.20 eV), WF2 (4.50 eV), and WF3 (Ti-TFET) with tri-input terminals. The major novelty of
(4.20 eV). The parameters and values of the device design the design is to develop the inventive T-shaped channel
are selected as equivalent oxide thickness(6 nm), chan- structure and this structure easily manipulates the capacity
nel region diameter (7 nm), and diameter of the nanowire among any two gates of all three gates. Leakage current,
(14 nm). This structure characteristic attains an average switching ratio of turn-on/turn-off current, and turn-on cur-
subthreshold swing (SS) = 43.5mv/dec at room temperature rent are optimized by properly selecting work function and
and ­ION current ­10–8 A/µm at the threshold voltage of 0/175 body thickness. This T-shape (Ti-TFET) structure can imple-
Volts. Figure 28 depicts the schematic view of the Tri-Metal ment the Majority-NOT logic function and reduces stack
Gate Tunnel FET. height and transistor number. Two horizontal channels and
DMTG-SON-TFET Priyanka Saha. et al. [37] proposed one vertical channel are developed in Ti-TFET using a spe-
a dual material(DM) Tri-gate(TG) Silicon On Nothing TFET cial T-channel structure, denoted as channel1, channel2, and
and ­SiO2/HfO2 chosen has a stacked gate oxide to enhance channel3. Gate1, Gate2, and Gate3 correspond to the three
the gate material. Kane’s tunneling method is used to find channels with dielectric S­ iO2/HfO2 stacked gate oxide. The
the drain current based on the derived electric field. The work function for the three-gate oxide range varies from

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Silicon (2023) 15:2385–2405 2397

corresponding work function W1, W2, and W3 are consid-

ered a value as 4 eV and 4. 8 eV.The parameter are used to
design novel SGTMTFET structure has gate oxide thickness
­tox = 2 nm, silicon thickness tsi = 50 nm, ­ND = 5 × ­1018 ­cm−3,
­NA = ­1020 ­cm−3, ­Nh = 3 × ­1017 ­cm−3, ­Nc = 4 × ­1016 ­cm−3. The
Silvaco TCAD simulator was used to investigate the results.
The device's ON-current (­ 10–4 A/µm) increases significantly
after the threshold voltage crosses 0.2 V, implying a bet-
ter ON/OFF current ratio (­ 109). Figure 31 shows the cross-
section view of the Surrounding gate Triple Material TFET.
TGETMG-TFET Komalavalli. et al. [39] proposed a
novel TFET structure of Tri-gate engineering(TGE) with
triple material gate(TMG) Tunnel FET (TGE-TMG-TFET).
The device ON current is improved by enhancing the gate
engineering across the channel region. Kane’s model is used
to evaluate drain current and to measure the tunneling rate.
The gate electrodes consist of three materials with three dif-
ferent works functions, and they are denoted as M1, M2,
M3, Φm1, Φm2, and Φm3, having corresponding gate lengths
Fig. 30  3D diagram of T-shaped Ti-TFET [32]
L1, L2, and L3, respectively. The channel length is taken as
X-axis, the device's width is taken as Y-axis, and the silicon
4.05 eV to 4.11 eV. Parameter used: Body thickness is 5 nm, substrate thickness is taken as Z-axis for designing a novel
the gate length is 30 nm, gate oxide thickness is 1 nm, the structure. The author uses the Silvanco TCAD simulator for
source length is 30 nm, and the drain length is 30 nm. SIL- a 3D analytical model of the novel TGE-TMG-TFET struc-
VACO TCAD simulators are used for 3D simulation analy- ture. The ION/IOFF ratio of 1­ 07 is achieved, with a low
sis of Ti-TFET. Figure 30 depicts the 3D diagram of the leakage ­IOFF state current (­ 10–12 A/mm) and a substantial
T-shaped Ti-TFET. increase in ON current (­ 10–5 A/mm). Figure 32 shows the
H-SGTMTFET Vanitha. et.al [38] presented a novel 3D Schematic view of TGETMG-TFET.
structure of the surrounding Gate(SG) Triple Material Tun- Table 2 describes the different parameter values for differ-
nel FET with halo doping (H-SGTMTFET) and derived ent structures of Tri-Gate TFET. Among the different struc-
the 2D analytical model of Poisson’s equation by using the tures of Tri-gate TFET, symmetric high-k spacer(SHS) Tri-
parabolic equation with proper boundary conditions. L1, gate (TG) SOI TFET is more efficient in terms of I­ ON-State
L2, and L3 are the halo length of the structure as 10 nm, current, ­IOFF-State current, improve ambipolar current, and
15 nm, and 20 nm, respectively. Tri-material gate has their attaining least subthreshold swing SS. Figure 33 shows the

Fig. 31  Surrounding gate Triple

Material TFET cross-section
view [38]

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2398 Silicon (2023) 15:2385–2405

Fig. 32  3D Schematic view of TGETMG-TFET [39]

Fig. 33  ID vs. ­VGS characteristics of Tri-gate TFET

drain current vs Gate voltage characteristics of Tri-Gate

TFET, and the figure indicates that the SHS Trigate SOI structure. The major novelty of this work is that the source
Tunnel FET [34] structure yields a higher ON current com- and channel regions are made up of low and medium band-
pared to other Tri-Gate TFET structures. gap materials InAs/Si, respectively to enhance the gate con-
trol of the tunneling process. The following parameters are
used for device simulation, gate tunneling length L ­ tunnel is
5 Heterojunction Tunnel Fet 25 nm, the gate-to-source length ­LGD is 50 nm, the gate
oxide thickness T ­ ox is 1 nm, and the InAs thickness T ­ InAs
The traditional Si-TFET has faced some issues like low ON- is 5 nm. ­NInAs = 1 × ­1015 ­cm−3, ­NSour = 5 × ­1019 ­cm−3, and
State current and ambipolar behavior due to the. ­NDrain = 1X ­1019 ­cm−3 are the doping concentrations in the
Drain and source region are made up of high bandgap channel region. The author claimed that by utilizing InAs/Si
materials and a BTBT rate. Various TFET designs like heterojunction TFETs, he obtained a minimum Subthreshold
Gate metal engineering and Heterojunction were developed Swing (SS) of 4.67 mv/decade. Effective tunneling area and
to conquer this problem. Heterojunction TFET is a suit- ­ION are achieved to meet the actual requirements of circuit
able candidate to overcome traditional TFET limits. III-IV design. The suggested InAs/Si heterojunction TFET achieves
low bandgap materials are used in the source and channel the highest I­ ON ­(10–6 A/µm) for V ­ GS < 0.15 V and low I­ OFF
region to form Heterojunction TFET. Heterojunction TFET ­(10−11A/µm) for V ­ GS = 0. 0.3 V supply voltage. Figure 34
improves the BTBT rate, which reduces the tunneling width shows the schematic view of InAs/Si Heterojunction TFET.
and enhances the drain current. Heterojunction TFET is InAs/GaSb Heterojunction TFET InAs/GaSb het-
widely used to increase the device performance like low erojunction face tunneling FETs were proposed by Zhijun
­ION current and high ­IOFF current, improve ­ION/IOFF ratio and Lyu et al. [41]. This device consists of implanted Drain for
achieve minimum subthreshold swing (SS). leakage reduction. Face tunneling is chosen for achieving
InAs/Si Heterojunction TFET Shizheng yang [40] a large tunneling current in InAs/GaSb HFTFET. Modi-
Proposed the InAs/Si heterojunction TFET for inverter fied local density approximation (MLDA) is used to ensure

Table 2  Comparison of various electrical parameters in Tri-Gate TFET Devices

Reference Device Architecture ION IOFF ION/IOFF Channel length Vth Subthreshold swing
–6 –12 6
[34] SHS Trigate SOI TFET 1.533 × ­10 A/µm 1.335 × ­10 A/µm 114.83 × ­10 20 nm 0.441 V 37.08 mv/dec
[33] GC-DMTG-TFET 4 × ­10–6 A/µm 1 × ­10–13 A/µm 4 × ­107 40 nm 0.5 V -
[35] TMTG-JL-TFET 1 × ­10–4 A/µm 8 × ­10−14A/µm - 152 nm 0.4 V 47mv/dec
[36] TMG-TFET 1 × ­10−8A/µm 1 × ­10−15A/µm 1 × ­107A/µm 28 nm 0.175 V 43.5 mv/dec
[38] H-SGTM-TFET 1 × ­10−4A/µm 1 × ­10−13A/µm 1 × ­109A/µm 90 nm 0.2 V -
[39] TGE-TMG-TFET 1 × ­10−5A/µm 1 × ­10−12A/µm 1 × ­107A/µm 60 nm 0.6 V -

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Silicon (2023) 15:2385–2405 2399

Fig. 34  Schematic view of

InAs/Si Heterojunction TFET
[40]

the accuracy of channel layer dimensions. Both InAs and

GaSb layer as separate tunnelling parameters, they are
­A(InAs) = 3 × ­1019 ­cm−3. ­S−1, ­B(InAs) = 2.6 × ­1016 V. ­cm−1,
­A(GaSb) = 2.7 × ­1020 ­cm−3. ­S−1, ­B(GaSb) = 1.2 × ­107 V. ­Cm−1.
Schooley Read Hall (SRH) and Fermi statistics are included
in this heterojunction face tunneling FET. InAs/GaSb HFT-
FET has the highest I­ ON ­(10–4) at the Drain to source voltage
of 0.3 v and Gate to source voltage of 1.0 V. Achieve ­IOFF
­(10–11) at Drain to source voltage = 0.3 V and Gate to source
voltage = 1.0 V. Figure 35 depicts the Schematic representa-
tion of InAs/GaSb HFTFET.
GaSb/Si Heterojunction Vertical Tunnel-FET
(V-TFET) Satyabrata et al. [42] presented the vertical tun-
Fig. 35  Schematic representation of InAs/GaSb HFTFET [41]
nel field-effect transistors with pockets and without pockets
for low-power applications. The author establishes GaSb
low bandgap material in the source region to strengthen the length ­LD = 20 nm for both VTFET-WNP and VTFET-WP,
carrier tunneling. The author developed the inverter and Gate work function(Φm) is 4.2 eV for both V-TFET-WP
ring oscillator application for the Vertical TFET. Doping and V-TFET-WNP, the thickness of gate oxide ­(tox) is 2 nm,
concentration of uniform donor N ­ D = 5 × ­1018 ­Cm−3. The thickness of channel ( ­tsi) is 10 nm.
proposed structure has achieved a significantly high I­ON NCV-Tunnel FET Yen-Kai Lin et al. [43] proposed
Current value at 1.89 × ­10–5 A/µm for vertical-TFET with- GaAsSb/InGaAs negative capacitance vertical(NCV)-Tunnel
out pocket and 2.068 × ­10–5 A/µm for vertical-TFET with FET. The results show that this device uses negative capac-
pocket. For V-TFETs without a pocket, the ­IOFF current is itance to enhance the vertical tunneling and Ferroelectric
2.75 × ­10–17 A/m, whereas, for V-TFETs with a pocket, it layer ( FE) to improve ­ION and Subthreshold Swing (SS).
is 2.76 × ­10–17 A/m. This design’s I­ ON/IOFF current ratio is The device parameters are Equivalent oxide thickness (EOT)
6.87 × ­1011 for V-TFET-WNP and 7.5 × ­1011 for V-TFET- is 0.65 nm, FE layer thickness (­ Tfe) is 3 nm, Gate-to-source
WP. V-TFET-WNP has an average subthreshold swing (SS) overlap length ­(LSON) is 20 nm, and tunnel layer thickness
of 43 mv/dec, while V-TFET-WP has an SS of 26 mv/Dec. ­(Tt) is 3 nm, channel length ­(LCH) is 20 nm. Doping concen-
Figure 36 shows the structure representation of VTFET- tration of three terminals are source ( 5 × ­1019 ­cm−3), drain
WNP and VTFET-WP. The author is presented different ( 1 × ­1018 ­cm−3) and channel ( 1 × ­1017 ­cm−3). For the NCV-
parameters in the proposed vertical-TFET, such as drain TFET analysis in TCAD simulations, the Landau FE model

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2400 Silicon (2023) 15:2385–2405

Fig. 36  Structure representation

of VTFET-WNP and VTFET-
WP [42]

SRAM satisfactorily illustrates the influence of t­ FE on noise

margin and read–write delay. This device has achieved high
­ION ­(10–3) for ­VDS = 0.4v and ­IOFF ( ­10–16) at ­VDS = 0.4v.
Figure 38 depicts the Schematic view of Negative capaci-
tance TFET.

(n-OS)/(p-IV) heterostructure TFET Kimihiko Kato

Fig. 37  Nominal NCVT-FET structure with vertical tunneling [43] [45] presents an (n-OS)/(p-IV) heterostructure to realize
both ­n− and p­ + channel TFET operations. In n-OS/p-IV
heterostructure TFET, bilayer devices of n-ZnSo/p-SiGe
has been combined with the nonlocal tunneling model in are fabricated on SiGe-on-insulator substrate for p-TFET
NCV-TFET. Figure 37 shows the structural representation operation. Top and back gate electrodes are used in both
of Nominal NCVT-FET with vertical tunneling. This verti- p-TFET and n-TFET Operations. Figure 39 shows the
cal tunneling exhibits low ­IOFF ( 10 pA/µm) and high ­ION ( schematic view of n-OS/p-IV heterostructure tunnel field
405 µA/µm). The excellent ­ION/IOFF current ratio ( 6 × ­105) effects transistors. In p-type Group-IV semiconductor
is obtained with an average subthreshold swing ( 13.8 mV/ (p-IV), MOS controls the band-to-band tunneling (BTBT)
dec) at ­VDD = 0.5 V. current. Electron affinity is 4.2 eV, the uniform impurity
concentration is 5 × ­1 0 18 ­c m −3, equivalent oxide thick-
Heterojunction Negative Capacitance Tunnel‑FET Sourav ness (EOT) is 100 nm, and the gate insulator is 4 nm, the
Guha et al. [44] proposed heterojunction negative capaci- derived parameters for the bilayer n-OS/ P-IV heterostruc-
tance Tunnel-FET. It obtained its accuracy by fixing the ture. It achieves steep ­ION/IOFF with a minimum subthresh-
polarization data with the L-K equation solution. Design old (SS) of 65.4 mv/decade.
NCTFET is used for the applications of digital logic circuits, DM-DDL-HTFET Amit Bhattacharyya et al. [46]
and it can be implemented in an inverter, 2:mux, 11-stage invented a dielectric material-dual side doping less het-
ring oscillator, and optimized full adder. In this device, low erojunction Tunnel field-effect transistors based on label-
bandgap materials SiGe-InGaAs materials are used in the ­p+ free biosensor architecture. The author has investigated
source region to improve the ON-Current and reduce OFF- the following parameters: gate-to-source spacer thick-
Current. Results show a significant improvement in the ­ION/ ness ­(Lgap,s), energy bandgap, and the mole fraction of
IOFF current ratio of ­1016 and an average subthreshold swing HJ material. In DM-DDL-HTFET, the variation in oxide
(SS) of 27 mv/decade over 9 decades. It also has reduced layer thickness(Tox) and source-side dielectric material
ambipolar conduction. At 0.4 VDD, an NCTFET-based 6-T enhance the threshold voltage up to 37.54% and 54% over

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Silicon (2023) 15:2385–2405 2401

Fig. 40  Structural design of DM-DLL-HTFET [46]

Fig. 38  Schematic view of Negative capacitance TFET [44]

Fig. 41  Schematic view of InAs/GaSb LTFET [47]

buried drain to segregate the source and drain in InAs/

GaSb LTFET. The line tunneling TFET results indicated
Fig. 39  n-OS/p-IV heterostructure tunnel field effects transistors [45] that the high ­I ON current is achieved and attains a low
subthreshold swing due to band-to-band tunneling. The
dual-material gate work function has WF1 = 4.9 eV, and
a single-side DL-SiTFET. Figure 40 shows the structural WF2 = 5.2 eV, respectively. The doping concentration of
design of DM-DLL-HTFET. The author has selected struc- the buried drain region is 1 × ­1019 ­cm−3, and the source
tural parameters of the proposed DM-DDL-HTFET such region is 1 × ­1019 ­cm−3. The buried drain region of InAs/
as cavity length ­(Lcavity) = 25 nm, gate region extent (­ Lgate), GaSb heterojunction line tunneling FET attained a 1­ 07 ­ION/
cavity thickness ­(Tcavity) = 10 nm, work function of the IOFF current ratio. Figure 41 shows the Schematic view of
metal gate (Φm) = 4.4 eV, ­Lsc = 20 nm, the extent of H ­ fO2 InAs/GaSb LTFET.
below gate = 25 nm, the extent of source/drain region ­(LS/ SPE-HJ-VTFET Satyabrata Jit. et al. [48] proposed a
LD) = 95 nm. Extent of gate/drain (­Lgap,D) = 15 nm and source-pocked engineering GaSb/Si Heterojunction verti-
extent of gate/source ­(Lgap,S) = 3 nm. A subthreshold slope cal TFETs with GO(gate oxide) stack. The novelty of the
of 49.4 mv/decade at ­VDS = 0.7 V and ­VGS = 1.2 V with design is to develop 8 T SRAM circuits using SPE-HJ-TFET
improved ON-current I­ ON is 80.6 µA/µm and an excellent with three gate-oxide stacked(GOS) engineers, namely,
ON/OFF current ratio is 2.92 × ­108. ­HfO2/Al2O3 laterally GOS, ­Al2O3/HfO2 vertically GOS,
InAs/GaSb LTFET Bin Lu et al. [47] presented a com- and ­Al2O3. The electrical performance parameters of three
bination of InAs/GaSb heterojunction and line tunneling different gate oxide stacked VTFET are analyzed using Sil-
mechanism to gain a low subthreshold swing (SS) and vaco TCAD, such as transfer characteristics, electric field,
high ON-state current in tunneling Field Effects Transis- surface potential, and drain characteristics. The doping
tors. The major novelty of the structure is introducing a concentration of the source, channel, drain, and pocket are

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2402 Silicon (2023) 15:2385–2405

­NA = 2 × ­1019 ­cm−3, ­NC = 5 × ­1016 ­cm−3, ­ND = 5 × ­1018 ­cm−3,

­NA = 7 × ­1018 ­cm−3 respectively. Homogeneous gate dielec-
tric HM-GD-VTFET, heterogeneous gate dielectric verti-
cally stacked TFET (HT-GD VTFET with VS), and het-
erogeneous gate dielectric laterally stacked TFET (HT-GD
VTFET with LS) are the three types of SPE GaSb/Si HJ-
TFET. In HM-GD-VTFET, it achieves better performance
in terms of ­ION = 2.068 × ­10−5A/µm, ­IOFF = 2.76 X ­10–11 A/
µm, ­ION/IOFF = 7.5 X ­1011A/µm, SS = 26 mv/dec, threshold
voltage ­Vth = 0.31 V, gate to drain capacitance ­Cgd = 7.15 X
­10–16 F/µm, and gate to source capacitance C ­ gs = 3,72 × ­10–17
F/µm. Figure 42 shows the Schematic view of SPE GaSb/
Si HJ-TFET.
Ge/GeSn HFET Christian Schulte-Braucks. et al. [49] Fig. 43  Cross-sectional view of Ge/GeSn pTFET [49]
proposed a Ge/GeSn low bandgap material heterojunc-
tion TFET. The device individually addresses the critical
process model such as high-k stack and p-i-n diode. The Equivalent oxide thickness and high-k stack gate accumula-
performance of GeSn p-type TFET with increased low tion capacitance are Cacc ~ 3µF/cm2, and EOT is 0.84 nm,
bandgap Sn content is investigated by a calibrated model. respectively. Figure 43 shows the cross-sectional view of Ge/
Low bandgap materials with low electrons and holes are GeSn pTFET. The calibrated model reduces the trap density
the massive results to enhance the Direct BTBT TFET. and projects toward the higher Sn content. GeSn pTFETs
structure achieves ­I60 = 0.4 μA/μm and attains subthreshold
swing-60 mV/decade for an operating voltage of 0.5 V. I­ 60 is
the ­ION current of GeSn p-TFETs Structure for 60 mv/decade
subthreshold swing(SS).
HDL-TFET Hu Lu. et al. [50] presented a hetero-
junction dopingless Tunnel FET with H ­ fO2/SiO2 hetero-
gate dielectric. The HDL-TFET source and drain region
are low bandgap materials such as In0.53Ga0.47As/
In0.52Al0.48As. N + pockets are formed in the HDLIT-
FET structure by adjusting the source-channel length
­L sc to boost the device performance. The HDL-TFET
structure suppressed the drain-induced barrier lowering
(DIBL) effects and ambipolar current, and its perfor-
mance was evaluated by using the TCAD software tool.
The cutoff frequency ­f T and maximum oscillation fre-
quency ­fmax of HDL-TFET are 13, and 4.73 GHz, respec-
tively, under low gate-drain biases. ON-State current of
HDL-TFET (~ ­10−5A/µm) with ­LSC = 4 nm is higher than
Si-DL-TFET (~ ­10–10 A/µm), and the subthreshold swing
of HDL-TFET achieves 36.6 mv/decade, that is lower
than Si-DL-TFET (89.2 mv/decade). This device, HDL-
TFET attains a low ON-state current of 1.67 × ­10–5 A/µm
and an OFF-State Current of 8.5 × ­10−14A/µm. Figure 44
depicts the Schematic view of Heterojunction Doping-
less TFET.
Table 3 describes the different parameter values for
various structures of Heterojunction TFET. Among the
different structures of Heterojunction TFET. It has been
concluded that InAs/Si heterojunction TFET is more effi-
cient in terms of ON-State current and OFF-State current,
improves ambipolar current, and attains average subthresh-
Fig. 42  Schematic view of SPE GaSb/Si HJ-TFET [48] old swing SS. Figure 45 shows the drain current vs Gate

13
Silicon (2023) 15:2385–2405 2403

Fig. 44  Schematic view of Heterojunction Dopingless TFET [50]

voltage characteristics of Heterojunction TFET. The figure

indicates that the InAs/GaSb Heterojunction Tunnel FET
[41] structure yields a higher ON current compared to other
Heterojunction TFET structures. Fig. 45  ID vs ­VGS characteristics of Heterojunction TFET

6 Conclusion
such as ­ION Current, ­IOFF Current, ­ION/IOFF Current ratio,
The exponential growth of the semiconductor industry has channel length, threshold voltage V ­ th, and subthreshold
been fueled by the quick and persistent development of the swing SS of the different TFET designs are analyzed and
MOS transistor over the last few decades. Due to the con- evaluated. Indium Arsenide and Gallium antimonide-based
sequent development of various channel substances, it can heterojunction TFET has provided better ­ION current and low
widen the transistor size to 3 nm. This paper is a survey ­IOFF current compared to others.
about the overview of the various architecture of TFET and The research survey shows how identifying optimal
compares the Double Gate TFET, Tri-Gate TFET, and Het- device configurations beneath Heterojunction TFETs can
erojunction TFET structure performance. The parameters improve drain current and reduce reverse leakage current.

Table 3  Comparison of various electrical parameters in Heterojunction TFET devices

References Structure Architecture ION IOFF ION/IOFF Channel length Vth Subthreshold Swing

[40] InAs/Si HTFET 1 × ­10–6 A/µm 1 × ­10–11 A/µm 1 × ­105 A/µm 50 nm 0.15 V 4.67 mv/dec
–4 –11
[41] InAs/GaSb HTFET 1 × ­10 A/µm 1 × ­10 A/µm 1 × ­107 A/µm 30 nm 0.4 V 20 mv/dec
[42] GaSb/Si Verti- 2.068 × ­10 A/µm 2.76 × ­10 A/µm 7.5 × ­1011A/µm
–5 –17
20 nm 0.31 V 26 mv/dec
cal HTFET
[43] NCVTFET 405 µA/µm 10 pA/µm 6 × ­105 A/µm 25 nm 0.5 V 13.8 mv/dec
[44] HNCTFET 1 × ­10–3 A/µm 1 × ­10–19 A/µm 1 × ­1016 A/µm 40 nm 0.5 V 27 mv/dec
[51] GaSb/AISb/InAs Verti- 150 µA/µm 10 pA/µm 15 × ­106 A/µm - 300 mv 22 mv/dec
cal HTFET
[46] DM-DDL-HTFET 80.6 µA/µm 2.76 × ­10–14 A/µm 2.92 × ­108 A/µm 20 nm 0.7 V 49.4 m/dec
[48] SPE-HJ-TFET 2.15 × ­10–5 A/µm 2.77 × ­10–17 A/µm 7.77 × ­1011 A/µm 25 nm 0.25 V 22 mv/dec
[50] HDL-TFET 1.67 × ­10–5 A/µm 8.5 × ­10–14 A/µm - 20 nm 0.3 V 36.6 mv/dec

13
2404 Silicon (2023) 15:2385–2405

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