ISSCC 2017 / SESSION 16 / GIGAHERTZ DATA CONVERTERS / 16.

16.1 A 13b 4GS/s Digitally Assisted Dynamic 3-Stage Figure 16.1.3a shows the topology of the IB. It consists on an NMOS source
Asynchronous Pipelined-SAR ADC follower with current feedback. The feedback loop maximizes the linearity of the
source follower by using the fact that any signal-dependent increase in current
drawn by A2 decreases the current flowing into the source of A3. This decrease
Bruno Vaz1, Adrian Lynam1, Bob Verbruggen1, Asma Laraba2, is then fed back through the current mirror A4-A7. A current ratio of 1:4 between
Conrado Mesadri1, Ali Boumaalif3, John Mcgrath3, Umanath Kamath1, A7 and A5 is used to optimize noise and speed. Parasitic capacitance in this loop
Ronnie De Le Torre1, Alvin Manlapat1, Daire Breathnach3, needs to be minimized to reduce the amount of AC current lost to charging
Christophe Erdmann1, Brendan Farley1 parasitic capacitors.

1
Xilinx, Dublin, Ireland Figure 16.1.3b shows the topology of the RA. While an open-loop integrator-type
2
Xilinx, San Jose, CA amplifier avoids the challenges associated with stability and settling, it does have
3
Xilinx, Cork, Ireland stringent linearity requirements. A folded-cascode OTA is used to minimize the
supply voltage. A linearized input differential pair [6] is selected because the first-
In recent years, the need for high performance RF sampling ADCs has driven stage quantizes only 5b and the residue is too large for the required linearity using
impressive developments of pipelined-SAR and pipelined ADCs, all supported by a simple differential pair. Switches are used to disable the RA when not in use.
time-interleaving [1-4]. All these designs use a closed loop MDAC amplifier in the Bias voltages are kept stable to allow fast start-up and a maximum of 350ps
first stage and digital calibration/equalization to alleviate finite gain, settling and integration time for both RAs. A switched-capacitor common mode feedback is
memory effects, but the closed-loop amplifier remains a scaling bottleneck. In used to set the output common mode. Figure 16.1.3c illustrates the integration
this work, a three-stage asynchronous pipelined-SAR with open-loop integrator- time generation used to calibrate the gain of the amplifier. It consists of two
based amplifiers is used to maximize the sampling frequency, resolution and current-starved inverters. Programmable capacitive loads are used to support 1ps
linearity. The solution is mostly supported by dynamic circuits and multiple steps.
calibration loops to reduce cost, power and noise, maximize process portability
and support production testability. The ADC is manufactured in 16nm CMOS. The total area including digital circuitry
and supply decoupling is 1.04mm2. Figure 16.1.7 presents the die micrograph.
Figure 16.1.1a illustrates the architecture of the ADC. The design is configurable Figure 16.1.4 shows INL and DNL within +/-1.5LSB and +/-0.3LSB respectively,
for dual-channel conversion (In0 and In2) at 2GS/s or single-channel conversion measured at 4GS/s in RF mode. Figure 16.1.4 also shows the capacitance and
(In1) at 4GS/s. This provides flexibility to support IQ and direct RF communication comparator calibration codes for thousands of samples demonstrating some of
architectures, respectively. Only two of four input buffers (IB) are enabled in each the self-test features of the design used for efficient production testing and debug.
configuration. Each 2GS/s ADC unit consists of four interleaved 500MS/s sub- Figure 16.1.5 (top-left) presents the output spectra with -1dBFS, 1.9GHz input
ADC slices and a sampling network composed of a front-end switch and four signal at 4GS/s in RF mode. SFDR and SNDR are 67.0dB and 57.3dB. The
channel switches used to interleave the four ADC slices without time-skew distortion is dominated by HD2/HD3 and all remaining spurs are lower than
calibration requirements. In IQ mode, only offset and gain mismatch calibration -80dBFS. Figure 16.1.5 (bottom) shows the SFDR and SNDR vs. input frequency
is required. In RF mode, the clock is divided by 2 and sent to each 2GS/s unit (left) and vs. sampling frequency (right). In RF mode, the peak SFDR and SNDR
ADC out of phase. In this case, an additional digitally controllable delay cell is are 76dB and 64dB respectively at 200MHz and 61dB and 55dB respectively at
used to minimize the sampling time-skew between 2GS/s units. Finally, each 2.3GHz input frequency. This level of performance is maintained up to 4.8GS/s.
500MS/s sub-ADC slice is supported by foreground (FG) and background (BG) Performance measurements for IQ mode are also illustrated for completeness.
calibration loops. Figure 16.1.5 (top-left) shows power dissipation vs. sampling frequency. The RF
ADC consumes 513mW at 4GS/s, including 282mW dissipated by the input
Figure 16.1.1b shows the topology of each sub-ADC. It uses three asynchronous buffers, 142mW consumed by the ADC cores and 89mW dissipated by the digital
5b SAR stages separated by two residue amplifiers (RA). For speed reasons, each calibration blocks.
stage uses a split-capacitor MDAC to maintain constant common mode and five
cascaded dynamic comparators. The use of two RAs reduces the noise/offset Figure 16.1.6 summarizes the relevant specs and compares this ADC to several
requirements of the back-end comparators. This allows aggressive optimization recently published ADCs. This work shows the best peak SNDR. At Nyquist, this
of comparator decision time and use of a single comparator design across the ADC achieves a Walden FOM of 214.2fJ/conv-step and a Schreier FOM of 153.2dB
pipeline chain. A single RA design is used to reduce design/verification effort, which compares well to existing designs and clearly shows that the chosen
with only a minor penalty to power consumption. The gain of the integrating RA architecture is a viable alternative to conventional closed loop pipeline solutions.
is adjusted by appropriately sizing its load capacitance. The FG calibration corrects
comparator offsets, RA offset and gain and capacitor mismatch. The BG References:
calibration adjusts the RA gain and comparator offset drift due to temperature [1] J. Wu, et al., “A 4GS/s 13b Pipelined ADC with Capacitor and Amplifier Sharing
and voltage variations during operation. FG and BG calibrations follow the in 16nm CMOS,” ISSCC, pp. 466-467, Feb. 2016.
approach used in [5]. [2] M. Straayer, et al., “A 4GS/s Time-Interleaved RF ADC in 65nm CMOS with
4GHz Input Bandwidth,” ISSCC, pp. 464-465, Feb. 2016.
Figure 16.1.2a details the clock interface of the pipelined-SAR ADC. The [3] A. Ali, et al., “A 14-bit 2.5GS/s and 5GS/s RF Sampling ADC with Background
integration time of the RAs varies considerably across PVT, and leakage limits Calibration and Dither,” IEEE Symp. VLSI Circuits, pp. 206-207, June 2016.
the achievable performance of the ADC at low sampling frequencies if using a [4] M. Brandolini, et al., “A 5GS/s 150mW 10b SHA-Less Pipelined/SAR Hybrid
synchronous clocking scheme. So, an asynchronous clocking scheme is selected ADC in 28nm CMOS,” ISSCC, pp. 468-469, Feb. 2015.
to maintain best performance across the sampling frequency range. By using [5] B. Verbruggen, et al., “A 2.1mW 11b 410MS/s Dynamic Pipelined SAR ADC
integrating RAs, it is necessary to completely reset the sampling capacitors of with Background Calibration in 28nm Digital CMOS,” IEEE Symp. VLSI Circuits,
stage 2 and stage 3 before connecting them to the preceding RA. A modular pp. 268-269, June 2013.
handshaking scheme is used to guarantee that the RA waits for the next stage to [6] A. Demosthenous, et al., “Low-Voltage MOS Linear Transconductor/Squarer
be ready before starting integration. The block diagram is shown in Fig. 16.1.2b and Four-Quadrant Multiplier for Analog VLSI,” IEEE TCAS-I, vol. 52, no. 9, pp.
and the sequence of events in Fig. 16.1.2c. This functionality is used by all stages. 1721-1731, Sept. 2005.

276 • 2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 ©2017 IEEE
 ISSCC 2017 / February 7, 2017 / 1:30 PM

Figure 16.1.1: Block diagrams: (a) time-interleaved ADC; (b) three-stage Figure 16.1.2: (a) Clock interface (b) Inter-stage block diagram (c) Inter-stage
asynchronous pipelined-SAR. timing diagram.

16

Figure 16.1.3: (a) Input buffer (b) residue amplifier (c) integration time
calibration. Figure 16.1.4: INL/DNL performance and calibration code histograms.

Figure 16.1.5: Measured dynamic performance and power dissipation. Figure 16.1.6: Performance summary and comparison to prior works.

DIGEST OF TECHNICAL PAPERS • 277

Figure 16.1.7: Die micrograph.

• 2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 ©2017 IEEE