CD74HC86, CD54HC86

SCHS137E – AUGUST 1997 – REVISED JUNE 2021

CDx4HC86 Quadruple 2-Input XOR Gates

1 Features 3 Description
• Buffered inputs This device contains four independent 2-input XOR
• Wide operating voltage range: 2 V to 6 V gates. Each gate performs the Boolean function
• Wide operating temperature range: Y = A ⊕ B in positive logic.
-55°C to +125°C
Device Information(1)
• Supports fanout up to 10 LSTTL loads
PART NUMBER PACKAGE BODY SIZE (NOM)
• Significant power reduction compared to LSTTL
logic ICs CD74HC86M SOIC (14) 8.70 mm × 3.90 mm
CD74HC86E PDIP (14) 19.30 mm × 6.40 mm
2 Applications CD54HC86F CDIP (14) 21.30 mm × 7.60 mm
• Detect phase differences in input signals
(1) For all available packages, see the orderable addendum at
• Create a selectable inverter / buffer
the end of the data sheet.

1 14
1A VCC
2 13
1B 4B
3 12
1Y 4A
4 11
2A 4Y
5 10
2B 3B
6 9
2Y 3A
7 8
GND 3Y

Functional pinout

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.2 Functional Block Diagram........................................... 8
2 Applications..................................................................... 1 8.3 Feature Description.....................................................8
3 Description.......................................................................1 8.4 Device Functional Modes............................................9
4 Revision History.............................................................. 2 9 Application and Implementation.................................. 10
5 Pin Configuration and Functions...................................3 9.1 Application Information............................................. 10
Pin Functions.................................................................... 3 9.2 Typical Application.................................................... 10
6 Specifications.................................................................. 4 10 Power Supply Recommendations..............................12
6.1 Absolute Maximum Ratings........................................ 4 11 Layout........................................................................... 13
6.2 ESD Ratings............................................................... 4 11.1 Layout Guidelines................................................... 13
6.3 Recommended Operating Conditions.........................4 11.2 Layout Example...................................................... 13
6.4 Thermal Information....................................................5 12 Device and Documentation Support..........................14
6.5 Electrical Characteristics.............................................5 12.1 Documentation Support.......................................... 14
6.6 Switching Characteristics............................................5 12.2 Support Resources................................................. 14
6.7 Operating Characteristics........................................... 6 12.3 Trademarks............................................................. 14
6.8 Typical Characteristics................................................ 6 12.4 Electrostatic Discharge Caution..............................14
7 Parameter Measurement Information............................ 7 12.5 Glossary..................................................................14
8 Detailed Description........................................................8 13 Mechanical, Packaging, and Orderable
8.1 Overview..................................................................... 8 Information.................................................................... 14

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (September 2003) to Revision E (June 2021) Page
• Updated to new data sheet standards................................................................................................................ 1
• Moved the HCT devices to a standalone data sheet (SCHS410) ......................................................................1
• RθJA increased for the D package from 86 to 133.6 ℃/W and decreased for the N package from 80 to 62.5
℃/W.................................................................................................................................................................... 5

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5 Pin Configuration and Functions

1A 1 14 VCC
1B 2 13 4B
1Y 3 12 4A
2A 4 11 4Y
2B 5 10 3B
2Y 6 9 3A
GND 7 8 3Y

D, N, or J Package
14-Pin SOIC, PDIP, or CDIP
Top View

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
1A 1 Input Channel 1, Input A
1B 2 Input Channel 1, Input B
1Y 3 Output Channel 1, Output Y
2A 4 Input Channel 2, Input A
2B 5 Input Channel 2, Input B
2Y 6 Output Channel 2, Output Y
GND 7 — Ground
3Y 8 Output Channel 3, Output Y
3A 9 Input Channel 3, Input A
3B 10 Input Channel 3, Input B
4Y 11 Output Channel 4, Output Y
4A 12 Input Channel 4, Input A
4B 13 Input Channel 4, Input B
VCC 14 — Positive Supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
VI < –0.5 V or VI > VCC +
IIK Input clamp current(2) ±20 mA
0.5 V
VO < –0.5 V or VO > VCC +
IOK Output clamp current(2) ±20 mA
0.5 V
VO > –0.5 V or VO < VCC +
IO Continuous output current ±25 mA
0.5 V
Continuous current through VCC or GND ±50 mA
TJ Junction temperature(3) 150 °C
Lead temperature (soldering 10s) SOIC - lead tips only 300 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/
±1000
JEDEC JS-001(1)
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC
±1000
specification JESD22-C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 V
VCC = 6 V 4.2
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 V
VCC = 6 V 1.8
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
VCC = 2 V 1000
tt Input transition time VCC = 4.5 V 500 ns
VCC = 6 V 400
TA Operating free-air temperature –55 125 °C

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6.4 Thermal Information

CD74HC86
THERMAL METRIC(1) N (PDIP) (D SOIC) UNIT
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 62.5 133.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 50.3 89.0 °C/W
RθJB Junction-to-board thermal resistance 42.3 89.5 °C/W
ΨJT Junction-to-top characterization parameter 29.9 45.5 °C/W
ΨJB Junction-to-board characterization parameter 42.0 89.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2V 1.9 1.9 1.9
IOH = –20
4.5 V 4.4 4.4 4.4
µA
6V 5.9 5.9 5.9
High-level VI = VIH or
VOH V
output voltage VIL IOH = –4
4.5 V 3.98 3.84 3.7
mA
IOH = –5.2
6V 5.48 5.34 5.2
mA
2V 0.1 0.1 0.1
IOL = 20
4.5 V 0.1 0.1 0.1
µA
Low-level output VI = VIH or 6V 0.1 0.1 0.1
VOL V
voltage VIL
IOL = 4 mA 4.5 V 0.26 0.33 0.4
IOL = 5.2
6V 0.26 0.33 0.4
mA
Input leakage
II VI = VCC or 0 6V ±0.1 ±1 ±1 µA
current
VI = VCC or
ICC Supply current IO = 0 6V 2 20 40 µA
0
Input
Ci 5V 10 10 10 pF
capacitance

6.6 Switching Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
TEST
PARAMETER FROM TO CONDITIO VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
NS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2V 120 150 180
A or B Y CL = 50 pF 4.5 V 24 30 36
tpd Propagation delay ns
6V 20 26 31
A or B Y CL = 15 pF 5V 9

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over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
TEST
PARAMETER FROM TO CONDITIO VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
NS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2V 75 95 110
tt Transition-time Y CL = 50 pF 4.5 V 15 19 22 ns
6V 13 16 19

6.7 Operating Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Power dissipation capacitance
Cpd No load 2 V to 6 V 22 pF
per gate

6.8 Typical Characteristics

TA = 25°C

7 0.3
2-V
6 4.5-V
0.25 6-V
VOH Output High Voltage (V)

VOL Output Low Voltage (V)

5
0.2
4
0.15
3
0.1
2

2-V 0.05
1 4.5-V
6-V
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
IOH Output High Current (mA) IOL Output Low Current (mA)
Figure 6-1. Typical output voltage in the high state Figure 6-2. Typical output voltage in the low state
(VOH) (VOL)

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7 Parameter Measurement Information

• Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
• The outputs are measured one at a time, with one input transition per measurement.

Test VCC
90% 90%
Point
Input
10% 10%
0V
From Output tr(1) tf(1)
Under Test
VOH
CL(1) 90% 90%
Output
10% 10%
VOL
A. CL= 50 pF and includes probe and jig capacitance. tr(1) tf(1)

Figure 7-1. Load Circuit A. tt is the greater of tr and tf.

Figure 7-2. Voltage Waveforms Transition Times
VCC
Input 50% 50%
0V
tPLH(1) tPHL(1)
VOH
Output 50% 50%
VOL
tPHL(1) tPLH(1)
VOH
Output 50% 50%
VOL
A. The maximum between tPLH and tPHL is used for tpd.
Figure 7-3. Voltage Waveforms Propagation Delays

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8 Detailed Description
8.1 Overview
This device contains four independent 2-input XOR gates. Each gate performs the Boolean function Y = A ⊕ B in
positive logic.
8.2 Functional Block Diagram

xA

xY

xB

8.3 Feature Description

8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device
may create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to
over-current. The electrical and thermal limits defined in the Section 6.1 must be followed at all times.
The CD74HC86 can drive a load with a total capacitance less than or equal to the maximum load listed in the
Section 6.6 connected to a high-impedance CMOS input while still meeting all of the datasheet specifications.
Larger capacitive loads can be applied, however it is not recommended to exceed the provided load value. If
larger capacitive loads are required, it is recommended to add a series resistor between the output and the
capacitor to limit output current to the values given in the Section 6.1.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground
in parallel with the input capacitance given in the Section 6.5. The worst case resistance is calculated with the
maximum input voltage, given in the Section 6.1, and the maximum input leakage current, given in the Section
6.5, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the Section
6.3 to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device
with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.

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8.3.3 Clamp Diode Structure

The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1.

CAUTION
Voltages beyond the values specified in the Section 6.1 table can cause damage to the device.
The recommended input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.

VCC
Device

+IIK +IOK

Input Logic Output

-IIK -IOK

GND

Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output

8.4 Device Functional Modes

Table 8-1. Function Table
INPUTS OUTPUT
A B Y
L L L
L H H
H L H
H H L

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

In this application, a 2-input XOR gate is used as a phase difference detector as shown in Figure 9-1. The
remaining three gates can be used for other applications in the system, or the inputs can be grounded and the
channels left unused.
The device is used to identify phase difference between a reference clock and another input clock. Whenever
the clock states are different, the XOR output will pulse HIGH until the clocks return to the same state. The
output is fed into a low-pass filter to obtain a DC representation of the phase difference.
9.2 Typical Application
Input Clock R
Output
Reference Clo ck
C

Figure 9-1. Typical application schematic

9.2.1 Design Requirements

9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Section 6.3. The supply voltage sets the
device's electrical characteristics as described in the Section 6.5.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
CD74HC86 plus the maximum supply current, ICC, listed in the Section 6.5. The logic device can only source
or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to exceed the
maximum total current through GND or VCC listed in the Section 6.1.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.

CAUTION
The maximum junction temperature, TJ(max) listed in the Section 6.1, is an additional limitation to
prevent damage to the device. Do not violate any values listed in the Section 6.1. These limits are
provided to prevent damage to the device.

9.2.1.2 Input Considerations

Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
CD74HC86, as specified in the Section 6.5, and the desired input transition rate. A 10-kΩ resistor value is often
used due to these factors.

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The CD74HC86 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge rates
can cause oscillations and damaging shoot-through current. The recommended rates are defined in the Section
6.3.
Refer to the Section 8.3 for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Section 6.5. Similarly, the ground voltage
is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as
specified by the VOL specification in the Section 6.5.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Section 8.3 for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Section 11.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the CD74HC86
to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Section 6.1 is not violated. Most CMOS inputs have a resistive load measured in
megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves

Reference
Clock

Input Clock

Out

Figure 9-2. Typical application timing diagram

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Section 6.3. Each VCC terminal should have a bypass capacitor to prevent power disturbance. A 0.1-μF
capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different
frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for best results, as shown in Figure 11-1.

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11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of
a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to
prevent them from floating. The logic level that must be applied to any particular unused input depends on the
function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic
function or is more convenient.
11.2 Layout Example
GND VCC

Recommend GND flood fill for

improved signal isolation, noise Bypass capacitor
reduction, and thermal dissipation placed close to the
0.1 F device

1A 1 14 VCC Unused
1B 2 13 4B inputs tied to
VCC
1Y 3 12 4A
Unused
2A 4 11 4Y output left
floating
2B 5 10 3B
2Y 6 9 3A
Avoid 90°
corners for GND 7 8 3Y
signal lines

Figure 11-1. Example layout for the CD74HC86

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12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• HCMOS Design Considerations
• CMOS Power Consumption and CPD Calculation
• Designing with Logic
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
part number (1) (2) (3) Ball material Peak reflow (6)
(4) (5)

CD54HC86F3A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8404601CA
CD54HC86F3A
CD74HC86E Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD74HC86E
CD74HC86M Obsolete Production SOIC (D) | 14 - - Call TI Call TI -55 to 125 HC86M
CD74HC86M96 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC86M
CD74HC86MT Obsolete Production SOIC (D) | 14 - - Call TI Call TI -55 to 125 HC86M

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without
limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available
for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the
finish value exceeds the maximum column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per
JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the
previous line and the two combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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OTHER QUALIFIED VERSIONS OF CD54HC86, CD74HC86 :

• Catalog : CD74HC86
• Military : CD54HC86

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC86M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

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TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC86M96 SOIC D 14 2500 367.0 367.0 38.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 29-Dec-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC86E N PDIP 14 25 506 13.97 11230 4.32
CD74HC86E N PDIP 14 25 506 13.97 11230 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

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 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

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 PACKAGE OUTLINE
D0014A SCALE 1.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID 0.1 C
AREA
12X 1.27
14
1

8.75 2X
8.55 7.62
NOTE 3

7
8
0.51
14X
4.0 0.31
B 1.75 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.13
SEE DETAIL A
0.25
GAGE PLANE

0.25
0 -8 1.27 0.10
0.40

DETAIL A
TYPICAL

4220718/A 09/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.

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 EXAMPLE BOARD LAYOUT
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(R0.05)
TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220718/A 09/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(5.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:8X

4220718/A 09/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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