SHRUTHI ACHUT
AafgyyyyyyyyyyyyA
Hyderabad, Telangana, India – 500049 [email protected]
Phone no. +919449551065
Professional Summary
2 years of experience as a Design Verification Engineer, in System Verilog and UVM, and demonstrated
ability in creating VIPs from the scratch.
Career Objective
My objective is to grow my way up the ladder in the industry as a Design Verification Engineer while
continuously contributing to the industry in terms of ideas, research, innovative solutions especially to
minimize the time duration of the DV cycle. Would like to get into the the R&D eventually.
Core Competency
● Proficient in System Verilog and UVM methodology
● Thorough understanding of functional coverage and code coverage
● Experienced in developing test plans and coverage plans
● Familiar with assertions and constraints
● Proven track record for driving verification strategy, writing Test Plan, developing/modifying
existing Test Bench.
● DV signoff using SV-UVM.
● Reuse of IP DV UVM components like agent, driver, monitor and score board
● Meeting with all structural and functional coverage goals.
● Collaborating with IP/Architecture and RTL teams to meet Verification goals.
● Have used simulation and Formal Verification Techniques.
● Thorough knowledge of standard protocols like Ethernet.
● Strong in digital design fundamentals.
● Excellent debugging and problem solving skill
SHRUTHI ACHUT
Industrial Experience AafgyyyyyyyyyyyyA
Cerium Systems, India 1+ Years Exp (2018 – 2019)
AISEMI private Limited, Hyderabad, India 1 Years Exp (2023–till date)
Design and Verification
Engineer – Aisemi Pvt Ltd,
Hyderabad
Aisemi Project-1. Ongoing
CNN IP FOR COMPUTER VISION - used for automobile products.
Tasks Handled in design and verification
o Understanding the specification and identifying the test scenarios
o RTL Debugging and report the test issues to designers
o Responsible for functional and code coverage closure
o Created UVM based verification environment for below tasks
o Familiar with assertions and constraint randomization
Systolic Array: Verified complete systolic array operation and clock cycle accuracy.
o Creating an input feature matrix and kernel matrix using the bf16 data type with
parameterized dimensions
o Elements are generated in parallelogram shape and sent to the rows and columns
of the systolic array
o Debugged bf16 arithmetic for incorrect computations
SRAM Adaptor: Verified the correctness of data storage and retrieve on SRAM Adaptor as per
systolic array.
o Dynamically storing the input feature matrix and kernel matrix in DRAM
o Writing the data to the required specific SRAM banks, Ensured the correctness of
data storage
o Verifying the SRAM adapter generated rows and columns data in the parallelogram
with clock accuracy
Instruction Fetch Unit (IFU):
o Initialization of Configured register
o Ensuring the data integrity of instruction fetch unit
Aisemi Project-2
COMCORES JESD204D IP
● Building the JESD204D IP , by reusing and enhancing the VIPs of JESD204B and JESD204C
IPs.
● Feature enhancement of JESD204 IP done to test the functioning of RS FEC Link layer.
● Performed sanity checks of the testbench .
Project Engineer - Verification
SHRUTHI ACHUT
Cerium Systems Project-1 AafgyyyyyyyyyyyyA
IFP-SEGMENTATION AND REASSEMBLY
● The project involves development of testbench and testcases to verify segmentation and
reassembly feature for an Ethernet and CBR traffic.
● Working with Architecture and Design teams to prepare and develop robust verification plan,
identifying what needs to be tested in the design, the basic design functionality, handling error
cases.
● Experience with developing test plan and test cases according to product definition documents,
and building a sophisticated directed random verification environment.
● Generating focused and random test cases, analyzing coverage and debugging failure cases.
● Test bench components and exposure to layered VIP component development using System
Verilog and UVM flows
● Coming up with the components of testbench like driver, monitor, scoreboard, writing testcases
and running regression, and debugging both the design and testbench.
Project-2.
COMCORES JESD204B and JESD204C IP
● Verifying various features using targeted/random/corner-case/coverage tests. Wrote testcases
to achieve the coverage goals and ran the regression tests for existing testbench architecture.
● Experience and understanding of Coverage driven verification techniques.
● Verification closure to ensure bug free design.
Tools & Languages
HDL/HVL : Verilog, System Verilog
Methodology : UVM
Functional Verification Tools : Synopsys VCS, Aldec Rivera Pro
Education
2022 PG in VLSI Chip design from IISC, Bangalore
2017 Advanced Diploma in ASIC Design -RTL Verification from RV-VLSI and
Embedded Systems design centre - Bangalore
2012- 2016 Telecommunications Engineering , Dayananda Sagar College of Engineering -
Bangalore
Graduated with FIRST CLASS, 65.49%, and Best Innovative Engineering Project Award
for the year 2016, Department of Telecommunications.
2010- 2012 Class 12 ISC, St Pauls English School,Bangalore
Graduated with Grade A, 86%
2010-2010 Class 10, ICSE,Kalpa School Hyderabad
Graduated with Distinction A in all subjects, with 91% aggregate.
Certifications
SHRUTHI ACHUT
PG Advanced certification in VLSI AafgyyyyyyyyyyyyA
Chip Design from IISC, Bangalore
Significant Achievements
IEEE Paper Publication, My Paper titled 'Replacing RF with VLC, in hand held mobile networks- Using Solar
powered Light Communication With Network Planning' was published in IEEE (ICCECS 2016), DOI:
10.1109/CEYS.2016.7889848.,
https://ieeexplore.ieee.org/document/7889848
