2V EdTech LLP | DTE (CO/AIML) (22320) | ALL Board Questions| V2V EDTECH LLP Online Coaching at an Affordable Price. OUR SERVICES: + Diploma in All Branches, All Subjects + Degree in All Branches, All Subjects + BSCIT/CS + Professional Courses @ +9193260 50669 €§ V2V EdTech LLP v2vedtech.com © v2vedtech 1 Fy-Diploma (URIA) [LIVE] (Sem 2) only at 4999/- BUY NOW Sy-Diploma (UMANG ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW, ‘Ty-Diploma (YUKTI ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW All Courses : CHECK NOW, YOUTUBE : SUBSCRIBE NOW. _ INSTA : FOLLOW NOW Download V2V APP on Playstore for more FREE STUDY MATERIAL Contact No : 9326050669 / 9326881428 © scanned wih onenScmnerDTE MSBTE PAPERS 2 MARKS QUESTIONS (WINTER-18 L.Write the radix of binary, octal, decimal and hexadecimal number system. Ans: Radix of: Binary - 2 Octal-8 Decimal - 10 Hexadecimal -16 2.Draw the circuit diagram for AND and OR gates using diodes. Ans: Diode AND gate : Diode OR gate : v 3. Write simple example of Boolean expression for SOP and POS. Ans: SOP form: Y=AB+BC+AC POS form: © scanned wih onenScmner(A+B) (B+ C)(A+O) 4. State the necessity of multiplexer. (write any two proper points) Ans: Necessity of Multiplexer: * It reduces the number of wires required to pass data from source to destination. © For minimizing the hardware circuit. * For simplifying logic design. © In most digital circuits, many signals or channels are to be transmitted, and then it becomes necessary to send the data on a single line simultaneously. # Reduces the cost as sending many signals separately is expensive and requires more wires to send. 5. Draw logic diagram of T flip-flop and give its truth table. Note: Diagram Using logic gates with proper connection also can be consider. s: \n: Logic Diagram: ‘Truth Table: be on © scanned wih onenScmnerInput Output Operation Performed Ta Ques 0 Qn No change 1 Qa Toggle 6. Define modulus of a counter. Write the numbers of flip flops required for Mod-6 counter. Ans: * Modulus of counter is defined as number of states/clock the counter countes. * The numbers of flip flops required for Mod-6 counter is 3. 7. State function of preset and clear in flip flop. Ans: © In the flip flop, when the power is switched on, the state of the circuit is uncertain i.e. may beQ=1orQ=0. * Hence, the function of preset is to set a flip flop ie Q=1 and the function of clear is to clear a flip flop i.e. Q= 0. om ‘Operation pe «~ ” @ T 7 0, (tae 7 Nowwal FIP ° ° 1 ° es e 1 1 Pree © scanned wih onenScmner(SUMMER-18) 1. List the binary, octal and hexadecimal numbers for decimal no. 0 to 15. Ans [DECIMAL | BINARY | OCTAL | _HEXADECIMAL | oO 0000 oO oO 1 0001 1 1 2 0010 2 2 a 0011 3 E] 4 0100 4 4 & 0101 5 5 6 0110 6 6 7 0111 7 x 8 1000 10 8 9 1001 11 9 10 1010 12 A ir ToT wm a 12 1100 14 c 13 1101 15 D 14 1110 16 E 15 1111 17 ¥ © scanned wih onenScmner2. Define fan-in and fan-out of a gate. Ans: Fan-in is a term that defines the maximum number of digital inputs that a single logic gate can accept. Most transistor-transistor logic (TTL) gates have one or two inputs, although some have more than two. A typical logic gate has a fan-in of 1 or 2. Fan-out is a term that defines the maximum number of digital inputs that the output of a single logic gate can feed. Most transistor-transistor logic (TTL) gates can feed up to 10 other digital gates. © scanned wih onenScmner3. State two specification of DAC. Ans: 1. Resolution: Resolution is defined as the ratio of change in analog output voltage resulting from a change of 1 LSB at the digital input VFS is defined as the full scale analog output voltage i.e. the analog output voltage when all the digital input with all digits 1. Resolution = VFS /(2n -1) 2. Accuracy: Accuracy indicates how close the analog output voltage is to its theoretical value. It indicates the deviation of actual output from the theoretical value. Accuracy depends on the accuracy of the resistors used in the ladder, and the precision of the reference voltage used. Accuracy is always specified in terms of percentage of the full scale output that means maximum output voltage 3. Linearity: The relation between the digital input and analog output should be linear. However practically it is not so due to the error in the values of resistors used for the resistive networks. 4. Temperature sensitivity: The analog output voltage of D to A converter should not change due to changes in temperature. But practically the output is a function of temperature. It is so because the resistance values and OPAMP parameters change with changes in temperature. 5. Settling time: The time required to settle the analog output within the final value, after the change in digital input is called as settling time. The settling time should be as short as possible. 6. Long term drift long term drift is mainly due to resistor and semiconductor aging and can affect all the characteristics. Characteristics mainly affected are linearity, speed etc. 7. Supply rejection Supply rejection indicates the ability of DAC to maintain scale, linearity and other important characteristics when the supply voltage is varied. Supply rejection is usually specified as percentage of full-scale change at or near full scale voltage at 250e 8. Speed: It is defined as the time needed to perform a conversion from digital to analog. It is also defined as the number of conversions that can be performed per second. © scanned wih onenScmner4. Compare between synchronous and asynchronous counter. (any two points) Ans: Synchronous Counter Asynchronous Counter All flip flops are triggered Different clock is applied to with same clock. different flip flops. It is faster. It is lower Design is complex. I Design is relatively easy. Decoding errors not present. Decoding errors present. Any required sequence can be designed Only fixed sequence can be designed. 5. Write the Gray code to given no.(1101)2 Ans: —————.0 EX-OR EX-OR 1 0 1 (1101), = (1011) Gray 2) Gray. 1 Binary Code 1 Gray Code 6. Define encoder, write the IC number of IC used as decimal I to BCD encoder. Ans: An encoder is a device or circuit that converts information from one format or code to. another, for the purpose of standardization, speed or compression. Decimal to BCD encoder IC- 74147. 7.Draw the logical symbol of EX-OR and EX-NOR gate. Ans: 8 © scanned wih onenScmnerEX-OR GATE:- © scanned wih onenScmner(WINTER-19 1, Convert (D8F) 16into binary and octal. 2. Draw symbol, Truth table and logic equation of Ex-OR gate. Ans: EK-OR gate ss v 3. bo bh “3 symbol i >y>- Logic Equation = AB+ABOR® G? © Truth Table: Tnputs | Output A [B |Y 0 fo jo 0 fi qi TY jo fa 1 | fo 10 © scanned wih onenScmner3, State the De Morgan’s Theorems. Ans: De Morgan’s 1st Theorem complement of sum is equal to product of their individual complements. AFB=A 0B De Morgan’s 2nd theorem Complement of product is equal to sum of their individual complements. u © scanned wih onenScmner4. Convert the following expression into standard SOP form. Y= AB+ AC + BC Ans: Y= AB+ AC +BC Total variable ABC 1* Product term = AB ( C is missing) 2™ Product term = AC (B is missing) 3" Product term = BC (A is missing) Y= ABel + AC el +BCe 1 Y= AB(C+C) AC(B+B) + BC(A+A) i a Le < =A Y= ABC+ ABC+ABC+ ABC +aBc+ Apc (+ AtA= A, Y= ABC + ABC + ABC + ABC Standard SOP Form 5. Draw symbol and write truth table of D and T Flip Flop. Ans: (Note: Symbol with other triggering method also can be consider) ¢ “ 2) D Flip Flop Tv FF HA yh smbel aap Gon (ERD le cloac FF | G,,, clo 5 eu Thath file (am) o Bave 6. Write down number of flip flops are required to count 16 clock pulses. Ans: No of states= no. of clock pulses = 16 12 © scanned wih onenScmner.0.0F flip flops requried m= no.of states Y= 16 4 flip flops are required to count 16 clock pulse. 7. List the types of DAC. Ans: 1) Binary weighted DAC. 2) R-2R ladder network DAC. (SUMMER-22) 1. Convert (1101011), = ( Jig and (IIM1011). = ( M Ans: a. First, convert 11010112 into decimal, by using above steps: = 11010112 = 1x 261 x 250 x 241 x 230 x 271 x 211 x 2° = 10710 Now, we have to convert 10710 to hexadecimal 107 / 16 = 6 with remainder 11 i.e. (B) 6 / 16 = 0 with remainder 6 Then just write down the remainders in the reverse order to get the answer, The binary number 1101011 converted to hexadecimal is therefore equal to : 6B b. First, convert 11110112 into decimal, by using above steps: 13 © scanned wih onenScmner= 11110112 = 1x 21 x 251 x 241 x 230 x 271 x 211 x 2° = 12310 Now, we have to convert 12310 to octal 123 / 8 = 15 with remainder 3 15/8 =1 with remainder 7 1/8 =O with remainder 1 Then just write down the remainders in the reverse order to get the answer, The binary number 1111011 converted to octal is therefore equal to : 173 2. List triggering methods used for triggering flip flops. Ans: a. Negative edge triggering b. Positive edge triggering. 14 © scanned wih onenScmner3. Define Minterm and Maxterm w.rt. K-map. Ans: We perform the Sum of minterm also known as Sum of products (SOP). # The minterm for each combination of the variables that produce a 1 in the function and then taking the OR of all those terms. We perform the Product of Maxterm also known as Product of sum (POS). ‘@ The maxterm for each combination of the variables that produce a 0 in the function and then taking the AND of all those terms. Out = ABC Out = ABC Minterm = ABC. Minterm = ABC Numeric =111 Numeric = 0 10 Out = ABC Out = ABC 4. Define shift register and list its types. Ans: Shift Register is a group of flip flops used to store multiple bits of data. The bits stored in such registers can be made to move within the registers and in/out of the registers by applying clock pulses. There are four types of shift register: a. Serial In Serial Out shift register (SISO) b. Serial In parallel Out shift register (SIPO) c. Parallel In Serial Out shift register (PISO) d. Parallel In parallel Out shift register (PIPO) 5. List any two specifications of IC-DAC 0808. 15 © scanned wih onenScmner+ Relative exactness at 20.19% highest error. + The range of voltage power supply will be +4.5V to £18VN. + Noninverting digital i/PS are compatible with CMOS & TTL. + The settling time is very fast 150 ns. + Highest power dissipation will be 1000 mW. 6. Draw logical circuit diagram of half adder circuit. Ans: SUM S = A+B CARRY C=A.B 7. Write truth table of D type flip-flop. Ans: 16 © scanned women Scanner© scanned wih onenScmner(WINTER-22) 1. Write radix of binary, octal, hexadecimal number system. Ans: decimal system has a radix of 10 octal system has a radix of 8 hexadecimal is radix 16 binary radix 2. 2. State necessity of demultiplexer. Ans: Demultiplexers are used in digital control systems to select one signal from a mutual stream of signals. Demultiplexers are also employed for data transmission in synchronous systems. Demultiplexers are also utilized in data acquisition systems. 3. Draw symbol and write the truth table for T-flipflop. Ans: SYMBOL TRUTH TABLE 4, Compare between synchronous and asynchronous counter. Ans: © scanned women ScannerGyaclaroaoas COREE 1 | Cuca Lagi cucaitis ample With increase in number ofstates, the logic cixcust becomes complicated Z| Connection | Outputorthe preceding | There ino connection pattem FF, sconnectedtoclocs | between output of ofthe next FF preceding PF and CLK of 3] Glock impat [All the FFs are not clocked | All FFrseceive clock ugmal =| Pespapation delay Simon Hrequencr of pasion PD =a= a whereas numberof PF and tdis bad Perr. Low because of the lone propagation delay. PD.=a"GaRF> tcbgate hat of asvachsonous igh due to shorter propagation delay. 5. Write Gray code to given number (11111)2 = (?)Gray. Ans: Binary Code : 11111 Gray Code : 10000 6. State two features of ADC ICO809. Ans: The ADC0809 offers high speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device ideally suited to applications from process and machine control to. consumer and automotive applications. 7. Draw four variable K-map. Ans: © scanned wih onenScmner© scanned witonen camerDTE MSBTE PAPERS 4 MARKS QUESTIONS (WINTER-18 1. Draw the block diagram of Programmable Logic Array. Ans: Diagram: - © scanned wih onenScmnerOR n Input Lines Programmable input or ™m Output Lines 22 © scanned wih onenScmnerConvert — (255)10= (2)6= (2)s (1S7)0= (2)ncv= (2) Escens Ans: (i) 2580 = (FF)6= 377)s (255)0 = (FF) 16)255 _ F (15) 18 OF (255)0 = (377)8 8|255 7 [st 7 3 (8 (ii) (157)10= (000101010111)aco= (010010001010) Fxcesss (157)10= (0001010101 11)aco a oe 0001 0101 0111 (000101010111)sco= (010010001010) rxcess 440494444 0001 0101 0111 + 0014 0011 0014 0100 1000 1010 3. Draw the symbol, truth table and logic expression of any one universal logic gate. Write reason why it is called universal gate. Ans: (Note: Any one universal gate has to be considered.) 23 © scanned wih onenScmnerUniversal Gates: NAND or NOR Symbol: > > }-0 1 iiiio} Logie expres lobo p =]=]°]2)>1 o/olo|=|<| * IJol=lelal Y=AB Y=(A+B) NAND and NOR gates are called as “Universal Gate” as it is possible to implement any Boolean expression using these gates. 4, Minimize the following expression using K-Map. f(A, B, C, D) = 3m (0, 1, 2, 4, 5, 7, 8, 9, 10) Ans: 24 © scanned wih onenScmner5. Compare TTL and CMOS logic families on the basis of following: (i) Propagation delay (ii) Power Dissipation (iii) Fan-out (iv) Basic gate ‘Ans: NOTE: - (Relevant points of comparison- 1 M for each point) 25 © scanned witonen camerParameter CMOS TTL Propagation delay 70-105 nsce/more than | 10 nsec/Less than TTL CMOS Power Dissipation Less 0.1 mW/Less than | More 10 mW/ More TTL than CMOS Fan-out 30/More than TTL 10/Less than CMOS Basic gate NAND/NOR | NAND 6. Describe the function of full Adder Circuit using its truth table, K-Map simplification and logic diagram. Ans: (Diagram- 1M, Truth table-1M, K-map- 1M, Logic diagram-1 M) A full adder is a combinational logic circuit that performs addition between three bits, the two input bits A and B, and carry C from the previous bit. Block diagram: ac— FULL Be apver Coo Truth Table: 26 © scanned wih onenScmnerInput Output A | 8 | Gin Sum Carry o | 0 0 ° 0 o | 0 1 7 ° o | a 0 I 0 o | 2 1 ° 1 i | 0 0 i 0 1 [0 1 ° 1 7] 2 ° ° 7 =] 4 7 i 7 Cy ABYA CyB Cie Sum = KBC,K0T,*ABT,,#ABC,, Logic Diagram: (Note: Logic Diagram using basic or universal gate also can be consider) . ASB Ola DH (AB + Ace +80) 7. Realize the basic logic gates, NOT, OR and AND gates using NOR gates only. 4M Ans: (NOT GATE USING NOR GATE:1 M) 27 © scanned wih onenScmner=A+B 8. Describe the working of JK flip-flop with its truth table and logic diagram. Ans: (Diagram-2 M, Working-1M, Truth table-1M) Truth Table: 28 © scanned wth onEW SconesTruth Table Jk ak] @Q oo 1 | Q,(no change) to ¢t {1 o1 t Jo 11 __t | @ (toggles) Diagram: oases on Toaing edo SRliptop 1 dock ageal i 1elipke ec \ 4 Flip-fop ee Ck Clk ke 0 +d a R smbol Circuit Working: The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”. Both the $ and the R inputs of the previous SR bistable have now been replaced by two inputs called the J and K inputs, respectively after its inventor Jack Kilby. Then this equates to: J = S and K = R. The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-input 29 © scanned wih onenScmnerNAND gates with the third input of each gate connected to the outputs at Q and Q. This cross coupling of the SR flip-flop allows the previously invalid condition of S = “1” and R= “1” state to be used to produce a “toggle action” as the two inputs are now interlocked. If the circuit is now “SET” the J input is inhibited by the “O” status of Q through the lower NAND gate. If the circuit is “RESET” the K input is inhibited by the “O” status of Q through the upper NAND gate. As Q and Q are always different, we can use them to control the input. When both inputs J and K are equal to logic “1”, the JK flip flop toggles 9. Draw and explain working of 4-bit serial Input parallel Output shift register. Ans: (Diagram:2M, Explaination:2M) Diagram = “bit Parallel Data Output eee Q Qs Qc Qo 4 4 4 a e_ =e Po oe} oo Sea | FFA FFB FFC FFD louk fou. LK leuk Clee Cock | J Explanation :- If logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the output of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the other outputs still remaining LOW at logic “0”. Assume now that the DATA input pin of FFA has returned LOW again to logic “0” giving us one data pulse or 0-1-0. The second clock pulse will change the output of FFA to logic “O” and the output of FF Band QB HIGH to logic “1” as its input D has the logic “1” level on it from QA. The logic “1” has now moved or been “shifted” one place along the register to the right as it is now at QA. When the third clock pulse arrives this logic “1” value moves to the output of FFC (QC) and so on until the arrival 30 © scanned wih onenScmnerof the fifth clock pulse which sets all the outputs QA to QD back again to logic level “0” because the input to FFA has remained constant at logic level “0”. The effect of each clock pulse is to shift the data contents of each stage one place to the right, and this is shown in the following table until the complete data value of 0-0-0-1 is stored in the register. This data value can now be read directly from the outputs of QA to QD. Then the data has been converted from a serial data input signal to a parallel data output. The truth table and following waveforms show the propagation of the logic “1” through the register from left to right as follows. Basic Data Movement nah A Shift «3 0 0 o |} o 0 1 1 o}o 0 0 1 0 0 3 0 0 1 0 4 0 0} 0 1 10. Draw 16:1 MUX tree using 4:1 MUX. 31 © scanned wih onenScmnerAns: Diagram: 11. Calculate analog output of 4-bit DAC for digital input 1101. Assume VES = SV. Ans: (Formula- 1M, Correct problem solving- 3M) Formula : VR = VFS V, = Vg ld 2°'+d,2°7+...+4, 27] © scanned wih onenScmner= S(1x2" + 1x2740x27+12 5(0.5+0.25+0+0.0625) = 4.0625 Volts Full Scale o/p mean bs b2 I bO= 1111 Vrs=3V S=Va-G4 i+ 24% Ve=533 For digital i/p b3 62 b1 bO = 1101 ) Vo=sasci+ t+ 24 Vo=433V 12. State De Morgan’s theorem and prove any one. Ans: (Each State and proof using table- 2M each) © scanned wih onenScmneri) AB=A+B" It states that compliment of product is equal to sum of their compliments 1 2 3 4 r} A B AB A B 4 oO oO 1 1 1 oO 1 1 1 oO 1 1 0 L 0 1 1 1 1 0 0 0 Column 03 = column 06 ie. AB= A+B Hence proved OR ii) GB- 4B It states that complement of sum is equal to product of their complements. 4 3 6 A B AB 1 1 1 i 0 o 0 1 0 0 0 0 2: AFB Hence proved. 13. Design one digit BCD Adder using IC 7483 Ans: (Diagram:4M) (Note: Labelled combinational circuit can be drawn using universal gate also) 34 © scanned wih onenScmnermap 0m binary adder tet Ss $2 81 Sp (SUMMER-19) 4, Convert: (il) (AD92.BCA)6= (2)10= (?)a= (?)2 Ans: (AD92.BCA)is = (10 x 16%) + (13 x 16%) + (9 x 16") + (2 x 16°) + (11 x 16") + (12 x 16°) + (10 x 16 = 40960 + 3328 + 144 + 2 + 0.6857 + 0.046875 + 0.00244 = (44434.7368),0 OR {AD92.BCA)ss =(1010 1101 1001 0010.1011 1100 1010), {AD92.BCA)ss = (1010 1101 1001 0010.1011 1100 1010): =(001 010 110 110 010 010.101 111 001 010), =(126622.5712)s Note: any other method can be considered. 2. Simplify the following and realize it 35 © scanned wih onenScmnerY=A+ABC + ABC+ ABC+ AB Y=A+ ABC + ABC+ ABC+ AB Y=A+RECPABT +H Be +Fe) - ACI+ 6c) 4 RECHT) HAE = A+KB +486 = AtRE = @4+7)-(a+@) = (A+ B) A@——_. 5 ae . B 3. Explain the following characteristics w.rt. logic families: (i) Noise margin (ii) Power dissipation (iii) Figure of merit (iv) Speed of operation Ans: Noise margin: Noise margin indicates the amount to noise voltage circuit can tolerate at its input for both logic 1 and logic0. Power Dissipation: It is the amount of power dissipated in an IC. 36 © scanned wih onenScmnerFigure of Merit: It is defined as the product of propagation delay and power dissipated by the gate. Speed of Operation: Speed of a logic circuit is determined by the time between the application of input and change in the output of the circuit. 4, Draw logic diagram of half adder circuit Ans: a ] > sum Pn th soe © scanned wih onenScmner5. Draw the circuit of successive approximation type ADC and explain its working Ans: Offset voltage = 1/2 LSB = 0.5 Analog S_+ %w°— D/A Converter 41 —o MsB 3 Comparator [= eee is zg tr ise J 8 Yo Programmer 3 Clock The successive approximation A/D converter is as shown in fig. An analog voltage (Va) is constantly compared with voltage Vi, using a comparator, The output produced by comparator (Vo) is applied to an electronic Programmer. If Va=Vi, then Vo=0 & then no conversion is required. The programmer displays the value of Vi in the form of digital O/P. But if Va Vi, then the O/P is changed by the programmer. If Va> Vi, then value of Vi is increased by 50% of earlier value. But if Va< Vi, then value of Vi is decreased by 50% of earlier value. This new value is converted into analog form, by D/A converter so as to compare it with Va again. This procedure is repeated till we get Vé changed successively, this method is called as successive-appro i. As the value of Vi is ation A/D converter. 6. Describe the operation of R-S flip flop using NAND gates only. Ans: © scanned wih onenScmnerJTDescription/explanation- When clock = 0, the outputs of NAND gates 3 and 4 will be forced to be 1 irrespective of the values of S and R. That means R’= S’ = 1. Hence the outputs of basic SR/F/F i.e. Qn+1 and QF 1 will not change. Thus if clock = 0, then there is no change in the output of the clocked SR flip-flop. R=0, clock = 1: No change =0 then outputs of NAND gate 3 and 4 are forced to become 1 Hence R' and S' both will be equal to 1. Since R' and S' are the inputs of the basic S—R flip- flop using NAND gates. There will be no change in the state of outputs. Case Now S=0, R=0, clock = 1: Set and a positive going edge is applied to the clock Output of NAND 3 i.e. R’ = 0 and output of NAND 4 i.e. S’ = 1. Hence output of SR flip-flop is Qn+4 = 1 and Qn + This is the set condition. Case Ill: S =0, R= 1, clock = 1: Reset Now S=0, R=1 and a positive edge is applied to the clock input. Since S=0, output of NAND ~3 i.e. R’= 1. And as R’ = 1 and clock = 1 the output of NAND-4 ie. S’ = 0. Hence output of SR flip-flop is Qn+1 =O and Qn + 1-1. This is the reset condition. Case IV: $=1, R=1, clock = Undefined/ forbidden As S=1, R=1 and clock = , the outputs of NAND gates 3 and 4 both are Oe. S' = cLK INPUTS OUTPUTS REMARK s R Qnti Qn+1 0 x x Qn @n | Nochange 1 0 ° Qn @n | Nochange a 0 1 oO a Reset ai 2 0 0 set x 1 1 ? ? Forbidden © scanned wih onenScmner7. classification of memory and compare RAM and ROM (any four points) Ans: classification of memory: I enimany— Rom PROM PROM EEPROM SRAM MEMORY Comparison between RAM and ROM SECONDARY —HDD FDD —pvp Pendrive RAM RAM 11. Temporary Storage. Permanent Storage. 2 Store data in MBs. 2.Store data in GBs. 3. Volatile 3.Non-Volatile 4. Writing data is Faster. 4.Writing data is Slower. 8. State the applications of shift register. 41 © scanned wih onenScmnerAns: 1] Shift register is used as Parallel to serial converter, which converts the parallel data into serial data. It is utilized at the transmitter section after Analog to Digital Converter (ADC) block. 2] Shift register is used as Serial to parallel converter, which converts the serial data into parallel data. It is utilized at the receiver section before Digital to Analog Converter (DAC) block. 3] Shift register along with some additional gate(s) generate the sequence of zeros and ones. Hence, it is used as sequence generator. 4] Shift registers are also used as counters. There are two types of counters based on the type of output from right most D flip-flop is connected to the serial input. Those are Ring counter and Johnson Ring counter. 9, Subtract the given number using 2’s compliment method. (i) (11011) - (11100), (ii) (1010), - (101), Ans: i) Subtract (1101), — (11100),using 2's complement binary arithmetic. Solution: (11011): ~ (11100): Now, 2's complement of (11100).= 1’s complement of (11100),+1 1's complement of (11100)2 = (00011)2 42 © scanned wih onenScmner2's complement = 00011+1 = 00100 Therefore, 2.1011 There is no carry it indicates that results is negative and in 2's complement form i.e.(11111):. Therefore, for getting true value i.e.(+1) take 2’s complement of (11111) is. 1's complement +1 =00000+1 ‘Ans= (00001)2 ‘Ans: (11011); ~ (11100), = 2’s complement of (11111)2 = (-1)so ii) Subtract (1010)2 - (101)zusing 2’s complement binary arithmetic. 2's complement of (0101)2 = 1's complement of (0101)2 +1 1's complement of (0101)2 = (1010). 2's complement = 1010+1 = 1011 Therefore, 1010 21 wy There is carry ignore it, which indicates that results is positive i.e.(+5) = (0101), Ans: (1010)2 - (101)2 = (0101)2= (+5):0 © scanned wih onenScmner10. State De-Morgan’s theorem and prove any one. Ans: De Morgan’s 1st Theorem: It states that the compliment of sum is equal to the product of the compliment of individual variables. (A¥B)=4 Proof B (A*B) AB a |B AB o fo [1 [1 Jo a a o fa [a fo [a o o ao fo [a [a o ° a |; fo |o | o o De Morgan’s 2nd Theorem: It states that the compliment of product is equal to the sum of the compliments of individual variables. (4B)= A+B Proof _ |B [as (a8) |a+® a |e |4 o fo {a1 [a fo 1 1 o [a [1 fo fo 1 1 1 jo jo |1 fo 1 1 1 [1 fo jo [a ° ° 11, Compare between PLA and PAL. Ans: © scanned wih onenScmnerPLA PAL 1) Both AND and ORarrays are 2) OR array is fixed and AND array is, programmable programmable. 2) Costliest and complex than PAL 2) Cheaper and simpler 3) AND array can be programmed to 3) AND array can be programmed to get desired minterms. get desired minterm. “2)_Large number of functions can be 4) Provides the limited number of implemented. functions. 5) Provides more programming 5) Offers less flexibility, but more likely flexibility. used. 12. Reduce the following expression using K-map and implement it. F(A,B,C,D ) = M (1,3,5,7,8,10,14) Ans: Lao) Zn) FAB.CDHAD) AT) Kepepy © scanned wih onenScmnerCoM Mocouiuaal ed t | @ @ | Nochange + | 0 4 | RESET + | 4 0 | ser t |Q @ | Toggle The clock signal is applied to CLK input. IF CLK =0 than F/F is disabled and 0/P Q and Q do not change 46 © scanned women ScannerIf CLK= Land then the output Q and Q will not change their state. If J=0 and K= 1 then JK flip flop will reset and Q= 0 & Q =1 If J=1 and K=0 then output will be set and Q=1 & Q =( If J= K=1 then Q & Q outputs are inverted and FF will toggle Race Around condition: Race around condition occurs in J K Flip-flop only when J=K=1 and clock/enable is high (logic 1) as shown below- ap ie ihe Propagation Multiple times, toggling will take place. This is Face around conaition In JK Flip-flop when J=K=1 and when clock goes high, output should toggle (change to opposite state), but due to multiple feedback, output changes/toggles many times till the clock/enable is high. ‘Thus toggling takes place more than once, called as racing or race around condition. © scanned wih onenScmner(WINTER-19) 1. Perform the subtraction using 2’S Complement methods (52)10 — (65)10 Ans: CMe) Checoool) (o1reree), (ioce0et), tooooo1 ! net genetateel 25 fhe he ac of Rest ° t Cheon Cue, ] 2. Simplify the following Boolean Expression and Implement using logic gate. ABCD + ABCD + ABCD + ABCD Ans: © scones wn ore saneABeD + ABCO + At 3. Minimize the four variable logic function using K map. F(A,B,C,D) = ¥m(0,1,2,3,5,7,8,9,11,14) Ans: © scones wn ore sane4. Implement the following function using demultiplexer. f1 = Im(0,2,4,6) f2= 3m(1,3,5) Ans: =m (0,2, 4,6) + masks) Sem O13, 5) A Be (me) say 5. Realize the following logic expression using only NAND gates. (i)R (i) AND (ii)NoT Ans: 50 © scanned wih onenScmner(OR OR gate from NAND gates wweure — > Gi)AND 10 se sy ior oO = (ii)NOT 6. Draw binary to Gray converter and write its truth table. Ans: 51 © scanned wih onenScmner‘Truth Table for 4 bit Binary to Gray code converter Binary Input T Gray Ouiput BR B2 BI BO | G3 @ Gi a 0 0 0 o | 0 0 0 oO 0 0 0 a) 0 o 1 ° o 1 o 0 0 1 r 0 o i i 0 0 1 o 0 1 0 o o 1 1 0 o 1 o o oO 1 1 1 0 H 1 0 0. T 0 1 o 1 1 1 o 1 0 o 1 0 ° 0 1 1 0 0 1 0 0 H r 1 oO i r 0 1 o 1 1 1 1 r 0 1 1 1 1 o 0 r i 0 0 1 0 1 o r H o 1 r 0 r T 1 H H o T 0 o r 1 H i 1 1 0 0 0 K-MAP FOR G3: G3=B3 K-MAP FOR G2 o no G2 = B3B2 + B2B3 33 XOR B2 K-MAP FOR G1. © scanned women ScannerG0 = B1B0+B1B0 =B1 XOR BO Diagram for 4 bt Binary to Gray code converter: Inpue D> $1 3-—$*,, ey Ouiat _—_D—* (Note: Realization of output equation can be done Basic or U 7. Describe the working of JK flip flop with truth table and logic Diagram. Ans: Logic Diagram 53 © scanned wih onenScmneros CLK— kK —i_> r-Q Truth Table JK aki Q 0 0 ft | Q (nochange) ro t |i o71 t oO 1 1__t | Q (toggles) Working The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”. Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs called the J and K inputs, respectively after its inventor Jack Kilby. Then this equates to: J = S and K = R. The two 2-input AND gates of the gated SR bistable have now been replaced by two 3- input NAND gates with the third input of each gate connected to the outputs at Q and Q. This cross coupling of the SR flip-flop allows the previously invalid condition of S = “1” and R = “1” state to be used to produce a “toggle action” as the two inputs are now interlocked. If the circuit is now “SET” the J input is inhibited by the “O” status Of Q through the lower NAND gate. If the circuit is “RESET” the K input is inhibited by the “O” status of Q through 54 © scanned wih onenScmnerthe upper NAND gate. As Q and Q are always different, we can use them to control the input. When both inputs J and K are equal to logic “1”, the JK flip flop toggles. 8, Describe the working of 4 bit SISO (serial in serial out) shift register with diagram and waveform if input is 01101. Ans: Diagram:(use SR or JK or D type flip flop) omo mo Working: The DATA leaves the shift register one bit at a time in a serial pattern, hence the name Serial-in to Serial-Out Shift Register or SISO. The SISO shift register is one of the simplest of the four configurations as it has only three connections, the serial input (SI) which determines what enters the left-hand flip-flop, the serial output (SO) which is taken from the output of the right-hand flip-flop and the sequencing clock signal (Clk). The logic circuit diagram below shows a generalized serial in serial-out shift register, Output of FFA is Q4, FFB Q3, FFC Q2 and FFD is QI 55 © scanned women Scanner(Clock Data input a a 2 a Eide Waveform: (Input is 01101) © scanned wih onenScmner/2V EdTech LLP | DTE (CO/AIML) (22320) | ALL Board Questions| (SUMMER-22 2. Draw circuit diagram of BCD to seven segment decoder and write its truth table. Ans: 3. Draw the block diagram of programmable array logic. Ans: 57 Fy-Diploma (URIJA) [LIVE] (Sem 2) only at 4999/- BUY NOW. Sy-Diploma (UMANG ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW, Ty-Diploma (YUKTI ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW All Courses : CHECK NOW, YOUTUBE : SUBSCRIBE NOW. _ INSTA : FOLLOW NOW Download V2V APP on Playstore for more FREE STUDY MATERIAL Contact No : 9326050669 / 9326881428 - © scanned witonen camer/2V EdTech LLP | DTE (CO/AIML) (22320) | ALL Board Questions| 4, Minimize following expression using K-map. f(A,B,C,D) = £m (1,5,6,7,11,12,13,15) Ans: 5. Realize the following logic operation using only NOR gates: ‘AND, OR, NOT. Ans: 58 Fy-Diploma (URJA) [LIVE] (Sem 2) only at 4999/- BUY NOW Sy-Diploma (UMANG ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW ‘Ty-Diploma (YUKTI ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW. + CHECKNOW YOUTUBE : SUBSCRIBE NOW _ INSTA: FOLLOW NOW. more FREE STUDY MATERIAL © scanned witonen camer/2V EdTech LLP | DTE (CO/AIML) (22320) | ALL Board Questions| 6. Describe the operation of 4 bit serial in serial out shift register Ans: Working: The operation of a SISO shift register relies on two primary components: the flip-flops and the clock signal. 1. Flip-Flops: A flip-flop is a fundamental building block of sequential circuits. In the case of a SISO shift register, each flip-flop stores a single bit of data. The number of flip-flops determines the length or size of the shift register. 59 Fy-Diploma (URIJA) [LIVE] (Sem 2) only at 4999/- BUY NOW. Sy-Diploma (UMANG ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW, Ty-Diploma (YUKTI ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW All Courses : CHECK NOW, YOUTUBE : SUBSCRIBE NOW. _ INSTA : FOLLOW NOW Download V2V APP on Playstore for more FREE STUDY MATERIAL Contact No : 9326050669 / 9326881428 50> © scanned witonen camer2. Clock Signal: The clock signal synchronizes the movement of data through the shift register. With each clock pulse, the data shifts from one flip-flop to the next. The clock signal ensures that the data propagates in a controlled and synchronized manner. When the clock signal transitions from low to high (or high to low, depending on the specific implementation), the input data is sampled and stored in the first flip-flop. On subsequent clock pulses, the stored data moves through the chain of flip-flops. The output of the shift register is taken from the last flip-flop in the series. 60 © scanned wih onenScmner6 MARKS QUESTIONS (WINTER-18) 1. Subtract using 2's compliment method Step 1 - Obtain binary equivalent of (35) 108 (5)i0 & then take 2's compliment of (S)i0- ise. (35)10 = (10001 1)> (So = (01) 2s compliment of (5)i0 = (000101): 111010 > 1's compliment + 1 (111011): 2’s Compliment Step -2: ‘Now add (100011)z and (111011)2 100011 + 11011 1] o1lni0 > Carry is generated so answer is in positive form, so will discard the carry generated ‘Therefore final answer will be (011110): =(30)2 2. Design a 4-bit synchronous counter and draw its logic diagram. Ans: 61 © scanned wih onenScmnerFlip flop inputs Tx Ts T Te To ‘Next state o = o o oF o ‘Present state T © scanned women Scanner3. Describe the working of Successive Approximation ADC. Define Resolution and conversion time associate with ADC. Ans: 63 © scanned witonen camerCircuit Diagram: Votage ee rae Er = ie I] Output buffer register | When the start signal goes low the successive approximation register SAR is cleared and output voltage of DAC will be OV. When start goes high the conversion starts. After starts, during first clock pulse the control circuit set MSB bit so SAR output will be 1000 0000. This is connected as input to DAC so output of DAC is (analog output) compared with Vin input voltage. If Voac is more than Vin the comparator output —Viaut, if Voac is less than Vis, the comparator output is +Vem. If output of DAC i.e. Vac is + Vea (Le unknown analog inpu voltage Vin> Voac) then MSB bit is kept set, otherwise it is reset. Consider MSB is set so SAR will contain 1000 0000. it ic Do a digital output of 1100 0000. The The next clock pulse will set next ‘output voltage of DAC i.e Vnac is compared with Vin. if it is + Vauthe De bit is kept as it is, but if it is Voor the De bit reset The process of checking and taking decision to keep bit set or to reset is continued upto Do. Then the DAC input will be digital data equal to analog input. When the conversation if finished the control circuits sends out an end of conversion signal and data is locked in buffer register 64 © scanned women Scanner65 Resolution: The voltage input change necessary for a one bit change in the output is called resolution. Conversion Time: The conversion time is the time required for conversion from an analog input voltage to the stable digital output OR Cireuit Diagram: © scanned wih onenScmnerExplanation: DAC= Digital to Analog converter EOC= End of conversion SAR =Succesive approximation register S/H= Sample and hold circuit Vin= input voltage Vref= reference voltage The successive approximation Analog to Digital converter circuit typically consisting of four sub circuits- 1. A sample and hold circuit to acquire the input voltage Vin. 2. An analog voltage comparator that compares Vin to the output of internal DAC and outputs the result of comparison to successive approximation register(SAR). 3. SAR sub circuits designed to supply an approximate digital code of Vin to the internal DAC. 4. An internal reference DAC that supplies the comparator with an analog voltage equivalent of digital code output of SAR for comparison with Vin, The successive approximation register is initialized so that most significant bit (MSB) is equal to digital 1. This code is fed into DAC which the supplies the analog equivalent of this digital code Vref/2 into the comparator circuit for the comparison with sampled input voltage. If this analog voltage exceeds Vin the comparator causes the SAR to reset the bit, otherwise a bit is left as 1. Then the © scanned wih onenScmnernext bit is set to 1 and the same test is done continuing this binary search until every bit in the SAR has been tested. The resulting code is the digital approximation of the sampled input voltage and is finally output by DAC at end of the conversion (EOC). Resolution and conversion time associate with ADC- Resolution Itis the maximum number of digital output codes. Resolution= 2n (OR) It is defined as the ratio of change in the value of input analog voltage required to change the digital output by 1 LSB Ves Pat . Resolution = Conversion time: The time difference between two instants i.e. 'to' where SOC signal is given as input to the ADC and ‘tI’ where EOC signal we get as output from ADC. it should be small as possible. fp} rgrion __y a a as eee t soc E0c 4. Design 4 bit Binary to Gray code converter Ans: © scanned wih onenScmnerTruth Table for 4 bit Binary to Gray code converter Binary Input (Gray output BB [Bi | Be Gs @ 1G Ge ojo jo {0 oO 0 0 0 ojo [o 1 o 0 1 0 [0 i 0 0 0 1 1 o lo 1 1 o 0 1 0 ot oo oO 1 1 0 ot 0 1 0 1 1 1 ot 1 o 0 1 0 1 ot 1 1 oO 1 0 1 |o oo 1 1 o 1 [0 [o 1 1 1 fo 1 110 1 0 1 1 1 1 1 [0 1 1 1 1 1 0 1 oo 1 0 1 0 1 0 1 1 0 1 1 i 1 o a 0 0 1 i 1 1 1 0 0 K-MAP FOR G3: NSIBO 09 a 4 10 6362 oo} 0 o 0 o 1) 0 0 oO oO nf fa 1 1 1 wo | tt 1 1 1 G3-B3 © scanned wih onenScmner\8180 oo a " 10 e3e2 oo | 0 o a 0 or} fa 1 1 1 | oo 9 0 0 w/b 1 1 1 K-MAP FOR G2. 2-8 p2+ BI Bs K-MAP FOR G G2-B3 R2+ BIBS =R3 XOR RI K-MAP FOR GI \B180 00 on 4" 10 s3e2 oo | o ° 1 1 al + ° ° afi 1 a ° 1 | o o 1 7 © scanned wih onenScmnerBL XOR B2 K-MAP FOR Go. 8180 00 a 4 10 e382 oo | o 7 o 7 a fo 1 o 1 ufo 1 ° 1 1] o t o 1 um for 4 bit Binary to Gray code converter Gray oy Output TH Note: Realization of output equations can be done using Basic or Universal gates 5. Compare the following (Any three points) i) Volatile with Non-volatile memory ii) SRAM with DRAM memory 70 © scanned wih onenScmnerAns: is retained only as Parameter Volatile memory Non-Volatile memory definition Memory required Memory that will keep electrical power to keep_| storing its information information stored is | without the need of called volatile memory | electrical power is called nonvolatile memory. iassification ‘All RAMs ROMs, EPROM, magnetic memories Effect of power ‘Stored information No effect of power ‘on stored Jong as power is on. information applications For temporary For permanent storage storage of information 2. SRAM with DRAM memory Parameter SRAM DRAM ‘rcuit configuration | Each SRAM cell is Each cell is one a flip flop MOSFET & a capacitor Bits stored In the form of In the form of charges voltage No of components per | More Less cell Storage capacity Less More Refreshing It does not require It require refreshing, refreshing Cost tis expensive Tis cheaper Speed Teis faster Itis slower comparativel} 6. Give block schematic of decade counter IC 7490. Design Mod-7 counter using this IC. Ans: © scanned wih onenScmner1. block schematic of decade counter IC 7490- Reh peal | ; i t G, mgt Oy 5 A Outpet -—! oun Mod-7 means states are from 0,1,2,3,4,5,6.0 ‘Therefore we have to reset counter IC 7490. when Qo,Qc,Qn,Qx-0111 Design reset logic: Output of reset circuit should be HIGH because RO(1) and RO(2) are active high inputs. ‘Therefore reset logic output should be low for states 0 to 6. Output should be HIG! H for states 7 onwards. ‘Truth table & K-map: Ce a ¥ * le ° ° ° elo ° 1 ° =i 2 ° ° =" A 1 ° o[ ° ° ° 2 (5 ° 1 ° iE 1 ° ° 7 i 7 7 = 2 ~ = = inva State To 2 2 1 © scanned women ScannerExpression for Y: Y= Oe Q8 Os Oo (SUMMER-19 1. Design BCD to seven segment decoder using IC 7447 with its truth table. Ans: 23 © scanned wih onenScmnerNote: Any one type of display shall be considered 1. BCD to 7 segment decoder is a combinational circuit that accepts 4 bit BCD input and generates appropriate 7 segment output. 2. In order to produce the required numbers from 0 to 9 on the display the correct combination of LED segments need to be illuminated. 3. Astandard 7 segment LED display generally has 8 input connections, one from each LED segment & one that acts as a common terminal or connection for all the internal segments 4. Therefore there are 2 types of display 1. Common Anode Display 2. Common Cathode Display ‘Common Anode Display Truth Table al ven segment clecoder Ay rommon onods isp eco pots Get 7. rin ¢ t =e 6 ¢ ¢ c i “a la t t cv © ' ‘ ¢ rts : t r 2 oy ¢ ¢ ‘ ° © Pte oe oT et et< haat t ‘ S1< ra os © iss ‘ cia © scanned wih onenScmner‘Common Cathode Display: Deuad «ane [sree 2. Describe the working of 4-bit universal shift register. Ans: => N Working: 1, PARALLEL LOAD: When mode control (M) is connected to logic 1, AND gates 2, 4, 6, 8 will be enables and AND gates 1, 3,5,7, will be disabled. The 4-bit binary data will be loaded parallel. The clock-2 input will be applied to the flip-flops, since M= 1, AND gates -10 is enabled and gate-9 is disabled. Input will transfer parallel data to QA to QD outputs. 75 © scanned witonen camer2. SHIFT RIGHT: When mode control (M) is connected to logic 0, AND gates 1,3,5,7 will be enabled and gates 2, 4, 6, 8, will be disabled. The data will be shifted serially. The clock -1, input will be applied to the flip-flops, Since M = 0, AND gates - 9 is enabled, and gates -10 is disabled. The data is shifted serially to right from QA to QD. 3. SHIFT LEFT: When mode control (M) is connected to logic 1, AND gates 2,4,6,8 will be enabled. This mode permits parallel loading of the resister and shift -left operation. The shift -left operation can be accomplished by connecting the output of each flip flop to the parallel input of the previous flip- flop and serial input is applied at the input. 3. Design basic logic gates using NAND and NOR gate. Ans: AND gate using NAND_ B-a-8 E> AND gate using NAND OR gate using NAND. B oO 5 NOT gate using NAND ALA =A OR gate using NOR gate: Expression for OR gate is Y=ATB=A+8 76 © scanned wih onenScmner‘A. (Applying De Morgan"s theorem) NOT gate using NOR Y= Ay A=A 4. Design a mod-6 Asynchronous counter with truth-table and logic. Ans: MOD 6 asynchronous counter will require 3 flip flops and will count from 000 to 101. Rest of the states are invalid. To design the combinational circuit of valid states, following truth table and K-map is drawn: Qc | Qs | Qa | Reset Logic 0 = |= |= |= Jo lo Jo lo = |= ]o[o [= |= = o|s]o[s]o [5 Jo ole |=|(=|(=/=|[= 7 © scanned wih onenScmnerFrom the above truth table, we draw the K-maps and get the expression for the MOD 6 asynchronous counter. Ge 4 Ga Fig: K-map for above truth table Thus reset logic is OR of complemented forms of QC and QB. This will be given to the reset inputs of the counter so that as soon as count 110 reaches, the counter will reset. Thus, the counter will count from 000 to 101. The implementation of the designed MOD 6 asynchronous counter is shown below: Fig: Circuit diagram of MOD 6 asynchronous counter 78 © scanned wih onenScmner5. Design 1:8 de multiplexer using 1:4 de multiplexer Ans: 79 © scanned wih onenScmner1:4 DEMUX Fig:1:8 Demultiplexer using 1:4 demultiplexer ate tmp output D Se % Ye Xs Ye Ms % ‘s Yo o | o °|o|olojloj{o|o|o o fe otetefefefe}ote o | 0} o|ele|lo|o|o|o ojo ofefelofofo}elo o [a | o|o|oj{o{o|oo o fa olelolofofelejo o° [a | o|elojfo|o|o|o o fa olelteleolole|e|o 6. Draw the circuit diagram of 4-bit R-2R ladder DAC and obtain its output voltage expression Ans: © scanned wih onenScmner81 Fig 1: 4 bit R-2R ladder DAC Fig 2:Simplified circuit diagram of Fig 1 Therefore output analog voltage Vois given by, © scanned women Scannerfo WB boy A. VEL ee a. wees whe) 2S e 0 e g 2: > ee . . © oT B % wa (WINTER-19 1, (Convert the following binary number (11001101); into Gray Code and Excess-3 Code. © scanned wth one SanGi (70+ 57) Ans: (170 0001.—O1T (570+ 0101 __O111 ond 1110 Valid Invalid BCD BCD (12M) ADD 0110 TO Invalid BCD (1/2 M) tou 010-1110 + o110 01110100) “(1/2 M) D 4 = (74)10 Perform the binary addition. (10110 © 110); + (1001 # 10), Ans: 83 © scanned witonen camer101 10.110), — (1001.10)> = (100000.010)2 Mi 10110.110 + 1001.10 100000.010 2. Design a 4bit ripple counter using JK flip flop, with truth table and waveforms. Ans: 84 © scanned wih onenScmner‘Truth Table: 415 16 ' sb j _JAL: \ 08 | L ' 2c | 5 L ao! oats ta aoe oases = 85 © scanned women Scanner3. Calculate the analog output for 4 bit weighted register type DAC for inputs @ 1011 (i) 1001 Assume (Vj) full scale range of voltage is SV Ans: Given; VR = Vis=5V Formula Used: Vo =- VR (B1.2' + B2.2? + B3.2°+B4.2*) 1. 1011 Vo = - VR (B1.2'+ B2.27 + B3.2°+ B42) S(I*1/2+0+ 191/23 +1 *1/24) =-5(1*1/2 + 11/8 + 1 *1/16) 5 (0.5 + 0.125 + 0.0625) = 3.4375V Vo = 3.4375 V 2. 1001 Vo =- VR (BI.2"+ B2.27 + B3.27+ B4.2*) 10 (1*1/2 +0+0+1*1/24) 10(1*1/2+0+0+1*1/16) 10 (0.5 + 0.0625) = 2.8125V 8125 V Vo 4. Compare TTL, CMOS and ECL logic family on the following points. (i) Basic Gates (ii) Propagation delay (iii)Fan out (iv)Power Dissipation (v) Noise immunity (vi)Speed power product Ans: 86 © scanned wih onenScmnerParameter TTL Mos ECL Basic gates NAND | NORNAND | OR/NOR Propagation delay 10 70-105 3 Fan out 10 50 25 Power Dissipation 10mW 101mw | 40-5smW Noise Immunity 0.2V sv 0.28V Speed Power 100 07 100 Product 5S. Design a BCD adder using IC 7483. Ans: (Note: Labelled combinational circuit can be drawn using universal gate also) 1) To implement BCD adder, we require: * 4-bit binary adder for initial addition * Logic circuit to detect sum greater than 9 * One more 4-bit adder to add 0110201102 in the sum if sum is greater than 9 or carry is 1 2) The logic circuit to detect sum greater than 9 can be determined by simplifying the Boolean expression of given truth Table. 87 © scanned wih onenScmner=$3.52453.51 3) Y=1 indicates sum is greater than 9. We can put one more term, C_out in the above expression to check whether carry is one. 4) If any one condition is satisfied, we add 6(0110) in the sum. 5) With this design information we can draw the block diagram of BCD adder, as shown in figure below. 88 © scanned women ScannerBy By By By Ay hy A A | | rete 83 82 8) 8 6. Design a 3-bit synchronous counter using JK Flip Flop. Ans: 1) Step1: Construct JK state table with corresponding excitation table: 89 © scanned wih onenScmnerState Table and Corresponding Excitation Table (d=don't care) Step 2: Build Karnaugh Map or Kmap for each JK inputs: asa go T2=Q1.Q0 K2-01.00 _K1=-00 Step3: Draw the complete design as below: 90 og Ourput State Transitions Present Next state State 22.0100 Flip-flop inputs 22.91.90 RK2 SKI JOKO 000 oor [ox] ox | 1x O01 oro [ox | ix [| XT 010 dit | ox] xo | 1x orl Too [1x | xT | XT 100 Tor [xo | ox | 1x TOT Tro [xo } 1x | xT 110 iit [xo | xo | 1x | tit [000 | xr] xi [xr | 30 map © scanned women ScannerNote: It can also be designed using any other Flip Flop. (SUMMER-22) 1. Draw and explain operation 4 bit universal shift register. Draw necessary waveforms. Working 1. PARALLEL LOAD: When mode control (M) is connected to logic 1, AND gates 2, 4, 6, 8 will be enables and AND gates 1, 3,5,7, will be disabled. The 4-bit binary data will be loaded CHECK Ni © scanned wih onenScmnerparallel. The clock-2 input will be applied to the flip-flops, since M= 1, AND gates -10 is enabled and gate-9 is disabled. Input will transfer parallel data to QA to QD outputs. 2. SHIFT RIGHT: When mode control (M) is connected to logic 0, AND gates 1,3,5,7 will be enabled and gates 2, 4, 6, 8, will be disabled. The data will be shifted serially. The clock -1, input will be applied to the flip-flops, Since M = 0, AND gates - 9 is enabled, and gates -10 is disabled, The data is shifted serially to right from QA to QD. 3, SHIFT LEFT: When mode control (M) is connected to logic 1, AND gates 2,4,6,8 will be enabled. This mode permits parallel loading of the resister and shift -left operation. The shift -left operation can be accomplished by connecting the output of each flip flop to the parallel input of the previous flip- flop and serial input is applied at the input. 2. Draw block diagram of Dual slope ADC and explain its working. Ans: 92 © scanned wih onenScmner/2V EdTech LLP | DTE (CO/AIML) (22320) | ALL Board Questions| 93 Fy-Diploma (URJA) [LIVE] (Sem 2) only at 4999/- BUY NOW Sy-Diploma (UMANG ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW, ‘Ty-Diploma (YUKTI ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW All Courses : CHECK NOW, YOUTUBE : SUBSCRIBE NOW. _ INSTA : FOLLOW NOW Download V2V APP on Playstore for more FREE STUDY MATERIAL Contact No : 9326050669 / 9326881428 9 © scanned witonen camer/2V EdTech LLP | DTE (CO/AIML) (22320) | ALL Board Questions| 3. Design 16:1 MUX using 4:1 MUX Ans: 94 Fy-Diploma (URJA) [LIVE] (Sem 2) only at 4999/- BUY NOW Sy-Diploma (UMANG ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW, ‘Ty-Diploma (YUKTI ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW All Courses : CHECK NOW, YOUTUBE : SUBSCRIBE NOW. _ INSTA : FOLLOW NOW Download V2V APP on Playstore for more FREE STUDY MATERIAL Contact No : 9326050669 / 9326881428 on © scanned witonen camerT 4. Compare TTL and CMOS with following points. (i) Fan IN (ii) FAN OUT (iii) Propogation delay (iv) Power dissipation Ans: Parameter ‘CMOS TTL Propagation delay 70-105 nsee/more than | 10 nsee/Less than TTL CMOS Power Dissipation Less 0.1 mW/Less than | More 10 mW/ More TTL than CMOS Fan-out 30/More than TTL 10/Less than CMOS Basic gate NAND/NOR- NAND 95 © scanned wih onenScmner/2V EdTech LLP | DTE (CO/AIML) (22320) | ALL Board Questions| (WINTER-22} 1. Explain 3 bit asynchronous counter with output waveforms. Ans: 96 Fy-Diploma (URJA) [LIVE] (Sem 2) iploma (UI © scanned witonen camer/2V EdTech LLP | DTE (CO/AIML) (22320) | ALL Board Questions| 2. Compare following (Any three points) i) RAM with ROM memory. ii) EPROM with EEPROM memory. Ans: 7 Fy-Diploma (URJA) [LIVE] (Sem 2) only at 4999/- BUY NOW Sy-Diploma (UMANG ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW, ‘Ty-Diploma (YUKTI ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW All Courses : CHECK NOW, YOUTUBE : SUBSCRIBE NOW. _ INSTA : FOLLOW NOW Download V2V APP on Playstore for more FREE STUDY MATERIAL Contact No : 9326050669 / 9326881428 al ss SSS © scanned witonen camer/2V EdTech LLP | DTE (CO/AIML) (22320) | ALL Board Questions| 3. Draw the circuit and explain the principle of TTL gate with totempole output Ans: 98 Fy-Diploma (URIJA) [LIVE] (Sem 2) only at 4999/- BUY NOW. Sy-Diploma (UMANG ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW, ‘Ty-Diploma (YUKTI ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW All Courses : CHECK NOW, YOUTUBE : SUBSCRIBE NOW. _ INSTA : FOLLOW NOW Download V2V APP on Playstore for more FREE STUDY MATERIAL Contact No : 9326050669 / 9326881428 oe © scanned witonen camer/2V EdTech LLP | DTE (CO/AIML) (22320) | ALL Board Questions| 99 Fy-Diploma (URJA) [LIVE] (Sem 2) only at 4999/- BUY NOW Sy-Diploma (UMANG ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW, ‘Ty-Diploma (YUKTI ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW All Courses : CHECK NOW, YOUTUBE : SUBSCRIBE NOW. _ INSTA : FOLLOW NOW Download V2V APP on Playstore for more FREE STUDY MATERIAL Contact No : 9326050669 / 9326881428 ao © scanned witonen camer/2V EdTech LLP | DTE (CO/AIML) (22320) | ALL Board Questions| 100 Fy-Diploma (URJA) [LIVE] (Sem 2) only at 4999/- BUY NOW Sy-Diploma (UMANG ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW, ‘Ty-Diploma (YUKTI ) [LIVE] (Sem 3 + sem 4) : only at 4999/- BUY NOW All Courses : CHECK NOW, YOUTUBE : SUBSCRIBE NOW. _ INSTA : FOLLOW NOW Download V2V APP on Playstore for more FREE STUDY MATERIAL Contact No : 9326050669 / 9326881428 $60 © scanned witonen camer