DIGITAL

ELECTRONIC
Chapter Five:
Sequential Logics (Flip-Flops)
 SYNCHRONOUS SEQUENTIAL LOGIC
 A sequential circuit is a logic circuit that employ memory
elements in addition to (combinational) logic gates.
 Their outputs are determined from the state of the memory cells
(as well as the present input combination).
 The state of the memory elements, in turn, is a function of the
previous inputs (and the previous state).
 Its behavior therefore is specified by a time sequence of inputs
and internal states.
 The binary information stored in the memory elements
(flip-flops) at any given time defines the state of the
sequential circuit.
 Example : Ring counter that starts the answering machine
after 4rings
 Sequential components can be
(1) Asynchronous or
(2) Synchronous
 An asynchronous sequential circuit changes their
states and output values whenever a change in input
values occurs.
 Its behavior depends on the order in which its input
signals change and
 can be affected at any time.

 A synchronous sequential circuit changes their states

and output values at fixed points of time, which are
specified by the rising and/or falling edge of a free-
running clock signal.
 Its behavior is defined at discrete instants of time.
 A synchronous sequential circuit can be modeled by a
finite state machine (FSM):
A synchronous sequential circuit changes their
states and output values at fixed points of
time, which are specified by the rising and/or
falling edge of a free-running clock signal.
 Its behavior is defined at discrete instants of
time.
 Synchronization usually is achieved by a timing device
called a clock generator, which generates a periodic train of
clock pulses distributed throughout the system to trigger the
memory elements.
FLIP FLOPS (FFS)

 The most important memory element is the flip-flop, which is

made up of an assembly of logic gates.
 Even though a logic gate, by itself, has no storage capability,
several can be connected together in the ways that permit
information to be stored.
 Several different gate arrangements are used to produce these
flip-flops (FF).
 Two outputs, labeled Q and Q’, That are the inverse of each
other.
CONT’D…
 Note that the High or 1 state (Q=1/Q’=0) is also referred to as the
SET state.
 Whenever the inputs to a FF cause it to go to the Q=1 state, we
call this setting the FF; The FF has been set.
 Similarly, LOW or 0 state (Q’=1/Q=0) is referred to as the CLEAR
or RESET state.
 Whenever the inputs to a FF cause it to go to the Q=0 state, this
is clearing or setting the FF.
 Fig above implies that a FF can have one or more inputs that are
used to cause the FF to switch back and forth (Flip-Flop) between
its possible output states.
 The FF inputs need only to be momentarily activated (Pulsed) in
order to cause a change in the FF o/p state.
 The O/p will remain in that new state even after the input pulse
is over. This is the FF’s memory characteristics
SR LATCH
 The SR latch is a basic memory element (FF)
which can store one bit of information.
 It consists of two cross-coupled NOR gates or two
cross-coupled NAND gates.

 It has two input signals, the Set signal (S) and the
Reset signal ®
 It has two output signals, Q and Q’.
 It has two states, the Set state (when Q= 1 and Q’ =
0) and the Reset signal (when Q = 0 and Q’ = 1)
RESETING AND CLEARING

Setting

Clearing
 Simultaneous Setting and Clearing
 When SET and CLEAR are both pulsed LOW, it will produce HIGH
level at both NAND o/p. this is an undesired condition since both o/p
has to be in inverse.
 Simultaneous transition of SET and CLEAR back to 1 produces
unpredictable o/p. for this reason SET=CLEAR=0 is not normally
used in NAND Latchs.
 From the description of the NAND latch operation, it the SET and
CLEAR inputs are active-LOW (fig 2).
 Therefore the NAND gate can be alternatively represented by Fig 1.

Fig 1 Fig 2
APPLICATION: NAND SWITCH
It is virtually impossible to
obtain a clean voltage transition
form a mechanical switch. Due
to contact bounce.

The multiple Transition on the

o/p signal generally (~ms) but
This is unacceptable. A NAND
Can be used to prevent the
Switch bounce.
APPLICATION 2: BURGLAR ALARM
 The light is focused on a phototransistor that is connected
in the common-emitter configuration to operate as a switch.
 Assume that the latch has previously been cleared to the 0
state by momentarily opening switch SW1.
 what will happen if the light beam is momentarily
interrupted.
With light on phototransistor, we
Can assume that it is fully conducting
So that resistance between the collector
And emitter is very small.
Thus v0 will be 0 V. SET = 0, CLEAR = 0
NOR
When light beam is interrupted?
Phototransistor turns off, and its CE
Resistance becomes very high (open ckt)
v0 =5 V. SET = 1, Alarm = ON
CLOCKED SIGNAL AND CLOCKED FF
 Digital Systems can operate either Asynchronously or Synchronously.
 In ASYN, the o/p of logic ckts can change state any time one or more of
the inputs change. It is generally more difficult to design and
troubleshoot than SYN system.
 In SYN systems, the exact times at which any o/p can change states are
determined by a signal commonly called the CLOCK.
 This clock signal is generally a rectangular pulse train or a square wave
as shown fig below.
 It is distributed to all parts of the system and most of the system o/p
can change state only when the clock makes a transition (edges).
 When the clock changes from a 0 to a 1, this is called the Positive-going-
transition (PGT), when it changes 1 to 0, it Negative-going-transition
(NGT).
 In SYN, almost everything is synchronized to the clock-signal
transition.
 The Synchronizing action of the clock signals is accomplished through
the use of clocked FFs that are designed to change states on one or the
other of the clock’s transition.
 CLOCKED FFS
 Several types of clocked FFs are used in a wide range of applications.
Before we begin our study of the different clocked FFs, we will describe
the principal ideas that are common to all of them.
 1. clocked FFs have a clock input that is typically labeled CLK, CK, CP.
 FF with a small triangle on its CLK input to indicate that this input
is activated only when PGT occurs
 FF with bubble as well as a triangle on its CLK input, the CLK
input is activated only when a NGT occurs
 2. Clocked FFs also have one or more control inputs that can have
various names, depending on their operation.
 This control inputs will have no effect on Q until the active clock
transition occurs.
 3. We can say, that the control inputs get the FF o/p ready to change,
while the active transition at the CLK input actually triggers the change.
 The control inputs controls the WHAT (what state the o/p will go to);
the CLK input determines the WHEN.
 Two timing requirements must be met if a clocked FF is to respond
reliably to its control inputs when the active CLK transition occurs.
 Setup time (ts) is the time Interval immediately preceding The active
transition of the CLK Signal during which the control Input must be
maintained At the proper level.
 Hold time (th) is the time Interval immediately following The active
transition of the CLK Signal during which the control Input must be
maintained At the proper level.

The control input must be

Stable for at least (th + ts)
Typicaly FFS have ts (5 – 50ns),
th (0 – 10ns).
CLOCKED SR FF
 Fig below shows a clocked SR FF that is PGT. The S and R inputs
control the state of the FF in the same manner as described
earlier for the NOR gate latch at PGT.
o The S and C inputs are SYN control inputs; they control which
state the FF will go to when the clock pulse occurs; the CLK input
is the trigger input that causes the FF to change states according
to what the S and C input are when the active clock transition
occurs.
o The circuit contains three sections
o A basic NAND latch formed by NAND-3 and NAND-4
o A pulse-steering ckt formed by NAND-1 and NAND-2
o An edge-detector ckt
 CLOCKED J-K FF
 Fig below shows a clocked J-K FF that is triggered by PGT of CLK.
 The J and K input control the state of the FF in the way as the S
and C input do for the clocked S-C FF except one condition
 In J-K FF, when J=K=1 condition does not result ambiguous o/p .
 At this condition the FF will always go to its opposite state upon PGT.
 This is called toggle mode of operation.
Note: FF is not affected by NGT
J and K i/p levels have no effect
Except upon the occurrence of the
PGT of the clock signal.
CLOCKED D FF
 Unlike S-C and J-K, Clocked/Edge-triggered D FF has only one
SYN control i/p, D, which stands for data.
 The operation of D FF is, Q will go to the same state that is
present on D i/p when PGT occurs at CLK.
 Assuming Q is initially HIGH
D LATCH/TRANSPARENT
 The edge-triggered D FF uses an edge-detector ckt to ensure that the
o/p will respond to the D i/p only when the active transition of the clock
occurs.
 If this edge detector is not used, the resultant ckt operates somewhat
differently, it is called D latch

Note: even though the EN i/p operates as CLK i/p of an edge triggered FF,
There is no small triangle on the EN i/p. this symbol is for i/p that cause an
o/p change only when a transition occurs. The D latch is not edge-triggered.
When EN is High, Q o/p
Will look like exactly as D.
At this time D latch is Transparent

When EN is Low, The o/p are latched

To their current value and can not
even if D is Changed.
TROUBLESHOOTING CASE STUDY

Troubleshoot
the circuit.
TROUBLESHOOTING CASE STUDY

• There are several possibilities:

– An internal open connection at Z1-1, which would
prevent Q from responding to the input.
– An internal component failure in NAND gate Z1 that
prevents it from responding properly.
– Q output is stuck LOW, which could be caused by:
• Z1-3 internally shorted to ground
• Z1-4 internally shorted to ground
• Z2-2 internally shorted to ground
• The Q node externally shorted to ground
FLIP-FLOP TIMING CONSIDERATIONS -
PARAMETERS
 Important timing parameters:
 Setup and hold times
 Propagation delay—time for a signal at the input to be
shown at the output. (tPLH and tPHL)
 Maximum clocking frequency—Highest clock frequency
that will give a reliable output. (fMAX)
 Clock pulse HIGH and LOW times—minimum clock-
time between HIGH/LOW changes.( tW(L); tW(H) )
 Asynchronous Active Pulse Width—time the
clock must HIGH before going LOW, and LOW
before going HIGH.
 Clock transition times—maximum time for clock
transitions,
 Less than 50 ns for TTL ; 200 ns for CMOS
 FLIP-FLOP TIMING CONSIDERATIONS -
PARAMETERS
FF propagation delays.

Clock Pulse HIGH and LOW and Asynch pulse width.

 FLIP-FLOP TIMING CONSIDERATIONS –
ACTUAL IC VALUES

Timing values for FFs

from manufacturer
data books.

All of the listed values

are minimum values,
except propagation
delays, which are
maximum values.
POTENTIAL TIMING PROBLEMS IN FF CIRCUITS
 When the output of one FF is connected to the
input of another FF and both are triggered by
the same clock, there is a potential timing
problem.
 Propagation delay may cause unpredictable outputs.
 Edge-triggeredFFs have hold time requirements
5 ns or less—most have tH = 0.
 They have no hold time requirement.
Assume the FF hold time requirement is short enough to
respond reliably according to the following rule:

Flip-Flop output will go to a state determined by

logic levels present at its synchronous control inputs
just prior to the active clock transition.
POTENTIAL TIMING PROBLEMS IN FF
CIRCUITS

Q2 will respond properly

to the level present at
Q1 prior to NGT of CLK—
provided Q2 ’s hold time
requirement, tH, is less than
Q1’s propagation delay.
FLIP-FLOP APPLICATIONS
 Examples of applications:
 Counting; Storing binary data
 Transferring binary data between locations
 Many FF applications are categorized sequential.
 Output follows a predetermined sequence of states.
FLIP-FLOP SYNCHRONIZATION
 Most systems are primarily synchronous in operation—
in that changes depend on the clock.
 Asynchronous and synchronous operations are
often combined—frequently through human input.
 The random nature of asynchronous inputs can
result in unpredictable results.

The asynchronous signal A can produce partial pulses at X.

FLIP-FLOP SYNCHRONIZATION

An edge-triggered D
flip-flop synchronizes
the enabling of the
AND gate to the NGTs
of the clock.
DETECTING AN INPUT SEQUENCE
 FFs provide features pure combinational logic gates do
not—in many situations, output activates only when inputs
activate in a certain sequence This requires the storage
characteristic of FFs.

Clocked D flip-flop used to respond to a particular

sequence of inputs.

To work properly, A must go HIGH,

prior to B, by at least an amount
of time equal to FF setup time.
DATA STORAGE AND TRANSFER
 FFs are commonly used for storage and transfer
of binary data.
 Groups used for storage are registers.
 Data transfers take place when data is moved between
registers or FFs.
 Synchronous transfers take place at clock PGT/NGT.
 Asynchronous transfers are controlled by PRE & CLR.
DATA STORAGE AND TRANSFER –
SYNCHRONOUS
Synchronous data transfer operation by various clocked FFs.

CLK inputs are used to perform the transfer.

DATA STORAGE AND TRANSFER –
ASYNCHRONOUS
Asynchronous data transfer operation.

PRE and CLR inputs are used to perform the transfer.

5-16 DATA STORAGE AND TRANSFER –
PARALLEL

Transferring the
bits of a register
simultaneously is
a parallel
transfer.
SERIAL DATA TRANSFER

 Transferring the bits of a register a bit at a time is a

serial transfer.
SERIAL DATA TRANSFER – SHIFT REGISTER

 A shift register is a group of FFs arranged so the binary

numbers stored in the FFs are shifted from one FF to the
next, for every clock pulse.

J-K flip-flops operated as a four-bit shift register.

SERIAL DATA TRANSFER – SHIFT REGISTER

Input data are shifted

left to right from FF
to FF as shift pulses
are applied.

In this shift-register arrangement,

it is necessary to have FFs with
very small hold time requirements.

There are times when the J, K

inputs are changing at about the
same time as the CLK transition.
SERIAL DATA TRANSFER – SHIFT REGISTER
Two connected three-bit shift registers.

The contents of the X register will be serially

transferred (shifted) into register Y.

The D flip-flops in each shift register require

fewer connections than J-K flip-flops.
SERIAL DATA TRANSFER – SHIFT REGISTER
Two connected three-bit shift registers.
The complete transfer of the three bits
of data requires three shift pulses.
SERIAL DATA TRANSFER – SHIFT REGISTER
Two connected three-bit shift registers.
On each pulse NGT, each FF takes on the value
stored in the FF on its left prior to the pulse.
 Widmer, Gregory L. Moss
SERIAL DATA TRANSFER – SHIFT REGISTER

Ronald J. Tocci, Neal S.

Applications, 11/e

Digital Systems:
Principles and
Two connected three-bit shift registers.
On each pulse NGT, each FF takes on the value
stored in the FF on its left prior to the pulse.
SERIAL DATA TRANSFER – SHIFT REGISTER
Two connected three-bit shift registers.
On each pulse NGT, each FF takes on the value
stored in the FF on its left prior to the pulse.
 SERIAL DATA TRANSFER – SHIFT REGISTER
Two connected three-bit shift registers.
The 1 initially in X2 is in Y2.
After three pulses: The 0 initially in X1 is in Y1.
The 1 initially in X0 is in Y0.

The 101 stored in the X

register has now been
shifted into the Y register.

The X register has lost its

original data, and is at 000.
SERIAL DATA TRANSFER VS. PARALLEL
 FFs in can just as easily be connected so that
information shifts from right to left.
 No general advantage of one direction over another.
Often dictated by the nature of the application.


 Parallel transfer requires more interconnections between

sending & receiving registers than serial.
 More critical when a greater number of bits of are being
transferred.
 Often, a combination of types is used
 Taking advantage of parallel transfer speed and serial
transfer the economy and simplicity of serial transfer.
FREQUENCY DIVISION AND COUNTING

J-K flip-flops wired

as a three-bit binary
counter (MOD-8).

Each FF divides the

input frequency by 2.

Output frequency
is 1/8 of the input
(clock) frequency.

A fourth FF would
make the frequency
1/16 of the clock.
 Widmer, Gregory L. Moss
Ronald J. Tocci, Neal S.
FREQUENCY DIVISION AND COUNTING

Applications, 11/e

Digital Systems:
Principles and
J-K flip-flops wired
as a three-bit binary
counter (MOD-8).

This circuit also acts

as a binary counter.

Outputs will count

from 0002 to 1112
or 010 to 710.

The number of states

possible in a counter
is the modulus
or MOD number.
FREQUENCY DIVISION AND COUNTING
A MOD-8 (23) counter.
If another FF is added it would
become a MOD-16 (24) counter.
SYNCHRONOUS OR PARALLEL COUNTERS

 The problems encountered with ripple counters are caused

by the accumulated FF propagation delays; stated another
way, the FFs do not all change states simultaneously in
synchronism with the input pulses. These limitations can be
overcome with the use of synchronous or parallel
counters in which all of the FFs are triggered
simultaneously (in parallel) by the clock input pulses.
 Unlike the asynchronous counters, the propagation delays of
the FFs do not add together to produce the overall delay.
 Instead, the total response time of a synchronouscounter like
the one in Figure 7-5 is the time it takes one FF to toggle
plus the time for the new logic levels to propagate
 Synchronous Counter

Asynchronous (Ripple Counter)

MICROCOMPUTER APPLICATION
 Microprocessor units (MPUs) perform many functions
involving use of registers for data transfer and storage.
 MPUs may send data to external registers
for many purposes, including:
 Solenoid/relay control; Device positioning.
 Motor starting & speed controls.
MICROCOMPUTER APPLICATION
Microprocessor transferring binary
data to an external register.
5ONE-SHOT (MONOSTABLE MULTIVIBRATOR)
• Like the FF, the OS has two outputs, Q and Q.
– The inverse of each other.
• One shots are called monostable multivibrators
because they have only one stable state.
– Prone to triggering by noise.
• Changes from stable to quasi-stable state for a
fixed time-period (tp).
– Usually determined by an RC time constant from
external components.
ONE-SHOT (MONOSTABLE MULTIVIBRATOR)
• Nonretriggerable devices trigger & return to
stable.
• Retriggerable devices can be triggered while in
the quasi-stable state, to begin another pulse.
 Widmer, Gregory L. Moss
ONE-SHOT (MONOSTABLE MULTIVIBRATOR)

Ronald J. Tocci, Neal S.

Applications, 11/e
OS symbol and typical waveforms

Digital Systems:
Principles and
for nonretriggerable operation.

PGTs at points a, b, c, and e will trigger

the OS to its quasi-stable state for a time tp.
After which it automatically returns to the stable state.
ONE-SHOT (MONOSTABLE MULTIVIBRATOR)
OS symbol and typical waveforms
for nonretriggerable operation.

PGTs at points d and f have no effect on the OS

because it has already been triggered quasi-stable.
OS must return to the stable before it can be triggered.
ONE-SHOT (MONOSTABLE MULTIVIBRATOR)
OS symbol and typical waveforms
for nonretriggerable operation.

OS output-pulse duration is always the same,

regardless of the duration of the input pulses.
Time tp depends only on RT, CT & internal OS circuitry.
ONE-SHOT (MONOSTABLE MULTIVIBRATOR)
Comparison of nonretriggerable and
retriggerable OS responses for tp = 2ms.
ONE-SHOT (MONOSTABLE MULTIVIBRATOR)

Widmer, Gregory L. Moss

Ronald J. Tocci, Neal S.
Applications, 11/e
Retriggerable OS begins a new tp interval

Digital Systems:
Principles and
each time it receives a trigger pulse.
ONE-SHOT (MONOSTABLE MULTIVIBRATOR)
74121 nonretriggerable one-shot IC.

Contains internal logic gates

to allow inputs A1 , A2 , and B
to trigger OS.

Input B is a Schmitt-trigger—
allowed to have slow transition
times & still reliably trigger OS.

Pins RINT, REXT/CINT, , and CEXT

connect to an external resistor
& capacitor to achieve desired
output pulse duration.
CLOCK GENERATOR CIRCUITS
 A third type multivibrator has no stable states—
an astable or free-running multivibrator.
 Astable or free-running multivibrators switch back
and forth between two unstable states.
 Useful for generating clock signals for synchronous
circuits.
CLOCK GENERATOR CIRCUITS
Schmitt-trigger oscillator using a 7414 INVERTER.
A 7413 Schmitt-trigger NAND may also be used.
CLOCK GENERATOR CIRCUITS
 The 555 timer IC is a TTL-compatible device
that can operate in several different modes.
 Output is a repetitive rectangular waveform that
switches between two logic levels.
 The time intervals at each logic level are determined
by the R and C values.
 The heart of the 555 timer is two voltage
comparators and an S-R latch.
 The comparators produce a HIGH out when voltage
on the (+) input is greater than on the (-) input.
CLOCK GENERATOR CIRCUITS

555 Timer IC used

as an astable
multivibrator.
CLOCK GENERATOR CIRCUITS
 Crystal control may be used if a very stable clock is
needed—used in microprocessor systems and
microcomputers where accurate timing intervals are
essential.
TROUBLESHOOTING FLIP-FLOP CIRCUITS
 FFs are subject to the same faults that occur in
combinational logic circuits.
 Timing problems create some faults and symptoms
that are not seen in combinational logic circuits.
 Unconnected or floating inputs are particularly
susceptible spurious voltage fluctuations—noise.
 Given sufficient noise amplitude and duration,
logic circuit output may change states in
response.
 In a logic gate, output will return to its original state
when the noise signal subsides.
 In a FF, output will remain in its new state due to its
memory characteristic.
TROUBLESHOOTING FLIP-FLOP CIRCUITS
 Clock skew occurs when CLK signals arrive
at different FFs at different times.
 The fault may be seen only intermittently, or
may disappear during testing.
TROUBLESHOOTING FLIP-FLOP CIRCUITS
Extra gating circuits can cause clock skew.
TROUBLESHOOTING FLIP-FLOP CIRCUITS
Extra gating circuits can cause clock skew.