CY8C41x5/CY8C41x6

PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU

Based on 32-bit Arm® Cortex®-M0+

General description
PSOC™ 4 HVMS-64K belongs to the PSOC™ 4 HV mixed signal (MS) series of products and is a fully integrated
programmable embedded system for several automotive HMI, body, and power-train applications. The system
features an Arm® Cortex®-M0+ processor with programmable and reconfigurable analog and digital blocks. It is
a combination of a microcontroller with a 12-bit SAR ADC, 5th generation multi-sense converter (MSC) block
supporting capacitive sensing (CAPSENSE™), digital peripherals such as PWMs and serial communication
interfaces along with a LIN interface with integrated PHY, and a high-voltage subsystem to operate directly off
the 12-V car battery.
Features
• Automotive Electronics Council (AEC)-Q100 qualified
• CPU subsystem
- 48-MHz 32-bit Arm® Cortex®-M0+ CPU, with
• Single-cycle multiply
• Memory protection unit (MPU)
- Data wire/peripheral DMA controller with 8 channels
- Integrated memories
• Up to 64 KB of flash
• Up to 8 KB of SRAM
• Programmable analog
- 12-bit 1-Msps SAR ADC with differential and single-ended modes, and channel sequencer with signal averaging
- 16-channel SAR multiplexer with in-built diagnostics (8 I/O channels + 8 diagnostic channels)
- Temperature sensor built into SAR ADC
- Two low-power comparators that operate in Deep Sleep low-power mode
• Programmable digital
- Programmable Smart I/O logic blocks allowing Boolean operations to be performed on port inputs and
outputs
• High-voltage subsystem
- Regulator output voltage supports 3.3- or 5-V selectable with ±2% trimmed accuracy
- Regulator current: up to 60 mA
- Thermal shutdown
- Operates directly off 12-V/24-V battery (tolerates up to 42 V)
- Integrated local interconnect network (LIN)/clock extension peripheral interface (CXPI) transceiver
• CAPSENSE™ (multi-sense converter) block
- Multi-sense converter (MSC) provides best-in-class signal-to-noise ratio (SNR) (> 5:1) and water tolerance for
capacitive sensing
- One MSC converter supported
- Autonomous channel scanning without CPU assistance
• Functional safety for ASIL-B
- The device will be developed according to the development process of ISO 26262 for ASIL B as a Safety Element
out of Context (acc. ISO26262-10:2018E, clause 9)
- Memory protection unit (MPU)
- Window watchdog timer (WDT) with Challenge-Response functionality
- Supply monitoring; detection of overvoltage and brownout events for 3.3-/5-V, and 1.8-V supplies
- Hardware error detection and correction (SECDED ECC) on all safety-critical memories (SRAM, flash)

Datasheet Please read the Important Notice and Warnings at the end of this document 002-33200 Rev. *G
www.infineon.com page 1 2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Features

• Timing and pulse-width modulation

- Five 16-bit timer/counter/pulse-width modulator (TCPWM) blocks
- Center-aligned, edge, and pseudo-random modes
- Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications
- Quadrature decoder
• Clock sources
- ±2% 24 to 48-MHz internal main oscillator (IMO)
- ±1% 2-MHz high-precision oscillator (HPOSC)
- ±5% 32-kHz precision internal low-power oscillator (PILO)
- ±1% accuracy on IMO and PILO when software calibrated to the HPOSC
- 40-kHz internal low-speed oscillator (ILO)
• Communication
- Two independent run-time reconfigurable serial communication blocks (SCB) with re-configurable I2C, SPI,
UART, or LIN slave functionality
- Up to two independent Local interconnect network (LIN) channels
• LIN protocol compliant with LIN 2.2A and ISO 17987
- Up to two CXPI channels with data rate up to 20 kbps
• I/O
- Up to 41 GPIOs
• Any GPIO pin can be CAPSENSE™, analog, or digital
• Drive modes, strengths, and slew rates are programmable
• Packages
- 32-lead QFN with wettable flanks (6 × 6 mm)
- 48-lead QFN with wettable flanks (7 × 7 mm)
- 56-lead QFN with wettable flanks (8 × 8 mm)

Datasheet 2 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Table of contents

Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Table of contents ...............................................................................................................................3
1 Block diagram ................................................................................................................................5
2 Functional definition.......................................................................................................................6
2.1 CPU and memory subsystem .................................................................................................................................6
2.1.1 CPU .......................................................................................................................................................................6
2.1.2 Memory with ECC .................................................................................................................................................6
2.1.3 Flash .....................................................................................................................................................................6
2.1.4 SRAM.....................................................................................................................................................................6
2.1.5 SROM ....................................................................................................................................................................6
2.1.6 DMA.......................................................................................................................................................................6
2.2 System resources....................................................................................................................................................7
2.2.1 Power system .......................................................................................................................................................7
2.2.2 Power system supervision and monitoring........................................................................................................9
2.2.3 Clock system ......................................................................................................................................................10
2.3 Analog blocks ........................................................................................................................................................12
2.3.1 12-bit SAR ADC ...................................................................................................................................................12
2.3.2 Low-power comparators (LPC) .........................................................................................................................12
2.3.3 Analog multiplexed buses .................................................................................................................................12
2.4 Programmable digital blocks ...............................................................................................................................13
2.4.1 Smart I/O block or PROG I/Os............................................................................................................................13
2.5 Fixed function digital ............................................................................................................................................13
2.5.1 Timer/counter/PWM (TCPWM) block ................................................................................................................13
2.5.2 LIN block.............................................................................................................................................................14
2.5.3 CXPI block...........................................................................................................................................................14
2.5.4 Serial communication block (SCB) ...................................................................................................................15
2.6 GPIO.......................................................................................................................................................................18
2.7 High-voltage subsystem .......................................................................................................................................19
2.7.1 AHB interface .....................................................................................................................................................19
2.8 ESD protection ......................................................................................................................................................23
2.9 Special function peripherals ................................................................................................................................24
2.9.1 CAPSENSE™ ........................................................................................................................................................24
3 PSOC™ 4 HVMS-64K address map ...................................................................................................25
4 Package pinouts ...........................................................................................................................26
4.1 Alternate pin functions .........................................................................................................................................30
5 Interrupts and wake-up assignments .............................................................................................35
6 Peripheral clocks ..........................................................................................................................36
6.1 Peripheral clock dividers ......................................................................................................................................36
7 Fault assignments.........................................................................................................................37
8 Trigger multiplexer .......................................................................................................................38
8.1 Trigger group inputs .............................................................................................................................................38
8.2 Trigger group outputs...........................................................................................................................................42
9 Electrical specifications.................................................................................................................43
9.1 Absolute maximum ratings ..................................................................................................................................43
9.2 Device-level specifications ...................................................................................................................................45
9.2.1 Operating current and wakeup times...............................................................................................................46
9.2.2 Voltage regulators..............................................................................................................................................50
9.3 GPIO.......................................................................................................................................................................51
9.3.1 SMART/PROG I/O specifications........................................................................................................................53
9.3.2 XRES....................................................................................................................................................................53

Datasheet 3 002-33200 Rev. *G

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Table of contents

9.3.3 Clocks .................................................................................................................................................................54

9.4 Analog....................................................................................................................................................................55
9.4.1 LIN transceiver ...................................................................................................................................................55
9.4.2 CXPI transceiver .................................................................................................................................................58
9.4.3 CAPSENSE™ block (MSC) specifications ...........................................................................................................61
9.4.4 Comparator ........................................................................................................................................................63
9.4.5 Temperature sensor ..........................................................................................................................................65
9.4.6 SAR ADC ..............................................................................................................................................................65
9.5 Digital peripherals.................................................................................................................................................67
9.5.1 Timer/counter/PWM (TCPWM) ..........................................................................................................................67
9.5.2 LIN.......................................................................................................................................................................68
9.5.3 CXPI.....................................................................................................................................................................69
9.5.4 Serial communication block .............................................................................................................................70
9.6 Memory..................................................................................................................................................................72
9.7 System resources..................................................................................................................................................73
10 Ordering information ..................................................................................................................74
10.1 Nomenclature diagram ......................................................................................................................................77
10.2 Part number nomenclature................................................................................................................................78
11 Packaging ..................................................................................................................................79
11.1 Package outline ..................................................................................................................................................80
12 Acronyms ...................................................................................................................................83
13 Document conventions................................................................................................................87
13.1 Units of measure .................................................................................................................................................87
Revision history ..............................................................................................................................88

Datasheet 4 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Block diagram

1 Block diagram

PSOCTM HVMS-64K CPU subsystem

M0S8 SWD/TC SPCIF
Architecture
DataWire/
Arm® Cortex®-M0+ Flash SRAM ROM
P-DMA
32-bit
48 MHz 64KB 8 KB 16 KB
8 ch
FAST MUL Read Accelerator SRAM Controller
AHB-Lite (w/ECC) (w/ECC) ROM Controller Initiator/MMIO
NVIC,IRQMUX,MPU

System Resources
High Voltage System interconnect (Single Layer AHB)
Power
Sleep Control Peripherals
WIC
POR REF PCLK Peripheral interconnect (MMIO)
PWRSYS
ASIL-B VMON
Clock
Clock Control HV SS Programmable
WDT+ Ch/Resp

2x LP Comparator
Analog

TMR/CTR/QD/PWM
ILO IMO

IOSS GPIO (7x PORTS)

5x TCPWM
PILO HPOSC

I2C/SPI/UART
SAR ADC

1x MSCv3
LIN/UART
Clock Calibration

2x CXPI

2x SCB
2x LIN
VBAT Voltage Divider

Reset (12-bit, 16 ch)

HV LDO + TSD

LIN/CXPI PHY

Reset Control
(3.3-/5-V)
VDDD

XRES
Test
TestMode Entry
Digital DFT
x1
Analog DFT

Diagnosis + SARMUX

HV Pads, ESD
High-speed I/O Matrix & 2x SMART I/O blocks

Power modes
Active/Sleep 41x GPIOs
DeepSleep
I/O Subsystem

Figure 1 Block diagram

PSOC™ 4 HVMS-64K devices include extensive support for programming, testing, debugging, and tracing both
hardware and firmware.
The Arm® serial-wire debug (SWD) interface supports all programming and debug features of the device.
Complete debug-on-chip functionality enables full-device debugging in the final system using the standard
production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the
standard programming connections are required to fully support debug.
The SWD interface is fully compatible with industry-standard third-party tools. PSOC™ 4 HVMS-64K provides a
level of security not possible with multi-chip application solutions or with microcontrollers. It has the following
advantages:
• Allows disabling of debug features
• Robust flash protection
• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks
The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way
to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new
firmware that enables debugging. Thus, firmware control of debugging cannot be over-ridden without erasing
the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled (device security) for applications concerned
about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and
interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when
maximum device security is enabled. Therefore, PSOC™ 4 HVMS-64K, with device security-enabled, may not be
returned for failure analysis. This is a trade-off the PSOC™ 4 HVMS-64K allows the customer to make.

Datasheet 5 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

2 Functional definition
2.1 CPU and memory subsystem
2.1.1 CPU
The Cortex®-M0+ CPU in the PSOC™ 4 HVMS-64K device is part of the 32-bit MCU subsystem, which is optimized
for low-power operation with extensive clock gating. Most instructions are 16 bits in length and execute a subset
of the Thumb-2 instruction set. This implementation includes a hardware multiplier that provides a 32-bit result
in one cycle. It includes a nested vectored interrupt controller (NVIC) block with 32 interrupt inputs and includes
a wakeup interrupt controller (WIC), which can wake the processor up from the Deep Sleep mode allowing power
to be switched off to the main processor when the chip is in the Deep Sleep mode. The Cortex®-M0+ CPU provides
a non-maskable interrupt (NMI) input, which is made available to the user when it is not in use for system
functions requested by the user.
Programs can execute from SROM, SRAM, or flash memory.
The CPU also includes a debug interface, the SWD interface, which is a 2-wire form of JTAG; the debug
configuration used for PSOC™ 4 HVMS-64K has four break-point (address) comparators and two watchpoint
(data) comparators.

2.1.2 Memory with ECC

Flash and SRAM include an error correction code (ECC) circuitry capable of correcting single-bit errors and
detecting 2-bit errors. If a single-bit error occurs, the data is corrected in-line, error information is stored (address
and data), and an error flag is set which can generate an interrupt. If a multi-bit error is detected, the error
information is stored and either an interrupt or reset is generated.

2.1.3 Flash
PSOC™ 4 HVMS-64K has a flash module (64 KB of flash) with dedicated controller for flash. The flash is with an
accelerator, tightly coupled to the CPU to improve average access times from the flash block. The flash
accelerator delivers 85% single-cycle SRAM access performance on average. Part of a flash module can be used
to emulate EEPROM.

2.1.4 SRAM
8 KB of volatile static RAM memory (SRAM) is used by the processor for storing variables and can program code,
which can be written and executed in SRAM. SRAM memory is retained in all power modes (Active, Sleep, and
Deep Sleep). At power-up, SRAM is uninitialized and should be written by application code before reading.

2.1.5 SROM
A 16 KB of supervisory read-only memory (ROM) contains boot and configuration routines which can’t be
modified.

2.1.6 DMA
A DMA engine with eight channels is provided that can do 32-bit transfers and has chainable ping-pong
descriptors. This DMA engine allows data transfer between memory, registers, and peripherals without CPU
intervention. DMA transfers can occur while the CPU is powered down. Descriptors identify the data source and
destination along with other information.

Datasheet 6 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

2.2 System resources

2.2.1 Power system
The power system includes regulators to generate appropriate voltages. The PSOC™ 4 HVMS-64K device operates
at full performance from a single supply on VBAT over a voltage range of 3.6 V to 28 V and remains functional up
to 42 V. In addition to an active mode, the PSOC™ 4 HVMS-64K device has two low-power modes called Sleep and
Deep Sleep. Transitions between the three power modes are managed by the power system in the system
resources subsystem (SRSS).
The high-voltage regulator generates a 3.3-V or 5-V supply from VBAT for VDDD and VDDA. VDDA powers analog
circuits, while VDDIO provides power for I/Os (GPIOs) and VDDD for 1.8-V core power regulators. There are
different internal core regulators to support the various power modes. These include Active Digital regulator and
Deep Sleep regulator. The core is able to supply up to 60 mA load current in Active power mode.
Refer to Figure 2 and Table 1 for the power system block diagram and current specifications.

Reverse
protection diode 4.7 Ω
Battery VBAT VDDA VDDD VDDIO VCCD
(4.5 – 42 V))
6.8 μF 0.1 μF 0.22 μF 0.1 μF 3.3 μF 0.1 μF 3.3 μF 0.15 μF
TVS
Optional

VDDIO

VCCD
VDDD
VDDA
VBAT

3.3/5.0 V Analog 3.3/5.0 V Digital

Domain Domain

High-Voltage (HV) Active Domain

Regulator GPIO Examples: CPU, IMO,
Flash, Peripherals

Active
Regulator
DeepSleep Domain
Examples: Low-speed
digital, ILO, I2C, SRAM
retention
LIN Interface DeepSleep
HV Domain Regulator
All VDDD, VDDIO to be
tied together, and
supplied by the HV
regulator.
VSSL VSSA VSSD

Figure 2 Power system block diagram[1, 2]

Notes
1. User can short VBAT and VDDX pins, and use a direct external 3.3 V or 5 V supply to it. It will not damage the
device and is a valid state.
2. In some use cases featuring multiple GPIO capacitive sensing via AMUX, it is recommended to short VDDIO and
VDDA to improve the performance of the capacitive sensing converter. This applies for use cases with more
than 16 capacitive sensors and a GPIOs switching load above 2 mA. Capacitive sensing via Control Mux is not
affected, but maximum sensor count is limited to 16.

Datasheet 7 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

Bypass capacitors must be used from VDDD, VDDIO, VDDA, and VCCD to ground, as shown in Table 1. These
capacitors should typically be X7R ceramic or better.

Table 1 Bypass capacitors

Supply pair Nominal cap Tolerance
0.1 µF +65% / –65%
VBAT–VSSD
6.8 µF +10% / –50%
0.1 µF +65% / –65%
VDDD–VSSD
3.3 µF +10% / –50%
0.1 µF +65% / –65%
VDDIO–VSSD
3.3 µF +10% / –50%
VDDA–VSSA 0.22 µF +10% / –50%
VCCD–VSSD 0.15 µF +10% / –50%

The system has a high-voltage (HV) regulator, which generates 3.3-/5.0-V supplies and several regulators for
various low-voltage core domains. The analog circuits run directly from the VDDA supply generated by the HV
regulator. The core regulators include an active digital regulator for digital circuitry and a separate regulator for
Deep Sleep. The Deep Sleep regulator has switches to pass high power regulator voltages to loads when the
low-power regulators are not required.
The HV regulator is always enabled. The active digital regulator is enabled during the Active or Sleep power
modes. It is turned off in the Deep Sleep power mode. The Deep Sleep regulator fulfills power requirements in
the low-power modes. Table 2 describes the different regulator operating modes.

Table 2 Regulators and operating modes

Mode HV regulator Active regulator Deep Sleep regulator
Active On On On
Sleep On On On
Deep Sleep On Off On

Datasheet 8 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

2.2.2 Power system supervision and monitoring

The power supply includes supervision and monitoring to assure voltage levels, as required, exist for the
respective modes. The voltage monitoring system includes power-on-reset (POR) and brownout detection (BOD).
The supervisor either delays mode transitions (on POR, for example) until the required voltage levels are achieved
for proper function or generates resets (BOD, OVD) as appropriate.
Power-on-reset (POR): POR circuits provide a reset pulse during the initial power ramp. POR circuits monitors
VDDD (core) voltage. The POR threshold is between 0.8 V and 1.5 V and guarantees all circuits have been properly
initialized prior to release. POR circuits are used during initial chip power-up and then disabled.
Brownout detection (BOD): The BOD circuit protects the operating or retaining logic from possibly unsafe
supply conditions by applying reset to the device. Two BOD circuits are available, one for monitoring the VDDD
supply and the other for monitoring the VCCD voltage. The BOD circuit generates a reset if the core voltage dips
below the minimum safe operating voltage (1.48 V–1.62 V in Active/Sleep and 1.11 V–1.5 V in Deep Sleep). The
system will not come out of RESET until the supply is detected to be valid again.
To enable firmware to distinguish a normal power cycle from a brownout event, a special register is provided
(PWR_BOD_KEY), which will not be cleared after a BOD generated RESET. However, this register will be cleared
if the device goes through POR or XRES.
Over-voltage detection (OVD): Two OVD circuits are available, one for monitoring the VDDD supply and the other
for monitoring the VCCD voltage. Similar to the BOD circuit, the OVD circuit detects supply conditions above a
threshold and applies a reset. As the name suggests, the OVD circuit maintains a device reset, if VCCD or VDDD
supply stays higher than thresholds. OVD on VDDD can be set to either 3.8 V or 5.75 V, and on VCCD to 2.08 V.
Voltage references: The SRSS includes a bandgap and current references for use by analog circuits and SRSS
voltage regulators. The HV regulator has another reference and the precision analog subsystem has a
high-precision voltage reference, which provides accurate voltage references for the ADCs. The ADCs may
measure the SRSS and HV regulator references and all supply voltage pins (VDDD, VDDA, VCCD, and VSS and VSSA)
for diagnostic purposes. To allow better SNR and better absolute accuracy, an external reference or an external
capacitor on the reference pin can improve accuracy by reducing noise.

Datasheet 9 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

2.2.3 Clock system

The PSOC™ 4 HVMS-64K device clock system is responsible for providing clocks to all subsystems that require
clocks and for switching between different clock sources without glitching and for synchronizing clocks
operating on different frequency domains to prevent meta-stable conditions.
The following four oscillators are implemented:
• One IMO for CPU and peripheral clock generation, which is usually configured for 24 MHz, but can be
programmed for frequencies from 24 MHz to 48 MHz in 4-MHz steps.
• One high-precision fixed frequency 2-MHz oscillator for precision timing (HPOSC)
• One low-power 40-kHz low-speed oscillator (ILO)
• One 32-kHz precision low-power oscillator (PILO) for wakeup timers and watchdog timers.
There are also provisions for an external clock supplied by a GPIO pin. The ILO and PILO are permanently powered
in all power modes.

HFCLK
SYSCLK
Prescaler
SYSCLK

Peripheral
Dividers

HFCLK
IMO clk_pump (PUMP) Divider 0
24 to 48 MHz For FLASH Memory
+/- 2%
(/16)
PER0_CLK
clk_ext clk_hf (HFCLK)
(EXTCLK)
HPOSC Divide By
2 MHz 2, 4, 8 Divider 3
+/- 1%
(/16)

Fractional
Divider 0
(/16.5)
ILO
40 kHz
- 50% to +100%
clk_lf (LFCLK) Fractional PER7_CLK
Divider 1
PILO (/16.5)
32 kHz
+/- 5%

Figure 3 PSOC™ 4 HVMS-64K device clocking architecture

Software can lock the IMO and ILO to the HPOSC to increase precision of those oscillators. Software can also lock
any of the oscillators to external time references such as the external clock input or LIN bit rate. Software lock is
accomplished with dedicated calibration counters that will be available in the system resources subsystem. The
oscillators are designed in such a way that trim changes do not glitch or disturb clock outputs.
IMO clock source: The IMO is the primary source of internal clocking in the PSOC™ 4 HVMS-64K device. It is
trimmed during testing to achieve the specified accuracy. Trim values are stored in nonvolatile memory.
Trimming can also be done on the fly to allow in-field calibration. The IMO default frequency is 24 MHz and it can
be adjusted from 24 MHz to 48 MHz in steps of 4 MHz. IMO tolerance with provided calibration settings is ±2%.
This clock runs in Active and Sleep modes.
HPOSC clock source: The HPOSC is a 2 MHz 1% precision oscillator, which is on in Active power and Sleep mode
and off in Deep Sleep modes. During Active mode, high-frequency precision is required for accurate timing of ADC
measurements to accurately determine charge and discharge energy (amp-hour) balance. This is achieved with
the IMO slaved to the HPOSC with software tracking.

Datasheet 10 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

PILO clock source: The precision internal low speed oscillator (PILO) is a very low power oscillator with a nominal
frequency of 32 kHz. It is primarily used to generate clocks for peripherals in low power modes. The PILO is
implemented with the focus on low-power in the DeepSleep mode to keep supply current under 50 µA. The
accuracy over temperature and lifetime without periodic synchronization to the HPOSC is FLSO_ACCY1 (±5%, see
parameter section). By means of regular synchronization with the HPOSC at least once per second, the same
accuracy as in normal mode can be achieved (FLSO_ACCY2, ±1%, see parameter section). This accuracy can be
maintained at least 60s after the last synchronization calibration while temperature and voltage are stable.
The PILO clocks low-power digital blocks including the watchdog timers and a lifetime counter. In active mode,
it can also generate strobes enabling TCPWM counters to be used with software for calibrating of the ILO.
ILO clock source: The ILO operates with no external components and outputs a stable clock at 40-kHz nominal.
The ILO is relatively low power and low accuracy. The ILO is available in all power modes. The ILO is a relatively
inaccurate (–50% to +100% over voltage and temperature) oscillator, which is used to generate low-frequency
clocks.
Lifetime counter: A 32-bit lifetime counter with a prescaler (/1 to /32) is available and triggered from the PILO
clock. This counter runs in all modes and can be reset by POR. With the prescaler, the net resolution of the counter
becomes 37-bit causing an overflow every 50 days. The counter will continue counting upon overflow.
Reset: The PSOC™ 4 HVMS-64K device can be reset from a variety of sources including a software reset. Reset
events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register,
which is sticky through reset and allows software to determine the cause of the reset. An XRES_L pin is reserved
for external reset to avoid complications with configuration and multiple pin functions during power-on or
reconfiguration.
The following events cause resets:
• POR
• Brownout/overvoltage
• Watchdog reset
• Software reset
• External reset via XRES_L pin
• Fault system
• Protection violation
Watchdog timers (WDT): The WDTs are used to automatically reset the device in the event of an unexpected
firmware execution path. They are also used as a wakeup source to periodically generate interrupts as a wakeup
source in low-power modes. There are two WDTs, one that is implemented in HV logic (will reset the part if VCCD
goes illegal) and a challenge-response WDT (CRWDT) implemented in the LV logic.
The CRWDT includes a window watchdog function, generating timeout events if the CRWDT is serviced too soon,
too late, or with the wrong software key. A register identifies the timeout cause. It generates a watchdog reset or
interrupt if serviced too soon or too late. Service too soon potentially means an infinite loop including watchdog
service is executing, while too late means the processor could be stuck and not processing properly. The
challenge/response means the watchdog service routines must present specific data or “keys” in the order
expected by the watchdog or a fault will occur. The fault will generate a watchdog reset or interrupt with the reset
recorded in the Reset Cause register. The causes can be conditions such as watchdog too soon, watchdog late,
or wrong key received.
Further details of the CRWDT can be found in the technical reference manual.

Datasheet 11 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

2.3 Analog blocks

2.3.1 12-bit SAR ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks
at that frequency to do a 12-bit conversion.
The sample-and-hold (S/H) aperture is programmable allowing the gain bandwidth requirements of the amplifier
driving the SAR inputs, which determine its settling time, to be relaxed if required. It is possible to provide an
external bypass (through a fixed pin location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through selected
channels autonomously (sequencer scan) with zero switching overhead (that is, aggregate sampling bandwidth
is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching
is effected through a state machine or through firmware driven switching. A feature provided by the sequencer
is buffering of each channel to reduce CPU interrupt service requirements. To accommodate signals with varying
source impedance and frequency, it is possible to have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers (low and high range values) is implemented with
a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast
detection of out-of-range values without the necessity of having to wait for a sequencer scan to be completed
and the CPU to read the values and check for out-of-range values in software.
The SAR is not available in Deep Sleep mode as it requires a high-speed clock (up to 18 MHz). The SAR operating
range is 1.71 V to 5.5 V.

AHB System Bus and Programmable Logic

Interconnect

SAR Sequencer
Sequencing
and Control Data and
Status Flags
vminus vplus

POS

SARADC
SARMUX
(Up to 8 inputs)

NEG
SARMUX Port

Reference External
Selection Reference and
Bypass
(optional )
VDDA /2 VDDA VREF

Inputs from other Ports

Figure 4 SAR ADC

2.3.2 Low-power comparators (LPC)

PSOC™ 4 HVMS-64K has a pair of low-power comparators, which can also operate in Deep Sleep modes. This
allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels
during low-power modes. The comparator outputs are normally synchronized to avoid metastability unless
operating in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch
event. The LPC outputs can be routed to pins.

2.3.3 Analog multiplexed buses

PSOC™ 4 HVMS-64K has two concentric independent buses that go around the periphery of the chip. These buses
(called amux buses) are connected to firmware-programmable analog switches that allow the chip's internal
resources to connect to any pin on the I/O ports.

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

2.4 Programmable digital blocks

2.4.1 Smart I/O block or PROG I/Os
The Smart I/O block (also referred to as programmable I/Os) is a fabric of switches and LUTs that allows Boolean
functions to be performed in signals being routed to the pins of a GPIO port. The Smart I/O can perform logical
operations on input pins to the chip and on signals going out as outputs. There are two Smart I/O blocks in the
PSOC™ 4 HVMS-64K device.

2.5 Fixed function digital

2.5.1 Timer/counter/PWM (TCPWM) block
The TCPWM in the PSOC™ 4 HVMS-64K device implements a 16-bit timer, counter, pulse width modulator (PWM),
and quadrature decoder functionality. There are five TCPWM blocks on the PSOC™ 4 HVMS-64K device. The block
can be used to measure the period and pulse width of an input signal (timer), count several events (counter),
generate PWM signals, or decode quadrature signals.
The block provides true and complementary outputs with programmable offset between them to allow
dead-band between outputs for driving complementary PWM loads. It also has a Kill input to force outputs to a
predetermined state; this is used to inhibit outputs when faults are detected without requiring the need and
delay of software intervention.
Features:
• The TCPWM block supports the following operational modes:
- Timer, counter, capture, quadrature decoding
- Pulse width modulation (PWM) including pseudo-random PWM and PWM with dead time
- PWM uses a period counter and capture counter - complementary outputs are available
• Multiple counting modes - up, down, and up/down
• Clock prescaling (division by 1, 2, 4, ... 64, 128)
• Double buffering of compare/capture and period values
• Generate triggers based on compare, overflow, or underflow.
• Supports interrupt on:
- Terminal count: The final value in the counter register is reached (zero or period count)
- Capture: When a capture event occurs (the counter value at the time of capture is saved)
- Compare: When the count equals the compare value
- Synchronized counters: The counters can reload, start, stop, and count at the same time

CPU Subsystem

System
Bus Interface
Interface
Synchronization

Configuration

Bus Interface Logic

Registers
Trigger

Trigger _in
[4:0]
5 Counter

Underflow , Interrupt line_out,

3 2
Overflow, line_compl_out
Capture/compare

Figure 5 TCPWM block diagram

Datasheet 13 002-33200 Rev. *G

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

2.5.2 LIN block

The PSOC™ 4 HVMS-64K device features a dedicated LIN communication block that supports autonomous
transfer of the LIN frame to off load the CPU. Some of the key features of this block include:
• Certified at C&S according to LIN 2.2A / ISO 17987 standards
• Can be used with external LIN PHY, or routed through the internal LIN PHY.
• LIN protocol support in hardware according to LIN 2.2A / ISO 17987 standard
- Master and slave functionality
- Master node
• Autonomous header transmission and autonomous response transmission and reception
- Slave node
• Autonomous header reception and autonomous response transmission and reception
- Message buffer for PID, data, and checksum fields
- Classic and enhanced checksum
- Timeout detection
- Error detection
- Test modes including hardware error injection
- Baud rate detection
- 16x bit time oversampling

2.5.3 CXPI block

The PSOC™ 4 HVMS-64K device contains up to two CXPI channels compliant with JASO D015 and ISO standard
20794 including the controller specification.
Each channel supports:
• Slave functionality
• Polling and event trigger method for both normal and long frames
• Non-return to zero (NRZ) and PWM signaling modes
• Collision resolution and carries sense multiple access
• Wakeup pulse generation and detection
• CRC8 and CRC16 for both normal and long frames
• Error detection
• Dedicated FIFO (16 B) for transmit and receive
• Can be used with external CXPI PHY, or routed through the internal CXPI PHY.

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

2.5.4 Serial communication block (SCB)

SCB supports three serial interface protocols: SPI, UART, and I2C. Only one of the protocols is supported by an
SCB at any given time. The PSOC™ 4 HVMS-64K device has two SCBs.
This block supports the following features:
• UART with standard, SmartCard reader, LIN, and IrDA protocols
• UART with LIN slave functionality with LIN v1.3 and LIN v2.1/2.2/2.2A specification compliance
• SPI master and slave functionality with Motorola, TI, and NSC protocols
• I2C master and slave functionality
• EZ mode for SPI and I2C, which enables operation without CPU intervention
• Low-power (Deep Sleep) mode of operation for SPI and I2C protocols (using external clocking)

2.5.4.1 UART mode

This is a full-feature UART operating at up to 1 Mbps supporting automotive single-wire interface (LIN), infra-red
interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the PSOC™ 4 HVMS-64K
device UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of
peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect,
and frame error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated.
The universal asynchronous receiver/transmitter (UART) protocol is an asynchronous serial interface protocol.
UART communication is typically point-to-point.
The UART interface consists of two signals:
• TX: Transmitter output
• RX: Receiver input
The UART can also connect to the internal local interconnect network (LIN) PHY.
The UART mode has the following features:
• Asynchronous transmitter and receiver functionality
• Supported UART protocols include Standard UART, LIN, SmartCard (ISO7816) reader, and IrDA
• LIN support includes
- Break detection
- Baud rate detection
- Collision detection (detect a dominant bus state when transmitting a recessive bit)
• Multi-processor mode
• Data frame size programmable from 4 to 9 bits
• Programmable number of STOP bits, which can be set in terms of half-bit periods between 1 and 4
• Parity (odd and even parity)
• Interrupt or polling CPU interface
• Programmable oversampling

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

2.5.4.2 SPI mode

The serial peripheral interconnect (SPI) mode supports full Motorola SPI, TI SSP (essentially adds a start pulse
used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO
and supports an EzSPI mode in which data interchange is reduced to reading and writing an array in memory.
The SPI protocol is a synchronous serial interface protocol. Devices operate in either master or slave mode. The
master initiates the data transfer. The SCB supports single-master-multiple-slaves topology for SPI. Multiple
slaves are supported with individual slave select lines.
You can use the SPI master mode when the PSOC™ 4 HVMS-64K must communicate with one or more SPI slave
devices. The SPI slave mode can be used when the PSOC™ 4 HVMS-64K must communicate with an SPI master
device.
The SPI mode has the following features:
• Supports master and slave functionality
• Supports three types of SPI protocols:
- Motorola SPI - modes 0, 1, 2, and 3
- Texas Instruments SPI, with coinciding and preceding data frame indicator for mode 1
- National Semiconductor (MicroWire) SPI for mode 0
• Supports up to four slave select lines
• Data frame size programmable from 4 bits to 16 bits
• Interrupts or polling CPU interface
• Programmable oversampling
• Supports EZ mode of operation - EzSPI mode allows for operation without CPU intervention
• Supports externally clocked slave operation:
- In this mode, the slave operates in Active, Sleep, and Deep Sleep system power modes
A standard SPI interface consists of the following four signals. These signals connect to GPIO pins:
• SCLK: Serial clock (output from the master, input to the slave).
• MOSI: Master-out-slave-in (data output from the master, input to the slave).
• MISO: Master-in-slave-out (data input to the master, output from the slave).
• Slave Select (SS): Usually an active low signal (output from the master, input to the slave).

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

2.5.4.3 I2C mode

The hardware I2C block implements a full multi-master and slave interface (it is capable of multimaster
arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has flexible
buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that creates a
mailbox address range in the memory of the PSOC™ 4 HVMS-64K device and effectively reduces I2C
communication to reading from and writing to an array in memory. The block supports an 8-deep FIFO for receive
and transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock
stretching caused by the CPU not having read data on time. The FIFO mode is available in all channels and is very
useful in the absence of DMA.
The I2C peripheral is compatible with the I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined
in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in
open-drain modes.
The PSOC™ 4 HVMS-64K device is not completely compliant with the I2C spec in the following respect:
• GPIO cells are not overvoltage-tolerant and, therefore, cannot be hot-swapped or powered up independently
of the rest of the I2C system
The I2C mode has the following features:
• Master, slave, and master/slave mode
• Slow-mode (50 kbps), standard-mode (100 kbps), fast-mode (400 kbps), and fast-mode plus
- (1000 kbps) data-rates
• 7- or 10-bit slave addressing (10-bit addressing requires firmware support)
• Clock stretching and collision detection
• Programmable oversampling of I2C clock signal (SCL)
• Error reduction using a digital filter on the input path of the I2C data signal (SDA)
• Glitch-free signal transmission with an analog glitch filter
• Interrupt or polling CPU interface

2.5.4.4 LIN slave mode

The LIN slave mode uses the SCB hardware block and implements a full LIN slave interface. This LIN slave is
compliant with LIN v1.3, v2.1/2.2, ISO 17987-6, and SAE J2602-2 specification standards. LIN slave can be
operated at baud rates of up to ~20 Kbps with a maximum of 40-meter cable length.

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

2.6 GPIO
This section describes the PSOC™ 4 HVMS-64K device I/O system. The GPIO pins are grouped into ports; a port
can have a maximum of eight GPIOs. The PSOC™ 4 HVMS-64K device has eight GPIOs arranged in one port.
The GPIOs have these features:
• Output drive modes include push-pull (strong or weak), open drain/source, high-z, and pull-up/pull-down
• Selectable CMOS and low-voltage LVTTL input buffer mode
• Edge-triggered interrupts on rising edge, falling edge, or on both the edges, on pin basis
• Individual control of input and output disables
• Hold mode for latching previous state (for retaining I/O state in Deep Sleep)
• Selectable slew rates allowing dV/dt control to assist with noise control to improve EMI
All GPIOs can be used to receive analog input signals for the ADCs.
During power-on and reset, GPIO outputs are disabled to prevent conflict with externally applied signals and
prevent crowbar and/or excessive turn-on current. Data output and pin state registers store, respectively, the
values to be driven on the pins and the states of the pins themselves. An interconnect network known as a
high-speed I/O matrix (HSIOM) is used to multiplex between various signals that may connect to an I/O pin.
Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt
service routine (ISR) vector associated with it.
The PSOC™ 4 HVMS-64K device HV VDDD regulator has enough capacity to drive internal loads and external loads
up to 60 mA. DC GPIO loads are considered external loads. The combined DC GPIO and external load current must
not exceed the available 30 mA. When driving DC loads, such as LEDs, make sure that the total current being
sourced from the GPIOs does not exceed this limit.

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

2.7 High-voltage subsystem

The PSOC™ 4 HVMS-64K device high-voltage subsystem includes the following functions:
• An AHB bus interface and control/status registers.
• The VBAT to VDDD/VDDA HV regulator (3.6 to 28-V input, 3.3-/5.0-V nominal outputs)
• Thermal shutdown (TSD)
• VBAT voltage divider
• A LIN/CXPI transceiver (physical interface or PHY)

2.7.1 AHB interface

The AHB includes the control and status registers needed for the HV subsystem.

2.7.1.1 HV regulator
The high-voltage regulator is always on, supplied by VBAT, and provides VDDD and VDDA. It supplies a nominal
output voltage of 3.3 V, but may drop as low as 2.7 V when VBAT drops below 4 V.

2.7.1.2 Thermal shutdown

The thermal shutdown function prevents deterioration and breakdown due to a significant increase in ambient
temperature and heat generation of the device itself due to an unintended large current load. It reduces power
dissipation and device overheating. TSD causes the HV LDO regulator repeatedly to turn OFF and ON till the
causes of overheating are removed.

2.7.1.3 VBAT voltage divider

Voltage divider is used on the device’s VBAT pin to scale battery voltage to levels compatible with on-chip
analog-to-digital converters, in order to measure the battery voltages. In typical applications, the VBAT input is
normally connected directly to the battery with a series 2.2 kΩ resistor to measure battery voltage.

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

2.7.1.4 LIN transceiver

• The LIN transceiver meets the requirements of LIN standard 2.2A and is downward compatible with the LIN 2.0
• Data rates up to 20kbps with high EM noise immunity
• A non-LIN fast slew rate is available, providing up to 115.2 kbps data rates for fast downloads for factory and
field flash program updates using the LIN pin
• Positive/negative DC tolerance for LIN pin: –27 V to 42 V
• LIN transceiver connects the LIN data link controller and the LIN bus line, and enables direct connection to the
vehicle battery with a high surge protection.
The LIN transceiver is guaranteed not to block the LIN bus with a dominant bit when the VBAT voltage is below
the minimum LIN supply voltage (6 V, VBAT_LIN, LIN 2.2A Parameter 10) and may continue to operate below that
voltage but communication is not guaranteed. The LIN transceiver is inhibited if VCCD is not valid to prevent
erroneous control signals from interference with the LIN bus. A timer is also present clocked by the low-speed
clock system, which disables the LIN if the bus is dominant for too long. The timer can generate an interrupt if the
LIN bus wakeup signal (LIN bus in dominant state for 250 µs to 5 ms) is detected. LIN compliance testing is
facilitated by making the transceiver data signals available on GPIO pins (LIN_RX, LIN_TX) as the serial control
block UART signals are also available (UART_RX, UART_TX).
The LIN transceiver has an open drain output and digital receiver connected to the LIN pin, which connects to the
LIN bus. The bus has pull-ups to VBAT with total pull-up resistance between 500  and 1 k. A series diode
between VBAT and the pull-ups prevents the bus from powering VBAT. The diode and pull-up resistor are usually
located at or near the LIN master. The transceiver has a weak slave resistor (nominally 30 k) on-chip and the
driver can be configured to provide a weak, normal, or fast pull-down. Both the pull-up and weak pull-down can
be used for diagnostics without disturbing LIN bus communications.
The pull-up resistor and ESD networks prevent parasitic current paths if VBAT or ground is disconnected. The LIN
driver will withstand differences of ±1 V if shorted to another ground and if continuously shorted to another
ground or VBAT, will not be permanently damaged. The LIN transceiver complies with Q100-2/IEC6100-4-2 ESD
and ISO 7637 capacitively coupled transient pulses. Heating of LIN driver in normal operation does not affect
measurement accuracy.

Positive
Battery Pole

VECU

500- (provided
1KΩ by master)
LIN BUS

LIN LIN
Master 220pf Slave
(typ)
VBAT LIN

LIN PHY

30K

filter
TXD/RXD Data: (5us>,>0.5us)
Driver
H = Recessive
L = Dominant

TXD EN_TX RXD

LIN Controller
One master/network,
one or more slaves/network

Figure 6 LIN transceiver (SEL_CXPI_LIN = LINPHY)

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

2.7.1.5 CXPI transceiver

• Compliant with the JASO CXPI (JASO D 015-3: 2015), SAE CXPI (J3076_201510), and ISO CXPI (ISO 20794-4: 2020)
standards
• Supports 2.4 kbps to 20 kbps bit-rate
• Wave-shaping for low electromagnetic interference (EMI)
• Master, and slave mode support
• CXPI PHY connects to the LIN pin which is externally connected to the LIN bus
• CXPI transceiver connects the CXPI data link controller and the LIN/CXPI Bus line, and enables direct connection
to the vehicle battery with a high surge protection

Positive
Battery Pole

VECU

500- (provided
1KΩ by master)
CXPI BUS

CXPI CXPI
Master 220pf Slave
(typ)
VBAT LIN

CXPI PHY

30K

filter
TXD/RXD Data: (5us>,>0.5us)
Driver
H = Recessive
L = Dominant

TXD EN_TX RXD

CXPI Controller

Figure 7 CXPI transceiver (SEL_CXPI_LIN = CXPIPHY)

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

Table 3 LIN/CXPI PHY transceiver truth table

Input DRIVER output
LIN Slew rate setting Slave
LIN_MODE LIN_TXD = LIN_TXD = pull-up
Transceiver [2:0] TX/RX SEL_CXPI_LIN = SEL_CXPI_LIN = 1 0
function LINPHY CXPIPHY
Disabled 000 Off/Off – – Hi-Z Hi-Z Off
Off/On
Sleep 001 (Low – – Recessive Recessive On
power)
Standby 010 Off/Off – – Recessive Recessive On1
Low
Diagnosis 011 On/On – – Recessive Off
(weak)
100 On/On 1.0 V/µs 2.0 V/µs Recessive Low (dom) On
Normal 101 On/On 1.5 V/µs 3.0 V/µs Recessive Low (dom) On
110 On/On 2.0 V/µs 4.0 V/µs Recessive Low (dom) On
2
Fast mode 111 On/On – – Recessive Low (dom) On
dom - dominant; For LIN_TXD and LIN_RXD recessive = 1, dominant = 0

Notes
3. 1: In weak (diagnosis) mode, slave pull-up is on when LIN_TXD = 1, Off when LIN_TXD = 0.
4. 2: non-lin compliant, up to 100kb/s capable.

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

2.8 ESD protection

The PSOC™ 4 HVMS-64K device requires sufficient protection to withstand the high-voltage ESD on specific pins.
The ESD on LIN, and VBAT is rated at ±8 kV, and is required to protected as shown in Figure 8.

OFF ON
CHIP CHIP
15 Ω
VBAT ESD VBAT

2.2 μF

0.1 μF
LIN Bus

LIN
ESD

220 pF
TVS

Figure 8 ESD protection

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Functional definition

2.9 Special function peripherals

2.9.1 CAPSENSE™
CAPSENSE™ is supported on all pins in PSOC™ 4 HVMS-64K via a MSC CAPSENSE™ block that can be connected
to any pin via the analog mux buses that any GPIO pin can be connected to. The MSC block in the PSOC™ 4
HVMS-64K can be used to scan sense inputs autonomously (without CPU sequencing and intervention) with
support for DMA, or can operate via CPU firmware driven switch sequencing via the analog mux buses that any
GPIO pin can be connected to. The CAPSENSE™ function can thus be provided on any pin or group of pins in a
system under software control.
PSOC™ 4 HVMS-64K will use the MSC block, which will support the following:
• Multi-sense (capacitive, resistive, impedance, and current sensing)
• Autonomous scanning (scan multiple sensors without CPU involvement)
• Improved water tolerance (uses both passive, and active shields)
• Improved linearity
• Higher sensitivity (system level chopping, SINC2 filter, baseline compensation))
• 14-bit resolution
• Ratio-metric sensing
• Capacitance sensing up to 200 pF
• 70 dB CMRR
• SINC2 filter for noise reduction
The CAPSENSE™ blocks provide both self as well as mutual capacitance sensing. Shield drive can be either Active
(with an opamp) or passive (less power, for shield loads less than 20 pF).

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
PSOC™ 4 HVMS-64K address map

3 PSOC™ 4 HVMS-64K address map

The PSOC™ 4 HVMS-64K microcontroller supports the memory spaces shown in Figure 9.
• 64 KB of flash
• 8 KB of SRAM
• 16 KB of ROM

0xF000 1FFF
Reserved
0xF000 0FFF CoreSight ROM CoreSight ROM-Table with
4 KB Ta ble Infineon Vendor/Silicon ID
0xF000 0000
Reserved
0xE00 F FF FF
Arm® System CPU & Debug Registers
Space

0xE00 0 00 00
Reserved
0x404F FFFF
Peripheral Mainly used for on-chip peripherals
Interconnect or
e.g., AHB or APB Peripherals
Memory map
0x4000 000 0
Reserved
0x2002 07FF Cortex®-CM0+ MTB SRAM Space
0x2002 000 0
2 KB CM0+ MTB
Reserved
0x2000 1FFF General purpose RAM,
0x2000 000 0
8 KB SRAM
mainly used for data
Reserved
0x1000 3FFF Boot ROM Test, Smart Write,
0x1000 000 0
16 KB ROM
jump to user mode etc.
Reserved
0x0FFF E3FF Flash Supervisory Used to store manufacture specific
0x0FFF E0 00 1 KB
Region 0 data like trim settings, wounding info etc.
Reserved
0x0000 FFFF

64 KB Flash Mainly used for user program code

0x0000 000 0

Figure 9 PSOC™ 4 HVMS-64K device address map[5]

Note
5. The size representation is not up to scale.

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Package pinouts

4 Package pinouts
The following table provides the pin list for the PSOC™ 4 HVMS-64K device for the supported packages.

Table 4 PSOC™ 4 HVMS-64K package pinouts

Package
Pin name 56-lead QFN 48-lead QFN 32-lead QFN GPIO Pin description
Pin Pin Pin
VDDA 1 1 1 NA Power supply for the analog section
VSSA 2 2 2 NA Ground pin for the analog section
P7.0 3 3 3 GPIO
P7.1 4 4 4 GPIO
P5.0 6 6 5 GPIO
P5.1 7 7 6 GPIO
P5.2 8 8 NA GPIO
P5.3 9 9 NA GPIO
P5.4 10 10 NA GPIO
P5.5 11 NA NA GPIO
P5.6 12 NA NA GPIO
P5.7 13 NA NA GPIO
P1.0 14 11 7 GPIO
P1.1 15 12 8 GPIO
VDDIO 16 13 9 NA I/O supply
VSSD 17 14 10 NA Ground pin for the digital section
XRES_L 18 15 11 NA External reset input pin (Active low)
P1.2 19 16 12 GPIO
P1.3 20 17 13 GPIO
P1.4 21 18 14 GPIO
P1.5 22 19 15 GPIO
P1.6 23 20 NA GPIO
P1.7 24 21 NA GPIO
P3.0 25 22 16 GPIO
P3.1 26 23 NA GPIO
P3.2 27 24 NA GPIO
P3.3 28 NA NA GPIO
P3.4 29 NA NA GPIO
P3.5 30 NA NA GPIO
P0.7 31 25 NA GPIO
P0.6 32 26 NA GPIO
P0.5 33 27 NA GPIO
P0.4 34 28 NA GPIO
P0.3 35 29 17 GPIO

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Package pinouts

Table 4 PSOC™ 4 HVMS-64K package pinouts (continued)

Package
Pin name 56-lead QFN 48-lead QFN 32-lead QFN GPIO Pin description
Pin Pin Pin
P0.2 36 30 18 GPIO
P0.1 37 31 19 GPIO
P0.0 38 32 20 GPIO
VDDIO 39 33 21 NA I/O supply
Power supply for the core (LV Logic)
VCCD 40 34 22 NA
(1.8 V ± 5%)
VDDD 41 35 23 NA Power supply for the digital section
VSSD 42 36 24 NA Ground pin for the digital section
VSSL 43 37 25 NA LIN/CXPI ground
LIN/CXPI signal from the internal
LIN/CXPI 44 38 26 NA
transceiver
VBAT 46 40 28 NA Supply input pin
P4.7 48 NA NA GPIO
P4.6 49 42 NA GPIO
P4.5 50 43 NA GPIO
P4.4 51 44 NA GPIO
P4.3 52 45 NA GPIO
P4.2 53 46 30 GPIO
P4.1 54 47 31 GPIO
P4.0 55 48 32 GPIO
P6.0 56 NA NA GPIO

Datasheet 27 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Package pinouts

LIN/CXPI
VBAT

VSSL
P4.0
P4.1
P4.2
NC

NC
32
31
30
29
28
27
26
25
VDDA 1 24 VSSD
VSSA 2 23 VDDD
P7.0
P7.1
3
4
32-lead 22
21
VCCD
VDDIO
P5.0
P5.1
5
6
QFN 20
19
P0.0
P0.1
P1.0 7 18 P0.2
P1.1 8 17 P0.3
10
11
12
13
14
15
16
9
VDDIO
VSSD
XRES_L
P1.2
P1.3
P1.4
P1.5
P3.0

Figure 10 32-lead QFN package pin assignment

LIN/CXPI
VBAT

VSSL
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
NC

NC
48
47
46
45
44
43
42
41
40
39
38
37

VDDA 1 36 VSSD
VSSA 2 35 VDDD
P7.0 3 34 VCCD
P7.1 4 33 VDDIO
NC 5 32 P0.0
P5.0
P5.1
6
7
48-lead QFN 31
30
P0.1
P0.2
P5.2 8 29 P0.3
P5.3 9 28 P0.4
P5.4 10 27 P0.5
P1.0 11 26 P0.6
P1.1 12 25 P0.7
13
14
15
16
17
18
19
20
21
22
23
24
VDDIO
VSSD
XRES_L
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.0
P3.1
P3.2

Figure 11 48-lead QFN package pin assignment

Datasheet 28 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Package pinouts

LIN/CXPI
VBAT

VSSL
P6.0
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
NC

NC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
VDDA 1 42 VSSD
VSSA 2 41 VDDD
P7.0 3 40 VCCD
P7.1 4 39 VDDIO
NC 5 38 P0.0
P5.0 6 37 P0.1
P5.1
P5.2
7
8
56-lead QFN 36
35
P0.2
P0.3
P5.3 9 34 P0.4
P5.4 10 33 P0.5
P5.5 11 32 P0.6
P5.6 12 31 P0.7
P5.7 13 30 P3.5
P1.0 14 29 P3.4
15
16
17
18
19
20
21
22
23
24
25
26
27
28
P1.1
VDDIO
VSSD
XRES_L
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.0
P3.1
P3.2
P3.3

Figure 12 56-lead QFN package pin assignment

Datasheet 29 002-33200 Rev. *G

2025-03-06
 4.1 Alternate pin functions

Based on 32-bit Arm® Cortex®-M0+

PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Datasheet

Package pinouts
Each port pin has can be assigned to one of multiple functions; it can, for example, be an analog I/O or a digital peripheral function. The pin assignments
are shown in the following table.

Table 5 Alternate pin functions

Active DeepSleep
SMART or HCon#4 HCon#5 HCon#8 HCon#9 HCon#10 HCon#11 HCon#12 HCon#13 HCon#14 HCon#15
Name Analog PROG
I/Os CSD_ CSD_
SENSE SHIELD ACT #0 ACT #1 ACT #2 ACT #3 DS #0 DS #1 DS #2 DS #3
csd. csd.
P7.0 csd.s_pad[5]
sense:0 shield:0
csd. csd.
P7.1 csd.s_pad[6]
sense:1 shield:1
pass. cxpi. tcpwm.
csd. csd. lin.lin_ scb[1]. scb[1].spi_ scb[1].i2c_ lpcomp[0].
P5.0 sarmux_ cxpi_ line_
sense:2 shield:2 tx[0]:1 uart_tx:1 miso:0 sda:1 comp[0]:0
pads[0] tx[0]:1 compl[0]:2
pass. cxpi.
30

csd. csd. lin.lin_ scb[1]. tcpwm. scb[1].spi_ scb[1].i2c_ lpcomp[0].

P5.1 sarmux_ cxpi_
sense:3 shield:3 rx[0]:1 uart_rx:1 line[0]:2 mosi:0 scl:1 comp[1]:0
pads[1] rx[0]:1
pass. cxpi. tcpwm.
csd. csd. lin.lin_ scb[1].
P5.2 sarmux_ cxpi_ line_
sense:4 shield:4 en[0]:2 uart_tx:2
pads[2] en[0]:2 compl[1]:2
pass. cxpi.
csd. csd. lin.lin_ scb[1]. tcpwm.
P5.3 sarmux_ cxpi_
sense:5 shield:5 rx[0]:2 uart_rx:2 line[1]:2
pads[3] tx[0]:2
pass. cxpi. tcpwm.
csd. csd. lin.lin_ scb[1].
P5.4 sarmux_ cxpi_ line_
sense:6 shield:6 tx[0]:2 uart_cts:2
pads[4] rx[0]:2 compl[2]:2
pass. tcpwm.
csd. csd. scb[1].
P5.5 sarmux_ line_
sense:7 shield:7 uart_rts:2
pads[5] compl[2]:3
pass.
csd. csd. tcpwm.
002-33200 Rev. *G

P5.6 sarmux_
sense:8 shield:8 line[2]:3
pads[6]
2025-03-06

Note
6. Internal connections to the integrated LIN/CXPI PHY.
 Table 5 Alternate pin functions (continued)

Based on 32-bit Arm® Cortex®-M0+

PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Datasheet

Package pinouts
Active DeepSleep
SMART or
Name Analog PROG HCon#4 HCon#5 HCon#8 HCon#9 HCon#10 HCon#11 HCon#12 HCon#13 HCon#14 HCon#15
I/Os CSD_ CSD_
ACT #0 ACT #1 ACT #2 ACT #3 DS #0 DS #1 DS #2 DS #3
SENSE SHIELD
pass.
csd. csd.
P5.7 sarmux_
sense:9 shield:9
pads[7]
srss.adft_
por_pad_hv
cxpi. cpuss.
pass.sar_ prgio[1]. csd. csd. hvss.lin_ scb[1]. tcpwm.
P1.0 cxpi_ fault_
ext_vref0 io[0] sense:10 shield:10 alt_en uart_cts:1 line[2]:2
en[0]:1 out[0]
pass.sar_
ext_vref1
csd.s_pad[7] tcpwm. cpuss.
prgio[1]. csd. csd. csd.ext_ hvss.lin_ scb[1]. scb[1].spi_
P1.1 lpcomp[0]. line_ fault_
io[1] sense:11 shield:11 sync alt_txd uart_rts:1 clk:0
in_p[0] compl[3]:2 out[1]
csd.s_pad[8]
prgio[1]. csd. csd. csd.ext_ hvss.lin_ scb[1]. tcpwm. scb[1].spi_ scb[1].i2c_
31

P1.2 lpcomp[0].
io[2] sense:12 shield:12 sync_clk alt_rxd uart_tx:0 line[3]:2 select1 sda:0
in_n[0]
csd.s_pad[9] csd.ext_ tcpwm.
prgio[1]. csd. csd. lin.lin_ scb[1]. scb[1].spi_ scb[1].i2c_
P1.3 lpcomp[0]. frm_ line_
io[3] sense:13 shield:13 en[0]:1 uart_rx:0 select0 scl:0
in_p[1] start compl[3]:1
csd.s_
tcpwm.
pad[10] prgio[1]. csd. csd. peri. scb[1]. scb[0].spi_ cpuss.
P1.4 line_
lpcomp[0]. io[4] sense:14 shield:14 virt_in_2 uart_cts:0 mosi:1 swd_clk
compl[4]:1
in_n[1]
csd.s_ prgio[1]. csd. csd. peri. scb[1]. tcpwm. scb[0].spi_ cpuss. lpcomp[0].
P1.5
pad[11] io[5] sense:15 shield:15 virt_in_1 uart_rts:0 line[3]:1 clk:1 swd_data comp[0]:1
csd.s_ prgio[1]. csd. csd. peri. tcpwm. scb[1].spi_
P1.6
pad[12] io[6] sense:16 shield:16 virt_in_3 line[4]:1 select2
pass.dsi_
csd.s_ prgio[1]. csd. csd. scb[1].spi_
P1.7 sar_
pad[13] io[7] sense:17 shield:17 select3
002-33200 Rev. *G

data[0]
Note
2025-03-06

6. Internal connections to the integrated LIN/CXPI PHY.

 Table 5 Alternate pin functions (continued)

Based on 32-bit Arm® Cortex®-M0+

PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Datasheet

Package pinouts
Active DeepSleep
SMART or
Name Analog PROG HCon#4 HCon#5 HCon#8 HCon#9 HCon#10 HCon#11 HCon#12 HCon#13 HCon#14 HCon#15
I/Os CSD_ CSD_
ACT #0 ACT #1 ACT #2 ACT #3 DS #0 DS #1 DS #2 DS #3
SENSE SHIELD
pass.dsi_ tcpwm.
csd.s_ csd. csd. csd.obs_ scb[0].spi_ lpcomp[0].
P3.0 sar_ line_
pad[14] sense:18 shield:18 data[0] miso:1 comp[1]:1
data[1] compl[4]:0
pass.dsi_
csd.s_ csd. csd. csd.obs_ tcpwm.
P3.1 sar_
pad[15] sense:19 shield:19 data[1] line[4]:0
data[2]
pass.dsi_ tcpwm.
csd. csd. csd.obs_
P3.2 sar_ line_
sense:20 shield:20 data[2]
data[3] compl[3]:0
pass.dsi_
csd. csd. csd.obs_ tcpwm.
P3.3 sar_
sense:21 shield:21 data[3] line[3]:0
data[4]
pass.dsi_ tcpwm.
32

csd. csd. scb[1].spi_

P3.4 sar_ line_
sense:22 shield:22 miso:1
data[5] compl[1]:3
pass.dsi_
csd. csd. tcpwm. scb[1].spi_
P3.5 sar_
sense:23 shield:23 line[1]:3 mosi:1
data[6]
pass.dsi_ tcpwm.
prgio[0]. csd. csd. scb[1].spi_
P0.7 sar_ line_
io[7] sense:24 shield:24 clk:1
data[7] compl[0]:3
pass.dsi_
prgio[0]. csd. csd. tcpwm. scb[0].spi_
P0.6 sar_
io[6] sense:25 shield:25 line[0]:3 select3
data[8]
pass.dsi_ tcpwm.
prgio[0]. csd. csd. tcpwm. scb[0].spi_
P0.5 sar_ line_
io[5] sense:26 shield:26 tr_in[0] select2
data[9] compl[2]:0
pass.dsi_
prgio[0]. csd. csd. tcpwm. tcpwm. scb[0].spi_
002-33200 Rev. *G

P0.4 sar_
io[4] sense:27 shield:27 tr_in[1] line[2]:0 select1
data[10]
2025-03-06

Note
6. Internal connections to the integrated LIN/CXPI PHY.
 Table 5 Alternate pin functions (continued)

Based on 32-bit Arm® Cortex®-M0+

PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Datasheet

Package pinouts
Active DeepSleep
SMART or
Name Analog PROG HCon#4 HCon#5 HCon#8 HCon#9 HCon#10 HCon#11 HCon#12 HCon#13 HCon#14 HCon#15
I/Os CSD_ CSD_
ACT #0 ACT #1 ACT #2 ACT #3 DS #0 DS #1 DS #2 DS #3
SENSE SHIELD
tcpwm.
prgio[0]. csd. csd. tcpwm. scb[0]. scb[0].spi_ scb[0].i2c_
P0.3 line_
io[3] sense:28 shield:28 tr_in[2] uart_cts:0 select0 sda:1
compl[1]:0
prgio[0]. csd. csd. tcpwm. lin.lin_ scb[0]. tcpwm. scb[0].spi_ scb[0].i2c_
P0.2
io[2] sense:29 shield:29 tr_in[3] en[0]:0 uart_rts:0 line[1]:0 miso:0 scl:1
tcpwm.
prgio[0]. csd. csd. srss.ext_ lin.lin_ scb[0]. scb[0].spi_ scb[0].i2c_
P0.1 line_
io[1] sense:30 shield:30 clk rx[0]:0 uart_tx:0 mosi:0 sda:0
compl[0]:0
prgio[0]. csd. csd. peri. lin.lin_ scb[0]. tcpwm. scb[0].spi_ scb[0].i2c_
P0.0
io[0] sense:31 shield:31 virt_in_0 tx[0]:0 uart_rx:0 line[0]:0 clk:0 scl:0
pass.dsi_ tcpwm.
csd. csd.
P4.7 csd.s_pad[0] sar_ line_
sense:32 shield:32
data[11] compl[2]:1
33

csd. csd. pass.tr_ tcpwm. lpcomp[0].

P4.6 csd.s_pad[1]
sense:33 shield:33 sar_out line[2]:1 comp[0]:2
pass.dsi_
cxpi. tcpwm.
csd. csd. lin.lin_ sar_ lpcomp[0].
P4.5 csd.s_pad[2] cxpi_ line_
sense:34 shield:34 en[0]:3 sample_ comp[1]:2
en[0]:3 compl[1]:1
done
cxpi. pass.dsi_
csd. csd. lin.lin_ tcpwm.
P4.4 csd.s_pad[3] cxpi_ sar_data_
sense:35 shield:35 rx[0]:3 line[1]:1
tx[0]:3 valid
csd.
cxpi. tcpwm.
cmod4pads csd. csd. lin.lin_ scb[0].
P4.3 cxpi_ line_
csd. sense:36 shield:36 tx[0]:3 uart_cts:1
rx[0]:3 compl[0]:1
cmod4padd
csd.
cxpi.
cmod3pads csd. csd. scb[0]. tcpwm.
P4.2 cxpi_
002-33200 Rev. *G

csd. sense:37 shield:37 uart_rts:1 line[0]:1

en[0]:0
cmod3padd
2025-03-06

Note
6. Internal connections to the integrated LIN/CXPI PHY.
 Table 5 Alternate pin functions (continued)

Based on 32-bit Arm® Cortex®-M0+

PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Datasheet

Package pinouts
Active DeepSleep
SMART or
Name Analog PROG HCon#4 HCon#5 HCon#8 HCon#9 HCon#10 HCon#11 HCon#12 HCon#13 HCon#14 HCon#15
I/Os CSD_ CSD_
ACT #0 ACT #1 ACT #2 ACT #3 DS #0 DS #1 DS #2 DS #3
SENSE SHIELD
csd.
cxpi. tcpwm.
cmod2pads csd. csd. scb[0].
P4.1 cxpi_ line_
csd. sense:38 shield:38 uart_tx:1
tx[0]:0 compl[4]:2
cmod2padd
csd.
cxpi.
cmod1pads csd. csd. scb[0]. tcpwm.
P4.0 cxpi_
csd. sense:39 shield:39 uart_rx:1 line[4]:2
rx[0]:0
cmod1padd
csd. csd.
P6.0 csd.s_pad[4]
sense:40 shield:40
hvss.pad_
LIN
lin_0
hvss.pad_
34

LIN
lin_1
hvss.pad_
VBAT
vbat_0
cxpi.
VirtLinEn lin.lin_
cxpi_
(P2.2)[6] en[1]
en[1]
cxpi.
VirtLinTxd lin.lin_ scb[0].
cxpi_
(P2.1)[6] tx[1] uart_tx:2
tx[1]
cxpi.
VirtLinRxd lin.lin_ scb[0].
cxpi_
(P2.0)[6] rx[1] uart_rx:2
rx[1]
Note
6. Internal connections to the integrated LIN/CXPI PHY.
002-33200 Rev. *G
2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Interrupts and wake-up assignments

5 Interrupts and wake-up assignments

Table 6 Peripheral interrupt assignments and wake-up sources

Interrupt Source Power Mode Description
NMI cpuss_nmi_sysreq_IRQn Active CPU NMI request
0 srss_interrupt_srss_IRQn DeepSleep SRSS global interrupts
1 srss_wdt_irq_IRQn DeepSleep Hardware watchdog timer interrupt
2 ioss_interrupt_gpio_IRQn DeepSleep GPIO consolidated interrupt
3 ioss_interrupts_gpio_0_IRQn DeepSleep GPIO port #0 interrupt
4 ioss_interrupts_gpio_1_IRQn DeepSleep GPIO port #1 interrupt
5 ioss_interrupts_gpio_2_IRQn DeepSleep GPIO port #2 interrupt
6 ioss_interrupts_gpio_3_IRQn DeepSleep GPIO port #3 interrupt
7 ioss_interrupts_gpio_4_IRQn DeepSleep GPIO port #4 interrupt
8 ioss_interrupts_gpio_5_IRQn DeepSleep GPIO port #5 interrupt
9 ioss_interrupts_gpio_6_IRQn DeepSleep GPIO port #6 interrupt
10 ioss_interrupts_gpio_7_IRQn DeepSleep GPIO port #7 Interrupt
11 hvss_interrupt_hvss_IRQn DeepSleep HVSS interface interrupt
12 lpcomp_0_interrupt_IRQn DeepSleep LPCOMP#0 trigger interrupt
13 Reserved Reserved
14 scb_0_interrupt_IRQn DeepSleep SCB#0 interrupt
15 scb_1_interrupt_IRQn DeepSleep SCB#1 interrupt
16 cpuss_interrupt_dma_IRQn Active DMA Interrupt
17 cpuss_interrupt_spcif_IRQn Active Flash controller#0 (flash) interrupt
18 cpuss_interrupt_fault_0_IRQn Active CPUSS fault structure #0 Interrupt
19 cpuss_interrupt_fault_1_IRQn Active CPUSS fault structure #1 Interrupt
20 lin_interrupts_0_IRQn Active LIN channel #0 Interrupt
21 lin_interrupts_1_IRQn Active LIN channel #1 Interrupt
22 tcpwm_interrupts_0_IRQn Active TCPWM counter#0 Interrupt
23 tcpwm_interrupts_1_IRQn Active TCPWM counter#1 Interrupt
24 tcpwm_interrupts_2_IRQn Active TCPWM counter#2 Interrupt
25 tcpwm_interrupts_3_IRQn Active TCPWM counter#3 Interrupt
26 tcpwm_interrupts_4_IRQn Active TCPWM counter#4 Interrupt
27 pass_interrupt_sar_IRQn Active SAR ADC consolidated interrupt
28 csd_interrupt_IRQn Active CAPSENSE™ block interrupt
29 cxpi_interrupts_0_IRQn Active CXPI interrupt, channel #0
30 cxpi_interrupts_1_IRQn Active CXPI interrupt, channel #1

Datasheet 35 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Peripheral clocks

6 Peripheral clocks

Table 7 Peripheral clock assignments

Output Destination Description
0 PCLK_SCB0_CLOCK SCB#0
1 PCLK_LIN_CLOCK_CH_EN0 LIN, Channel#0
2 PCLK_LIN_CLOCK_CH_EN1 LIN, Channel#1
3 PCLK_TCPWM_CLOCKS0 TCPWM counter #0
4 PCLK_TCPWM_CLOCKS1 TCPWM counter #1
5 PCLK_TCPWM_CLOCKS2 TCPWM counter #2
6 PCLK_TCPWM_CLOCKS3 TCPWM counter #3
7 PCLK_TCPWM_CLOCKS4 TCPWM counter #4
8 PCLK_SCB1_CLOCK SCB#1
9 PCLK_PRGIO_CLOCK_PRGIO_1 SMART/PROG I/O#1
10 PCLK_PRGIO_CLOCK_PRGIO_2 SMART/PROG I/O#2
11 PCLK_CSD_CLOCK_MSC CAPSENSE™ module clock
12 PCLK_CSD_CLOCK_SYNC CAPSENSE™ module sync clock
13 PCLK_PASS_CLOCK_SAR SAR ADC clock
14 PCLK_CXPI_CLOCK_CH_EN0 CXPI, channel #0
15 PCLK_CXPI_CLOCK_CH_EN1 CXPI, channel #1

6.1 Peripheral clock dividers

Table 8 Peripheral clock dividers

Type Number/Quantity Description
div_16 6 Integer divider, 16 bits
div_16_5 6 Fractional divider, 16.5 bits (16 integer bits, 5 fractional bits).

Datasheet 36 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Fault assignments

7 Fault assignments

Table 9 Fault assignments

Fault Source Description
System memory controller 0 correctable ECC violation:
0 cpuss.fault_ramc_c_ecc DATA0[31:0]: Violating address.
DATA1[6:0]: Syndrome of 32-bit SRAM code word.
System memory controller 0 non-correctable ECC violation.
1 cpuss.fault_ramc_nc_ecc
See cpuss.fault_ramc_c_ecc description.
Flash controller 0 correctable ECC violation
4 cpuss.fault_flashc_c_ecc DATA0[31:0]: Violating address
DATA1[7:0]: Syndrome of 64-bit FLASH code word.
Flash controller 0 non-correctable ECC violation.
5 cpuss.fault_flashc_nc_ecc
See cpuss.fault_flashc_nc_ecc description.
Flash controller 0 Bus Error
DATA0[31:0]: Violating address
DATA1[[9:8]: Master identifier
6 cpuss.fault_flashc_bus_err
DATA1[29]: ‘1’ = Protection Violation
DATA1[30]: ‘1’ = Memory Hole
DATA1[31]: ‘1’ = Flash Read during Write operation
Fault output for CRWDT
DATA0[0]: CRWDT LOWER_LIMIT
10 srss.fault_crwdt
DATA0[1]: CRWDT UPPER_LIMIT
DATA0[2]: CRWDT WARN_LIMIT
Fault output for HVREG
11 hvss.fault_pwr
DATA[0]: HVREG power not good

Datasheet 37 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Trigger multiplexer

8 Trigger multiplexer
8.1 Trigger group inputs

Table 10 Trigger group inputs

Input Source Description
GP_DMA_Requests: DMA request assignments
1 cpuss.dmac_tr_out[0]:0 Chaining dmac channel #0
2 cpuss.dmac_tr_out[1]:0 Chaining dmac channel #1
3 cpuss.dmac_tr_out[2]:0 Chaining dmac channel #2
4 cpuss.dmac_tr_out[3]:0 Chaining dmac channel #3
5 cpuss.dmac_tr_out[4]:0 Chaining dmac channel #4
6 cpuss.dmac_tr_out[5]:0 Chaining dmac channel #5
7 cpuss.dmac_tr_out[6]:0 Chaining dmac channel #6
8 cpuss.dmac_tr_out[7]:0 Chaining dmac channel #7
9 cpuss.tr_fault[0]:0 Fault structure output #0
10 cpuss.tr_fault[1]:0 Fault structure output #1
11 tcpwm.tr_overflow[0]:0 TCPWM overflow, counter #0
12 tcpwm.tr_overflow[1]:0 TCPWM overflow, counter #1
13 tcpwm.tr_overflow[2]:0 TCPWM overflow, counter #2
14 tcpwm.tr_overflow[3]:0 TCPWM overflow, counter #3
15 tcpwm.tr_overflow[4]:0 TCPWM overflow, counter #4
16 tcpwm.tr_underflow[0]:0 TCPWM underflow, counter #0
17 tcpwm.tr_underflow[1]:0 TCPWM underflow, counter #1
18 tcpwm.tr_underflow[2]:0 TCPWM underflow, counter #2
19 tcpwm.tr_underflow[3]:0 TCPWM underflow, counter #3
20 tcpwm.tr_underflow[4]:0 TCPWM underflow, counter #4
21 tcpwm.tr_compare_match[0]:0 TCPWM compare, counter #0
22 tcpwm.tr_compare_match[1]:0 TCPWM compare, counter #1
23 tcpwm.tr_compare_match[2]:0 TCPWM compare, counter #2
24 tcpwm.tr_compare_match[3]:0 TCPWM compare, counter #3
25 tcpwm.tr_compare_match[4]:0 TCPWM compare, counter #4
26 scb[0].tr_tx_req:0 SCB #0 TX request
27 scb[0].tr_rx_req:0 SCB #0 RX request
28 scb[1].tr_tx_req:0 SCB #1 TX request
29 scb[1].tr_rx_req:0 SCB #1 RX request
30 pass.dsi_sar_sample_done:0 PASS Data Valid
31 pass.tr_sar_out:0 PASS SAR EOC
32 peri.virt_in_0:0 GPIO input trigger #0
33 peri.virt_in_1:0 GPIO input trigger #1
34 peri.virt_in_2:0 GPIO input trigger #2
35 peri.virt_in_3:0 GPIO input trigger #3

Datasheet 38 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Trigger multiplexer

Table 10 Trigger group inputs (continued)

Input Source Description
36 csd.tr_wr_req_out:0 MSCv3 Request DMA write
37 csd.tr_rd_req_out:0 MSCv3 Request DMA Read
38 lpcomp[0].comp_out[0]:2 LPCOMP#0, Output#0
39 lpcomp[0].comp_out[1]:2 LPCOMP#0, Output#1
40 Reserved Reserved
41 Reserved Reserved
42 cxpi.tr_tx_req[0]:0 CXPI TX Trigger #0
43 cxpi.tr_tx_req[1]:0 CXPI TX Trigger #1
44 cxpi.tr_rx_req[0]:0 CXPI RX Trigger #0
45 cxpi.tr_rx_req[1]:0 CXPI RX Trigger #1
TCPWM Triggers: Trigger sources for TCPWM
1 cpuss.dmac_tr_out[0]:1 Chaining dmac channel #0
2 cpuss.dmac_tr_out[1]:1 Chaining dmac channel #1
3 cpuss.dmac_tr_out[2]:1 Chaining dmac channel #2
4 cpuss.dmac_tr_out[3]:1 Chaining dmac channel #3
5 cpuss.dmac_tr_out[4]:1 Chaining dmac channel #4
6 cpuss.dmac_tr_out[5]:1 Chaining dmac channel #5
7 cpuss.dmac_tr_out[6]:1 Chaining dmac channel #6
8 cpuss.dmac_tr_out[7]:1 Chaining dmac channel #7
9 cpuss.tr_fault[0]:1 Fault structure output #0
10 cpuss.tr_fault[1]:1 Fault structure output #1
11 tcpwm.tr_overflow[0]:1 TCPWM overflow, counter #0
12 tcpwm.tr_overflow[1]:1 TCPWM overflow, counter #1
13 tcpwm.tr_overflow[2]:1 TCPWM overflow, counter #2
14 tcpwm.tr_overflow[3]:1 TCPWM overflow, counter #3
15 tcpwm.tr_overflow[4]:1 TCPWM overflow, counter #4
16 tcpwm.tr_underflow[0]:1 TCPWM underflow, counter #0
17 tcpwm.tr_underflow[1]:1 TCPWM underflow, counter #1
18 tcpwm.tr_underflow[2]:1 TCPWM underflow, counter #2
19 tcpwm.tr_underflow[3]:1 TCPWM underflow, counter #3
20 tcpwm.tr_underflow[4]:1 TCPWM underflow, counter #4
21 tcpwm.tr_compare_match[0]:1 TCPWM compare, counter #0
22 tcpwm.tr_compare_match[1]:1 TCPWM compare, counter #1
23 tcpwm.tr_compare_match[2]:1 TCPWM compare, counter #2
24 tcpwm.tr_compare_match[3]:1 TCPWM compare, counter #3
25 tcpwm.tr_compare_match[4]:1 TCPWM compare, counter #4
26 scb[0].tr_tx_req:1 SCB #0 TX request
27 scb[0].tr_rx_req:1 SCB #0 RX request
28 scb[1].tr_tx_req:1 SCB #1 TX request
29 scb[1].tr_rx_req:1 SCB #1 RX request

Datasheet 39 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Trigger multiplexer

Table 10 Trigger group inputs (continued)

Input Source Description
30 pass.dsi_sar_sample_done:1 PASS Data Valid
31 pass.tr_sar_out:1 PASS SAR EOC
32 peri.virt_in_0:1 GPIO input trigger #0
33 peri.virt_in_1:1 GPIO input trigger #1
34 peri.virt_in_2:1 GPIO input trigger #2
35 peri.virt_in_3:1 GPIO input trigger #3
36 lpcomp[0].comp_out[0]:0 LPCOMP#0, Output#0
37 lpcomp[0].comp_out[1]:0 LPCOMP#0, Output#1
38 Reserved Reserved
39 Reserved Reserved
40 cxpi.tr_tx_req[0]:1 CXPI TX Trigger #0
41 cxpi.tr_tx_req[1]:1 CXPI TX Trigger #1
42 cxpi.tr_rx_req[0]:1 CXPI RX Trigger #0
43 cxpi.tr_rx_req[1]:1 CXPI RX Trigger #1
PASS Triggers: Trigger sources for PASS conversions
1 tcpwm.tr_overflow[0]:2 TCPWM overflow, counter #0
2 tcpwm.tr_overflow[1]:2 TCPWM overflow, counter #1
3 tcpwm.tr_overflow[2]:2 TCPWM overflow, counter #2
4 tcpwm.tr_overflow[3]:2 TCPWM overflow, counter #3
5 tcpwm.tr_overflow[4]:2 TCPWM overflow, counter #4
6 tcpwm.tr_underflow[0]:2 TCPWM underflow, counter #0
7 tcpwm.tr_underflow[1]:2 TCPWM underflow, counter #1
8 tcpwm.tr_underflow[2]:2 TCPWM underflow, counter #2
9 tcpwm.tr_underflow[3]:2 TCPWM underflow, counter #3
10 tcpwm.tr_underflow[4]:2 TCPWM underflow, counter #4
11 tcpwm.tr_compare_match[0]:2 TCPWM compare, counter #0
12 tcpwm.tr_compare_match[1]:2 TCPWM compare, counter #1
13 tcpwm.tr_compare_match[2]:2 TCPWM compare, counter #2
14 tcpwm.tr_compare_match[3]:2 TCPWM compare, counter #3
15 tcpwm.tr_compare_match[4]:2 TCPWM compare, counter #4
16 peri.virt_in_0:2 GPIO input trigger #0
17 peri.virt_in_1:2 GPIO input trigger #1
18 peri.virt_in_2:2 GPIO input trigger #2
19 peri.virt_in_3:2 GPIO input trigger #3
20 pass.dsi_sar_sample_done:2 PASS Data Valid
21 pass.tr_sar_out:2 PASS SAR EOC
22 lpcomp[0].comp_out[0]:1 LPCOMP#0, Output#0
23 lpcomp[0].comp_out[1]:1 LPCOMP#0, Output#1
24 Reserved Reserved
25 Reserved Reserved

Datasheet 40 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Trigger multiplexer

Table 10 Trigger group inputs (continued)

Input Source Description
LIN Triggers: Trigger sources for LIN
1 tcpwm.tr_compare_match[0]:3 TCPWM compare, counter #0
2 tcpwm.tr_compare_match[1]:3 TCPWM compare, counter #1
3 tcpwm.tr_compare_match[2]:3 TCPWM compare, counter #2
4 tcpwm.tr_compare_match[3]:3 TCPWM compare, counter #3
5 tcpwm.tr_compare_match[4]:3 TCPWM compare, counter #4
6 peri.virt_in_0:3 GPIO input trigger #0
7 peri.virt_in_1:3 GPIO input trigger #1
8 peri.virt_in_2:3 GPIO input trigger #2
9 peri.virt_in_3:3 GPIO input trigger #3
CSD Triggers: Trigger sources for CSD
1 cpuss.dmac_tr_out[0]:2 DMA trigger output
2 cpuss.dmac_tr_out[1]:2 DMA trigger output
3 cpuss.dmac_tr_out[2]:2 DMA trigger output
4 cpuss.dmac_tr_out[3]:2 DMA trigger output
5 cpuss.dmac_tr_out[4]:2 DMA trigger output
6 cpuss.dmac_tr_out[5]:2 DMA trigger output
7 cpuss.dmac_tr_out[6]:2 DMA trigger output
8 cpuss.dmac_tr_out[7]:2 DMA trigger output
CXPI Triggers: Trigger sources for CXPI
1 tcpwm.tr_compare_match[0]:4 TCPWM compare, counter #0
2 tcpwm.tr_compare_match[1]:4 TCPWM compare, counter #1
3 tcpwm.tr_compare_match[2]:4 TCPWM compare, counter #2
4 tcpwm.tr_compare_match[3]:4 TCPWM compare, counter #3
5 tcpwm.tr_compare_match[4]:4 TCPWM compare, counter #4
6 peri.virt_in_0:4 GPIO input trigger #0
7 peri.virt_in_1:4 GPIO input trigger #1
8 peri.virt_in_2:4 GPIO input trigger #2
9 peri.virt_in_3:4 GPIO input trigger #3

Datasheet 41 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Trigger multiplexer

8.2 Trigger group outputs

Table 11 Trigger group outputs

Output Destination Description
GP_DMA_Requests: DMA request assignments
0 cpuss.dmac_tr_in[0] Triggers to DMA #0
1 cpuss.dmac_tr_in[1] Triggers to DMA #1
2 cpuss.dmac_tr_in[2] Triggers to DMA #2
3 cpuss.dmac_tr_in[3] Triggers to DMA #3
4 cpuss.dmac_tr_in[4] Triggers to DMA #4
5 cpuss.dmac_tr_in[5] Triggers to DMA #5
6 cpuss.dmac_tr_in[6] Triggers to DMA #6
7 cpuss.dmac_tr_in[7] Triggers to DMA #7
TCPWM Triggers: Trigger sources for TCPWM
0 tcpwm.tr_in[4] TCPWM global triggers #4 (triggers 0–3 are in HSIOM table)
1 tcpwm.tr_in[5] TCPWM global triggers #5
2 tcpwm.tr_in[6] TCPWM global triggers #6
3 tcpwm.tr_in[7] TCPWM global triggers #7
4 tcpwm.tr_in[8] TCPWM global triggers #8
5 tcpwm.tr_in[9] TCPWM global triggers #9
6 tcpwm.tr_in[10] TCPWM global triggers #10
7 tcpwm.tr_in[11] TCPWM global triggers #11
8 tcpwm.tr_in[12] TCPWM global triggers #12
9 tcpwm.tr_in[13] TCPWM global triggers #13
PASS Triggers: Trigger sources for PASS conversions
0 pass.tr_sar_in General PASS triggers (Triggers 0–1 are in HSIOM table)
LIN Triggers: Trigger sources for LIN
0 lin.tr_cmd_tx_header[0] LIN timed trigger, channel #0
1 lin.tr_cmd_tx_header[1] LIN timed trigger, channel #1
CSD Triggers: Trigger sources for CSD
0 csd.tr_wr_req_in CSD(MSCv3) Trigger write input
1 csd.tr_rd_req_in CSD(MSCv3) Trigger read input
CXPI Triggers: Trigger sources for CXPI
0 cxpi.tr_cmd_tx_header[0] CXPI timed trigger, channel #0
1 cxpi.tr_cmd_tx_header[1] CXPI timed trigger, channel #1

Datasheet 42 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9 Electrical specifications
9.1 Absolute maximum ratings
Within the maximum ratings, no damage shall occur. Parametric and device functionality may deviate from
specifications. All analog voltages are relative to VSSA and all digital voltages are relative to VSSD. A negative
current if flowing out of a pin, and positive current into a pin.

Table 12 Absolute maximum ratings

Spec ID# Parameter Description Min Typ Max Units Details/conditions
HBM ESD on all pins except
SIDA1 VESDHBM ±2000 – – V
VBAT, LIN/CXPI
As per ISO10605.
With required
external protection
ESD on LIN/CXPI, VBAT, and
SIDA2 VESDHV ±8000 – – V as per the
GPIO
guidelines in the
“ESD protection”
on page 23.
SIDA3 VESDCDMCOR CDM ESD on corner pins ±750 – – V
SIDA4 VESDCDM CDM ESD on non-corner pins ±500 – – V
SIDA5 VBAT Supply voltage VBAT[7] –0.3 – 42 V Refer Note 8.
[7]
SIDA10 VLIN LIN/CXPI pin voltage –27 – 42 V
[7]
SIDA11 ILIN LIN/CXPI pin current – – 200 mA
SIDA12 VGPIO GPIO pin input voltage –0.5 – VDDD + 0.5 V
SIDA13 VDDA, VDDD VDDA, VDDD supply voltage –0.3 – 5.5 V
[9]
SIDA13A IBATABS VBAT supply current – – 160 mA Refer Note 8.
VBAT supply current,
SIDA13B IBATABSDC – – 60 mA Refer Note 8.
long-term average
SIDA14 VCCD VCCD core supply voltage –0.3 – 1.95 V
SIDA16 IGPIO Current per GPIO pin –20 – 20 mA
SIDA18 TA Ambient temperature –40 – 125 °C
SIDA19 TS Storage temperature –55 – 125 °C
SIDA20 TJ Junction temperature –40 – 150 °C
SIDA21 Life time 15 – – Years
SIDA22 Storage time 5 – – Years TA = 55°C, 85% r.H.
SIDA23 Storage time 15 – – Years TA = 40°C, 80% r.H.
Notes
7. To prevent damage caused by high-voltage pulses, external protection (that is, series resistor, diode, TVS)
may be required. To allow a minimum system level supply voltage of 4.5 V, external protection circuits
including reverse protection diodes are designed in a way that guarantees the device minimum functional
voltage VBAT of at least 3.6 V.
8. Conditions of VBAT and current consumption must guarantee that maximum power dissipation is always
below 1 W.
9. Absolute max current includes inrush / transient current during power-up.
10.Current limited to prevent thermal runaway and catastrophic part damage. If junction temperature exceeds
limits in SIDA20, part operation is not guaranteed and part reliability might get affected.
11.60 minutes is cumulative and applies only when the local transmitter is enabled and driving dominant state
onto the LIN bus. Part testing is performed for 60 minutes with LIN driving dominant state continuously.

Datasheet 43 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

Table 12 Absolute maximum ratings (continued)

Spec ID# Parameter Description Min Typ Max Units Details/conditions
Short circuit tolerance time: – – 60 min VBAT: 3.6 V to 28 V
SID24 tSCVHVREG
HVREG[10] – – 500 ms VBAT: 28 V to 42 V
VBAT = LIN: 3.6 V to
– – 60[11] min
28 V
SID24A tSCLIN Short circuit tolerance: LIN
VBAT = LIN: 28 V to
– – 500 ms
42 V
Notes
7. To prevent damage caused by high-voltage pulses, external protection (that is, series resistor, diode, TVS)
may be required. To allow a minimum system level supply voltage of 4.5 V, external protection circuits
including reverse protection diodes are designed in a way that guarantees the device minimum functional
voltage VBAT of at least 3.6 V.
8. Conditions of VBAT and current consumption must guarantee that maximum power dissipation is always
below 1 W.
9. Absolute max current includes inrush / transient current during power-up.
10.Current limited to prevent thermal runaway and catastrophic part damage. If junction temperature exceeds
limits in SIDA20, part operation is not guaranteed and part reliability might get affected.
11.60 minutes is cumulative and applies only when the local transmitter is enabled and driving dominant state
onto the LIN bus. Part testing is performed for 60 minutes with LIN driving dominant state continuously.

Unless otherwise noted, functionality and parameters are valid over operating voltage and temperature range.
All analog voltages are relative to VSSA, all digital voltages are relative to VSSD. A negative current if flowing out of
a pin, and positive current into a pin.

Table 13 Operating conditions

Spec ID# Parameter Description Min Typ Max Units Details/conditions
SID1 VBAT Supply voltage VBAT 3.6 – 28 V
VBAT range for LIN LIN2.2A spec
SID2 VBAT_LIN 7 – 18 V
communications Parameter#10
VBAT range for LIN Extended LIN2.2A
SID2A VBAT_LIN_EXT 6 – 28 V
communications[12] spec Parameter#10
SID5 VLIN LIN output voltage 6 – 28 V

SID6 RLIN_PU LIN pull-up resistor 20 30 47 kΩ

GPIO input voltage range
SID9A VINGPIO –0.3 – VDDIO + 0.3 V
(digital)
SID10 TA Ambient temperature range –40 – 125 °C

SID11 fCPU CPU operating frequency 0 – 48 MHz

Note
12.The LIN interface should only be active when the supply voltage is within VBAT_LIN. Outside VBAT_LIN,
the LIN module will not interfere with bus communications (will not block the bus with a dominant bit).
LIN v2.2A specifications are based on 7 V ≤ VBAT ≤ 18 V; the AC/DC behavior can change for 6 V ≤ VBAT < 7 V,
and 18 V < VBAT < 28 V.

Datasheet 44 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.2 Device-level specifications

Unless otherwise noted, functionality and parameters are valid over operating conditions and lifetime (range of
functionality). All analog voltages are relative to VSSA, digital voltages are relative to VSSD. A negative current is
flowing out of a pin, positive current into a pin.

Datasheet 45 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.2.1 Operating current and wakeup times

Table 14 Operating current and wakeup times
Spec ID# Parameter Description Min Typ Max Units Details/conditions
Average supply current IMO = 48 MHz,
IBAT_ACTIVE_
SID12 in active mode without – 5 10 mA HFCLK = IMO/2,
NoPERI_24MHz any peripherals CPU Core only
Clocks:
IMO = 48 MHz
HFCLK = IMO/2
SYSCLK = HFCLK
SRSS PUMP Clock =
Disabled

TCPWM: 1 counter
enabled

LIN: 20 kHz,
25% active
dominant,
25% active
recessive,
50% standby

SAR: Enabled and

continuously
Average supply current converting
IBAT_ACTIVE_
SID12A in active mode with – – 14 mA Sample rate =
PERI_24MHz peripherals 666.7 Ksps

MSC: One self-cap

button scanned
continuously

CPU: void main()

{int i = 1; while(1)
{i = i + 1; i = i + 2;
i = i + 3; i = i + 4;
i = i + 5;}}
Designed to
provide constant
activity + code flash
access, not
absolute worst
case CPU current
Prefetch enabled,
flash wait states = 1
for 24.576 MHz [13]
Notes
13.PSOC™ 4 power mode = sleep; CPU powered down, all other high- and low-speed clocks are active;
peripherals off, DMA inactive, RAM retained.
14.PSOC™ 4 power mode = deepsleep; CPU powered down, high-speed clocks and peripherals off, low-speed
clocks active; all RAM and registers except internal CPU registers retained; LIN and watchdog timers active;
periodic CapSense wake-up every 100 ms with ‘y’ ms for scan & processing a self-cap button (‘z’ pF).
15.Same as SID15-15C (PSOC™ 4 power mode = deepsleep) but without any periodic wake-up.

Datasheet 46 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

Table 14 Operating current and wakeup times (continued)

Spec ID# Parameter Description Min Typ Max Units Details/conditions
Average supply current IMO = 48 MHz,
IBAT_ACTIVE_
SID13 in active mode without – – 12 mA HFCLK = IMO,
NoPERI_48MHz any peripherals CPU Core only
Clocks:
IMO = 48 MHz
HFCLK = IMO
SYSCLK = HFCLK
SRSS PUMP Clock =
Disabled

TCPWM: 1 counter
enabled

LIN: 20 kHz,
25% active
dominant,
25% active
recessive,
50% standby

SAR: Enabled and

continuously
Average supply current converting
IBAT_ACTIVE_
SID13A in active mode with – – 20 mA Sample rate =
PERI_48MHz peripherals 666.7 Ksps

MSC: One self-cap

button scanned
continuously

CPU: void main()

{int i = 1; while(1)
{i = i + 1; i = i + 2;
i = i + 3; i = i + 4;
i = i + 5;}}
Designed to
provide constant
activity + code flash
access, not
absolute worst
case CPU current
Prefetch enabled,
flash wait states = 1
for 24.576 MHz [13]
Notes
13.PSOC™ 4 power mode = sleep; CPU powered down, all other high- and low-speed clocks are active;
peripherals off, DMA inactive, RAM retained.
14.PSOC™ 4 power mode = deepsleep; CPU powered down, high-speed clocks and peripherals off, low-speed
clocks active; all RAM and registers except internal CPU registers retained; LIN and watchdog timers active;
periodic CapSense wake-up every 100 ms with ‘y’ ms for scan & processing a self-cap button (‘z’ pF).
15.Same as SID15-15C (PSOC™ 4 power mode = deepsleep) but without any periodic wake-up.

Datasheet 47 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

Table 14 Operating current and wakeup times (continued)

Spec ID# Parameter Description Min Typ Max Units Details/conditions
Clocks:
IMO = 48 MHz
HFCLK = IMO
Average supply current SYSCLK = HFCLK
SID14 IBAT_NOCPU with CPU in Sleep – 2 – mA SRSS PUMP Clock =
mode[13] Disabled

Peripherals =
Disabled
Average supply current
IBAT_DPSLP_ in DeepSleep mode
SID15 – 25 33 µA TA = 25°C
WKUP_25C with periodic timer
[14]
wakeup
Average supply current
IBAT_DPSLP_ in DeepSleep mode
SID15A – 35 80 µA TA = 65°C
WKUP_65C with periodic timer
[14]
wakeup
Average supply current
IBAT_DPSLP_ in DeepSleep mode
SID15B – 50 155 µA TA = 85°C
WKUP_85C with periodic timer
[14]
wakeup
Average supply current
IBAT_DPSLP_ in DeepSleep mode
SID15D – 100 450 µA TA = 105°C
WKUP_105C with periodic timer
wakeup
Average supply current
IBAT_DPSLP_ in DeepSleep mode
SID15C – 195 740 µA TA = 125°C
WKUP_125C with periodic timer
wakeup[14]
Average current in
IBAT_DPSLP_ DeepSleep mode
SID17 – 25 31 µA TA = 25°C
NoWKUP_25C without any periodic
wakeup[15]
IBAT_ Average current in
DPSLP_ DeepSleep mode
SID17A – 30 80 µA TA = 65°C
NoWKUP_ without any periodic
65C wakeup[15]
IBAT_ Average current in
DPSLP_ DeepSleep mode
SID17B – 45 155 µA TA = 85°C
NoWKUP_ without any periodic
85C wakeup[15]
Notes
13.PSOC™ 4 power mode = sleep; CPU powered down, all other high- and low-speed clocks are active;
peripherals off, DMA inactive, RAM retained.
14.PSOC™ 4 power mode = deepsleep; CPU powered down, high-speed clocks and peripherals off, low-speed
clocks active; all RAM and registers except internal CPU registers retained; LIN and watchdog timers active;
periodic CapSense wake-up every 100 ms with ‘y’ ms for scan & processing a self-cap button (‘z’ pF).
15.Same as SID15-15C (PSOC™ 4 power mode = deepsleep) but without any periodic wake-up.

Datasheet 48 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

Table 14 Operating current and wakeup times (continued)

Spec ID# Parameter Description Min Typ Max Units Details/conditions
IBAT_D- Average supply current
PSLP_ in DeepSleep mode
SID17D – 95 450 µA TA = 105°C
NoWKUP_10 without any periodic
5C wakeup
IBAT_ Average current in
DPSLP_ DeepSleep mode
SID17C – 185 750 µA TA = 125°C
NoWKUP_ without any periodic
125C wakeup[15]
Current with XRES_L
SID19 IBAT_XRES – 80 – µA XRES_L input low
low
XRES_L or POR
release
Start time from reset
SID20 tSTARTUP – – 8 ms Includes the ROM
release
boot time and the
SWD listen window.
Wakeup from Sleep sysclock
SID21 tSLEEP – – 6
power mode cycles
Wakeup from
SID22 tDEEPSLEEP – – 35 µs
DeepSleep power mode
Notes
13.PSOC™ 4 power mode = sleep; CPU powered down, all other high- and low-speed clocks are active;
peripherals off, DMA inactive, RAM retained.
14.PSOC™ 4 power mode = deepsleep; CPU powered down, high-speed clocks and peripherals off, low-speed
clocks active; all RAM and registers except internal CPU registers retained; LIN and watchdog timers active;
periodic CapSense wake-up every 100 ms with ‘y’ ms for scan & processing a self-cap button (‘z’ pF).
15.Same as SID15-15C (PSOC™ 4 power mode = deepsleep) but without any periodic wake-up.

Datasheet 49 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.2.2 Voltage regulators

Table 15 Voltage regulators

Spec ID# Parameter Description Min Typ Max Units Details/conditions
5 V output voltage
SID.HVREG1 VDDX setting, 4.9 5 5.1 V
VBAT > 6 V
5 V output voltage
SID.HVREG2 VDDX setting, 4.5 5 5.15 V
6 V ≥ VBAT ≥ 5.5 V
3.3 V output voltage
SID.HVREG4 VDDX setting, 3.234 3.3 3.366 V
VBAT > 4.3 V
3.3 V output voltage
SID.HVREG5 VDDX setting, 2.7 – 3.39 V
4.3 V ≥ VBAT ≥ 3.6 V
Typical internal
loads = 30 mA +
SID.HVREG6 IDDD Digital regulator current – – 60 mA
external loads from
VDDD = 30 mA
6 V ≤ VBAT ≤ 28 V;
SID. Maximum VDDD load –40°C ≤ T ≤ 125°C;
IDDD_TRANS – – 90 mA
HVREG6B transient current Max transient
duration t = 200 ms
SID.HVREG7 VCCD Core regulator voltage 1.75 1.8 1.95 V
Not to be used
SID.HVREG8 ICCD Core regulator current – – 30 mA
off-chip
Thermal shutdown
Guaranteed by
SID.HVREG9 TSDJT trigger junction 175 – 235 °C
design
temperature
Thermal shutdown
SID. Guaranteed by
TSDJ release junction 160 – 222 °C
HVREG10 design
temperature

Datasheet 50 002-33200 Rev. *G

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.3 GPIO

Table 16 GPIO DC specifications

Spec ID# Parameter Description Min Typ Max Units Details/conditions
Input voltage high
SID.GPIO.1 VIH 0.7 × VDDIO – – V CMOS input
threshold
Input voltage low
SID.GPIO.2 VIL – – 0.3 × VDDIO V CMOS input
threshold
LVTTL input,
SID.GPIO.3 VIH – – 2 V
VDDIO > 2.7 V
LVTTL input,
SID.GPIO.4 VIL – – 0.8 V
VDDIO > 2.7 V
IOH = –4 mA |
Output voltage high VDDIO 3 V
SID.GPIO.5 VOH VDDIO – 0.45 – – V
level IOH = –1 mA |
2.7 V VDDIO < 3 V
Output voltage low IOL = 10 mA |
SID.GPIO.6 VOL – – 0.45 V
level VDDIO  2.7 V
SID.GPIO.7 RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ
SID.GPIO.8 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 kΩ
Input leakage current TA = 25°C,
SID.GPIO.9 IIL – 2 – nA
(absolute value) VDDIO = 3.0 V
Input leakage current TJ = 150°C,
SID.GPIO.10 IIL – – 1 µA
(absolute value) VDDIO = 3.0 V
SID.GPIO.11 CIN Input capacitance – – 10 pF
Input hysteresis LVTTL
SID.GPIO.12 VHYSTTL 25 40 – mV
VDDIO > 2.7 V
SID.GPIO.13 VHYSCMOS Input hysteresis CMOS 0.05 × VDDIO – – V
Current through
Input = VDDIO + 0.5 V
SID.GPIO.14 IDIODE protection diode to – – 100 µA
or VSSD – 0.5 V
VDDIO/VSSD
Total sum of GPIO
Maximum total source
SID.GPIO.15 ITOT_GPIO – – 60 mA source or sink
or sink chip current[16]
current.
Note
16.Actual maximum GPIO current allowed is application dependent, and must be included in a total application
current budget that meets the HV Regulator maximum allowed current spec.

Datasheet 51 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

Table 17 GPIO AC specifications

Spec ID# Parameter Description Min Typ Max Units Details/conditions
Rise time 3.3-V VDDIO,
SID.GPIO.16 tRISEF 1.5 – 10 ns
in fast strong mode CLOAD = 25 pF
Fall time 3.3-V VDDIO,
SID.GPIO.17 tFALLF 1.5 – 10 ns
in fast strong mode CLOAD = 25 pF
Rise time 3.3-V VDDIO,
SID.GPIO.18 tRISES 10 – 60 ns
in slow strong mode CLOAD = 25 pF
Fall time 3.3-V VDDIO,
SID.GPIO.19 tFALLS 10 – 60 ns
in slow strong mode CLOAD = 25 pF
GPIO fan out; 90/10%,
SID.GPIO.20 fGPIOUTF 3.3 V  VDDIO  5.15 V. – – 33 MHz 25-pF load,
fast strong mode. 60/40 duty cycle
GPIO fan out; 90/10%,
SID.GPIO.21 fGPIOUTS 3.3 V  VDDIO  5.15 V. – – 7 MHz 25-pF load,
slow strong mode. 60/40 duty cycle
GPIO input operating
SID.GPIO.22 fGPIOIN frequency; – – 48 MHz 90/10% VDDIO
2.7 V  VDDIO  5.15 V

Datasheet 52 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.3.1 SMART/PROG I/O specifications

Table 18 SMART/PROG I/O specifications

Spec ID# Parameter Description Min Typ Max Units Details/conditions
SMART/PRG I/O
SID.PRGIO.1 fCLK_PRGIO peripheral clock – – 48 MHz
frequency
Setup time of I/O[7:0]
SID.PRGIO.2 tPRGIO_SETUP with respect 15 – – ns
to the clock edge
Hold time of I/O[7:0]
SID.PRGIO.3 tPRGIO_HOLD with respect 10 – – ns
to the clock edge
Propagation output
delay of I/O[7:0]
SID.PRGIO.4 tPRGIO_DELAY – – 50 ns CLOAD = 25 pF
with respect
to the clock edge
Skew between port
outputs that are driving
SID.PRGIO.6 tPRGIO_SKEW – – 3.5 ns
the same root signal
using fabric LUTs

9.3.2 XRES

Table 19 XRES DC specifications

Spec ID# Parameter Description Min Typ Max Units Details/conditions
SID.XRES.1 VIH Input voltage high threshold – – 0.7 × VDDIO V CMOS input
SID.XRES.2 VIL Input voltage low threshold – – 0.3 × VDDIO V CMOS input
SID.XRES.3 RPULLUP Pull-up resistor – 60 – kΩ
SID.XRES.4 CIN Input capacitance – – 7 pF
SID.XRES.5 VHYSXRES Input voltage hysteresis 135 – – mV
Input = VDDIO + 0.5 V
Current through protection
SID.XRES.6 IDIODE – – 100 µA or
diode to VDDD/VSSD
VSSIO – 0.5 V

Table 20 XRES AC specifications

Spec ID# Parameter Description Min Typ Max Units Details/conditions
SID.XRES.7 tRESETWIDTH Reset pulse width 1 – – µs
Wake-up time
SID.XRES.8 tRESETWAKE – – 8 ms
from reset release[17]

Note
17.Includes the ROM boot time and the SWD listen window.

Datasheet 53 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.3.3 Clocks

Table 21 Internal oscillators and clocks

Spec ID# Parameter Description Min Typ Max Units Details/conditions
SID53 fIMO IMO clock frequency[18] – 24 48 MHz
IMO frequency variation –45°C < TA < 130°C,
SID54 IMO_ACCY1 –3.0 – 3.0 %
(not locked to HPOSC) IMO = 48 MHz
IMO frequency variation –45°C < TA < 130°C,
SID55A IMO_ACCY_LKD –1.5 – 1.5 %
(locked to HPOSC) IMO = 48 MHz
Frequency high precision
SID56 fHPOSC – 2 – MHz
reference oscillator
HPOSC_ Precision 2-MHz reference
SID57 –1.0 – 1.0 %
ACCY oscillator
Precision Internal Low
SID58 fPILO – 32 – kHz
speed oscillator (PILO)[19]
PILO frequency variation
SID59 PILO_ACCY1 –7.0 – 7.0 %
(no periodic calibration)
PILO frequency variation
SID60 PILO_ACCY2 (with periodic –1.5 – 1.5 %
calibration)[20]

Notes
18.fIMO is factory trimmed and is user adjustable between 24 MHz (CY8C412x), and 48 MHz (CY8C414x) in 4-MHz
steps.
19.The PILO runs in all power modes and is used for low power interval timers and counters.
20.Periodic calibration - locked to HPOSC at least once per second during stop mode. Power required for
periodic calibration is included in average stop mode supply current (IBAT_STOP).

Datasheet 54 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.4 Analog
9.4.1 LIN transceiver

Table 22 LIN transceiver specifications[21]

Spec ID# Parameter Description Min Typ Max Units Details/conditions
LIN2.2A spec
SIDL63 IBUS_LIN LIN output current 40 – 200 mA
Parameter#12
Receiver dominant state
input leakage LIN2.2A spec
SIDL64 IBUS_PAS_DOM –1 – 0 mA
(Driver off; Parameter#13
VBUS = 0 V, VBAT = 12 V)
Receiver recessive state
input leakage
LIN2.2A spec
SIDL66 IBUS_PAS_REC (Driver off; – – 20 µA
Parameter#14
7 V < VBUS < 18 V,
7 V < VBAT < 18 V)
Loss of local ground
LIN2.2A spec
SIDL68 IBUS_NO_GND (VSSL = VBAT < 18 V, –1 – 1 mA
Parameter#15
7 V < VBUS < VBAT < 18 V)
Loss of battery power
LIN2.2A spec
SIDL70 IBUS_NO_BAT (VBAT disconnected, – – 30 µA
Parameter#16
7 V < VBUS < 18 V)
LIN2.2A spec
SIDL72 VBUS_DOM Receiver dominant state – – 0.4 V
Parameter#17
LIN2.2A spec
SIDL73 VBUS_REC Receiver recessive state 0.6 – – V
Parameter#18
LIN2.2A spec
SIDL74 VBUS_CNT Receiver center voltage 0.475 0.5 0.525 V
Parameter#19
LIN2.2A spec
SIDL75 VBUS_HYS Receiver hysteresis – – 0.175 V
Parameter#20
Bus transmitter recessive Not a LIN 2.2A
SIDL76 VOH VBAT – 2 – VBAT V
output voltage specification
Bus transmitter dominant
RL = 500 Ω
SIDL77 VOL output voltage – – 1.2 V
(IOL < 12 mA)
(VBAT = VBUS = 7 V)
Bus transmitter dominant
RL = 500 Ω
SIDL79 VOL output voltage – – 2 V
(IOL < 32 mA)
(VBAT = VBUS = 18 V)
Voltage drop at external LIN2.2A spec
SIDL81 VSER_DIODE 0.4 0.7 1 V
series diodes Parameter#21
LIN2.2A spec
Internal slave pull-up
SIDL82 RLIN_PU 20 30 47 kΩ Parameter#26
resistor[22]
(RSLAVE)
Internal pull-down resistor Not a LIN2.2A
SIDL83 RLIN_PD – 30 – kΩ
for diagnosis specification

Notes
21.LIN V2.2A specifications are based on VBAT = 18 V, the AC/DC behavior can change for 18 V < VBAT < 28 V.
22.LIN V2.2A specifies 20 k  RSLAVE  60 k. Infineon is specifying a lower maximum RSLAVE value of 47 k.

Datasheet 55 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

Table 22 LIN transceiver specifications[21] (continued)

Spec ID# Parameter Description Min Typ Max Units Details/conditions
LIN2.2A spec
Parameter#27
D1 =
tBUS_REC(min) /
SIDL84 D1 Duty cycle 1 (20 kbps) 0.396 – 0.581 –
(2 × tBIT)
for baud rate =
20 kbps
VBAT_LIN = 7 V to 18 V
LIN2.2A spec
Parameter#28
D2 =
tBUS_REC(max) /
SIDL85 D2 Duty cycle 2 (20 kbps) – – 0.581 – (2 × tBIT)
for baud rate =
20 kbps
VBAT_LIN =
7.6 V to 18 V
LIN2.2A spec
Parameter#29
D3 =
SIDL86 D3 Duty cycle 3 (10 kbps) 0.417 – 0.5 – tBUS_REC(min) /
(2 × tBIT)
for baud rate =
10.4 kbps
LIN2.2A spec
Parameter#30
D4 =
SIDL87 D4 Duty cycle 4 (10 kbps) – – 0.59 – tBUS_REC(max) /
(2 × tBIT)
for baud rate =
10.4 kbps
Propagation delay of LIN2.2A spec
SIDL88 tRX_PD – – 6 µs
receiver Parameter#31
Symmetry of receiver LIN2.2A spec
SIDL89 tRX_PD –2 – 2 µs
propagation delay Parameter#32
1 nF/1 kΩ,
SIDL90 tR Rise time 3.5 – 22.5 µs 6.8 nF/660 Ω,
10 nF/500 Ω
1 nF/1 kΩ,
SIDL91 tF Fall time 3.5 – 22.5 µs 6.8 nF/660 Ω,
10 nF/500 Ω
1 nF/1 kΩ,
Difference between rise time
SIDL92 tD(TR-TF) –4 – 4 µs 6.8 nF/660 Ω,
to fall time
10 nF/500 Ω
Baud rate for LIN 10 kbps
SIDL93 BR_LIN10K – 10 – kbps
mode

Notes
21.LIN V2.2A specifications are based on VBAT = 18 V, the AC/DC behavior can change for 18 V < VBAT < 28 V.
22.LIN V2.2A specifies 20 k  RSLAVE  60 k. Infineon is specifying a lower maximum RSLAVE value of 47 k.

Datasheet 56 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

Table 22 LIN transceiver specifications[21] (continued)

Spec ID# Parameter Description Min Typ Max Units Details/conditions
Baud rate for LIN 20 kbps
SIDL94 BR_LIN20K – 20 – kbps
mode
LIN2.2A
Baud rate for 100 kbps for
specifications are
SIDL95 BR_PROG fast program transfer – 100 – kbps
not applicable in
mode[23]
this mode

Notes
21.LIN V2.2A specifications are based on VBAT = 18 V, the AC/DC behavior can change for 18 V < VBAT < 28 V.
22.LIN V2.2A specifies 20 k  RSLAVE  60 k. Infineon is specifying a lower maximum RSLAVE value of 47 k.

Per LIN2.2A, comments reference appropriate LIN specification parameters. If no parameter is included in the
comment, this parameter is not a requirement of the LIN2.2A specification.

Datasheet 57 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.4.2 CXPI transceiver

Table 23 CXPI transceiver specifications (ISO 20794-4-2020 compliance)

Spec ID# Parameter Description Min Typ Max Units Details/conditions
DC specifications
Operating voltage
SID.CXPIT.1 VBAT 3.6 – 18 V Param#8
range
CXPI bus pin pull-up
SID.CXPIT.2 RCXPI_BUS_PU 20 30 47 kΩ
resistance
CXPI bus short circuit Param#10, for
SID.CXPIT.3 IBUS_LIM 40 – 200 mA
current VBUS = VBAT (max)
Param#11,
IBUS_PAS_ CXPI bus input leakage
SID.CXPIT.4 –1 – – mA VBUS = 0 V,
DOM current (LOW)
VBAT = 12 V
Param#12,
CXPI bus input leakage 8 V < VBAT < 18 V,
SID.CXPIT.5 IBUS_PAS_REC – – 20 µA
current (HIGH) 8 V < VBUS < 18 V,
VBUS > VBAT
Param#13,
CXPI bus leakage
VGND = VBAT,
SID.CXPIT.6 IBUS_NO_GND current for loss of –1 – 1 mA
0 V < VBUS < 18 V,
ground
VBAT = 12 V
Param#14,
CXPI bus leakage
VBAT disconnected,
SID.CXPIT.7 IBUS_NO_BAT current for loss of – – 30 µA
VBAT = VGND,
battery
0 V < VBUS < 18 V
Param#15,
VSHIFT_BAT =
VBATTERY –
VSHIFT_GND – VBAT
SID.CXPIT.8 VSHIFT_BAT Battery shift voltage 0 – 0.1 VBAT
VBATTERY = Voltage
of vehicle battery
Guaranteed by
Design
Param#16,
VSHIFT_GND = VGND –
VGND_BATTERY

SID.CXPIT.9 VSHIFT_GND GND shift voltage 0 – 0.1 VBAT VGND_BATTERY =

Voltage of vehicle
battery GND
Guaranteed by
Design
Param#17,
VSHIFT_GND =
Difference between
|VSHIFT_BAT –
SID.CXPIT.10 VSHIFT_DIFF battery shift and GND 0 – 0.08 VBAT
VSHIFT_GND|
shift voltage
Guaranteed by
Design

Datasheet 58 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+

Table 23 CXPI transceiver specifications (ISO 20794-4-2020 compliance) (continued)

Spec ID# Parameter Description Min Typ Max Units Details/conditions
VTXD = 0 V,
VBAT = 7 V,
SID.CXPIT.11 – – 1.4 V
Bus pull-up
CXPI bus low level resistance = 500 Ω
VO_DOM
output voltage VTXD = 0 V,
VBAT = 18 V,
SID.CXPIT.12 – – 2 V
Bus pull-up
resistance = 500 Ω
Receiver dominant
SID.CXPIT.13 VBUS_DOM state (low level) – – 0.423 VBAT Param#18
threshold voltage
Receiver recessive state
SID.CXPIT.14 VBUS_REC (high level) threshold 0.556 – – VBAT Param#19
voltage
Param#20,
Receiver center
VBUS_CNT =
SID.CXPIT.15 VBUS_CNT recessive threshold 0.475 0.5 0.525 VBAT
(VTH_DOM + VTH_REC)
voltage
/2
Hysteresis voltage
between the recessive Param#21,
SID.CXPIT.16 VHYS threshold voltage and – – 0.133 VBAT VHYS =
the dominant threshold VTH_REC – VTH_DOM
voltage of the receiver
AC specifications
Param#30, CXPI
network load
condition
(CBUS = 1 nF,
Duty cycle of LOW level
RBUS = 1 kΩ,
of logical value ‘1’ for
tBIT = 50 µs,
DTX_1_LO_ dominant threshold
SID.CXPIT.17 11 – – % tTX_PWM_LO =
DOM voltage of the driver
13.75 µs,
node,
VTHTX_DOM =
VTHTX_DOM = 30% of VBAT
0.3 × VBAT)

DTX_1_LO_DOM =
tTX_1_LO_DOM/tBIT

Datasheet 59 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

Table 23 CXPI transceiver specifications (ISO 20794-4-2020 compliance) (continued)

Spec ID# Parameter Description Min Typ Max Units Details/conditions
Param#31,
CXPI network load
condition
(CBUS = 10 nF,
Duty cycle of LOW level
RBUS = 500 Ω,
of logical value ‘1’ for
tBIT = 50 µs,
DTX_1_LO_ recessive threshold
SID.CXPIT.18 – – 45 % tTX_PWM_LO =
REC voltage of the driver
11.25 µs,
node,
VTHTX_REC =
VTHTX_REC = 70% of VBAT
0.7 × VBAT)

DTX_1_LO_REC =
tTX_1_LO_REC/tBIT
Param#32,
CXPI network load
condition
(CBUS = 1nF,
Duty cycle of LOW level
RBUS = 1 kΩ,
of logical value ‘0’ for
tBIT = 50 µs,
recessive threshold
SID.CXPIT.19 DTX_0_LO 17 – – % tTX_PWM_LO =
voltage of the driver
16.75 µs,
node,
VTHTX_REC =
VTHTX_REC = 30% of VBAT
0.3 × VBAT)

DTX_0_LO(min) =
tTX_0_LO_DOM/tBIT

Datasheet 60 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.4.3 CAPSENSE™ block (MSC) specifications

Table 24 MSC specifications

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
MSC specifications
VDDD > 2 V (with
Max allowed ripple on ripple), 25°C TA,
SID.MSC.1 VDD_RIPPLE power supply, – – ±50 mV sensitivity =
1 kHz to 10 MHz 50 counts/0.1 pF,
2 pF < Cs < 50 pF
VDDD > 1.75 V (with
Max allowed ripple on ripple), 25°C TA,
VDD_RIPPLE_
SID.MSC.2 power supply, – – ±25 mV sensitivity =
1.8V 1 kHz to 10 MHz 50 counts/0.1 pF,
2 pF < Cs < 50 pF
VDDD > 2 V (with
ripple), 25 °C TA,
VDC_VDD_
SID.MSC.x1 Min PSR from 2 V to 5.5 V – – ±50 mV sensitivity = 50
RIPPLE counts/0.1 pF,
2 pF < Cs < 50 pF
VDDD > 1.75 V (with
ripple), 25°C TA,
VDD_RIPPLE_ Min PSR from 1.75 V to
SID.MSC.x2 – – ±25 mV sensitivity =
1.8V 2V
50 counts/0.1 pF,
2 pF < Cs < 50 pF
Maximum block
current in dynamic
(switching) mode
SID.MSC.3 IMSC Maximum block current – – 4000 µA
including
comparators and
switching current
Capacitance range
Ratio of counts of finger
of 5 pF to 50 pF,
to noise.
SID.MSC.6 SNR 5 – – Ratio sensitivity =
Guaranteed by
50 counts/pF.
characterization
VDDA > 2 V.
5 V rating,
C0G / NP0
capacitor.
Recommended
CMOD is 100 times
External modulator
SID.MSC.7 CMOD – 2.2 300 nF the sensor
capacitor.
capacitance Cs.
Max CMOD of
300 nF to support
external Cref mode
up to Cs = 3 nF
Note
23.Fast program transfer mode exceeds the 20 kBps maximum LIN2.2A transfer rate and is not a LIN compliant
operating mode. In this mode, LIN Bus specification parameters do not apply. This is mode can be used
for factory and field software updates.

Datasheet 61 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

Table 24 MSC specifications (continued)

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
CMOD External modulator Tolerance on
SID.MSC.x7 –5 – 5 %
tolerance capacitor. CMOD capacitor.
Capacitive sense freq.
SID.MSC.x8 fSENSE 45 – 6000 kHz
range
NOISE_ Capacitive noise
With 8-pF input
SID.MSC.9 FLOOR_ sensitivity for self-cap – – 0.1 fF-rms
SELF capacitance
scans
With a 1.5 pF
NOISE_ Capacitive noise mutual-
SID.MSC.9A FLOOR_ sensitivity for – – 0.1 fF-rms capacitance
MUTUAL mutual-cap scans sensor;
Typical conditions
Input capacitance Internal Cref Mode
SID.MSC.10 CIN_SELF_CAP 2 – 200 pF
range (default)
Input capacitance
CIN_MUTUAL_
SID.MSC.10A range for mutual-cap 0.5 – 30 pF
CAP mode
Extended input
CIN_SELF_
SID.MSC.10B capacitance range for 200 – 3000 pF External Cref Mode
CAP_EXT self-cap mode
Note
23.Fast program transfer mode exceeds the 20 kBps maximum LIN2.2A transfer rate and is not a LIN compliant
operating mode. In this mode, LIN Bus specification parameters do not apply. This is mode can be used
for factory and field software updates.

Datasheet 62 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.4.4 Comparator

Table 25 Comparator DC specifications

Spec ID# Parameter Description Min Typ Max Units Details/conditions
Input offset voltage, Fast mode,
SID.COMP.1 VOFFSET1 –24.5 – 24.5 mV
factory trim –45°C to 155°C
Input offset voltage, Slow mode,
SID.COMP.2 VOFFSET1.1 –15.5 – 15.5 mV
factory trim –45°C to 155°C
Input offset voltage, Fast mode,
SID.COMP.3 VOFFSET2.1 –8 – 8 mV
custom trim –45°C to 155°C
Input offset voltage, Slow mode,
SID.COMP.4 VOFFSET2.2 –7.5 – 13.5 mV
custom trim –45°C to 155°C
Hysteresis when For both fast and
SID.COMP.5 VHYST – 10 35 mV
enabled slow modes
Input common mode
SID.COMP.6 VIN_CM1 0 – VDDD – 0.15 V
voltage in fast mode
Input common mode
SID.COMP.7 VIN_CM2 0 – VDDD V
voltage in slow mode
Input common mode
VDDD ≥ 2.2 V
SID.COMP.8 VIN_CM3 voltage in ultra low 0 – VDDD – 1.15 V
at –40°C
power mode
Common mode
SID.COMP.9 CMRR –43 – – dB VDDD ≥ 2.7 V
rejection ratio
Block current,
SID.COMP.11 ICMP1 – – 600 µA
fast mode
Block current,
SID.COMP.12 ICMP2 – – 150 µA
slow mode
Block current in ultra VDDD ≥ 2.2 V
SID.COMP.13 ICMP3 – 6 38 µA
low-power mode at –40°C

Datasheet 63 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

Table 26 Comparator AC specifications

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
Response time,
SID.COMP.21 tRESP1 fast mode, – 38 60 ns CLOAD = 15pF
50 mV overdrive
Response time,
SID.COMP.22 tRESP2 slow mode, – 70 200 ns CLOAD = 15pF
50 mV overdrive
Response time,
VDDD ≥ 2.7 V
SID.COMP.23 tRESP3 ultra-low power mode, – 2.3 35 µs
at –40°C
50 mV overdrive
Time taken for
comparator output to
SID.COMP.24 tENABLE1_EN – – 0.26 µs Fast mode
be available after
asserting ‘en’ signal
Time taken for
comparator output to
SID.COMP.25 tENABLE2_EN – – 0.9 µs Slow mode
be available after
asserting ‘en’ signal
Time taken for
comparator output to Ultra low-power
SID.COMP.26 tENABLE3_EN – – 310 µs
be available after mode
asserting ‘en’ signal
Time taken for
comparator output to
tENABLE1_
SID.COMP.27 be available after – – 0.22 µs Fast mode
EN_HV
asserting ‘enable_hv’
signal
Time taken for
comparator output to
tENABLE1_
SID.COMP.28 be available after – – 0.59 µs Slow mode
EN_HV
asserting ‘enable_hv’
signal
Time taken for
comparator output to
tENABLE1_ Ultra low-power
SID.COMP.29 be available after – – 300.5 µs
EN_HV mode
asserting ‘enable_hv’
signal

Datasheet 64 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.4.5 Temperature sensor

Table 27 Temperature sensor specifications

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
Temperature sensor
SID93 TSENSACC –5 – 5 °C 25°C to 85°C
accuracy
Temperature sensor
SID93A TSENSACC –10 – 10 °C –40°C to +125°C
accuracy

9.4.6 SAR ADC

Table 28 SAR ADC specifications

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
SAR ADC DC specifications
SID94 A_RES Resolution – – 12 bits
8 direct IO channels
+ 8 diagnostic
channels at full
speed (1 Msps)
Number of channels - single + 2 AMuxBus
SID95 A_CHNLS_S – – 20 channels
ended
+ 2 Temp sensor
channels at
reduced speed
(< 1 Msps)
Number of channels - Diff inputs use
SID96 A_CHNKS_D – – 4
differential neighboring I/Os
SID97 A_MONO Monotonicity – – – Yes
With external
SID98 A_GAINERR Gain error – – ±0.1 %
reference
Measured with 1 V
SID99 A_OFFSET Input offset voltage –2 – 2 mV
reference
SID100 A_ISAR Current consumption – – 1 mA
Input voltage range - single
SID101 A_VINS VSSA – VDDA V
ended
Input voltage range -
SID102 A_VIND VSSA – VDDA V
differential
SID103 A_INRES Input resistance – – 2.2 KΩ
SID104 A_INCAP Input capacitance – – 10 pF
Trimmed internal reference
SID260 VREFSAR 1.18 1.2 1.22 V
to SAR
SAR ADC AC specifications
SID106 A_PSRR Power supply rejection ratio 70 – – dB
Note
24.SAR settings:
For 1.8 MHz ≤ Sample CLK < 9 MHz set dly_inc = 1, dcen = 0;
For 9 MHz ≤ Sample CLK < 18 MHz set dly_inc = 0, dcen = 1

Datasheet 65 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

Table 28 SAR ADC specifications (continued)

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
Common mode rejection
SID107 A_CMRR 66 – – dB Measured at 1 V
ratio
SID108 A_SAMP Sample rate – – 1 Msps
fIN = 1 kHz;
Signal-to-noise and –40°C ≤ TJ ≤ 125°C
SID109 A_SINAD 67 – – dB
distortion ratio (SINAD) External Clock
Source
Input bandwidth without A_SAMP /
SID110 A_BW – – kHz
aliasing 2
VREF = 1.0 V to VDDA
Integral non linearity. (both internal &
SID111 A_INL VDDA = 2.7 V to 5.5 V, –1.5 – 1.5 LSB external ref)
100 ksps to 1 Msps –40°C ≤ TJ ≤
150°C[24]
VREF = 1.0 V to VDDD
Integral non linearity. (both internal &
SID111B A_INL_150 VDDD = 2.7 V to 5.5 V, –3.0 – 3.0 LSB external ref)
100 ksps to 1 Msps 125°C ≤ TJ ≤
150°C[24]
VREF = 1.0 V to VDDA
Differential non linearity. (both internal &
SID112 A_DNL VDDA = 2.7 V to 5.5 V, –1 – 1.75 LSB external ref)
100 ksps to 1 Msps –40°C ≤ TJ ≤
150°C[24]
fIN = 1 kHz;
SID113 A_THD Total harmonic distortion – – –67.5 dB
–40°C ≤ TJ ≤ 125°C
fIN = 1 kHz;
SID113A A_THD1 Total harmonic distortion – – –65 dB
125°C ≤ TJ ≤ 150°C
SAR operating speed
SID261 FSARINTREF without external reference – – 100 Ksps 12-bit resolution
bypass
Note
24.SAR settings:
For 1.8 MHz ≤ Sample CLK < 9 MHz set dly_inc = 1, dcen = 0;
For 9 MHz ≤ Sample CLK < 18 MHz set dly_inc = 0, dcen = 1

Datasheet 66 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.5 Digital peripherals

9.5.1 Timer/counter/PWM (TCPWM)

Table 29 TCPWM specifications

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
Block current consumption
SID140 ITCPWM1 – – 45 µA All modes (TCPWM)
at 3 MHz
Block current consumption
SID141 ITCPWM2 – – 155 µA All modes (TCPWM)
at 12 MHz
Block current consumption
SID142 ITCPWM3 – – 650 µA All modes (TCPWM)
at 48 MHz
fC max = fCPU
SID143 fTCPWMFREQ Operating frequency – – fC MHz
Maximum = 48 MHz
Trigger events can
be stop, start,
reload, count,
Input trigger pulse width for capture, or kill
SID144 tPWM_ENEXT 2/fC – – ns
all trigger events depending on
which mode of
operation is
selected.
Minimum possible
width of overflow,
underflow, and CC
SID145 tPWM_EXT Output trigger pulse widths 2/fC – – ns
(Counter equals
compare value)
trigger outputs
Minimum time
SID146 tCRES Counter resolution 1/fC – – ns between
successive counts
Minimum pulse
SID147 tPWMRES PWM resolution 1/fC – – ns width of PWM
output
Minimum pulse
Quadrature inputs width between
SID148 tQRES 1/fC – – ns
resolution quadrature phase
inputs.

Datasheet 67 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.5.2 LIN

Table 30 LIN specifications

Spec ID# Parameter Description Min Typ Max Units Details/conditions
Internal clock frequency to
SID249 fLIN – – 2 MHz
the LIN block
Guaranteed by
SID250 BR_NOM Bit rate on the LIN bus 1 – 20 Kbps
design
Bit rate on the LIN bus (not in
standard LIN specification) Guaranteed by
SID250A BR_REF 1 – 115.2 Kbps
for re-flashing in LIN slave design
mode

Datasheet 68 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.5.3 CXPI

Table 31 CXPI specifications

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
Param#1,
Difference of width of
tBIT = 1/BR_CXPI,
LOW-level at the
tTX_DIFF_CONT =
constant threshold that
SID.CXPIC.1 tRX_DIF_CONT 0.05 – – tBIT tTX_0_LO_CONT –
receiving node should
tTX_1_LO_CONT
discriminate logic “1”
Guaranteed by
and logic “0”.
design
The value in which this
parameter is added to
the width of LOW-level Param#2
SID.CXPIC.2 tSAMPLE_CONT of last logical value ‘1’ is 0.016 – – tBIT Guaranteed by
to be a threshold used design
for the decoding
processing
Width of clock disparity
Param#3
against the ideal bit
SID.CXPIC.3 ∆tBIT_CONT –0.5 – +0.5 % Guaranteed by
width tBIT_REF of
design
nominal signaling rate
At the time of logical
value “0” outputs, time Param#4,
from the LOW level tTX_0_PD_CONT =
tTX_0_PD_
SID.CXPIC.4 detection of the – – 0.5 µs 0.01 × tBIT
CONT communication bus Guaranteed by
until falling of the design
voltage “TH_dom”
Param#5,
tRX_0_HI_CONT =
The time that should be
(0.06 × tBIT) –
SID.CXPIC.5 tRX_0_HI_CONT detected as HIGH level 1 – – µs
tRX_PWM_PD_SYM
by the receiving node
Guaranteed by
design
Dominant level of the Param#6,
wake-up pulse tTX_WAKEUP = 8 × tBIT
SID.CXPIC.6 tTX_WAKEUP 400 – 2500 µs
transmitted by Guaranteed by
transmitter mode design
Interval time between
Param#7
tTX_WAKEUP_ two of dominant level of
SID.CXPIC.7 5 – 10 ms Guaranteed by
SPACE transmitting wake-up
design
pulses
Guaranteed by
SID.CXPIC.8 BR_CXPI Bit rate – – 20 kbps
design
Guaranteed by
SID.CXPIC.9 OS Oversampling factor – – 400
design

Datasheet 69 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.5.4 Serial communication block

9.5.4.1 I2C

Table 32 Fixed I2C DC specifications[25]

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
II2C1 Block current consumption
SID149 – – 50 µA
at 100 kHz

II2C2 Block current consumption

SID150 – – 150 µA
at 400 kHz
II2C3 Block current consumption
SID151 – – 310 µA
at 1 Mbps

SID152 II2C4 I2C enabled – – 2 µA

in Deep Sleep mode

Table 33 Fixed I2C AC specifications[25]

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
SID153 BR_I2C Bit rate – – 1 Mbps

9.5.4.2 UART

Table 34 UART DC specifications

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
Block current consumption
SID160 IUART1 – – 60 µA
at 100 Kbps
Block current consumption
SID161 IUART2 – – 320 µA
at 1000 Kbps

Table 35 UART AC specifications

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
SID162 BR_UART Bit rate – – 1 Mbps IMO as source clock
IMO locked to High
SID162A BR_UART_2 Extended bit rate – – 2 Mbps Precision Oscillator
(HPOSC)

Note
25.Guaranteed by characterization.

Datasheet 70 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.5.4.3 SPI

Table 36 SPI DC specifications[26]

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
ISPI1 Block current consumption
SID163 – – 360 µA
at 1 Mbps

ISPI2 Block current consumption

SID164 – – 560 µA
at 4 Mbps
ISPI3 Block current consumption
SID165 – – 800 µA
at 8 Mbps

Table 37 SPI AC specifications[26]

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
SPI operating frequency fC max = fCPU/6,
SID166 fSPI – – fC MHz
(Master; 6X oversampling) fCPU max = 48 MHz

Table 38 Fixed SPI master mode AC specifications[26]

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
MOSI valid after Sclock – – 15 ns
SID167 tDMO
driving edge
MISO valid before Sclock Full clock, late
SID168 tDSI 20 – – ns
capturing edge MISO sampling

Previous MOSI data hold Referred to slave

SID169 tHMO 0 – – ns
time capturing edge

Table 39 Fixed SPI slave mode AC specifications[26]

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
MOSI valid before Sclock 30 – – ns
SID170 tDMI
capturing edge
MISO valid after Sclock 48 +
SID171 tDSO – – ns
driving edge 3 × tSCB

MISO valid after Sclock – – 48 ns

SID171A tDSO_EXT
driving edge in Ext. clk mode
Previous MISO data hold 0 – – ns
SID172 tHSO
time
SSEL valid to first SCK valid 125 – – ns
SID172A tSSELSSCK
edge

Note
26.Guaranteed by characterization.

Datasheet 71 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.6 Memory

Table 40 Flash AC specifications

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
Row (block) write
Row (block) =
SID174 tROWWRITE[27] time (erase and – – 24 ms
128 Bytes
program)
SID175 tROWERASE[27] Row erase time – – 17 ms
Row program time
SID176 tROWPROGRAM[27] – – 7 ms
after erase
Bulk erase time (32
SID178 tBULKERASE – – 35 ms
KB)
Total device Using Bulk Erase +
SID180 tDEVPROG[27] – – 10.8 s
program time Program Row APIs
SID181 FEND Flash endurance 100K – – cycles
SID181C FDIST Flash Disturb Cycle 1M – – cycles For TA = 125°C
TA ≤ 105°C,
Flash retention per
10K P/E cycles,
SID182 FRETQ application usage 15 – – years
≤ three years
profile
at TA ≥ 85°C
Time for Non-blocking
non-blocking system calls should
SID183 tRESUMESYSCALL – – 25 ms
system calls to be be used only for
resumed data flash
Number of wait CPU execution from
SID256 TWS48 3 – –
states at 48 MHz flash
Number of wait CPU execution from
SID257 TWS36 2 – –
states at 36 MHz flash
Number of wait CPU execution from
SID258 TWS24 1 – –
states at 24 MHz flash
Number of wait CPU execution from
SID259 TWS12 0 – –
states at 12 MHz flash

Note
27.It can take as much as 20 ms to write to Flash. During this time the device should not be reset, or flash
operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES_L
pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and
watchdogs. Make certain that these are not inadvertently activated.

Datasheet 72 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Electrical specifications

9.7 System resources

Table 41 Power-on reset (PRES)

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
SID185 VIPOR POR trip voltage 0.7 – 1.5 V

Table 42 Brown-out detect (BOD) for VDDX, VCCD

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
BOD trip voltage
SID190 VDDX_BOD 2.34 – 2.63 V
for VDDX (VDDD/VDDA)
SID190A VCCD_BOD BOD trip voltage for VCCD 1.64 – 1.74 V
VCCD_BOD_ BOD trip voltage
SID190B 1.1 – 1.5 V
DPSLP for VCCD in DeepSleep

Table 43 Overvoltage detect (OVD) for VDDX, VCCD

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
OVD trip voltage
SID192 VDDX_OVD 3.62 – 3.96 V
for 3.3 V VDDX
OVD trip voltage
SID192A VDDX_OVD 5.52 – 6.0 V
for 5.0 V VDDX
SID192B VCCD_OVD OVD trip voltage for VCCD 1.97 – 2.17 V

Table 44 SWD interface specifications

Spec ID# Parameter Description Min Typ Max Unit Details/conditions
SID213 fSWDCLK1 SWD clock input frequency – – 14 MHz SWDCLK 1/3 fCPU
T = 1 / fSWDCLK
SID215 tSWDI_SETUP SWDI setup time 0.25 × T – – ns Guaranteed by
design
T = 1 / fSWDCLK
SID216 tSWDI_HOLD SWDI hold time 0.25 × T – – ns Guaranteed by
design
T = 1 / fSWDCLK
SID217 tSWDO_VALID SWDO valid time – – 0.5 × T ns Guaranteed by
design
T = 1 / fSWDCLK
SID217A tSWDO_HOLD SWDO hold time 1 – – ns Guaranteed by
design

Datasheet 73 002-33200 Rev. *G

2025-03-06
 10 Ordering information

Based on 32-bit Arm® Cortex®-M0+

PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Datasheet

Ordering information
Table 45 PSOC™ 4 HVMS-64K ordering information

internal and external supply (V)

Temperature grade
(1- Msps) channels
MSC (CAPSENSE™)
SMART/PROG I/Os
CPU max. speed

LP Comparators

(–40°C to 125°C)
12-bit SAR ADC

LDO output for

TCPWM Blocks

CXPI channels
SCB channels
LIN channels
SRAM (KB)
Flash (KB)

CXPI PHY
with ECC

with ECC
Package
Product

LIN PHY
(MHz)

GPIO
CY8C4125LCE-HVS003 32-lead QFN 24 32 4 18 10 – 16 2 5 2 – 2 3.3 Y – E-grade
CY8C4125LCE-HVS013 32-lead QFN 24 32 4 18 10 Y 16 2 5 2 – 2 3.3 Y – E-grade
74

CY8C4126LCE-HVS003 32-lead QFN 24 64 8 18 10 – 16 2 5 2 – 2 3.3 Y – E-grade

CY8C4126LCE-HVS013 32-lead QFN 24 64 8 18 10 Y 16 2 5 2 – 2 3.3 Y – E-grade
CY8C4146LCE-HVS003 32-lead QFN 48 64 8 18 10 – 16 2 5 2 – 2 3.3 Y – E-grade
CY8C4146LCE-HVS013 32-lead QFN 48 64 8 18 10 Y 16 2 5 2 – 2 3.3 Y – E-grade
CY8C4146LCE-HVS003X 32-lead QFN 48 64 8 18 10 – 16 2 5 2 2 2 3.3 Y Y E-grade
CY8C4146LCE-HVS013X 32-lead QFN 48 64 8 18 10 Y 16 2 5 2 2 2 3.3 Y Y E-grade
CY8C4125LCE-HVS103 32-lead QFN 24 32 4 18 10 – 16 2 5 2 – 2 5.0 Y – E-grade
CY8C4125LCE-HVS113 32-lead QFN 24 32 4 18 10 Y 16 2 5 2 – 2 5.0 Y – E-grade
CY8C4126LCE-HVS103 32-lead QFN 24 64 8 18 10 – 16 2 5 2 – 2 5.0 Y – E-grade
CY8C4126LCE-HVS113 32-lead QFN 24 64 8 18 10 Y 16 2 5 2 – 2 5.0 Y – E-grade
CY8C4146LCE-HVS103 32-lead QFN 48 64 8 18 10 – 16 2 5 2 – 2 5.0 Y – E-grade
CY8C4146LCE-HVS113 32-lead QFN 48 64 8 18 10 Y 16 2 5 2 – 2 5.0 Y – E-grade
002-33200 Rev. *G

CY8C4146LCE-HVS103X 32-lead QFN 48 64 8 18 10 – 16 2 5 2 2 2 5.0 Y Y E-grade

CY8C4146LCE-HVS113X 32-lead QFN 48 64 8 18 10 Y 16 2 5 2 2 2 5.0 Y Y E-grade
2025-03-06

CY8C4125LDE-HVS004 48-lead QFN 24 32 4 33 16 – 16 2 5 2 – 2 3.3 Y – E-grade

 Table 45 PSOC™ 4 HVMS-64K ordering information (continued)

Based on 32-bit Arm® Cortex®-M0+

PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Datasheet

Ordering information
internal and external supply (V)

Temperature grade
(1- Msps) channels
MSC (CAPSENSE™)
SMART/PROG I/Os
CPU max. speed

LP Comparators

(–40°C to 125°C)
12-bit SAR ADC

LDO output for

TCPWM Blocks

CXPI channels
SCB channels
LIN channels
SRAM (KB)
Flash (KB)

CXPI PHY
with ECC

with ECC
Package
Product

LIN PHY
(MHz)

GPIO
CY8C4125LDE-HVS014 48-lead QFN 24 32 4 33 16 Y 16 2 5 2 – 2 3.3 Y – E-grade
CY8C4126LDE-HVS004 48-lead QFN 24 64 8 33 16 – 16 2 5 2 – 2 3.3 Y – E-grade
CY8C4126LDE-HVS014 48-lead QFN 24 64 8 33 16 Y 16 2 5 2 – 2 3.3 Y – E-grade
CY8C4146LDE-HVS004 48-lead QFN 48 64 8 33 16 – 16 2 5 2 – 2 3.3 Y – E-grade
CY8C4146LDE-HVS014 48-lead QFN 48 64 8 33 16 Y 16 2 5 2 – 2 3.3 Y – E-grade
75

CY8C4146LDE-HVS004X 48-lead QFN 48 64 8 33 16 – 16 2 5 2 2 2 3.3 Y Y E-grade

CY8C4146LDE-HVS014X 48-lead QFN 48 64 8 33 16 Y 16 2 5 2 2 2 3.3 Y Y E-grade
CY8C4125LDE-HVS104 48-lead QFN 24 32 4 33 16 – 16 2 5 2 – 2 5.0 Y – E-grade
CY8C4125LDE-HVS114 48-lead QFN 24 32 4 33 16 Y 16 2 5 2 – 2 5.0 Y – E-grade
CY8C4126LDE-HVS104 48-lead QFN 24 64 8 33 16 – 16 2 5 2 – 2 5.0 Y – E-grade
CY8C4126LDE-HVS114 48-lead QFN 24 64 8 33 16 Y 16 2 5 2 – 2 5.0 Y – E-grade
CY8C4146LDE-HVS104 48-lead QFN 48 64 8 33 16 – 16 2 5 2 – 2 5.0 Y – E-grade
CY8C4146LDE-HVS114 48-lead QFN 48 64 8 33 16 Y 16 2 5 2 – 2 5.0 Y – E-grade
CY8C4146LDE-HVS104X 48-lead QFN 48 64 8 33 16 – 16 2 5 2 2 2 5.0 Y Y E-grade
CY8C4146LDE-HVS114X 48-lead QFN 48 64 8 33 16 Y 16 2 5 2 2 2 5.0 Y Y E-grade
CY8C4125LWE-HVS005 56-lead QFN 24 32 4 41 16 – 16 2 5 2 – 2 3.3 Y – E-grade
CY8C4125LWE-HVS015 56-lead QFN 24 32 4 41 16 Y 16 2 5 2 – 2 3.3 Y – E-grade
002-33200 Rev. *G

CY8C4126LWE-HVS005 56-lead QFN 24 64 8 41 16 – 16 2 5 2 – 2 3.3 Y – E-grade

2025-03-06

CY8C4126LWE-HVS015 56-lead QFN 24 64 8 41 16 Y 16 2 5 2 – 2 3.3 Y – E-grade

CY8C4146LWE-HVS005 56-lead QFN 48 64 8 41 16 – 16 2 5 2 – 2 3.3 Y – E-grade
 Table 45 PSOC™ 4 HVMS-64K ordering information (continued)

Based on 32-bit Arm® Cortex®-M0+

PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Datasheet

Ordering information
internal and external supply (V)

Temperature grade
(1- Msps) channels
MSC (CAPSENSE™)
SMART/PROG I/Os
CPU max. speed

LP Comparators

(–40°C to 125°C)
12-bit SAR ADC

LDO output for

TCPWM Blocks

CXPI channels
SCB channels
LIN channels
SRAM (KB)
Flash (KB)

CXPI PHY
with ECC

with ECC
Package
Product

LIN PHY
(MHz)

GPIO
CY8C4146LWE-HVS015 56-lead QFN 48 64 8 41 16 Y 16 2 5 2 – 2 3.3 Y – E-grade
CY8C4146LWE-HVS005X 56-lead QFN 48 64 8 41 16 – 16 2 5 2 2 2 3.3 Y Y E-grade
CY8C4146LWE-HVS015X 56-lead QFN 48 64 8 41 16 Y 16 2 5 2 2 2 3.3 Y Y E-grade
CY8C4125LWE-HVS105 56-lead QFN 24 32 4 41 16 – 16 2 5 2 – 2 5.0 Y – E-grade
CY8C4125LWE-HVS115 56-lead QFN 24 32 4 41 16 Y 16 2 5 2 – 2 5.0 Y – E-grade
76

CY8C4126LWE-HVS105 56-lead QFN 24 64 8 41 16 – 16 2 5 2 – 2 5.0 Y – E-grade

CY8C4126LWE-HVS115 56-lead QFN 24 64 8 41 16 Y 16 2 5 2 – 2 5.0 Y – E-grade
CY8C4146LWE-HVS105 56-lead QFN 48 64 8 41 16 – 16 2 5 2 – 2 5.0 Y – E-grade
CY8C4146LWE-HVS115 56-lead QFN 48 64 8 41 16 Y 16 2 5 2 – 2 5.0 Y – E-grade
CY8C4146LWE-HVS105X 56-lead QFN 48 64 8 41 16 – 16 2 5 2 2 2 5.0 Y Y E-grade
CY8C4146LWE-HVS115X 56-lead QFN 48 64 8 41 16 Y 16 2 5 2 2 2 5.0 Y Y E-grade
002-33200 Rev. *G
2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Ordering information

10.1 Nomenclature diagram

CY8C 4 A B C DE F HVS X Y Z X ES T
Blank –– Tray
Blank Tray shipment
shipment
Shipment type
T – Tape and reel shipment

ES – Engineering samples
Quality grade
Blank –– Productions
Blank Production samples

X – CXPI
CXPI feature
Blank/Non-X
Blank – Non-CXPI
– Non-CXPI

3 – 32-pins
No. of pins 4 – 48-pins
5 – 56-pins
0 – No CAPSENSETM
CAPSENSE
1 – CAPSENSETM

0 – 3.3 V regulator output

LDO output
1 – 5 V regulator output

Series HVMS series

Temperature
E-grade (–40°C to 125°C)
grade

LC – WQFN (6 x 6 mm)
Package type LD – WQFN (7 x 7 mm)
LW – WQFN (8 x 8 mm)
5 – 32 KB flash
Flash size
6 – 64 KB flash

2 – 24 MHz
CPU core speed
4 – 48 MHz

Sub-family 1 – PSOCTM 4100 family

Architecture 4 – PSOCTM 4

Prefix and
CY – Infineon, PSOCTM
Architecture

Figure 13 Nomenclature diagram

Datasheet 77 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Ordering information

10.2 Part number nomenclature

Table 46 Part number nomenclature

Field Description Values Meaning
CY Company ID CY CY: Infineon
8C Product family 8C PSOC™
4 Architecture 4 PSOC™ 4
A Sub-family 1 PSOC™ 4100 family
2 24 MHz
B CPU core speed
4 48 MHz
5 32 KB flash
C Flash size
6 64 KB flash
LC WQFN (6 × 6 mm)
DE Package type LD WQFN (7 × 7 mm)
LW WQFN (8 × 8 mm)
F Temperature grade E E-grade (–40°C to 125°C)
HVS Series HVS HVMS Series
0 3.3 V regulator output
X LDO output voltage
1 5 V regulator output
0 No CAPSENSE™
Y CAPSENSE™
1 CAPSENSE™
3 32 pins
Z Number of pins 4 48 pins
5 56 pins
X CXPI
X CXPI feature
Blank Non-CXPI
ES Engineering samples
ES Quality grade
Blank Production
Blank Tray shipment
T Shipment type
T Tape and reel shipment

Datasheet 78 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Packaging

11 Packaging
The PSOC™ 4 HVMS-64K devices will be offered in a 32-lead QFN, 48-lead QFN, and 56-lead QFN packages.
Package dimensions and drawing numbers are in the following table.

Table 47 Package list

Package Description Package Dwg
32-lead QFN with wettable flanks 6 × 6 × 0.9-mm height with 0.5-mm pitch 002-34265
48-lead QFN with wettable flanks 7 × 7 × 0.9-mm height with 0.5-mm pitch 002-34266
56-lead QFN with wettable flanks 8 × 8 × 0.9-mm height with 0.5-mm pitch 002-34267

Table 48 Package thermal characteristics

Parameter Description Package Min Typ Max Units
TA Operating ambient temperature –40 25 125 °C
TJ Operating junction temperature –40 – 150 °C
32-lead QFN – – 16.3 °C/W
TJA Package θJA 48-lead QFN – – 16.2 °C/W
56-lead QFN – – 16.0 °C/W
32-lead QFN – – 1.8 °C/W
TJC Package θJC 48-lead QFN – – 1.9 °C/W
56-lead QFN – – 1.8 °C/W

Table 49 Solder reflow peak temperature, package moisture sensitivity level (MSL), IPC/JEDEC
J-STD-020
Package Maximum peak temperature Maximum time at peak temperature MSL
32-lead QFN 260°C 30 seconds 3
48-lead QFN 260°C 30 seconds 3
56-lead QFN 260°C 30 seconds 3

Datasheet 79 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Packaging

11.1 Package outline

NOTES:
DIMENSIONS
SYMBOL 1. ALL DIMENSIONS ARE IN MILLIMETERS.
MIN. NOM. MAX.
2. N IS THE TOTAL NUMBER OF TERMINALS.
e 0.50 BSC 3 DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
N 32
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS
ND 8
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE
L 0.30 0.40 0.50
DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
b 0.20 0.25 0.30 ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
4
D2 4.50 4.60 4.70
5 PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
E2 4.50 4.60 4.70
6 COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK
D 6.00 BSC
SLUG AS WELL AS THE TERMINALS.
E 6.00 BSC 7. JEDEC SPECIFICATION NO. REF. : N/A.
A - - 0.90
A1 0.00 - 0.05
A3 0.203 REF
K 0.30 MIN

002-34265 Rev. **

Figure 14 32-lead QFN ((6.0 × 6.0 × 0.9 mm) LV32C, 4.60 × 4.60 mm EPAD (Step-cut wettable flank, Sawn
type)) package outline, 002-34265

Datasheet 80 002-33200 Rev. *G

2025-03-06
PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Packaging

002-34266 Rev. *A

Figure 15 48-lead QFN ((7.0 × 7.0 × 0.9 mm) LV48B, 5.15 × 5.15 mm EPAD (Step-cut wettable flank, Sawn
type)) package outline, 002-34266

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Packaging

NOTES:
DIMENSIONS
SYMBOL 1. ALL DIMENSIONS ARE IN MILLIMETERS.
MIN. NOM. MAX.
2. N IS THE TOTAL NUMBER OF TERMINALS.
e 0.50 BSC 3 DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
N 56
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS
ND 14
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE
L 0.30 0.40 0.50
DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
b 0.20 0.25 0.30 ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
4
D2 4.60 4.70 4.80
5 PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
E2 4.60 4.70 4.80
6 COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK
D 8.00 BSC
SLUG AS WELL AS THE TERMINALS.
E 8.00 BSC 7. JEDEC SPECIFICATION NO. REF. : N/A.
A - - 0.90
A1 0.00 - 0.05
A3 0.203 REF
K 1.25 MIN

002-34267 Rev. **

Figure 16 56-lead QFN ((8.0 × 8.0 × 0.9 mm) LV56B, 4.7 × 4.7 mm EPAD (Step-cut wettable flank, Sawn
type)) package outline, 002-34267

Datasheet 82 002-33200 Rev. *G

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Acronyms

12 Acronyms

Table 50 Acronyms used in this document

Acronym Description
abus analog local bus
ADC analog-to-digital converter
AG analog global
AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm® data
AHB
transfer bus
ALU arithmetic logic unit
AMUXBUS analog multiplexer bus
API application programming interface
APSR application program status register
Arm® advanced RISC machine, a CPU architecture
ATM automatic thump mode
BW bandwidth
CAN Controller Area Network, a communications protocol
CMRR common-mode rejection ratio
CPU central processing unit
CRC cyclic redundancy check, an error-checking protocol
DAC digital-to-analog converter, see also IDAC, VDAC
DFB digital filter block
DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
DMIPS Dhrystone million instructions per second
DMA direct memory access, see also TD
DNL differential nonlinearity, see also INL
DNU do not use
DR port write data registers
DSI digital system interconnect
DWT data watchpoint and trace
ECC error correcting code
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only memory
EMI electromagnetic interference
EMIF external memory interface
EOC end of conversion
EOF end of frame
EPSR execution program status register
ESD electrostatic discharge
ETM embedded trace macrocell
FIR finite impulse response, see also IIR

Datasheet 83 002-33200 Rev. *G

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Acronyms

Table 50 Acronyms used in this document (continued)

Acronym Description
FPB flash patch and breakpoint
FS full-speed
GPIO general-purpose input/output, applies to a PSOC™ pin
HVI high-voltage interrupt, see also LVI, LVD
IC integrated circuit
IDAC current DAC, see also DAC, VDAC
IDE integrated development environment
I2C, or IIC Inter-Integrated Circuit, a communications protocol
IIR infinite impulse response, see also FIR
ILO internal low-speed oscillator, see also IMO
IMO internal main oscillator, see also ILO
INL integral nonlinearity, see also DNL
I/O input/output, see also GPIO, DIO, SIO, USBIO
IPOR initial power-on reset
IPSR interrupt program status register
IRQ interrupt request
ITM instrumentation trace macrocell
LCD liquid crystal display
LIN Local Interconnect Network, a communications protocol.
LR link register
LUT lookup table
LVD low-voltage detect, see also LVI
LVI low-voltage interrupt, see also HVI
LVTTL low-voltage transistor-transistor logic
MAC multiply-accumulate
MCU microcontroller unit
MISO master-in slave-out
NC no connect
NMI nonmaskable interrupt
NRZ non-return-to-zero
NVIC nested vectored interrupt controller
NVL nonvolatile latch, see also WOL
opamp operational amplifier
PAL programmable array logic, see also PLD
PC program counter
PCB printed circuit board
PGA programmable gain amplifier
PHUB peripheral hub
PHY physical layer
PICU port interrupt control unit

Datasheet 84 002-33200 Rev. *G

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Acronyms

Table 50 Acronyms used in this document (continued)

Acronym Description
PLA programmable logic array
PLD programmable logic device, see also PAL
PLL phase-locked loop
PMDD package material declaration data sheet
POR power-on reset
PRES precise power-on reset
PRS pseudo random sequence
PS port read data register
PSOC™ Programmable System-on-Chip™
PSRR power supply rejection ratio
PWM pulse-width modulator
RAM random-access memory
RISC reduced-instruction-set computing
RMS root-mean-square
RTC real-time clock
RTL register transfer language
RTR remote transmission request
RX receive
SAR successive approximation register
SC/CT switched capacitor/continuous time
SCL I2C serial clock
SDA I2C serial data
S/H sample and hold
SINAD signal to noise and distortion ratio
SIO special input/output, GPIO with advanced features. See GPIO.
SOC start of conversion
SOF start of frame
SPI Serial Peripheral Interface, a communications protocol
SR slew rate
SRAM static random access memory
SRES software reset
SWD serial wire debug, a test protocol
SWV single-wire viewer
TD transaction descriptor, see also DMA
THD total harmonic distortion
TIA transimpedance amplifier
TRM technical reference manual
TTL transistor-transistor logic
TX transmit
UART Universal Asynchronous Transmitter Receiver, a communications protocol

Datasheet 85 002-33200 Rev. *G

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Acronyms

Table 50 Acronyms used in this document (continued)

Acronym Description
UDB universal digital block
USB Universal Serial Bus
USBIO USB input/output, PSOC™ pins used to connect to a USB port
VDAC voltage DAC, see also DAC, IDAC
WDT watchdog timer
WOL write once latch, see also NVL
WRES watchdog timer reset
XRES_L external reset I/O pin
XTAL crystal

Datasheet 86 002-33200 Rev. *G

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Document conventions

13 Document conventions
13.1 Units of measure

Table 51 Units of measure

Symbol Unit of measure
°C degrees Celsius
dB decibel
fF femto farad
Hz hertz
KB 1024 bytes
kbps kilobits per second
Khr kilohour
kHz kilohertz
k kilo ohm
ksps kilosamples per second
LSB least significant bit
Mbps megabits per second
MHz megahertz
M mega-ohm
Msps megasamples per second
µA microampere
µF microfarad
µH microhenry
µs microsecond
µV microvolt
µW microwatt
mA milliampere
ms millisecond
mV millivolt
nA nanoampere
ns nanosecond
nV nanovolt
 ohm
pF picofarad
ppm parts per million
ps picosecond
s second
sps samples per second
sqrtHz square root of hertz
V volt

Datasheet 87 002-33200 Rev. *G

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PSOC™ 4 high voltage (HV) mixed signal (MS) Automotive MCU
Based on 32-bit Arm® Cortex®-M0+
Revision history

Revision histor y

Document
Date of release Description of changes
revision
*G 2025-03-06 Post to external web.

Datasheet 88 002-33200 Rev. *G

2025-03-06
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