High-Performance Resonant Converters for Battery Chargers: Efficiency

and Dynamics Improvement

by

Jhih-Da Hsu

B. Science, National Chiao Tung University, 2005

M. Science, National Chiao Tung University, 2007

A THESIS SUBMITTED IN PARTIAL FULFILLMENT

OF THE REQUIREMENTS FOR THE DEGREE OF

Doctor of Philosophy

in

THE FACULTY OF GRADUATE AND POSTDOCTORAL STUDIES

(Electrical and Computer Engineering)

The University of British Columbia

(Vancouver)

November 2022

© Jhih-Da Hsu, 2022

The following individuals certify that they have read, and recommend to the Faculty of Graduate and Post-

doctoral Studies for acceptance, the dissertation entitled:

High-Performance Resonant Converters for Battery Chargers: Efficiency and Dynamics Improvement

submitted by Jhih-Da Hsu in partial fulfillment of the requirements for

the degree of Doctor of Philosophy

in Electrical and Computer Engineering

Examining Committee:

Dr. Martin Ordonez, Professor, Electrical and Computer Engineering, UBC

Supervisor

Dr. Wilson Eberle, Associate Professor, Electrical and Computer Engineering, UBC Okanagan

Co-supervisor

Dr. Yu Christine Chen, Associate Professor, Electrical and Computer Engineering, UBC

Supervisory Committee Member

Dr. Shahriar Mirabbasi, Professor, Electrical and Computer Engineering, UBC

University Examiner

Dr. Ryozo Nagamune, Professor, Mechanical Engineering, UBC

University Examiner

ii
Abstract

As the requirement for clean energy grows, the demand for high-performance power conversion for energy

storage and battery charging applications has been soaring. Resonant converters, in particular, LLC or CLLC

converters, have been broadly adopted for high-power battery chargers. The purpose of this work is to further

improve the performance of the resonant converters from both the efficiency and dynamics aspects.

In terms of improving the efficiency, this work focuses on reducing the conduction losses of the output

rectifiers using Synchronous Rectification (SR). Conventional SR controllers detect the drain-source voltage

during the SR turn-on phase (vds.on ) as the control input. However, vds.on is low-magnitude and sensitive to

the voltage noise caused by parasitic elements. The distorted vds.on causes SR mis-triggering, undermining

the efficiency. With the focus on mainstream LLC resonant converters, this work first introduces a new SR

driving strategy based on the resonant capacitor voltage (RCV). Next, a simplified SR method is proposed;

it is based on the Volt-Second Product (VSP) of SR drain-source blocking voltage and rectifier current con-

duction time. Both methods employ large-magnitude voltages, which are insensitive to the noise generated

by parasitic components, reducing SR on-time error. The proposed SR methods are compared with the

conventional vds.on based SR to demonstrate the efficiency improvement.

Regarding the dynamics aspect, this work focuses on improving the small-signal dynamic model for

charge-controlled resonant converters. Charge mode control has been applied to resonant converters to im-

prove the system dynamics, and yet the conventional small-signal model emphasizes only the low-frequency

region, which is not suitable for high-bandwidth designs. This work establishes the small-signal modeling

methodology based on Extended Describing Functions (EDF) and phasor analysis, which successfully pre-

dicts the system frequency response across low- to high-frequency regions, enabling high-bandwidth designs.

As the proposed noise-tolerant SR methods improve the efficiency performance, the enhanced small-signal

model assists to achieve wide loop bandwidth, improving the dynamic performance. This work provides

solutions and insights to the design of high-performance resonant battery chargers.

iii
Lay Summary

Power converters are core elements interfacing electricity and batteries and they shape the modern world.

While high-performance converter design involves many aspects, this work emphasizes improvements to

efficiency and dynamic performance. In terms of efficiency, this work proposes two advanced solutions

to controlling the active switches that replace the lossy and passive components. Traditional methods for

controlling the switches are easily mistriggered by non-ideal behaviors of circuit elements. The proposed

solutions successfully increase the efficiency compared with the traditional methods. Regarding the system

dynamics aspect, this work establishes an enhanced dynamic model of the converter which predicts the ac-

tual behavior better than the conventional model. This model assists to achieve high-bandwidth designs, so

that the converter output recovers quickly after external disturbances. This work provides advanced solu-

tions to improving efficiency and dynamic performance of battery chargers. All the results are validated by

simulation and experiments.

iv
Preface

This work is based on research performed at the Department of Electrical and Computer Engineering of the

University of British Columbia by Jhih-Da Hsu, under the supervision of Prof. Martin Ordonez and Prof.

Wilson Eberle. Chapter 1 contains modified portions of text from all the below-listed publications. Portions

of Chapters 2, 3, and 4 have been published in IEEE Transactions on Power Electronics and IEEE Journal

of Emerging and Selected Topics in Power Electronics [1–3].

• J. -D. Hsu, M. Ordonez, W. Eberle, M. Craciun and C. Botting, “LLC Synchronous Rectification

Using Resonant Capacitor Voltage,” in IEEE Transactions on Power Electronics, vol. 34, no. 11, pp.

10970-10987, Nov. 2019.

• J. -D. Hsu, M. Ordonez, W. Eberle, M. Craciun and C. Botting, “Noise-Tolerant LLC Synchronous

Rectification Using Volt-Second Product,” in IEEE Journal of Emerging and Selected Topics in Power

Electronics, Early Access.

• J. -D. Hsu, M. Ordonez, W. Eberle, M. Craciun and C. Botting, “Enhanced Small-Signal Modeling

for Charge-Controlled Resonant Converters,” in IEEE Transactions on Power Electronics, vol. 37, no.

2, pp. 1736-1747, Feb. 2022.

I was the lead investigator of the above papers, developed the proposed concepts, built simulation models,

performed experimental verifications, and wrote the manuscripts. Prof. Martin Ordonez and Prof. Wilson

Eberle were the supervisory coauthor on the above papers and were involved throughout the project and

provided technical advice and edited manuscripts. Mr. Marian Craciun and Mr. Chris Botting were industry

partners (Delta-Q Technologies, Vancouver, BC) in this project and valuable comments on the research from

industrial application aspects.

v
Table of Contents

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Lay Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x

List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii

Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviii

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3.1 Synchronous Rectification Using Current Transformers . . . . . . . . . . . . . . . . 4

1.3.2 SR Based on the Drain-Source Voltage During the Turn-on Phase (vds.on based) . . . 5

1.3.3 vds.on based Adaptive SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3.4 Alternative SR Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.3.5 Small-signal Modeling for Resonant Converters . . . . . . . . . . . . . . . . . . . . 11

1.4 Contributions of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.5 Dissertation Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

vi
2 LLC Synchronous Rectification Using Resonant Capacitor Voltage . . . . . . . . . . . . . . . 16

2.1 Operating Modes of LLC Resonant Converters . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2 Fundamentals of the Proposed RCV SR Algorithm . . . . . . . . . . . . . . . . . . . . . . 21

2.2.1 Below-Resonance Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.2.2 Above-Resonance Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.2.3 Light-load Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.2.4 Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.2.5 Sensitivity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.2.6 RCV SR Driving Strategy for Half-Bridge LLC Converters . . . . . . . . . . . . . . 31

2.2.7 RCV SR Driving Strategy for Full-Bridge LLC Converters . . . . . . . . . . . . . . 32

2.3 Implementation of RCV SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.4 Simulation and Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3 LLC Synchronous Rectification Using Volt-Second Products . . . . . . . . . . . . . . . . . . 45

3.1 Time Domain Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.2 VSP SR Driving Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.2.1 Steady-State Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.2.2 Transient Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.3 Implementation of VSP SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.4 Simulation and Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4 Enhanced Small-Signal Modeling of Charge-Controlled Resonant Converters . . . . . . . . . 67

4.1 Small-Signal Modeling for Open-Loop CLLC Resonant Converters . . . . . . . . . . . . . 68

4.2 Small-Signal Modeling of Charge-Controlled Resonant Converters . . . . . . . . . . . . . . 76

4.2.1 Conventional Charge Mode Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.2.2 Enhanced Charge Mode Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.2.3 LLC Resonant Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.3 Simulation and Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

vii
5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.1 Conclusions and Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

viii
List of Tables

Table 1.1 Comparisons of Existing LLC SR Technologies . . . . . . . . . . . . . . . . . . . . . . 11

Table 2.1 Key Components for Prototyping RCV SR . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 2.2 System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 3.1 System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 3.2 Comparisons of the proposed SR with vds.on based SR methods . . . . . . . . . . . . . . 65

Table 4.1 System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 4.2 Compensator Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

ix
List of Figures

Figure 1.1 a) The block diagram of a two-stage on-board battery charger. b) The block diagram of

a typical DC/DC resonant converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 1.2 Conventional LLC SR control methods: current-driven method with the CT mounted on

the secondary side for sensing the rectifier current, which occupies space and introduces

extra conduction losses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 1.3 Conventional LLC SR control methods: current-driven method with the CT located on

the primary side for sensing the resonant current, which exchanges space with increased

circuit complexity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 1.4 Conventional LLC SR control methods: vds.on sensing method. vds.on is the voltage

across the SR switches in the on-state for controlling the SR. The magnitude is small

and can be easily affected by the parasitic components, such as the leak inductance (Llk )

and the SR output capacitance (Cds ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 1.5 Typical waveforms of the vds.on based adaptive SR tracking the rectifier current conduc-

tion time by comparing vds.on1 with the internal voltage thresholds. . . . . . . . . . . . . 8

Figure 1.6 Potential challenges of the vds.on based adaptive SR: early turn-on in the below-resonance

region due to voltage ringing-induced SR body diode conduction. . . . . . . . . . . . . 9

Figure 1.7 Potential challenges of the vds.on based adaptive SR: premature turn-off in the above-

resonance region, due to drastic change in the current slope and voltage across the leak-

age inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

x
Figure 1.8 a) Schematic diagram of a charge-controlled CLLC resonant converter. b) Conventional

small-signal model of the charge loop, where the charge feedback is approximated by

using irec , overlooking the effect of magnetizing current (im ). c) Conceptual illustration

of the frequency response of the conventional charge-loop model, which indicates the

prediction error caused by the approximation. . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2.1 Schematic diagram of a half-bridge center-tapped LLC resonant converter with syn-

chronous rectification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 2.2 a) The key waveforms and b) the corresponding equivalent models of the resonant tank

in the below-resonance region. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 2.3 a) The key waveforms and b) the corresponding equivalent models of the resonant tank

in the above-resonance region. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 2.4 Light-load conditions: a) the key waveforms and b) the corresponding equivalent models

of the resonant tank in the below-resonance region. . . . . . . . . . . . . . . . . . . . . 20

Figure 2.5 Light-load conditions: a) the key waveforms and b) the corresponding equivalent models

of the resonant tank in the above-resonance region. . . . . . . . . . . . . . . . . . . . . 21

Figure 2.6 The proposed RCV strategy senses the large voltage signals ➊ and controls the SR by

simply integrating and comparing the voltage signals ➋. The typical waveforms show

the below-resonance operation for SR1 as an example to visualize the concept of the

proposed RCV strategy, where v p1.int and vCr .int are the voltage integrations of linear

combinations of the sensed voltages, defined in the following section. . . . . . . . . . . 22

Figure 2.7 The key switching sequence of the proposed RCV SR method in the below-resonance

region, heavy-load conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 2.8 The key switching sequence of the proposed RCV SR method in the above-resonance

region, heavy-load conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 2.9 The key waveforms in light-load conditions for a) below resonance, and b) above reso-

nance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 2.10 The geometric representation of sensitivity analysis using the first harmonic approximation. 31

Figure 2.11 Block diagram of the RCV SR control method. . . . . . . . . . . . . . . . . . . . . . . 34

xi
Figure 2.12 Simulation results for the constant current mode operation. The converter operates at

27 A, a) 250 kHz, b) 230 kHz, c) 220 kHz, and d) 200 kHz; the RCV-controlled SR on-

time (tRCV ) is very close to the ideal rectifier current conduction time (tCOND ) as shown

in each condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 2.13 Simulation results for the constant power mode operation. The converter operates at

650 W, a) 180 kHz, b) 175 kHz, c) 173 kHz, and d) 167 kHz. In each condition, the

RCV strategy accurately enables the SR during the ideal rectifier current conduction time. 37

Figure 2.14 Simulation results for the constant voltage mode operation, where the LLC converter

operates at 30 V output and a) 60 %, b) 45 %, c) 23 %, and d) 5 % load. Regardless of

the load change, the ideal rectifier current conduction time is accurately predicted by the

RCV strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 2.15 The experimental setup: the prototype of the RCV SR controller on the 650 W/ 24 V

LLC resonant converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 2.16 Experimental results at the maximum power and below resonance, 650 W/ 170 kHz:

a) the vds.on sensing method turns off the SR early due to the inductive voltage offset

induced from the stray inductance, whereas b) the RCV strategy effectively estimates

the zero current crossing point by comparing the integrals of large and stable voltage

signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 2.17 Experimental results at the maximum current, 27 A/ 250 kHz: a) because of the parasitic

effects, the traditional vds.on sensing method turns off the SR prematurely, while b) the

RCV strategy effectively estimates the zero current crossing by comparing the integrated

voltage signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 2.18 Experimental results at light-load conditions, 5 A/ 30 V: a) the traditional vds.on sensing

method turns off the SR early due to the effect of parasitic elements. b) By using the

integrated voltage signals, the on-time error at light load is short in comparison. . . . . . 40

Figure 2.19 The ideal, RCV-controlled and traditional vds.on sensing-based SR on-time are compared.

Experiments are conducted in a) the constant voltage mode in light-load conditions,

b) the constant power mode, and c) the constant current mode. The RCV strategy is

effective in multiple operating conditions by using the integrations of the large voltage

signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

xii
Figure 2.20 Comparison of the effect of the SR on-time error on a) the efficiency and b) the SR

MOSFET temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 2.21 The dynamic test waveforms under a large frequency step change, a) from 235 kHz to

190 kHz, and b) from 190 kHz to 235 kHz: the RCV-controlled SR tracks the actual rec-

tifier current conduction time instantaneously under severe voltage and current dynamics. 43

Figure 3.1 Typical waveforms of a half-bridge LLC resonant converter in the above-resonance region. 46

Figure 3.2 Typical waveforms of a half-bridge LLC resonant converter in the below-resonance region. 49

Figure 3.3 a) a typical LLC resonant converter with synchronous rectification, including circuit

parasitic components. b) block diagram of the conventional vds.on based SR and the

proposed Volt-Second Product (VSP) based SR; the former depends on the drain-source

voltage during the turn-on phase, while the latter employs the drain-source voltage dur-

ing the turn-off phase. c) vds.on1 and vds.on2 are in millivolt range and are easily affected

by the parasitic effects, whereas the proposed VSP SR uses large-magnitude voltage

signals and improves the SR on-time. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 3.4 Functional block diagram of the proposed Volt-Second Product (VSP) SR. . . . . . . . . 52

Figure 3.5 Typical waveforms of the proposed VSP SR: a) above-resonance and b) below-resonance

operations. The Tsc time window allows for correct setting of the SR for both cases. . . . 54

Figure 3.6 System block diagram of a typical closed-loop controlled LLC resonant converter with

the proposed VSP SR controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 3.7 The relationship between the change in the switching period (∆ts ) and the closed-loop

controller gain defines the rate of change in the rectifier current conduction time in the

above-resonance region. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 3.8 Block diagram for implementation of the proposed VSP SR using TMS320F28379D

with only a few external logic gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 3.9 Timing sequence of the VSP SR controller for below- and above-resonance operations.

tSR1 [k] is computed at ADC1 where vDp1 [k] is sampled. Sync1 resets the time counter,

while Cap1 captures tcnd1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 3.10 Flowchart of ADC1 interrupt service routine (ISR). In the kth cycle, it executes the core of

the VSP SR algorithm to determine the SR on-time tSR1 [k] based on tcnd1 [k − 1], vDp1 [k],

and vT [k]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

xiii
Figure 3.11 Plot of the theoretical, normalized rectifier current conduction time, tA , and time window

Tsc , considering 25 %, 50 %, 75 %, and 100 % load. The selection of Tsc is around the

center with sufficient margin between the rectifier current conduction time and tA . . . . 61

Figure 3.12 Simulation results of the VSP SR and the conventional adaptive SR under closed-loop

regulation: a) vo rising and b) vo falling. In both cases, the VSP SR maintains the dead

time δ T above the preset safe margin DT , whereas the conventional adaptive SR has

multiple cycles with insufficient safe margin during frequency rise, increasing the risk

of cross conduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 3.13 The prototype of the 650 W/ 24 V LLC resonant converter with the proposed VSP SR

controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 3.14 Steady-state test results in constant voltage regulation at 30 V/ 650 W, fs = 167 kHz: a)

the conventional adaptive SR turns on the switch early due to voltage ringing-induced SR

body diode conduction, introducing reverse current; b) the proposed VSP SR controls

SR on-time properly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 3.15 Steady-state test results in constant current regulation at 27 A/ 540 W, fs = 238 kHz:

a) the conventional adaptive SR turns off the switch prematurely due drastic change in

the current slope and voltage across the leakage inductance; b) the proposed VSP SR is

tolerant to the parasitic effects, maintaining consistent dead time. . . . . . . . . . . . . . 63

Figure 3.16 Efficiency test results under: a) constant voltage regulation, Vo = 30 V , and b) constant

current regulation, Io = 27 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 3.17 The dynamic test waveforms under a large command change, a) from Vmin to Vmax , and

b) from Vmax to Vmin : the VSP SR tracks the rectifier current conduction time properly

under severe voltage and current dynamics. . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 4.1 The schematic diagram of a half-bridge CLLC resonant converter. . . . . . . . . . . . . 68

Figure 4.2 The AC equivalent circuit of the resonant tank using a transformer T-model. . . . . . . . 69

Figure 4.3 Extended Describing Functions (EDF) model of an open-loop, direct frequency-controlled,

half-bridge CLLC resonant converter. Input current is proportional to the sine compo-

nent of the primary resonant current, which forms the basis of the proposed enhanced

charge-control model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

xiv
Figure 4.4 a) Schematic diagram of a CLLC resonant converter with charge mode control. b) Block

diagram of the charge loop: the conventional model approximates the charge loop by

using irec , overlooking the effect of magnetizing current (im ). c) Conceptual illustration

of the frequency response of the charge loop: the proposed model removes the prediction

error, which is useful for high-bandwidth design. . . . . . . . . . . . . . . . . . . . . . 77

Figure 4.5 Block diagram of the conventional charge model. The equivalent feedback loop from

the output does not fully represent the actual charge loop. . . . . . . . . . . . . . . . . . 79

Figure 4.6 Timing sequence diagram for charge control without slope compensation along with the

perturbation applied for linearization. . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 4.7 Relationship between the sine and cosine components of the resonant current using Ex-

tended Describing Functions (EDF) in: a) time domain and b) complex plane. . . . . . . 81

Figure 4.8 Proposed block diagram of the small-signal model of a charge-controlled resonant con-

verter: a) direct b) cascade form. The feedback signal is the sine component of the

primary resonant current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 4.9 Timing sequence diagram for charge control with slope compensation along with the

perturbation applied for linearization. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 4.10 Proposed equivalent small-signal circuit of a charge-controlled CLLC converter: focused

on the resonant tank that is affected by the charge loop. . . . . . . . . . . . . . . . . . . 86

Figure 4.11 Comparison of the conventional and proposed analytical models (charge control-to-

output transfer function, Gvc (s)) with circuit simulation results at a) 234 V / 3.3 A; b)

320 V / 3.3 A; c) 400 V / 2.5 A; d) 400 V / 0.8 A. Estimation errors from the conventional

model render it unsuitable for control-loop analyses especially in a high-bandwidth de-

sign. The proposed model successfully predicts the frequency response across all the

conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 4.12 The effect of slope compensation on the charge loop gain Gvc (s) predicted by the pro-

posed model assists rapid selection of slope compensation. . . . . . . . . . . . . . . . . 92

Figure 4.13 Simplified schematic diagram and key components of the test setup for verifying the

proposed model using a commercial charge controller. . . . . . . . . . . . . . . . . . . 93

Figure 4.14 Analytical and experimental loop frequency response under a) constant-voltage and

b) constant-current regulation; the analytical results using the proposed model closely

match the experimental measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . 94

xv
Figure 4.15 Experimental transient response under closed-loop regulation: a) 100 % – 80 % load; b)

60 % – 40 % load. The time domain response demonstrates stable operation, as predicted

in the frequency domain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

xvi
List of Abbreviations

AC Alternating Current

ADC Analog to Digital Conversion

BBCC Bang-Bang Charge Control

CT Current Transformer

DC Direct Current

EDF Extended Describing Functions

EV Electric Vehicle

FHA First Harmonic Approximation

HHC Hybrid-Hysteretic Control

IC Integrated Circuit

ISR Interrupt Service Rutine

MOSFET Metal–Oxide–Semiconductor Field-Effect Transistor

PCB Printed Circuit Board

RC Resistor-Capacitor

RCV Resonant Capacitor Voltage

SR Synchronous Rectification

VSP Volt-Second Product

xvii
Acknowledgments

I would like to take this opportunity to express my sincere gratitude to my supervisor, Prof. Martin Ordonez,

for all his support, guidance, and mentoring on my Ph.D. study throughout the past five years, during which

I have gained so much experience as well as technical and soft skills from him. This is the most precious

period in my career.

Special thanks to my committee members, Prof. William Dunford, and Prof. Wilson Eberle, for their

feedback on my research, which make it more well-rounded.

My appreciation also goes to the University of British Columbia (UBC), the Natural Sciences and En-

gineering Research Council (NSERC), and Delta-Q Technologies for supporting my research project. In

particular, Mr. Marian Craciun and Mr. Chris Botting from Delta-Q Technologies generously shared their

industrial experience with me, making my research more practical.

Many thanks to my colleagues, especially Mr. Franco Degioanni, Mr. Abbas Arshadi, Mr. Ettore Scabeni

Glitz, Dr. Ali Saket, Dr. Ignacio Galiano, Dr. Francisco Paz, and Dr. Ion Isbasescu, for all the informative

discussions and technical support.

Finally but importantly, I thank my family, especially my beloved wife, Bonnie, for all their unconditional

love, accompaniment and support as always.

xviii
Chapter 1

Introduction

1.1 Motivation
In recent years, the demand for electric vehicles (EVs) has been growing as many countries are aiming for

lower carbon emissions. To charge EV batteries, battery chargers are required to convert alternating current

(AC) from the utility grid to direct current (DC). Therefore, the power conversion performance is critical.

High-performance battery chargers convert power efficiently, which has environmental and financial benefits.

Moreover, they regulate the charging voltage in a certain range to avoid battery overcharge and undercharge,

which extends the battery life and makes the batteries and EVs more sustainable.

To convert AC to DC and facilitate EV battery charging, on-board battery chargers are equipped not only

on passenger EVs [4–6] but also on utility vehicles, such as golf carts and fork lifts [7, 8]. On-board battery

chargers have size and weight constraints, which makes the power conversion efficiency and loss reduction

even more critical. Conventionally, on-board battery chargers are composed of two stages: an AC/DC power

converter followed by a DC/DC converter, as shown in Fig. 1.1 (a). The first stage is mainly responsible

for maintaining power quality, which benefits the utility grid in many ways, such as maximizing real power

distribution. It also provides a constant, direct voltage to the second stage. The second stage takes the DC

output from the first stage and converts it to the required output voltage or current to charge the battery. It

responds to the command and regulate the output dynamically. In this research, the efficiency performance

and dynamic response of the DC/DC converter are the main focus.

In terms of efficiency improvement, a common approach is to reduce switching and conduction losses

of the power converter. Switching losses are caused by the switching of active components in the circuit.

These losses are proportional to the switching frequency and the overlap area of voltage and current of the

1
 On-Board Battery Charger
Iout

vac AC/DC DC/DC

Vin Vout Battery
(grid) Converter Converter

(a)

Iout

Vin Vout

Active Resonant Passive

Filter
Switch Tank Rectifier
(b)

Figure 1.1: a) The block diagram of a two-stage on-board battery charger. b) The block diagram of a
typical DC/DC resonant converter.

switch during the transition. When the switches are switched at zero voltage or current, this is considered

soft-switching, and the switching losses are small. To achieve soft switching, advanced power converter

designs employ a resonant topology. A typical DC/DC resonant converter is composed of active switches

followed by a resonant tank, a transformer for isolation, a rectifier stage, and a output filter stage, as shown

in Fig. 1.1 (b). It achieves zero-voltage or zero-current switching using the resonant behaviors among the

capacitors and inductors in the resonant tank [9–11]. Among various topologies of resonant converters, the

LLC resonant converter, of which the resonant tank is composed of two inductors and one capacitor, has been

broadly applied to power converter designs [12–14]. LLC resonant converters are suitable for the DC/DC

stage of battery chargers primarily due to the ability to step up and down the output voltage in a certain

range [15–18].

LLC resonant converters first convert the DC input to AC to enable the resonance in the resonant tank.

The resonant voltage and current are high-frequency AC, which facilitates the power transfer using a com-

pact, high-frequency transformer. To charge batteries with DC power, the AC power inevitably needs to be

rectified. In LLC converters, the rectifier stage after the transformer is conventionally composed of rectifier

diodes. When conducting, the forward voltage drop of the diode and the average current flowing through

cause conduction losses. For high-power and high-current applications, the high current stress results in high

conduction losses, decreasing the efficiency [19–21].

To reduce the conduction loss of the output rectifiers and further boost the power conversion efficiency,

2
synchronous rectification (SR) technologies are developed [22–24]. SR replaces the rectifier diodes with

active switches. The SR switches have low resistance in the on state and have the same characteristics as

diodes in the off state. Due to the small on-state resistor, the conduction loss of SR is very little. Therefore,

SR is particularly effective to reduce the conduction loss and improve the efficiency of high power, high

current battery chargers. From the efficiency point of view, to benefit the most from SR, it is ideal to make

the SR on-time the same as the rectifier current conduction time. The efficiencies of different SR methods

are mainly determined by the difference between the SR on-time and the actual rectifier current conduction

time. The larger the on-time error is, the less efficient the SR becomes. There are other aspects such as noise

tolerance and transient response, which opens the door to research opportunities.

In terms of the dynamic performance, to make the resonant converter in the DC/DC stage respond to the

battery charging command quickly, high loop bandwidth is desirable. Conventionally, when only the output

voltage is sensed and controlled, the control scheme is categorized as voltage mode control [25–27]. Since

the output voltage is the only variable that is controlled, the dynamics of current can complicate the design of

the voltage mode controller. Consequently, current mode control is applied to overcome this limitation. With

current mode control, it is common to use the inductor current as the feedback. Together with the output

voltage feedback, the control system forms a cascade loop architecture, where the current feedback is the

inner loop and the voltage feedback is the outer loop [28–30], and the compensator for each of the loops can

be designed individually. With this design strategy, both the current and voltage are controlled, and with a

couple of basic compensators, high loop bandwidth design can be achieved.

For resonant converters, because the resonant inductor current is alternating, it is convenient to use the

integration of the current as the variable to be controlled. Since the integration of current over time is the

amount of electric charge, this control scheme is named charge mode control [31–33]. In this case, the charge

control loop is the inner loop and the output voltage loop is the outer loop. Similar to current mode control,

the charge inner loop also changes the dynamics of the system, and it makes the design of the outer loop

compensator easier to achieve high loop bandwidth. Since charge mode control also benefits high-bandwidth

design but differs from current mode control, it is essential to explore the small-signal dynamic model and

proper compensator design to unlock its potential.

1.2 Objectives
The objectives of this work are to explore new Synchronous Rectification (SR) technologies that further

boost the efficiency of LLC resonant converters and to find the dynamic model of the resonant converter

3
to achieve high-bandwidth design, so that both the efficiency and dynamic performance improvements are

covered. SR is effective for reducing the conduction loss in the rectifier stage, particularly for high power and

high current applications. One of the major challenges of the conventional SR for LLC resonant converters

is to overcome the voltage noise introduced by the parasitic components, for the parasitic effects reduce the

efficiency. In this work, two SR solutions will be introduced. The control of the SR in both cases are based

on large-magnitude voltage signals, rejecting the parasitic effects and improving the efficiency.

Regarding the dynamic performance aspect, this work will look into the drawbacks of existing small-

signal models and propose an enhanced model that unlocks high-bandwidth designs. In particular, this work

develops the model for resonant converters under charge mode control. A systematic methodology will

be introduced. It is applicable to the mainstream resonant topologies, such as LLC and CLLC resonant

converters. The following literature review starts with investigations in existing SR technologies, followed

by explorations in the small-signal modeling of resonant converters.

1.3 Literature Review

1.3.1 Synchronous Rectification Using Current Transformers

In current-driven methods, current transformers (CT) are widely applied as the current sensor, and in this

work, it is categorized as the first group of the existing Synchronous Rectification (SR) technologies. The

CT monitors the rectifier current for controlling the SR switches, as illustrated in Fig. 1.2. Since the CT

on the secondary side is in series with the SR switches, the sensed current signal can be directly used as

the SR control signal. The SR switches are on and off when the sensed current is higher or lower than

a threshold [34, 35]. Yet, the main challenge of CT is the space occupied, which causes constraints for

high-power density design. In addtion, it introduces extra conduction losses. In the research [36], an energy

recovery current-driven SR is proposed. A set of energy recovery winding is integrated with the CT for

recycling the current sensing energy, improving the efficiency of the CT. However, each SR requires one

CT for gate driving; two CTs for center-tapped full-wave rectification are needed, which occupy even more

space. For full-bridge rectification, the transformer structure is even more complicated. The high volume

occupied by the CT is unfavorable for a compact design. A current-driven SR for center-tapped full-wave

rectifiers in [37] requires only one CT. The CTs are integrated into one, and the utilization of the CT is

improved. In the publications [38–40], the application targets toward voltage-doubler and full-bridge rectifier

topology, and the current sensor count for each topology is reduced to one as well. Another idea to reduce the

space occupied by the CTs is to integrate them with the main transformer, as investigated in the literature [41].

4
 Gate Driver Circuit
extra conduction
vgs.SR1
losses
HS
n::
iD1
vgs.HS
ir Lr SR 
Vin CT
LS irec
vgs.LS vinv Lm
Cr im CT Co Ro vo
iD SR 
vCr

vgs.SR2

Gate Driver Circuit

Figure 1.2: Conventional LLC SR control methods: current-driven method with the CT mounted on
the secondary side for sensing the rectifier current, which occupies space and introduces extra
conduction losses.

Intrinsically, placing the CT in series with the power loop introduces extra losses. The peak rectifier current

of LLC converters is high, and the CT in series with the power loop has to be well-designed to prevent

saturation.

For avoiding high current sensing, the other group of the current-driven methods places the CT in series

with the resonant tank on the primary side [42–45], as illustrated in Fig. 1.3. The current stress of this kind is

less than that of secondary-side CTs for most applications using LLC converters. Only one CT is needed for

sensing the resonant current. However, the zero-current crossing of the resonant current (ir ) is different from

that of the rectifier current (irec ) due to the component of magnetizing current (im ). Therefore, additional

circuits for canceling im are needed. Since the slope of im is proportional to the output voltage (Vout ) when

the transformer is coupled, the output voltage is sensed and converted to cancel im . As a result, as long as

the portion of im is completely subtracted from ir , the remaining portion is in-phase and proportional to the

rectifier current and can be applied to generate the SR gate driving signal.

1.3.2 SR Based on the Drain-Source Voltage During the Turn-on Phase (vds.on based)

Recent research and development of SR technologies has shifted from incorporating current sensors or cur-

rent transformers to current sensor-less methods to reduce the associated size and conduction losses. The

mainstream of current sensor-less methods focuses on the drain-source voltage (vds.on ) sensing method,

where the SR drain-source voltage during the turn-on phase is used as the feedback signal. The primary

benefit compared with the current-driven methods is the removal of the current sensors, which eliminates the

power losses and reduces the layout space.

5
 vgs.SR1
HS
n::
iD1 SR 
vgs.HS
ir Lr
Vin
LS irec
vgs.LS vinv Lm
vCr CT
im Co Ro vo
iD
Cr
SR 

ir sensing & vo vgs.SR2

im cancellation
extra conduction losses
vgs.SR1
vgs.SR2

Figure 1.3: Conventional LLC SR control methods: current-driven method with the CT located on
the primary side for sensing the resonant current, which exchanges space with increased circuit
complexity.

The first group of this category, which is also widely adopted in the industry, directly senses the voltage

across the SR MOSFETs during the turn-on phase (vds.on ) without any compensation [46–48]. Due to the

small turn-on resistance of the SR MOSFETs, the sensed voltage is minimal. As a result, high accuracy,

small offset, and fast response comparator design is needed. Besides, the small vds.on is easily affected by

the voltage drops on the parasitic components. As illustrated in Fig. 1.4, the sensed voltage signal contains

the voltage across the leakage inductance (Llk ). The inductive voltage offsets the sensed vds.on , which causes

premature turn-off of the SR.

The leakage inductance exists in both the signal sensing loop and the MOSFET package. The leakage

inductance in the signal sensing loop can be reduced by taking extra care in the PCB (printed circuit board)

layout design, such as placing the SR controller as close to the SR switch as possible, which creates PCB

layout constraints. The leakage inductance in the MOSFET package, however, is still significant [49]. Pre-

mature turn-off of the SR leads to on-time error; a larger portion of the rectifier current is conducted by the

MOSFET body diode, which sacrifices the power conversion efficiency and increases the device temperature.

Therefore, system design effort is spent on reducing the parasitic effects. For instance, the voltage sensing

circuitry must be placed as close as possible to the SR switch to create a Kelvin connection; this introduces

design constraints.

The second group of the vds.on sensing method is to add an Resistor-Capacitor (RC) compensation net-

work in parallel with the MOSFET to compensate for the inductive voltage offset and further reduce the SR

on-time error. In the literature [50], a resettable RC circuit is introduced to compensate for the voltage offset

caused by the leakage inductance. In order to achieve good performance, the time constant of the RC circuit

6
 vds.on sensing &
vgs.SR1
L lk compensation
vds.on vds.on is small and noisy;
HS Cds
i
n:: D1 vlk vulnerable to parasitic effects
vgs.HS
ir Lr SR  Llk
Vin
LS irec vgs.SR1
vgs.LS vinv Lm
Cr vgs.SR2
im Co Ro vo
iD SR  Llk
vCr
vlk
Cds
vds.on
vds.on sensing &
L lk compensation vgs.SR2

Figure 1.4: Conventional LLC SR control methods: vds.on sensing method. vds.on is the voltage across
the SR switches in the on-state for controlling the SR. The magnitude is small and can be easily
affected by the parasitic components, such as the leak inductance (Llk ) and the SR output capaci-
tance (Cds ).

must be carefully selected to match the impedance ratio of the leakage inductance and the MOSFET on-state

resistance. However, the leakage inductance varies with the MOSFET package and is usually not a confined

specification in datasheets. Besides, the MOSFET on-state resistance varies with manufacturing tolerances

and drifts with temperature. Therefore, it is challenging to match the impedance ratio. Another RC compen-

sation circuit to tackle the inductive voltage offset issue is proposed in [51, 52]. Compared with the prior

research, the compensation circuit is simplified, and yet accurate impedance matching is still required.

1.3.3 vds.on based Adaptive SR

Considering the uncertainty of the leakage inductance and the associate voltage offset, vds.on based adaptive

SR has been developed to reduce the SR on-time error [53–56], and this is categorized as the third group

in the vds.on based methods. Adaptive SR is achieved by adjusting the SR on-time according to the time

difference between the rectifier conduction time and the SR on-time from the previous switching cycle. The

adaptive algorithm is purely based on time; first, the on-time error is detected, and then the SR conduction

time is changed by a time step in the next cycle. The adaptive SR is initially for adjusting the SR turn-off

instant; this concept is also used for reducing the SR turn-on error in the follow-up research [55, 57]. Some

SR methods deliberately leave a dead-time period for safe operation margin to prevent reverse current or

even cross-conduction of the SR switches [58–60]. The objective is to track the rectifier current conduction

time while maintaining the safe margin; however, following the adaptive algorithm, the safe margin can be

smaller in transient response, particularly when frequency increases. Other research in this field integrates

7
 vds1

vds.on1
tcnd1[k-1] tcnd1[k]
vth.rev
vth.off
vth.on
iD1
iD2

vgs.SR1
tSR1[k-1] tSR1[k]

t0 t1 t2 t3 t4 t5 t6 t

Figure 1.5: Typical waveforms of the vds.on based adaptive SR tracking the rectifier current conduction
time by comparing vds.on1 with the internal voltage thresholds.

the adaptive SR method with the primary closed-loop controller [61–63]. Nevertheless, as the adaptive SR

methods still rely on measuring vds.on , improving the noise immunity remains a challenge. More details are

explained as follows.

Fundamentally, vds.on based SR contains a high-precision comparator that compares vds.on with two

threshold voltages (vth.on and vth.o f f ) to determine the SR on-time. As in the typical operating waveforms

shown in Fig. 1.5, the drain-source voltage of SR1 , vds1 , is illustrated to give a holistic view. The SR1 drain-

source voltage during the turn-on phase, vds.on1 , controls SR1 . The SR is on when vds.on1 is lower than vth.on

and off when it is higher than vth.o f f . Note that vds.on1 is not a perfect replica of the inverse of the current

waveform due to the voltage drops on the leakage inductance in the package of the switch as well as in the

voltage sensing loop. This leads to the premature turn-off of SR, as the time difference t1 to t2 shows in

Fig. 1.5.

For an adaptive SR, generally, there is a third threshold level (vth.rev ) to detect the time when the body

diode is reverse-biased, which is used as a reference for the next switching cycle to adjust the SR on-time. For

example, in Fig. 1.5, by comparing vds1 with vth.o f f and vth.rev , the time difference from t1 to t2 is detected.

If the time difference in the k − 1th cycle is sufficiently large, the controller increases tSR1 in the kth cycle

(from t4 to t5 ) to compensate for the time difference. Conversely, if the time difference is small, the controller

shrinks the SR on-time for the next cycle.

Although the adaptive SR effectively compensates for the on-time loss caused by the leakage inductance,

there are several challenges in practical applications. The first challenge is filtering the sub-resonance caused

by the parasitic components during the discontinuous conduction intervals. Figure 1.6 illustrates the typical

waveforms for below-resonance operation considering the effect of leakage inductance and parasitic capaci-

8
 vds1

vds.on1
vth.rev
vth.off
vth.on

iD1
iD2
vgs.SR1
(ideal)
(non-ideal)

t0 t1 t2 t3 t4 t5 t6 t7 t

Figure 1.6: Potential challenges of the vds.on based adaptive SR: early turn-on in the below-resonance
region due to voltage ringing-induced SR body diode conduction.

vds1

vds.on1
vth.rev
vth.off
vth.on

iD1
iD2
vgs.SR1
(ideal)
(non-ideal)

t0 t1 t2 t3 t4 t5 t6 t7 t

Figure 1.7: Potential challenges of the vds.on based adaptive SR: premature turn-off in the above-
resonance region, due to drastic change in the current slope and voltage across the leakage in-
ductance.

tance (as Llk and Cds shown in Fig. 1.4). During the discontinuous conduction interval, the lumped parasitic

capacitors and the equivalent inductor Lr ∥ Lm cause the sub-resonance, the amplitude of which varies with

the initial voltage and current. As the initial current in the equivalent inductor is load-dependent, the voltage

amplitude can be larger in heavy loads, forcing the body diode to conduct.

The waveforms in Fig. 1.6 illustrate a scenario where the amplitude is large enough to force the body

diode of the SR MOSFET to conduct. Note that from t0 to t1 , when vds1 is lower than the turn-on threshold

(vth.on ), it meets the criteria to turn on the SR, which consequently causes early turn-on. Turning on the SR

MOSFET during this interval forces current to flow from the output to the input side; this reverse current

then circulates between the input and the output, which reduces the system efficiency. A common approach

to avoid mis-triggering is to set a blanking time that neglects any turn-on triggering. And yet, the parasitic

component resonant frequency depends on the system parameters, which makes the blanking time difficult

to determine.

9
 The second challenge is premature turn-off due to the voltage drop on the leakage inductance in the

above-resonance region. As shown in Fig. 1.7, vds1 increases instantaneously at t2 , which is caused by the

drastic change in the current slope, as well as in the voltage across the leakage inductance, known as Llk didtD1 .

This voltage increase can reach the vth.rev level, causing false detection of the body diode conduction time

and consequently premature SR turn-off.

1.3.4 Alternative SR Technologies

Since the vds.on method is sensitive to noise and parasitic effects, other SR control methods based on high-

magnitude voltage signals have been developed to avoid noise issues. These methods are categorized in the

alternative SR category; they require neither lossy current sensors nor sensitive voltage detection. A fixed

on-time approach for approximating the SR on-time is proposed in [64], while the SR on-time is estimated

using the output voltage in [65]. Nevertheless, both of methods apply only to the below-resonance operation,

which is not suitable for battery charging applications where the above-resonance operation exists. To cover

both below- and above-resonance operations, a method using the polarity of the inverter and the rectifier

voltage is introduced in [66], which is also based on high-magnitude voltage signals. However, the SR

on-time error increases with the switching frequency in the above-resonance region. For battery chargers,

this region corresponds to the state of charge where the battery is charged with high current at low voltage.

Another publication [67] proposes a dual edge tracking control method for the SR. This method also utilizes

large voltage signals to determine the SR conduction time. Yet, the SR on-time tracking method is similar

to conventional adaptive SR, creating opportunities for further improvement. Recent research on SR for

resonant converters has focused on computing the SR on-time using time-domain models [68–70]. Since SR

on-time solutions depend on the system parameters, the challenges are to overcome the parameter deviation

and reduce the computational complexity.

Table 1.1 summarizes the existing LLC SR control technologies in terms of the amount of current sensors,

noise tolerance, operating range, circuit complexity, and system parameter dependency. The current-driven

methods employ CTs as the current sensor introduces more power losses than the others, especially for CTs

mounted on the secondary side. As opposed to the current-driven method, vds.on sensing methods do not

require extra sensing components, and the induced extra power losses are minimized. Yet, the parasitic

effects have a significant impact on the conventional vds.on sensing method, causing premature turn-off of the

SR and affecting the operating range. With the SR on-time compensation circuit, due to the improvement in

noise tolerance, the on-time error can be reduced. However, it increases the circuit complexity and the SR

10
on-time variation range depends on the system parameters. The alternative methods attempt to avoid using

current sensors and the sensitive vds.on signal, and yet most of them are applicable only to a narrow operating

range or are highly dependent on the system parameters. Overall, the adaptive vds.on based method has good

characteristics from the listed aspects; however, there remain some challenges that will be discussed in the

Chapter 2 and 3.

1.3.5 Small-signal Modeling for Resonant Converters

Charge control for hard-switching topologies along with the small-signal model was introduced in [31–33].

In contrast with the well-known ripple-based control methods, particularly peak current mode control [71–

73], charge control first integrates the switching current and then compares the resulting charge signal with

the command to determine the duty cycle, switching frequency, or other control signals cycle-by-cycle. The

integrated current information is particularly useful for non-monotonic current that does not necessarily

peak at the end of switching. As this behavior is commonly seen in resonant topologies, charge control has

been applied to zero-voltage-switching multi-resonant forward converters [74] and was later developed for

resonant power converters.

Originally, charge controllers contain an integrator to integrate the sensed resonant current in every half

switching cycle [75, 76]. Recent publications studying LLC resonant converters utilize the resonant capacitor

voltage, as it resembles the integration of resonant current [77–79]. An example of a charge-controlled

resonant converter is shown in Figure 1.8 (a). The resonant converter under charge control has an inner

charger loop and an outer voltage loop. In the charge loop, the command vch is the result of the voltage loop

controller, and the feedback signal V1 is the resonant capacitor voltage. To determine the primary gate driving

signals, Bang-Bang Charge Control (BBCC) proposed in [77] compares the resonant capacitor voltage with

Table 1.1: Comparisons of Existing LLC SR Technologies

Current Noise Operating Circuit Sys. Parameter

Category Subgroup
Sensors Tolerance Range Complexity Dependency
current- 2nd -side two high wide high low
driven pri.-side one high wide high low
non-adaptive none low medium low low
vds.on sensing compensated none medium medium medium low
adaptive none medium wide low low
fixed on-time none high narrow low low
vo based none high narrow low low
alternative
model based none high wide low high
inverter polarity none high medium medium low

11
 vch Conventional ws Converter vo
Charge Model Model
irec
equivalent feedback: irec
vHS Cr1 Cr2 secondary current
L1 i t n:1 i2 overlooks the
Cf Ro effect of im
Vg vLS Lm im L2 vo
i1 (b)
Cr1
Cr2 conventional
V1 V2 measured
vo ws 100 ws 10 ws
ws Charge Loop Voltage Loop vch

prediction error
V1 vch votlage loop
Latch vsaw
controller Vref
vo
vch
prediction
error

(a) (c)

Figure 1.8: a) Schematic diagram of a charge-controlled CLLC resonant converter. b) Conventional

small-signal model of the charge loop, where the charge feedback is approximated by using irec ,
overlooking the effect of magnetizing current (im ). c) Conceptual illustration of the frequency
response of the conventional charge-loop model, which indicates the prediction error caused by
the approximation.

the command directly, whereas in Hybrid-Hysteretic Control (HHC) proposed in [78], a ramp signal (vsaw )

served as the slope compensation, is injected to the feedback or the command as illustrated in Fig. 1.8 (a).

Both methods demonstrate the benefits of charge control.

Modeling charge-controlled resonant converters requires modeling the power stage. Due to the nature

of large resonant current and voltage swing around the operating point, the linear approximation technique

for hard-switching topologies is not applicable [80]. To tackle small-signal modeling of resonant converters,

numerous methods have been researched [81–87]; these include sampled-data modeling methods, phasor

transformation, Extended Describing Functions (EDF), and averaged modeling methods, to name a few.

Among these methods, the EDF model using the first harmonic approximation is able to predict the fre-

quency response up to the Nyquist frequency, considering a reasonable amount of deviation from the reso-

nant frequency [88].

The EDF method has been widely used due to its systematic approach and relatively low computational

complexity. Modern resonant topologies such as LCC, LLC [89–92], and bidirectional resonant convert-

ers [93–96] have applied the EDF method for modeling. One drawback of the EDF method is the large size

of the derived state-space matrix, due to splitting the harmonic approximated signals into sine and cosine

12
components. Yet, thanks to the systematic procedure, the computation can be quickly executed, and the

frequency response can be plotted for control loop design.

The analytical model for charge-controlled resonant converters, however, has been rarely discussed. In

the literature [76, 78], the behavior of charge control is described based on circuit simulation results, while

the full analytical model is absent. Bang-bang Charge Control (BBCC) proposed by [77] employs an input-

output energy balance concept to derive the model, which results in a single-pole system that oversimpli-

fies the loop response. Follow-up studies modeling Hybrid-Hysteretic Control (HHC) used the same ap-

proach [97, 98]. As shown in Fig. 1.8 (b), the conventional model derived by input-output energy balance

leads to an equivalent feedback loop from the AC component of the rectifier current (irec ). Nevertheless, this

path overlooks the dynamics of the resonant tank, particularly the effect of magnetizing current (im ) that con-

tributes to the charge accumulated in the primary side. This omission causes estimation errors in forecasting

system frequency response as illustrated in Fig. 1.8 (c).

Charge control is known as a type of current control that simplifies the system dynamics. For a cascade

control design, a well-compensated inner charge or current loop leads to a system with two real poles in

the frequency range of interest [28–30]. The compensation for the outer loop is thus simplified, and a high-

bandwidth design can be easily achieved. The charge or current control loop is also beneficial to multiphase

or paralleled converters that require current balancing [99–101]. Other advantages include fast overcurrent

protection that makes the presence of the inner loop valuable.

1.4 Contributions of the Work

This work aims to improve both the efficiency and dynamic performance of resonant converters through

comprehensive analysis with a particular focus on conduction loss reduction using novel Synchronous Recti-

fication (SR) technologies and achieving high-bandwidth design using an enhanced small signal model. Two

novel SR methods, namely Resonant Capacitor Voltage based SR (RCV SR) and Volt-Second Product based

SR (VSP SR) for LLC resonant converters, are proposed in this work. Both are based on large-magnitude

voltage signals that reject the parasitic effects. Thus, the SR on-time errors due to parasitic components are

reduced, improving the efficiency. The RCV SR covers all the operating modes of LLC resonant convert-

ers, whereas the VSP SR offers a low component count solution, with a focus on the efficiency improve-

ments in the most lossy operating conditions. On the other hand, regarding the improvement of dynamic

performance, the enhanced small-signal modeling is developed for a dual loop, charge-controlled resonant

converter. Compared with the conventional model, this enhanced model successfully predicts the frequency

13
response in both low-frequency and high-frequency ranges, which enables a high-bandwidth design. The

developed methodology applies to both LLC and CLLC resonant converters. Detailed contributions for each

part are summarized as follows:

1. Resonant Capacitor Voltage based SR (RCV SR): In contrast to traditional current-driven methods,

the RCV SR controls the SR on-time without any current sensing components. The bulky and lossy current

transformer (CT) can be removed, simplifying the converter design and eliminating related losses. Since

the RCV SR uses integrations of large-magnitude voltage signals, it is insensitive to noise on parasitic com-

ponents. Compared with conventional vds.on sensing methods, which rely on small-magnitude drain-source

voltage during the on-state, the RCV SR significantly reduces the on-time error, improving the efficiency.

As opposed to other alternative methods such as the fixed on-time approximation, the RCV SR driving strat-

egy can be applied to multiple operating modes regardless of load and frequency variations. This work will

present the detailed operating sequence and prove that the proposed RCV SR applies to both below- and

above-resonance regions and covers heavy-load to light-load conditions, improving the efficiency perfor-

mance.

2. Volt-Second Product based SR (VSP SR): With the focus on industrial battery charging applications,

this work proposes another noise-tolerant SR method to improve the efficiency performance. The SR on-

time is determined based on the product of SR drain-source blocking voltage and rectifier current conduction

time. This Volt-Second Product based SR (VSP SR) employs the high-magnitude voltage signal instead of

the low-magnitude, noise-sensitive vds.on and so is more tolerant of the parasitic effects that cause SR on-

time error, improving the efficiency. The simplicity in the voltage sensing also demands fewer PCB (printed

circuit board) layout constraints. In steady-state operation, the VSP SR tracks the rectifier conduction time

following the drain-source blocking voltage; in transient operation, the volt-second product modulates the SR

on-time and maintains the safe operation margin, preventing reverse current and potential cross-conduction.

Moreover, the VSP SR can be implemented using a microcontroller with only a pair of voltage dividers and

a couple of basic logic gates, which is beneficial to a highly integrated design.

3. Enhanced Small-Signal Modeling for Charge-Controlled Resonant Converters: With the focus

on dynamic performance improvement, this part of the work introduces a small-signal modeling method-

ology for charge-controlled resonant converters to enable high-bandwidth design. The systematic approach

is applicable to both LLC and CLLC resonant converters. The proposed model corrects the conventional

charge mode control model and reveals that charge control forms an equivalent feedback path from the sine

component of the resonant current. This equivalent feedback loop directly corresponds to the actual feedback

14
path of the charge loop, which is not shown in the conventional model, and hence it provides comprehensive

and enhanced prediction of the system frequency response. In particular, the proposed model corresponds to

the actual frequency response across the frequency range of interest, whereas the conventional model starts

to deviate from the mid-frequency range. Due to the improvement in the mid- to high-frequency range, the

proposed model enables the design of high-bandwidth charge-controlled resonant converters.

1.5 Dissertation Outline

This work is organized as follows: in Chapter 2, the operating modes of LLC resonant converters are defined

first; a half-bridge, center-tapped LLC resonant converter is used as an example. It is followed by the

introduction of the proposed Resonant Capacitor Voltage based SR (RCV SR), where the operating principles

for below- and above-resonance regions are explained in detail, as well as the consideration in light-load

conditions. In addition, the sensitivities regarding system parameter deviation, especially the resonant tank

parameters, are analyzed and discussed. At the end of this chapter, the efficiency performance of RCV SR is

compared with an industrial vds.on based SR controller.

In Chapter 3, the LLC resonant converter is first analyzed using time-domain equations, which establishes

the fundamentals of the proposed Volt-Second Product based SR (VSP SR). Next, the operating principles of

VSP SR are introduced, followed by the transient analysis. Details of the implementation using a microcon-

troller are given. This chapter finishes with the efficiency performance comparison with an industrial vds.on

based adaptive SR controller.

Chapter 4 discusses the small-signal modeling of resonant converters. It starts with the modeling of

an open-loop, five-order CLLC resonant converter as an example and continues with a brief review of the

charge mode control and the conventional modeling method. Next, the proposed modeling methodology is

explained; the developed high-order CLLC resonant converter model can be directly reduced and applied to

LLC resonant converters. Finally, the proposed model is compared with the conventional model, with both

simulation and experimental results. A closed-loop design example using the proposed model is also given

to demonstrate that high loop bandwidth can be achieved with a simple compensator.

Chapter 5 concludes the contributions of this work and suggests potential research topics for the future.

This work contributes to the field of design of high-performance resonant converters for battery chargers in

terms of the improvement in efficiency and dynamics. The research outcomes are published in three IEEE

Transaction journals.

15
Chapter 2

LLC Synchronous Rectification Using

Resonant Capacitor Voltage

The essence of synchronous rectification (SR) drive is to synchronize the SR driving signal with the rectifier

current. Ideally, the SR MOSFET is on when the rectifier current starts conduction and off when the rectifier

current stops. When the SR MOSFET is on, it is equivalent to a resistor (Rds.on ); intrinsically, the voltage

drop on Rds.on is much less than the body diode forward voltage drop. Therefore, to minimize the conduction

loss is to maximize the SR MOSFET turn-on time. Late turn-on or early turn-off result in longer body-

diode conduction time, which sacrifices the efficiency performance. Early turn-on or late turn-off lead to

reverse current or even catastrophic shoot-through, which should be avoided. Since the SR drive relates to

the rectifier current, it is worthwhile to first define the operating modes of LLC resonant converters. In this

chapter, a half-bridge, center-tapped LLC resonant converter is studied; the schematic diagram is shown in

Fig. 2.1.

2.1 Operating Modes of LLC Resonant Converters

The conversion gain of the LLC resonant converter in this work is frequency-modulated. According to

the switching frequency, the operating regions can be divided into below-resonance and above-resonance

region, corresponding to the frequencies below and above the resonant frequency, respectively. Depending

on the voltage applied to the resonant tank and the transformer, each switching cycle can be divided into

four subsequences or operating modes in heavy-load conditions, despite the frequency region. In light-load

conditions, the subsequences are extended to six. This section begins with the heavy-load conditions.

In the below-resonance region, the key waveforms and the equivalent circuit of the resonant tank in each

16
 vgs.SR1
HS
n::
iD1 SR 
vgs.HS
ir Lr
Vin
LS irec
vgs.LS vinv Lm
Cr im Co Ro vo
iD
vCr
SR 

vgs.SR2

Figure 2.1: Schematic diagram of a half-bridge center-tapped LLC resonant converter with syn-
chronous rectification.

subsequence are illustrated in Fig. 2.2 (a) and (b). In Mode 1, from t0 to t1 , the transformer is decoupled

because vLm is smaller than the reflected output voltage nVo . In this mode, since the transformer is decoupled,

the resonant current and the magnetizing current must be equal. In this mode, Lm and Lr connected in series

starts to resonate with the resonant capacitor (Cr ). Since no current is transferred to the secondary side, the

rectifier current irec is zero in this mode.

Mode 2 starts at t1 and ends at t2 when the transformer is once again decoupled. At t1 , when the inverter

voltage (vinv ) switches to Vin , as long as vLm is greater than nVo , the secondary rectifier is forward biased and

the transformer is coupled, clamping the vLm at nVo . As a result, Lr and Cr starts resonate. The difference

between the resonant current ir and the magnetizing current im is transferred to the secondary side as irec .

Mode 2 ends at t2 when ir decreases and reaches im . At this moment, the rectifiers are reverse biased and the

transformer is decoupled, which completes the first half of the switching cycle.

The general form of the differential equation describing this circuit based on KVL is

dir dim
vinv (t) = vCr + Lr + Lm . (2.1)
dt dt

In Mode 1, the transformer is decoupled, Lr and Lm in series resonate with Cr , therefore,

dvCr
ir = im = Cr , (2.2)
dt

and
dir
0 = vCr + (Lr + Lm ) . (2.3)
dt

17
vinv vLr ir vLr ir irec n
Lr Lm Vin Lr Lm

vLm vLm nVo

ir Cr Cr
im im
im
vCr vCr
Mode 1: t0 ~ t1 Mode 2: t1 ~ t2

Vp2
vCr vLr ir vLr ir irec n
Vp1 V in
 Vin Lr Lm Lr Lm
vLm vLm nVo
irec Cr Cr
im im

vCr vCr
t0 t1 t2 t3 t4 t Mode 3: t2 ~ t3 Mode 4: t3 ~ t4

(a) (b)

Figure 2.2: a) The key waveforms and b) the corresponding equivalent models of the resonant tank in
the below-resonance region.

In Mode 2, since the transformer is coupled,

ir = im + irec /n, (2.4)

and vLm is clamped by nVo

dir
Vin = vCr + Lr + nVo . (2.5)
dt

During this period, only Lr resonates with Cr . The other half cycle is composed of Mode 3 and 4, which are

similar to Mode 1 and 2, having the same KCL equations as (2.2) and (2.4), respectively. The differences are

the voltage across the resonant tank and the polarity of the voltage across Lm . In Mode 3,

dir
Vin = vCr + (Lr + Lm ) , (2.6)
dt

whereas in Mode 4,
dir
0 = vCr + Lr − nVo . (2.7)
dt

In the above-resonance region, the key waveforms and the equivalent circuit of the resonant tank in each

subsequence and are illustrated in Fig. 2.3 (a) and (b). Unlike the below-resonance region, the transformer

is continuously coupled among the four modes in heavy-load conditions; the voltage across the magnetizing

inductor is alternatively clamped by the reflected output voltage, ± nVo .

Mode 1 starts at t0 when vinv switches to Vin and ends at t1 when vLm changes its polarity from negative to

18
 vLr ir irec n vLr ir irec n
vinv
Vin Lr Lm Vin Lr Lm

vLm nVo vLm nVo

ir Cr Cr
im im
im
vCr vCr
Mode 1: t0 ~ t1 Mode 2: t1 ~ t2
Vp2
vCr vLr ir irec n vLr ir irec n
Vp1 V in
 Lr Lm Lr Lm

vLm nVo vLm nVo

Cr Cr
irec im im

vCr vCr
t0 t1 t2 t3 t4 t Mode 3: t2 ~ t3 Mode 4: t3 ~ t4

(a) (b)

Figure 2.3: a) The key waveforms and b) the corresponding equivalent models of the resonant tank in
the above-resonance region.

positive nVo . Mode 2 is between t1 and t2 , where the behavior is the same as Mode 2 in the below-resonance

region. Mode 3 and 4 in the second-half cycle is similar to Mode 1 and 2, respectively; the differences are

vinv and the inversed voltage across Lm . It is worthwhile to notice that in Mode 1 and 3, the slope of ir is

steeper than the prior mode. It is because the voltage applied to the resonant tank has the maximum absolute

value and is aligned with the sign of dir /dt.

The KVL equation in the above-resonance region is the same as (2.1), with


dim nVo
 Mode 2, 3
Lm = (2.8)
dt 
−nVo
 Mode 1, 4.

The KCL equation for all the four modes is the same as (2.4), since the transformer is continuously coupled.

In the light-load conditions, there are two more subsequences with transformer decoupled due to the

nature of decreased output current. In the below-resonance region, as shown in Fig. 2.4, the transformer is

not coupled in Mode 2 when vinv switches to Vin at t1 . At this moment, the resonant voltage vCr is close to

Vin /2, which is relatively high in the first half cycle. Consequently, vLm is relatively small. If vLm is less than

nVo , the rectifier diodes are reverse biased, prohibiting the transformer from coupling. Mode 1 ends at t2

when the transformer is coupled, and the criteria is

Vp1 > vCr , (2.9)

19
 vLr ir vLr ir

Lr Lm Vin Lr Lm

vinv vLm vLm

Cr Cr
im im

vCr vCr
Mode 1: t0 ~ t1 Mode 2: t1 ~ t2
ir
im vLr ir irec n vLr ir

Vin Lr Lm Vin Lr Lm

vLm nVo vLm

Cr Cr
im im
Vp2
vCr vCr vCr
Vp1 V in Mode 3: t2 ~ t3 Mode 4: t3 ~ t4


vLr ir vLr ir irec n

Lr Lm Lr Lm
irec
vLm vLm nVo
Cr Cr
im im
t
t0t1t2 t3t4t5 t6t7
vCr vCr
Mode 5: t4 ~ t5 Mode 6: t5 ~ t6

(a) (b)

Figure 2.4: Light-load conditions: a) the key waveforms and b) the corresponding equivalent models
of the resonant tank in the below-resonance region.

where
Lr
Vp1 = Vin − nVo (1 + ). (2.10)
Lm

Similarly, in Mode 5, after vinv switches to zero, the transformer keeps decoupled until the amplitude of vCr

is large enough to forward bias the rectifier diodes. The criteria to end Mode 5 is

vCr > Vp2 , (2.11)

where
Lr
Vp2 = nVo (1 + ). (2.12)
Lm

In the above-resonance region, there are also two more subsequences with the transformer decoupled in

light-load conditions. As shown in Fig. 2.5, Mode 2 starts at t1 when ir reaches im and the transformer is

decoupled. At this moment, the transformer is not coupled as in the heavy-load condition, which is also

because vCr is larger than Vp1 . It results in insufficient voltage across the transformer to forward bias the

20
 vLr ir irec n vLr ir

Vin Lr Lm Vin Lr Lm

vinv vLm nVo vLm

Cr Cr
im im

vCr vCr
ir Mode 1: t0 ~ t1 Mode 2: t1 ~ t2
im
vLr ir irec n vLr ir irec n

Vin Lr Lm Lr Lm

vLm nVo vLm nVo

Cr Cr
Vp2 im im
vCr
Vp1 V in vCr vCr

Mode 3: t2 ~ t3 Mode 4: t3 ~ t4

vLr ir vLr ir irec n

irec Lr Lm Lr Lm

vLm vLm nVo

Cr Cr
t0t1t2 t3t4t5 t6t7 im im

vCr vCr
Mode 5: t4 ~ t5 Mode 6: t5 ~ t6

(a) (b)

Figure 2.5: Light-load conditions: a) the key waveforms and b) the corresponding equivalent models
of the resonant tank in the above-resonance region.

rectifier diodes. Similarly, in Mode 5, the transformer keeps decoupled until vCr is larger than Vp2 . It is

worthwhile to notice that when the load further decreases, ir can reach im before vinv switches. In this case,

the transformer is decoupled in both Mode 1 and 4, which makes the sequence the same as the below-

resonance condition.

In summary, for a frequency-modulated LLC resonant converter, the operating modes for heavy-load and

light-load conditions are discussed. The modes are divided by the voltages applied to the resonant tank and

the transformer. When the transformer is coupled, ±nVo is applied to the magnetizing inductor, and only

Lr resonates with Cr . When the transformer is decoupled, Lr and Lm are equivalently in series and resonate

with Cr . These operating modes affects the conduction angle of the rectifier diode, so they are essential to

the design of the synchronous rectification, which will be discussed in the following section.

2.2 Fundamentals of the Proposed RCV SR Algorithm

This section introduces the derivation of the proposed Resonant Capacitor Voltage-based Synchronous Rec-

tification (RCV SR) algorithm. The RCV SR driving strategy is simple and lossless while covering a wide

21
 vgs.SR1
HS
n::
iD1
vgs.HS
ir Lr SR 
Vin
LS irec
vgs.LS vinv Lm
Cr
im Co Ro vo
iD SR 
vCr

vgs.SR2
irec
Proposed RCV Strategy
vCr voltage
Integration/ integrations
vCr
Comparison
Vin low pass filter vgs.SR1
vgs.SR2
voltage vp.int
Vout
integrations
vCr .int
Simple and lossless
Large and stable signals involved; vgs.SR1
high noise immunity
Wide operating range covered
t

Figure 2.6: The proposed RCV strategy senses the large voltage signals ➊ and controls the SR by
simply integrating and comparing the voltage signals ➋. The typical waveforms show the below-
resonance operation for SR1 as an example to visualize the concept of the proposed RCV strategy,
where v p1.int and vCr .int are the voltage integrations of linear combinations of the sensed voltages,
defined in the following section.

operating range. It uses the integration of large voltage signals, which is noise-tolerant compared with con-

ventional vds.on based methods. Also, current sensors are not needed, which saves the associated conduction

losses and cost comparing with conventional current-transformer (CT) based methods. To apply the RCV

strategy, the inverter of the LLC converter can be half-bridge or full-bridge with symmetric duty ratio, and

the rectifier can be center-tapped or full-bridge. Among those combinations, the topology shown in Fig. 2.6

is considered as an example. Figure 2.6 also depicts the simplified block diagram of the proposed RCV

SR control method, which involves three large voltage signals: the input voltage (Vin ), the output voltage

(Vout ), and primarily, the resonant capacitor voltage (vCr ). By comparing the integrations of the large voltage

signals, the control of the SR MOSFETs can be determined.

22
2.2.1 Below-Resonance Region

Following the KVL equation (2.1), in Mode 2 and 3, the inverter voltage vinv is a constant Vin . Integrating

both sides of (2.1) and assuming zero initial conditions yield

Z t3 Z t3 Z t2 Z t2 Z t3 Z t3
Vin = vCr dt + Lr dir + Lm dim + Lr dir + Lm dim . (2.13)
t1 t1 t1 t1 t2 t2

Since the difference between ir (t1 ) and ir (t2 ) is equal to the difference of im (t1 ) and im (t2 ), and the magne-

tizing inductor voltage is clamped at nVo , (2.13) can be expressed as

Z t3 Z t3
Lr
Vin dt = vCr dt + nVo (1 + ) · (t2 − t1 ) + (Lr + Lm ) · [ir (t3 ) − ir (t2 )]. (2.14)
t1 t1 Lm

The difference between ir (t3 ) and ir (t2 ) is not necessarily zero and cannot be ignored. Furthermore, in order

to avoid current sensing, this term must be replaced by voltage signals. In Mode 3, as (2.6) indicates, Lr

and Lm in series resonate with Cr . By integrating both sides of (2.6), the term for the change in the resonant

current from t2 to t3 is derived as

Z t3
(Lr + Lm ) · [ir (t3 ) − ir (t2 )] = Vin · (t3 − t2 ) − vCr dt. (2.15)
t2

Therefore, (2.14) can be fully expressed as integrals of voltage signals by replacing the current terms using

(2.15), which gives

Z t2 Z t2
Vp1 dt = vCr dt, (2.16)
t1 t1

where the DC voltage Vp1 is defined in (2.10).

By applying the same procedure to the subsequence Mode 3 and 4, the RCV strategy for the other SR

MOSFET, SR2 , is obtained as

Z t4 Z t4
Vp2 dt = vCr dt, (2.17)
t3 t3

where Vp2 is defined in (2.12).

As a result, the RCV strategy to drive the SR MOSFET SR1 and SR2 in the below-resonance region is

expressed by (2.16) and (2.17), respectively. The time to turn off SR1 is at t2 when the integrations of the DC

voltage Vp1 and the resonant capacitor voltage vCr are equal. As shown in Fig. 2.7, v p1.int and vCr .int represent

the time integrals of Vp1 and vCr , respectively; the two voltage integrations starts at t1 and cross over at t2 ,

which corresponds to the instant when the magnetizing current reaches the resonant current and irec reaches

23
 vinv

ir
im

vCr
V in

irec

vp1.int
vCr.int

vp2.int
vCr.int

vgs.SR1

vgs.SR2

t0 t1 t2 t3 t4 t

Figure 2.7: The key switching sequence of the proposed RCV SR method in the below-resonance re-
gion, heavy-load conditions.

zero. This is exactly the time for the gate drive signal vgs.SR1 to be terminated. Similarly, in the second half

of the cycle, vCr .int and the integration of Vp2 (denoted by v p2.int ), start at t3 and intersect at t4 . This is exactly

the time when irec reaches zero, which is the instant to switch off the vgs.SR2 .

Note that the DC voltage and the resonant capacitor voltage in (2.16) and (2.17) are large voltage signals.

Therefore, the RCV strategy is more robust than traditional vds.on sensing methods which rely on small and

sensitive signals. In addition, the action of integration also filters out high frequency noise, which further

enhances the noise rejection capability.

In heavy-load conditions, the turn-on of SR1 and the start of the integration are both synchronous with

the rising edge of the inverter voltage at t1 , defined by vinv > Vin /2; whereas the corresponding instant for

SR2 is synchronous with the falling edge of the inverter voltage at t3 , defined by vinv < Vin /2. In terms of

light-load conditions, there is another constraint that needs to be considered. However, it will be proved later

that by using the resonant capacitor voltage, the turn-on triggering for different loading conditions can be

determined and combined with simple logic operations.

24
2.2.2 Above-Resonance Region

In the above-resonance region, although the operating sequence is different from the below-resonance, the

SR conduction time can be found by comparing the integrated voltage signals. In Mode 1, the vinv is Vin and

vLm is −nVo ; integrating the KVL equation (2.1) in this time interval yields

Z t1 Z t1 Z t1
Vin dt = vCr dt − nVo dt + Lr [ir (t1 ) − ir (t0 )], (2.18)
t0 t0 t0

whereas in Mode 3, the voltage integrations are described as

Z t3 Z t3
0= vCr dt + nVo dt + Lr [ir (t3 ) − ir (t2 )]. (2.19)
t2 t2

If the turns ratio of the secondary windings of the center-tapped transformer is unity, and the duty ratio is

symmetric, then the magnetizing and demagnetizing of Lm is also symmetric. It leads to the fact that the sum

of ir (t0 ) and ir (t2 ), and the sum of ir (t1 ) and ir (t3 ) are zero, and that the time intervals from t0 to t1 and from

t2 to t3 are equal. Therefore, by adding (2.18) and (2.19), the terms for the resonant current and the time

integrals of the reflected output voltage are canceled, which gives

Z t1 Z t1 Z t3
Vin dt = vCr dt + vCr dt. (2.20)
t0 t0 t2

The magnetizing inductor Lm is charged from t1 to t3 , from which there is an important characteristic: the

resonant current and the magnetizing current are the same at the beginning and at the end, and the voltage

cross Lm is nVo . The voltage integrations during this interval are therefore represented as

Z t2 Z t3
Lr
Vin dt = vCr dt + nVo (1 + )(t3 − t1 ). (2.21)
t1 t1 Lm

As a result, for the operation above resonance, the RCV strategy for SR1 is obtained by adding (2.20) and

(2.21), which yields

Z t2 Z t3
[Vp1 − vCr ]dt = 2 vCr dt. (2.22)
t0 t2

According to (2.22), the integral of Vp1 − vCr over the time interval t0 to t2 (v p.int1 ) is equal to twice the

integral of vCr from t2 to t3 (vCr .int1 ); by comparing the two integrals, the instant t3 to switch off SR1 can be

obtained. Note that t0 and t2 are synchronous with the inverter voltage and hence can be obtained. As shown

in Fig. 2.8, the first integral, v p.int1 , starts at t0 and stops at t2 ; the integration result is retained and compared

25
with the second integral, vCr .int1 . The SR driving signal vgs.SR1 is terminated at t3 , the instant when the two

integrals are equal. This moment exactly corresponds to the time when irec is zero.

By applying the same analysis on the second half of the cycle, the voltage integrations to determing the

on-time of SR2 can be determined.

Z t4 Z t5
[vCr −Vp2 ]dt = 2 [Vin − vCr ]dt. (2.23)
t2 t4

As (2.23) indicates, the integral of vCr − Vp2 over the time interval t2 to t4 (v p.int2 ), is equal to twice the

integral of Vin − vCr from t4 to t5 (vCr .int2 ). Hence, the turn-off instant for the present SR switching cycle is

at t5 where the two integrals are equal; this is also the moment to turn on the other SR MOSFET, SR1 . As

a result, the RCV strategy in the above-resonance region is described by (2.22) and (2.23). Similar to the

below-resonance region, the RCV strategy is in the form of large voltage integrations, and it is dominated

by the resonant capacitor voltage. By applying the integrations of large voltage signals, the RCV strategy

is more reliable than traditional vds.on sensing methods in terms of noise immunity. In addition, considering

that the turns ratio of the secondary windings of the center-tapped transformer is unity, (2.22) is equivalent

to
Z t2 Z t1
[Vp1 − vCr ]dt = 2 [Vin − vCr ]dt, (2.24)
t0 t0

and (2.23) is equivalent to

Z t4 Z t3
[vCr −Vp2 ]dt = 2 vCr dt. (2.25)
t2 t2

These two equations offer an alternative to control the SR above resonance.

2.2.3 Light-load Conditions

In light-load conditions, according to the analysis in Section 2.1, there are two additional modes with trans-

former decoupled in both below- and above-resonance regions (Mode 2 and 5). After these two modes, the

transformer is coupled and the rectifier current (irec ) starts conduction. From the perspective of SR, it means

that the SR turn-on timing is delayed due to the existence of these two modes. Therefore, (2.9) – (2.12) that

describe the conditions for the transformer to be coupled have to be considered as the criteria to turn on the

SR switches. As shown in Fig. 2.9 (a) and (b), vgs.SR1 is on when vCr falls below Vp1 ; vgs.SR2 is on when vCr

rises above Vp2 . These are the instants when the transformer is coupled and irec starts conduction.

Regarding the turn-off instant of SR, it is also determined by comparing the same voltage integration

signals because the operating modes in the time intervals when the transformer is coupled are identical. As

26
 vinv

ir
im

vCr
V in


irec

vp.int1
vCr.int1

vp.int2
vCr.int2

vgs.SR1

vgs.SR2

t0 t1 t2 t3 t4 t5 t

Figure 2.8: The key switching sequence of the proposed RCV SR method in the above-resonance re-
gion, heavy-load conditions.

shown in Fig. 2.9 (a), for example, the transformer is coupled from t2 to t3 and decoupled from t3 to t4 , the

equivalent circuits of which are the same as Mode 2 and 3 in the heavy-load conditions. Therefore, the same

analysis in Section 2.2.1 remain true for light-load conditions.

In the above-resonance region, as illustrated in Fig. 2.9 (b), the criteria for turning on the SR MOSFETs

(2.9) – (2.12) are also valid. Thus, vgs.SR1 and vgs.SR2 are turned on at t2 and t5 , where vCr intersects Vp1 and

Vp2 , respectively. From t2 to t4 and from t5 to t7 , the transformer is coupled, despite the switch of the inverter

voltage at t3 and t6 . Therefore,

Z t3 Z t4
Lr
Vin dt = [vCr + nVo (1 + )]dt, (2.26)
t2 t2 Lm

and
Z t7 Z t7
Lr
Vin dt = [vCr − nVo (1 + )]dt. (2.27)
t6 t5 Lm

By taking Vp1 and Vp2 into (2.26) and (2.27) yields

Z t3 Z t4
[Vp1 − vCr ]dt = [vCr +Vp2 ]dt, (2.28)
t2 t3

27
 vinv vinv

ir ir
im im

Vp2
vCr Vp2
Vp1 V in vCr
 Vp1 V in
irec 

irec
vp1.int
vCr.int vp.int1
vCr.int1
vp2.int vp.int2
vCr.int vCr.int2

vgs.SR1 vgs.SR1

vgs.SR2 vgs.SR2

t0t1 t2 t3t4 t5 t6 t t0t1t2 t3 t4 t5 t6t7 t

(a) (b)

Figure 2.9: The key waveforms in light-load conditions for a) below resonance, and b) above reso-
nance.

and
Z t6 Z t7
[vCr −Vp2 ]dt = [Vin − vCr +Vp2 ]dt. (2.29)
t5 t6

From t3 to t4 , vCr is close to Vp2 due to the small time difference between t3 and t5 , and hence, (2.28) can be

written as
Z t3 Z t4
[Vp1 − vCr ]dt = 2 vCr dt, (2.30)
t2 t3

which is in the same form as (2.22). Similarly, Vin − vCr is close to Vp2 from t6 to t7 , and (2.29) can be

replaced by
Z t6 Z t7
[vCr −Vp2 ]dt = 2 [Vin − vCr ]dt, (2.31)
t5 t6

which is in the same form as (2.23).

As the loading current further decreases, if irec reaches zero before t3 in the first half cycle or before

t6 in the second half cycle, the operating modes are equivalent to the below-resonance region, despite the

frequency. In this case, (2.30) and (2.31) remains valid because the right-hand side of the equations are zero

(from the time interval t2 to t3 and t5 to t6 ), and (2.30) and (2.31) are essentially equivalent to (2.16) and

28
(2.17), the SR turn-off criteria for below-resonance operation.

In summary, for light-load operations, the criteria (2.9) and (2.11) indicates the instant to turn on SR and

to start the integration. As for the turn-off of SR, the voltage integrations employed for both heavy-load

and light-load conditions are identical; in the below-resonance region, they are (2.16) and (2.17), and in the

above-resonance region, they are (2.22) and (2.23). Under very light-load conditions, the modes for below-

and above-resonance operation are the same, and so are the SR turn-off criteria.

2.2.4 Boundary Conditions

Although the SR driving strategies for below and above the resonant frequency are derived individually, the

two sets of the control laws are equivalent at the boundary where the switching frequency is at the resonant

frequency. At the boundary, the right-hand side of the above-resonance equations (2.22) and (2.23) are zero,

and on the left-hand side, t0 and t2 are replaced with t1 and t3 . As a result, they become equivalent to the

below-resonance equations (2.16) and (2.17) at the boundary. Therefore, the transition of the two modes at

the resonant frequency is seamless.

Considering the light-load condition, the criteria described in (2.9) and (2.11) delay the start of integration

and the turn-on of the SR, but the forms of the voltage integrations for below and above resonance are

not changed as discussed in Section 2.2.3. The reason that the forms are kept the same is that when the

criterion are satisfied, the transformer is coupled, and the equivalent circuits for light-load and heavy-load

conditions are identical. When (2.9) and (2.11) take place prior to the start of integration defined in heavy-

load conditions, the latter becomes the more stringent criterion for defining the SR turn-on instant, and the

former has no effect on the control of SR. Therefore, the transition of light-load and heavy-load conditions

to turn on SR is also seamless.

2.2.5 Sensitivity Analysis

The SR on-time is obtained simply by comparing the voltage integrations in RCV SR, but the closed-form

expression of SR on-time is complicated. In order to give the insight into the impact of SR on-time error

versus the mismatch of the inductance ratio (Lr /Lm ) and simplify the sensitivity analysis procedure, the first

harmonic approximation is performed as follows.

The resonant current (ir ) is defined as

ir = i pk sin(ωt − φ ), (2.32)

29
where the angle φ defines the phase delay of the resonant current referring to the resonant tank voltage, and

i pk is the peak resonant current; both parameters are related to loading conditions. The integral of vCr is the

integration of the input voltage subtracts the total voltage across the resonant and magnetizing inductance,

which yields
Z t
vCr dt = (Vin − nVo )t − Lr i pk [sin(ωt − φ ) + sinφ ]. (2.33)
0

Combining (2.33) with (2.16) and (2.17), the SR on-time can be approximated by solving the equation:

−nVo λt = −Lr i pk [sin(ωt − φ ) + sinφ ], (2.34)

where λ is the inductance ratio, Lr /Lm . Let the expression of the left side of (2.34) be a linear function fc (t)

and the right side be a trigonometric function g(t):

fc (t) = −nVo λt, (2.35)

g(t) = −Lr i pk [sin(ωt − φ ) + sinφ ]. (2.36)

As illustrated in Fig. 2.10, the geometric representation indicates that the crossover of fc (t) and g(t) corre-

sponds to tc , which is the cut-off of the rectifier current and the turn-off instant of the SR.

Considering that there is a mismatch of the inductance ratio between the actual value and the one set by

the RCV SR controller, the inductance ratio set by the controller is hence defined as

λ ′ = (1 + ε)λ , (2.37)

where ε is the mismatch of the inductance ratio. ε equals zero for no mismatch, and 0.2 for 20 % mismatch

in the inductance ratio. The linear curve with the mismatched inductance ratio is defined as fe (t):

fe (t) = −nVo λ ′t. (2.38)

The crossover of fe (t) with g(t) at te is the displaced SR turn-off instant, and the difference between the

actual cut-off of the rectifier current is ∆t, which defines the SR on-time error. The slope determined by the

two crossover points (A and B) is ∆y/∆t defined by:

∆y −nVo λtc + nVo λ ′te −nVote (λ − λ ′ )

= ≃ . (2.39)
∆t ∆t ∆t

30
 y g(t)

te tc g ’(tc )
-nVo l Dt t
C A
-nVo l tc
-nVo l' Dy fc(t)
-nVo l' te
B
fe(t)

Figure 2.10: The geometric representation of sensitivity analysis using the first harmonic approxima-
tion.

As the slope of fc (t) is relatively low, the approximation is performed by using the distance from B to C

for simplifying the analysis. The slope ∆y/∆t is close to the differential of g(t) at the instant of tc , which is

defined by:

g′ (t) = −Lr i pk ωcos(ωtc − φ ). (2.40)

Solving for ∆t using (2.39) and (2.40), the relationship between the mismatch of the inductance ratio (ε) and

the SR on-time error (∆t) is described as:

−nVotc ε
∆t = (2.41)
i pk Lm ωcos(π − φ ) − nVo ε

Based on the relationship defined in (2.41), the SR on-time error is less sensitive to the mismatch of

the inductance ratio at heavy-load conditions as the peak current (i pk ) is larger and the phase delay (φ ) is

shorter. This characteristic is important to the efficiency performance as the on-time error is more critical at

heavy-load than light-load conditions.

2.2.6 RCV SR Driving Strategy for Half-Bridge LLC Converters

According to the discussions above, the resultant SR driving strategy using RCV is described as below with

simple comparison statements



on,
 for (vinv > Vin /2) & (vCr < Vp1 ) & (vCr .int2 > v p.int2 )
SR1 : (2.42)

off,
 for (vCr .int > v p1.int ) ∥ (vCr .int1 > v p.int1 )

31
 

on,
 for (vinv < Vin /2) & (vCr > Vp2 ) & (vCr .int1 > v p.int1 )
SR2 : (2.43)

off,
 for (vCr .int < v p2.int ) ∥ (vCr .int2 > v p.int2 )

By combining the SR turn-on and turn-off criteria with elementary logic operations, the RCV strategy ac-

commodates itself to each operating mode without having to detect the information of loading current and

resonant frequency. Take the turn-on of SR1 for example, at heavy-load conditions, the criterion vCr < Vp1 is

already satisfied prior to the rising edge of vinv , and hence the other two criteria are dominant. In this con-

dition, for above resonance, vCr .int2 is zero and less than v p.int2 at the rising edge of vinv , so vCr .int2 > v p.int2

naturally becomes the most strict criterion and determines the turn-on instant. As a result, the RCV strategy

adapts itself to different switching frequencies and load conditions. Moreover, the RCV SR driving strategy

is developed based on the integration and comparison of large voltage signals. In contrast to traditional vds.on

sensing methods which rely on small and noise-sensitive signals, the RCV strategy is less subject to noise

interference for using large voltage signals and integrations.

2.2.7 RCV SR Driving Strategy for Full-Bridge LLC Converters

Although this work focuses on the half-bridge LLC topology, the same procedure can be applied to full-

bridge LLC converters with the consideration of the differences between the two inverter voltages. For the

half-bridge topology, the input is switching between Vin and zero; whereas for the full-bridge topology, the

input is between Vin and −Vin . By following the same procedure for the half-bridge topology, the signal Vp2

defined in (2.12) and the signal vCr .int1 defined in (2.22) are redefined as follows:

Lr
Vp2 = nVo (1 + ) −Vin , (2.44)
Lm

and
Z t3
vCr .int1 = 2 [Vin + vCr ]dt. (2.45)
t2

As a result, the other definitions for the voltage integrations are kept the same, and the RCV SR driving

strategy for full-bridge LLC resonant converters is described as



on,
 for (vinv > 0) & (vCr < Vp1 ) & (vCr .int2 > v p.int2 )
SR1 : (2.46)

off,
 for (vCr .int > v p1.int ) ∥ (vCr .int1 > v p.int1 )

32
 

on,
 for (vinv < 0) & (vCr > Vp2 ) & (vCr .int1 > v p.int1 )
SR2 : (2.47)

off,
 for (vCr .int < v p2.int ) ∥ (vCr .int2 > v p.int2 )

2.3 Implementation of RCV SR

In order to verify the functionality of the RCV SR driving strategy, the control circuit is built for a half-bridge

LLC resonant converter based on the conclusion of Section 2.2.6. It is possible to implement the control

strategy directly using (2.42) and (2.43). And yet, the turn-off criteria for below- and above-resonance

regions can be merged to simply the implementation.

According to the vgs.SR1 turn-off criteria (2.16) for the below-resonance operation, moving all the terms

to the left-hand side of the equation results in the same form as the turn-off criteria (2.22). On the right-

hand side of (2.22), the integration starts after the switch of vinv , so as long as it is set as zero before the

integration, (2.22) is the same as (2.16) in the below-resonance region. Therefore, the combined turn-off

criteria is expressed as



Z t 0,
 for t0 ≤ t ≤ t2
[Vp1 − vCr ]dt = , (2.48)
t0
 tt 2vCr dt, for t > t2

R
2

where t0 indicates the start of integration and t2 refers to the falling edge of vinv .

The implementation is shown in Fig. 2.11. The constant gain K at the Vo input terminal represents

n(1 + Lr /Lm ), and the output of the amplifier is Vp2 as defined in (2.12). The sum of the input voltages is

fed into the corresponding integrator one to four. The first integrator represents the right-hand side of (2.48).

The reset signal of the first integrator, RES, is synchronous with the inverter voltage, vinv . Hence, the output

is zero during the time interval t0 ≤ t ≤ t2 , and the integration of 2vCr starts after t2 expires. The second

resettable integrator implements the left-hand side of (2.48). As shown in Fig. 2.11, the second integrator

integrates Vp1 − vCr , and the output (v p.int1 ) is compared with the output of the first integrator (vCr .int1 ). The

reset signal of the second integrator is determined by the inverse of the intersection of RES and the output of

the comparator A. Thus, the second integrator starts integration when the inverter voltage is high (controlled

by RES), and the criterion Vp1 > vCr for light-load SR turn-on control has to be satisfied before the start of

integration.

As discussed in Section 2.2.3, the rectifier current starts conduction when vCr is lower than Vp1 . This

criterion is met before the inverter voltage is high for heavy-load conditions, and hence the start of the

33
 vCr vCr.int1

RES
C
Vin
Vp1 vCr vp.int1 R Q SR1
S 
RES S Q

vCr A

Vp2 vCr Vp2 vp.int2

Vo K S 
RES S Q

B R Q SR2
Vin vCr D
S  vCr.int2
RES RES

v inv

Figure 2.11: Block diagram of the RCV SR control method.

second integrator is synchronous with the rising edge of RES. However, for light-load conditions, Vp1 is

larger than vCr after the rising of vinv , and the criterion Vp1 > vCr becomes more strict than RES to start

the integration. Therefore, by taking the intersection of the two criteria, the start of the second integrator

naturally accommodates both of the light-load and heavy-load conditions. The comparator C compares the

output of the first and the second integrator, which connects the left- and right-hand side of (2.48). As a

result, the crossover of v p.int1 and vCr .int1 determines the turn-off of the SR MOSFET SR1 .

Similarly, the turn-off criteria of vgs.SR2 described in (2.17) and (2.31) can be combined, which leads to



Z t 0,
 for t2 ≤ t ≤ t4
[vCr −Vp2 ]dt = (2.49)
t2
 tt 2[Vin − vCr ]dt, for t > t4

R
4

Table 2.1: Key Components for Prototyping RCV SR

Category Part Number Quantity Purpose

OPAMP MC33079 2 , , and adders
LMV793 2 and
Comparator MCP6564 1 A to D

Inverter SN74LVC2GU04 3 RES, the reset of

Gate to , and other
inverse signals
SR Latch CD4043B 2 set/ reset logic circuitry
AND Gate SN74F08 1 SR1 and SR 2 control

34
where t2 indicates the start of integration and t4 refers to the rising edge of vinv . As illustrated in Fig. 2.11,

the third integrator implements the left-hand side of (2.49), and the fourth integrator implements the right-

hand side. The reset signal of the fourth integrator is the inverse of RES, denoted as RES. It makes the

output of the fourth integrator zero when the inverter voltage is low, which corresponds to the time interval

t2 ≤ t ≤ t4 . The fourth integrator starts integrating Vin − vCr at t4 , which is controlled by the falling edge of

RES. Regarding the third integrator, the reset signal is the inverse of the intersection of RES and the output

of the comparator B. This logic circuit is symmetrical to the reset signal of the second integrator, and the

purpose is also to control the start of integration in heavy-load and light-load conditions. In the last stage, the

output of the two integrators, vCr .int2 and v p.int2 , are fed to the comparator D, which completes the turn-off

control of the SR MOSFET SR2 .

The implementation of the turn-on of SR1 and SR2 follows (2.42) and (2.43), respectively. In order to

prevent the two SR switches from cross-conduction, the inverse of each gate driving signal is fed into the

logic gate that controls the set signal of the other SR switch to prohibit the turn-on triggering as shown in

Fig. 2.11. It generates the dead-time between the two SR switches when the switching frequency is nearby

or above the resonant frequency. As a result, the input voltages are integrated and compared to determine

the turn-on and turn-off of the SR switches. With simple logic combinations, the controller naturally adapts

itself to light-load and heavy-load conditions regardless of the frequency change.

The block diagram shown in Fig. 2.11 can be implemented by analog, digital, or mixed-signal circuitry.

In this work, the prototype is built using analog circuits, in which the key components are listed in Table 2.1.

The logic gates are general-purpose; conventional summing amplifier and inverting integrator circuits are

applied to the adder and the resettable integrator. The main design considerations for the adders and the

integrators are the bandwidth and the slew rate. The bandwidth of the adder is suggested to be at least ten

times of the maximum operational switching frequency to avoid the phase delay of the sensed vCr . The slew

rate of the operational amplifiers for the integrator one and four are recommended to be higher than the other

two, since the voltage integrations are doubled as indicated by (2.48) and (2.49).

2.4 Simulation and Experimental Results

This section presents the simulation results of the RCV strategy and the experimental validations on a

650 W/ 24 V LLC converter for battery charging applications, with the system parameters given in Table 2.2.

The simulation and experiments are performed under the constant current, constant power, and constant volt-

age mode, which are essential operating modes for battery chargers. The simulation results for heavy-load

35
 SR Triggering [V] Rectifier Current [A]
fS = 250 kHz fS = 230 kHz fS = 220 kHz fS = 200 kHz
40 Vout = 16.5 V Vout = 19.3 V Vout = 20.8 V Vout = 23.5 V

20
tCOND tCOND tCOND tCOND
0

2.5
tRCV tRCV tRCV tRCV
0
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4
Time [ms] Time [ms] Time [ms] Time [ms]
(a) (b) (c) (d)

Figure 2.12: Simulation results for the constant current mode operation. The converter operates at
27 A, a) 250 kHz, b) 230 kHz, c) 220 kHz, and d) 200 kHz; the RCV-controlled SR on-time
(tRCV ) is very close to the ideal rectifier current conduction time (tCOND ) as shown in each con-
dition.

conditions shown in Fig. 2.12 and Fig. 2.13 are for the constant current mode and the constant power mode

operation respectively. In the constant current mode, the output current is fixed at its maximum value, and

the switching frequency is above the resonance. In this mode, (2.22) and (2.23) determines the turn-off of

SR. In Fig. 2.12, the simulation results indicate that the RCV controls the turn-off instant accurately at each

switching frequency, despite the change in the output voltage. The falling edge of the SR triggering signal

is exactly at the zero crossing of the rectifier current, and the RCV-controlled SR on-time (tRCV ) is close to

the ideal rectifier current conduction time (tCOND ). Note that the difference between tCOND and tRCV at the

beginning of each cycle is caused by the deadtime set to prevent cross conduction of the SR MOSFETs.

In the constant power mode operation, the LLC resonant converter operates in the below-resonance re-

gion, where the output voltage is above the nominal value. The output voltage and current change at the same

time according to the frequency, while the output power is kept at its maximum. In this operating mode, tRCV

Table 2.2: System Parameters

Parameter Values
input voltage, Vin 400 V
nominal power, Pout 650 W
nominal output voltage, Vo 24 V
switching frequency, fsw 150–250 kHz
magnetizing inductance, Lm 103.4 µH
resonant inductance, Lr 37.7 µH
resonant capacitor, Cr 18.8 nF
transformer turns ratio, n 8.1

36
 SR Triggering [V] Rectifier Current [A]
fS = 180 kHz fS = 175 kHz fS = 173 kHz fS = 167 kHz
40 i iout = 24.4 A iout = 24 A iout = 23 A
out = 25.7 A

20
tCOND tCOND tCOND tCOND
0

2.5
tRCV tRCV tRCV tRCV
0
0 2 4 6 0 2 4 6 0 2 4 6 0 2 4 6
Time [ms] Time [ms] Time [ms] Time [ms]
(a) (b) (c) (d)

Figure 2.13: Simulation results for the constant power mode operation. The converter operates at
650 W, a) 180 kHz, b) 175 kHz, c) 173 kHz, and d) 167 kHz. In each condition, the RCV
strategy accurately enables the SR during the ideal rectifier current conduction time.

30
SR Triggering [V] Rectifier Current [A]

fS = 159 kHz fS = 160 kHz fS = 160 kHz fS = 161 kHz

iout = 5 A iout = 1 A
20 iout = 13 A iout = 10 A

10 tCOND tCOND
tCOND tCOND
0

2.5
tRCV tRCV tRCV tRCV
0
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4
Time [ms] Time [ms] Time [ms] Time [ms]
(a) (b) (c) (d)

Figure 2.14: Simulation results for the constant voltage mode operation, where the LLC converter op-
erates at 30 V output and a) 60 %, b) 45 %, c) 23 %, and d) 5 % load. Regardless of the load
change, the ideal rectifier current conduction time is accurately predicted by the RCV strategy.

is automatically determined by (2.16) and (2.17) since they are the most strict criteria in (2.48) and (2.49).

As the simulation results illustrated in Fig. 2.13 (a) to (d), the SR on-time of employing the RCV strategy,

is exactly the same as tCOND at each switching frequency regardless of variations in the output voltage and

current.

As the constant voltage and constant power mode demonstrate the operations under heavy-load condi-

tions, the simulation results from medium-load to light-load conditions are demonstrated under the constant

voltage mode. The RCV-controlled SR on-time and the theoretical conduction time of the rectifier current

from 60 % to 5 % load are compared in Fig. 2.14 (a) to (d). The behavior in the heavy-load conditions is

similar to Fig. 2.13. As the output current decreases, the amplitude of vCr shrinks, and the start of the rectifier

37
current is delayed; the rectifier current starts conducting at the instant when (2.9) or (2.11) is satisfied, and

hence by using the information of vCr , the instant of triggering on the SR can be controlled by using the

RCV strategy. The turn-off of the SR follows (2.16) and (2.17) by comparing the integrated voltage signals.

According to simulation results, the switching of the SR is synchronous with the start and cutoff of the recti-

fier current in each load condition. As a result, the RCV-controlled SR on-time is equal to the ideal rectifier

current conduction time from below to above resonant frequency, as well as from heavy-load to light-load

conditions.

The 650 W/ 24 V LLC resonant converter shown in Fig. 2.15 is set up with the system parameters listed

in Table III. The DSP sets the frequency of the primary switches for the LLC resonant converter; the RCV

SR controller detects Vin , Vo , and vCr and determines the driving signal for the SR MOSFETs. The block

diagram and the key components used for implementing the RCV SR controller are shown in Fig. 2.11 and

Table 2.1, respectively.

In order to verify the functionality of the RCV strategy, the integrated voltages are displayed and com-

pared with the conduction time of the rectifier current and that of a conventional vds.on sensing SR controller

under the constant power, constant current, and constant voltage mode, respectively. In the constant power

mode, the output power is set at 650 W. As Fig. 2.16 shows, the LLC converter is below the resonant

frequency. Under the same condition, the result of the conventional vds.on sensing method is displayed in

Fig. 2.16 (a), whereas the proposed RCV strategy is presented in Fig. 2.16 (b). As shown in Fig. 2.16 (a), the

drain-source voltage of SR1 , vds.SR1 , is zoomed to show the behavior when SR1 conducts the rectifier current.

As the zoomed vds.SR1 waveform in the bottom part shows, vds.SR1 reaches the proximity of zero, and the SR

is switched off. Due to the inductive voltage offset across the stray inductance, the zero-voltage crossing

of vds.SR1 is much earlier than the actual zero-current crossing of iD1 . The SR turns off prematurely, and

the body diode of the MOSFET starts to conduct, which reduces the efficiency and increases the operating

temperature of the device.

As opposed to the vds.on sensing method, the proposed RCV SR driving strategy does not rely on the small

and sensitive vds.on signal. The input signals, Vin , Vo , and vCr , are large in magnitude and stable. Besides,

the integrators of the RCV SR controller are equivalent to low pass filters and resistive to high-frequency

noise. As a result, the estimated SR turn-off instant is very close to the zero current crossing. As depicted in

Fig. 2.16 (b), the crossover of the two integrated signals, v p1.int and vCr .int , corresponds to the moment when

the rectifier current is nearly zero.

When operating in the constant current mode, the output current is fixed at 27 A, and the switching

38
 RCV SR SR Control
Controller Output
Resonant
Capacitor

Resonant
Inductor

Transformer

DSP for Primary SR Control Secondary Side

Switches Input

Figure 2.15: The experimental setup: the prototype of the RCV SR controller on the 650 W/ 24 V LLC
resonant converter.

vinv
iD1 32 A iD1
vds.SR1 Zero-current Crossing

vgs.SR1 Zero-current Crossing zoom-in

Large On-time Error
vp1.int
vds.SR1 Early Turn-off Due RCV Turn-off
(zoomed) to Parasitic Effects vCr.int (noise resistant)

(a) (b)

Figure 2.16: Experimental results at the maximum power and below resonance, 650 W/ 170 kHz: a)
the vds.on sensing method turns off the SR early due to the inductive voltage offset induced from
the stray inductance, whereas b) the RCV strategy effectively estimates the zero current crossing
point by comparing the integrals of large and stable voltage signals.

frequency of the LLC converter is above resonance. The critical waveforms of the traditional vds.on sensing

and the RCV method are displayed in Fig. 2.17 (a) and (b) in parallel. As Fig. 2.17 (a) shows, the slope of iD1

soars at the instant when the inverter voltage changes. As a result, the inductive voltage offsets vds.on even

more significantly. The zoomed vds.SR1 waveform shows that it reaches zero before the actual zero-current

crossing and hence turns off the SR early.

Under the same condition, the RCV SR driving strategy is not affected by the inductive voltage due to

large magnitude input signals and the filtering effect of the voltage integration. The experimental results

shown in Fig. 2.17 (b) demonstrate that the crossover of the voltage integrations, representing the turn-off

instant of the SR, is very close to the zero current crossing point. Therefore, the proposed RCV strategy also

effectively determines the turn-off instant in the above-resonance region.

39
 vinv
iD1 29 A
iD1
vds.SR1 Zero-current Crossing

vgs.SR1 Zero-current Crossing zoom-in RCV Turn-off

Large On-time Error vp.int1 vCr.int1 (noise resistant)

vds.SR1 Early Turn-off Due

(zoomed) to Parasitic Effects

(a) (b)

Figure 2.17: Experimental results at the maximum current, 27 A/ 250 kHz: a) because of the parasitic
effects, the traditional vds.on sensing method turns off the SR prematurely, while b) the RCV
strategy effectively estimates the zero current crossing by comparing the integrated voltage sig-
nals.

Vp1 V p1
vCr vCr
7.6 A Zero-current Crossing
iD1 iD1 2.6 A
vds.SR1 vinv

Zero-current Crossing zoom-in

vgs.SR1
Large On-time Error
vp1.int
vds.SR1 Early Turn-off Due vCr.int RCV Turn-off
(zoomed) to Parasitic Effects (noise resistant)

(a) (b)

Figure 2.18: Experimental results at light-load conditions, 5 A/ 30 V: a) the traditional vds.on sensing
method turns off the SR early due to the effect of parasitic elements. b) By using the integrated
voltage signals, the on-time error at light load is short in comparison.

Concerning light-load operations, the experiment is performed in the constant voltage mode, where the

output voltage is at 30 V. As illustrated in Fig. 2.18 (a) and (b), the conventional vds.on sensing and the

RCV-based method are compared at 5 A load. In this load condition, the rectifier current starts conducting

after the switching of the inverter voltage which is the rising edge of vinv in this case. As indicated in (2.9),

the rectifier current is not conducted until the criterion is satisfied, and this is verified in Fig. 2.18. At the

leftmost side of the waveform, the resonant capacitor voltage vCr crosses over Vp1 , and it is close to the start

of the rectifier current. As depicted in Fig. 2.18 (a), the conventional vds.on sensing method turns on the SR

MOSFET near the crossover of Vp1 and vCr ; however, regarding the turn-off instant, there exists a significant

discrepancy caused by the inductive voltage offset. For around 25 % of the conduction time, the rectifier

current is conducted through the body diode according to Fig. 2.18 (a). By comparison, the RCV strategy

40
determines the SR turn-off time slightly earlier than the zero current crossing, and yet, the on-time error is

merely around 6 % as indicated in Fig. 2.18 (b). Overall, by comparing the integrations of the large voltage

signals, the RCV strategy is less sensitive than the conventional vds.on sensing method, and the SR on-time

is closer to the actual rectifier current conduction time, particularly at heavy-load conditions.

The experimental results of the ideal SR on-time (corresponding to the actual rectifier current conduction

time), the RCV-controlled and the traditional vds.on sensing-based SR on-time in each operating mode are

summarized and compared in Fig. 2.19. In light-load conditions, as demonstrated in Fig. 2.19 (a), the output

current (Iout ) tapers from 7.5 A to 1 A as the output voltage is regulated at 30 V. According to the experimental

results, the on-time error of the vds.on sensing method is around 23 % to 30 % of the ideal SR on-time. In

comparison, the RCV-controlled SR on-time follows the trend of the ideal SR on-time over the load range.

In the constant power mode, as shown in Fig. 2.19 (b), the output power (Pout ) is limited at its maximum,

650 W, whereas the output voltage transits from 30 V to 24 V as the frequency increases; correspondingly,

the output current is increased from 21.7 A to 25.5 A. For each load condition, the RCV method estimates

the actual rectifier current conduction time effectively by using the large voltage signals, whereas the on-time

error of the vds.on sensing method is up to 36 % of the conduction time.

In the constant current mode, as presented in Fig. 2.19 (c), Iout is set at 27 A, and Vo is decreased from

23 V to 16.5 V as the frequency increases. The RCV-controlled SR on-time also closely follows the trend

of the ideal SR on-time in each condition, while by vds.on sensing, the error is about 25 % to 35 % of the

on-time. Therefore, the experimental results verified that by using the large voltage integrations, the RCV

strategy effectively covers a wide operating range from below to above resonance as well as from light-load

to heavy-load conditions.

By employing the integrations of the large magnitude voltage signals, the RCV SR driving strategy is less

sensitive to the parasitic effects over a wide operating range as opposed to the conventional vds.on sensing

method. The on-time error is reduced so that the power conversion efficiency and the thermal performance

of the SR MOSFET can be improved. Figure 2.20 (a) and (b) compare the LLC converter efficiency and the

SR MOSFET temperature under different loading conditions when the converter operates at 30 V. In light-

load conditions, due to lower current and fewer differences in SR on-time, the efficiency and the thermal

improvement is insignificant. However, as the load increases, the impact is more considerable. At the full-

load condition, the power loss is reduced by 6 %, which decreases the temperature of the SR MOSFET by

8.5 ◦ C. The reduction accounts for 28 % in the temperature rise relative to 25◦ C room temperature.

The experimental results verified that by using the large voltage integrations, the RCV strategy effectively

41
 3 Vout : 30 V 3 Pout : 650 W 3 Iout : 27 A

2.5 2.5 2.5

SR on-time [µs]

SR on-time [µs]

SR on-time [µs]
2 30 % error 2 36 % error 2 35 % error

1.5 1.5 1.5

1 Ideal 1 Ideal 1 Ideal

RCV RCV RCV
0.5 Traditional
0.5 Traditional
0.5 Traditional
0 0 0
1 2 3 4 5 6 7 8 170 175 180 185 190 195 210 220 230 240 250
Output Current [A] Operating Frequency [kHz] Operating Frequency [kHz]
(a) (b) (c)

Figure 2.19: The ideal, RCV-controlled and traditional vds.on sensing-based SR on-time are compared.
Experiments are conducted in a) the constant voltage mode in light-load conditions, b) the con-
stant power mode, and c) the constant current mode. The RCV strategy is effective in multiple
operating conditions by using the integrations of the large voltage signals.

95.4 95.27 % SR MOSFET Temperature [℃] 60

95.19 % 55.7 ℃
95.2 95.07 % 55
0.25 %
48.9 ℃ 8.5 ℃
95.0 0.34 % 50
Efficiency [%]

0.22 %
94.8 95.02 % 45
94.6 % 42 ℃ 7.5 ℃ 47.2 ℃
94.85 % 94.85 % 39.2 ℃
94.6 40 4.7 ℃
36.3 ℃ 4.3 ℃ 41.4 ℃
94.4 94.23 % 0.35 % 35 2.5 ℃ 37.3 ℃
RCV 34.9 ℃ RCV
94.2 0.09 % 30
Traditional 94.25 % 33.8 ℃ Traditional
94.0 94.14 % 25
150 275 400 650 150 275 400 650
Output Power [W] Output Power [W]
(a) (b)

Figure 2.20: Comparison of the effect of the SR on-time error on a) the efficiency and b) the SR MOS-
FET temperature.

covers a wide operating range from below to above resonance as well as from light-load to heavy-load

conditions. By reducing the on-time error from the conventional vds.on sensing method, the power conversion

efficiency and the thermal performance are improved.

The proposed RCV SR driving strategy employs the resonant capacitor voltage that contains the instan-

taneous information of input current and hence can respond to the dynamics of the system rapidly. The dy-

namic test result is demonstrated as shown in Fig. 2.21. The switching frequency steps down from 235 kHz

to 190 kHz within one cycle as shown in Fig. 2.21 (a) and steps up from 190 kHz to 235 kHz also within one

cycle as shown in Fig. 2.21 (b). The evaluated frequency variation range accounts for nearly half of the reg-

ular operating frequency range (150 kHz to 250 kHz). The step change is large and extremely fast compared

with a regular control loop design. The frequency change rate of a closed-loop controller is often limited

42
 severe dynamics in
severe dynamics in
Vout voltage and current Vout voltage and current
iD1 iD1

vgs.SR1 vgs.SR1
zoom-in RCV tracks instantaneously zoom-in
RCV tracks instantaneously
235 kHz 190 kHz
190 kHz 235 kHz

(a) (b)

Figure 2.21: The dynamic test waveforms under a large frequency step change, a) from 235 kHz to
190 kHz, and b) from 190 kHz to 235 kHz: the RCV-controlled SR tracks the actual rectifier
current conduction time instantaneously under severe voltage and current dynamics.

by the loop bandwidth; a sudden frequency change is rare in regular operations. However, for validation

purposes, this test condition is applied to verify the proposed RCV SR control method can respond to the

extreme condition properly. The resonant frequency of this LLC converter is around 200 kHz; thus, the test

condition forces the converter switching between the two regions: below and above the resonant frequency.

Therefore, this test condition also validates the ability of RCV SR switching between different operating

modes.

As shown in Fig. 2.21 (a), the switching frequency jumps from 235 kHz down to 190 kHz in the fourth

switching cycle, and hence the on time is increased and so is the peak of the rectifier current (iD1 ). During

the transient response time, both of the output voltage and the rectifier current swings in large amplitudes

drastically. As the waveform shows, the SR gate (vGS.SR1 ) driven by the RCV strategy tracks the actual

rectifier current cycle-by-cycle under this severe dynamic test condition. The frequency step-up test result is

shown in Fig. 2.21 (b); as the zoom-in waveforms show, the switching frequency is increased from 190 kHz

to 235 kHz in the fourth cycle. During the transient, the output voltage dips from 26 V to 22 V, and the peak

of the rectifier current is suddenly cut in half, and yet, the RCV SR on-time tracks the actual rectifier current

conduction time very well. As the rectifier current reduces, the SR on-time shrinks accordingly because

the amplitude of vCr is decreased simultaneously as discussed in Section 2.2.3. At the sixth switching cycle

shown in Fig. 2.21 (b), when the rectifier current reaches zero, the SR switching automatically stops because

the amplitude of vCr is less than nVo (1 + Lr /Lm). In the following cycles, the rectifier current increases and

so does the SR on-time. Therefore, the extreme test condition validates that the proposed RCV SR responds

to the system dynamics instantaneously.

43
2.5 Summary
In this chapter, an LLC synchronous rectification (SR) strategy based on the Resonant Capacitor Voltage

(RCV) is presented. The RCV strategy does not require current sensors; the SR turn-on and turn-off instants

are determined by simply comparing the integrations of the large-magnitude signals: the resonant capacitor

voltage, the converter input voltage, and the output voltage. By integrating the large voltage signals, the

RCV strategy provides a more noise-immune solution than traditional vds.on sensing methods. Significantly,

it is effective for multiple operating modes, covering both the below- and above-resonance regions. The

functionality and the effectiveness of the RCV strategy are validated by the simulation and experiments of a

650 W/ 24 V LLC converter. The results prove that the RCV controls the SR effectively over a wide operating

range. The dynamic test demonstrates that the RCV strategy can track the actual rectifier current conduction

time cycle-by-cycle under severe frequency variations. Compared with the traditional vds.on sensing method,

the proposed RCV SR driving strategy significantly reduces the on-time error caused by the parasitic effects.

As a result, the power loss is reduced by 6 % in the full-load condition, and for the SR MOSFET, 28 %

in the temperature rise relative to 25◦ C room temperature is reduced. Therefore, the RCV strategy offers a

noise-insensitive and effective solution for the synchronous rectification of LLC resonant converters.

44
Chapter 3

LLC Synchronous Rectification Using

Volt-Second Products

In Chapter 2, the resonant capacitor voltage based synchronous rectification (RCV SR) is introduced. This

large-magnitude voltage based method effectively reduces the SR on-time error and improves the efficiency

performance compared with the conventional vds.on based, non-adaptive SR. However, the amount of reset-

table integrators needed can add complexity to the circuit. For simplifying the design, this chapter introduces

the other SR method of this work, which is also based on large-magnitude voltage signals, and the SR on-

time control is insensitive to the voltage across leakage inductance. This method controls the SR using the

product of the blocking voltage of the SR switch and the rectifier current conduction time, and thus it is called

Volt-Second Product (VSP) SR. This chapter covers the fundamentals of the VSP SR algorithm as well as

the implementation. The proposed VSP SR is compared with an vds.on based adaptive SR to demonstrate the

efficiency improvement.

3.1 Time Domain Analysis

Before establishing the VSP SR algorithm, it is worthwhile to describe the resonant voltage and current in

the time domain, as synchronous rectification is essentially synchronization in time. Figure 3.1 illustrates

the typical above-resonance waveforms of a half-bridge LLC resonant converter, the schematic of which

is shown in Fig. 2.1. The Rectifier Current Equations [102] of a half-bridge LLC resonant converter are

established by solving the following differential equations. In the above-resonance region, defining t0 to be

zero, t2 simply equals half of the switching period Ts /2. For a given input and output voltage, the resonant

45
 vLS
vHS Ts 2

vCr VP1
IP1 V in

ir VS1 IS1
im
-IS1
vD2 -IP1
tA
irec

t0 t1 t2 t3 t4 t5 t

Figure 3.1: Typical waveforms of a half-bridge LLC resonant converter in the above-resonance region.

current and voltage in the first time interval (t0 – t1 ) are


ir.T 1 = Cr dvCr.T

 1


 dt


vCr.T 1 = Vin + nVo − Lr didtr.T 1 (3.1)



 dim.T 1 = −nVo


dt Lm

Solving the differential equations yields

 q
Cr




i r.T 1 = −IP1 cos(Ω r t) − (VP1 −Vin − nVo ) Lr sin(Ωr t)

 q
−I Lr (3.2)
v Cr.T 1 = P1 Cr sin(Ωr t) +Vin + nVo + (VP1 −Vin − nVo ) cos(Ωr t)



im.T 1 = −nVo (t − tA ) − IS1


Lm

where
1
Ωr = √ (3.3)
LrCr

Similarly, for the above-resonance operation, in the second time interval (t1 – t2 ),

ir.T 2 = Cr dvCr.T

 2


 dt


vCr.T 2 = Vin − nVo − Lr didtr.T 2 (3.4)



 dim.T 2 nVo

 =
dt Lm

and the solutions are

46
  q
Cr



i
 r.T 2 = −I S1 cos(Ω r (t − t A )) − (VS1 −Vin + nVo ) Lr sin(Ωr (t − tA ))

 q
−I Lr (3.5)
v Cr.T 2 = S1 Cr sin(Ωr (t − tA )) +Vin − nVo + (VS1 −Vin + nVo ) cos(Ωr (t − tA ))



im.T 2 = nVo (t − tA ) − IS1


Lm

In (3.5), tA is simply the interval from t0 to t1 and is dependent on the operating point Vin , Vo , and Ts ,

which will be defined later. In (3.2) and (3.5), the initial conditions VP1 , VS1 , IP1 , and IS1 are the four

independent unknowns. Therefore, four equations are needed to solve for the initial conditions. According

to the waveform of the magnetizing current im , it takes Ts /2 for im to rise from −IS1 to IS1 , and thus

Ts
im.T 2 (tA + ) = IS1 (3.6)
2

The other three equations are derived by considering the continuity of the resonant current and voltage

ir.T 1 (tA ) = ir.T 2 (tA ), (3.7)

vCr.T 1 (tA ) = vCr.T 2 (tA ). (3.8)

And for half-bridge resonant converters,

Ts
vCr.T 1 (t0 ) + vCr.T 2 ( ) = Vin . (3.9)
2

Applying the relationships (3.6) – (3.9) to (3.2) and (3.5), the initial conditions VP1 , VS1 , IP1 , and IS1 can be

derived as a function of Vin , Vo , Ts , and tA :



VP1 = Vin + nVo −Vm1





  
VS1 = Vin + nVo 1 − φS tan φA −Vm1


m
q (3.10)
 nVo Ts Cr
IP1 = 4Lm cos φA + Lr Vm1 tan φA






I = nVo Ts

 S1 4Lm

where
Lm Ωr Ts
m= , φA = Ωr tA , φS = , (3.11)
Lr 4

47
and

φS sin(2φS )
Vin m cos φA + 2 cos φA − 4 cos φS cos(φA − φS )
Vm1 = − nVo (3.12)
2 cos φS (cos φS + sin φS tan φA ) 2 cos φS (cos φS + sin φS tan φA )

By taking the initial conditions (3.10) back to (3.5) and considering ir.T 2 ( T2s ) = IP1 , the steady-state gain

equation for the above-resonance operation is derived as

nVo sin(Ωr (Ts /4 − tA ))

= r Ts
, (3.13)
Vin /2 sin(Ωr Ts /4) + Ω4m cos(Ωr Ts /4)

√
where Ωr is the short-circuit resonant frequency 1/ LrCr . As a result, the duration tA is explicitly expressed

as
Ts α
tA = − (3.14)
4 Ωr

where
n 2nV   Ω T  Ω T 
Ωr Ts
 o
−1 o r s r s
α = sin sin + cos (3.15)
Vin 4 4m 4

As for the below-resonance region, the typical operating waveforms are shown in Fig. 3.2. Defining t0

– t1 and t1 – t2 as the first and second interval, the resonant current and voltage in the first time interval are

expressed as 
ir.T 1 = Cr dvCr.T 1


dt
(3.16)
vCr.T 1 = −(Lr + Lm ) dir.T 1


dt

Solving the differential equations yields


q
−IS2 cos(Ωot) −VS2 Lr C+L

ir.T 1 =
 r
sin(Ωot)
m
q (3.17)
vCr.T 1 = −IS2 Lr +Lm sin(Ωot) +VS2 cos(Ωot)


Cr

where
1
Ωo = p (3.18)
(Lr + Lm )Cr

48
 vLS
vHS Ts 2

vCr VS2
VP2 V in
IS2 IP2 
ir
im

-IS2 -IP2
vD2
tB
irec

t0 t1 t2 t3 t4 t

Figure 3.2: Typical waveforms of a half-bridge LLC resonant converter in the below-resonance region.

In the second time interval (t1 – t2 ) in Fig. 3.2,


ir.T 2 = Cr dvCr.T

 2


 dt


vCr.T 2 = Vin − nVo − Lr didtr.T 2 (3.19)



 dim.T 2 = nVo


dt Lm

and the solutions are

 q
−IP2 cos(Ωr (t − tB )) − (VP2 −Vin + nVo ) Cr

ir.T 2 = Lr sin(Ωr (t − tB ))





 q
vCr.T 2 = −IP2 CLrr sin(Ωr (t − tB )) +Vin − nVo + (VP2 −Vin + nVo ) cos(Ωr (t − tB )) (3.20)




im.T 2 = nVo (t − tB ) − IP2


Lm

Similarly, to solve for the four initial conditions, VP2 , VS2 , IP2 , and IS2 , four voltage and current equa-

tions have to be established. In the second time interval, the magnetizing current is IS2 at t2 , and this time

corresponds to Ts /2 by letting t0 be zero. Thus,

Ts
im.T 2 ( ) = IS1 (3.21)
2

The other three equations are derived by considering the continuity of the resonant current and voltage

ir.T 1 (tB ) = ir.T 2 (tB ), (3.22)

49
 vCr.T 1 (tB ) = vCr.T 2 (tB ). (3.23)

And for half-bridge resonant converters,

Ts
vCr.T 1 (t0 ) + vCr.T 2 ( ) = Vin . (3.24)
2

Applying the relationships (3.21) – (3.24) to (3.17) and (3.20), the initial conditions VP2 , VS2 , IP2 , and IS2 can

be derived as a function of Vin , Vo , Ts , and tB :






VP2 = Vm2 +Vm3


 √
VS2 = Vm2 +Vm3 sin(2β ) cos(φB )+ √1+m cos(2β ) sin(φB )


sin(2β )− 1+m sin(φB )
q (3.25)
 Cr sin(φB ) cos(2β√ )+cos(φB )



IP2 = Lr (Vm2 1+m(1+cos(φB )) +Vm3 sin(2β )− 1+m sin(φB ) )
√


 q
 Cr sin(φB ) 1+cos(2β √ )+cos(φB ) sin(2β ) sin(φB )
Lr (−Vm2 1+m(1+cos(φ )) +Vm3 sin(2β )− 1+m sin(φ ) −Vm3 1+m sin(2β )−(1+m) sin(φ ) )
IS2 =
 √ √
B B B

where
Ωr Ts
φB = ΩotB , β = ( − tB ), (3.26)
2 2

and
√
1 + m(1 + cos(φB ))((Vin − nVo ) cos(2β ) + nVo )
Vm2 = √ (3.27)
1 + m(1 + cos(2β ))(1 + cos(φB )) − sin(2β ) sin(φB )
2nβVo √
m ( 1 + m sin(2β ) − (1 + m) sin(φB ))
Vm3 = √ (3.28)
1 + m(1 + cos(2β ))(1 + cos(φB )) − sin(2β ) sin(φB )

Note that Ts /2 − tB corresponds to the rectifier conduction time in the below-resonance operation.

By taking the initial conditions 3.25 back to 3.20 and considering ir.T 2 ( T2s ) = IS2 , the gain equation in the

below-resonance region is derived as

nVo m
= √ , (3.29)
Vin /2 β cot(β ) − β 1 + m tan( φB ) + m
2

Although tB or β can only be expressed implicitly according to (3.29) due to the coexistence of trigonometric

and non-trigonometric terms, the critical information to the proposed VSP SR algorithm is the range of tA

and Ts /2 − tB , which will be explored in the following section.

50
 vgs.SR1
HS
vHS iD1 Llk
n::
Vin vlk irec
ir Lr
Cds
LS irec vds.on1
vLS Lm
Co vD1
Cr vds.on2 vD2
im Cds vo
iD vlk Ro Plateau Voltage Plateau Voltage
vCr vDp1 vDp2
Ra Ra Llk

Rb R vgs.SR2
vD1 b vD2 vds.on1
vds.on2
(a) vth.rev

millivolt range
vth.on vth.off
Conventional vgs.SR1 plateau volt.
vds.on1 vgs.SR1
vds.on based vgs.SR2 sampling Proposed vth.on
vgs.SR2
vds.on2 vD1 VSP SR Proposed:
SR logic Conventional:
vD2 rising edge logic based on vds.on1,2 based on vDp1,2
( vth.rev for detection vgs.SR1
vth.off
vgs.SR2
adaptive SR) Premature Premature
vHS , vLS turn-off turn-off
small and sensitive signal simple implementation
easily affected by parasitic large voltage signal sensing, tolerant of
Improved SR on-time
components parasitic effects
(b) (c)

Figure 3.3: a) a typical LLC resonant converter with synchronous rectification, including circuit par-
asitic components. b) block diagram of the conventional vds.on based SR and the proposed Volt-
Second Product (VSP) based SR; the former depends on the drain-source voltage during the turn-
on phase, while the latter employs the drain-source voltage during the turn-off phase. c) vds.on1
and vds.on2 are in millivolt range and are easily affected by the parasitic effects, whereas the pro-
posed VSP SR uses large-magnitude voltage signals and improves the SR on-time.

3.2 VSP SR Driving Strategy

With the focus on industrial battery charging applications, where there is a microcontroller on the output

stage for communication purposes, this part of the work proposes a noise-tolerant SR method that can be

easily integrated with the microcontroller. The SR on-time is determined based on the product of SR drain-

source blocking voltage during the turn-off phase and rectifier current conduction time. This Volt-Second

Product based SR (VSP SR) employs the large-magnitude voltage signal instead of the low-magnitude,

noise-sensitive vds.on used by the conventional SR controllers, and hence the VSP SR is more tolerant of

parasitic effects, reducing the SR on-time error. As illustrated in Fig. 3.3 (a) and (b), the proposed VSP

SR simply uses a pair of voltage dividers to sense the drain-source voltage during the turn-off phase (vD1

and vD2 ). Along with the primary switch driving signals, the VSP SR algorithm determines the SR on-

time. Figure 3.3 (c) shows an example of the parasitic effects on the SR gating signals. The small vds.on

voltage is susceptible to the effects of voltage across the stray inductance, which can cause premature turn-

off even with the conventional adaptive scheme. The proposed VSP SR, on the other hand, improves the

51
 plateau voltage sampling
vD1
vDp1 CMPB1
ADC1
CMPB2 vgs.SR1
vDp2
CMPA1 Saw1 VSP SR PWM vgs.SR2
Sync 1
vD1.logic Cap 1 algorithm generation
tcnd1 tcnd1 Sync 2
Saw1
vref sampling tcnd2
Sync 1
Saw1 Saw2
rising edge vLS.sync vLS.sync T sc (digital counter)
detection generation

plateau voltage sampling

vD2 ADC2

CMPA2 Saw2 PWM vLS

vD2.logic generation vHS
Cap 2
vref tcnd2
Saw2
Sync 2 sampling
rising edge
detection vHS.sync vHS.sync T sc
generation

Figure 3.4: Functional block diagram of the proposed Volt-Second Product (VSP) SR.

SR efficiency performance by employing large-magnitude voltage signals. More details are provided in the

following sections.

A more detailed functional block diagram of the proposed VSP SR control logic is shown in Fig. 3.4. The

sensed (vD1 , vD2 ) are fed into the plateau voltage sampling block, where the plateau of the blocking voltage

vDpx (x = 1, 2) are sampled. This information is used as the voltage control signal of the Volt-Second Product

(VSP) SR. The time control signal (tcndx ), on the other hand, comes for the tcndx sampling block. The tcndx

sampling block is controlled by the time capture signal (Capx ), the synchronization signal (Syncx ) and the

sawtooth digital counter signal (Sawx ). The Capx signal captures the instantaneous value of Sawx , which

corresponds to the rectifier current conduction time (namely the time control signal tcndx ), while the Syncx

signal resets Sawx in every switching cycle.

Based on the voltage and time control signals, the VSP SR algorithm determines the SR on-time control

signal CMPBx . The VSP SR algorithm also includes the calculation of the SR control time window, Tsc ,

which is a period of time that allows turn-on trigger of the SR. This Tsc time window starts at the falling

edge of the primary switches control signals (vLS , vHS ) and finishes when the time expires, which will be

discussed in the following section. As shown in the block diagram, vLS.sync is a pulsating signal that is

synchronized with the falling edge of vLS and has a pulse width of Tsc ; the other corresponding signal is

vHS.sync . These two signals and the logic-level signals of vDx , namely vDx .logic , determine the synchronization

signals (Syncx ). The logic-level signals are generated simply by comparing vDx with a threshold voltage

52
(vre f ), which is commonly around 1 to 2 V . Detailed operating waveforms and sequence are explained in the

following sections.

3.2.1 Steady-State Operation

The turn-on of SR using the proposed VSP method is determined by the logic level of the drain-source

voltage (vD1 , vD2 ) and the primary gate-drive signals (vLS , vHS ). As illustrated in Fig. 3.5, vD1.logic and

vD2.logic are the logic levels of the corresponding drain-source voltages, which are determined by comparing

vD1 and vD2 with a reference voltage, vre f . The other pair of control signals is vLS.sync and vHS.sync , which

is respectively set at the falling edge of vLS and vHS , and is reset after a SR control time window, Tsc . The

SR driving signal vgs.SR1 is set when both vD2.logic and vLS.sync are high; correspondingly, vgs.SR2 is set when

both vD1.logic and vHS.sync are high. Since the operation principles for vgs.SR1 and vgs.SR2 are symmetrical, the

following discussion focuses on the first set of SR only.

For the above-resonance operation, as shown in Fig. 3.5 (a), the primary low-side switch vLS turns off at

t0 , and vLS.sync is set at the same time. From t0 to t1 , because the rectifier current is conducting, the rectifier

voltage vD2 is clamped low until the current iD2 reaches zero, which means that vD2.logic changes its state after

the rise of vLS.sync . Therefore, vgs.SR1 is set at the rising edge of vD2.logic in the above-resonance region. Note

that the minimum duration of the SR control time window Tsc is determined by the maximum time interval

from t0 to t1 , which takes place at the maximum switching frequency. Ideally, the SR on-time tSR1 is equal to

the rectifier current conduction time tcnd1 ; in practice, a safe operation margin is reserved at the falling edge

of vgs.SR1 for preventing reverse current and potential cross-conduction.

For the below-resonance operation, as shown in Fig. 3.5 (b), from t0 to t1 , the transformer is decoupled

despite the residual energy circulating in the loop. The voltage ringing causes vD2.logic to change its states

frequently and the rising edges are not necessarily synchronous with the conduction of iD1 as in the case of

above-resonance. Rather, when the input voltage changes its polarity, the transformer is coupled, and the

rectifier current iD1 starts to conduct. This instant is synchronous with the falling edge of vLS or the rising

edge of vLS.sync . Because vLS.sync rises when the transformer is coupled, where vD2.logic is in the high state,

vLS.sync determines the turn-on of vgs.SR1 in this case. Note that the pulse width of vLS.sync , namely Tsc , cannot

be longer than Ts /2 − tB in order to drive the SR correctly.

The selection of the time window Tsc is based on the range of tA and Ts /2 −tB . To unify the SR algorithm

across above- and below-resonance regions, it is necessary to select Tsc such that the time interval applies to

both operation modes. In the above-resonance region, Tsc must be larger than tA . According to (3.14) and

53
 vD1
vD2 tcnd1[k-1] vDp1 [k] tcnd1[k]
vDp1 [k-1]
vref

vLS
vHS
vD1.logic

vD2.logic
tA
vLS.sync
vHS.sync T sc T sc

iD1
iD2

vgs.SR1
tSR1[k-1] tSR1[k]

t0 t1 t2 t3’ t3 t4 t5 t6 t7’ t7 t
(a)

vD1
vD2 tcnd1[k-1] vDp1 [k] tcnd1[k]
vDp1 [k-1]
vref

vLS
vHS
vD1.logic

vD2.logic
tB
vLS.sync
vHS.sync T sc T sc

iD1
iD2
vgs.SR1
tSR1[k-1] tSR1[k]

t0 t1 t2’ t2 t3 t4 t5 t6’ t6 t7 t
(b)

Figure 3.5: Typical waveforms of the proposed VSP SR: a) above-resonance and b) below-resonance
operations. The Tsc time window allows for correct setting of the SR for both cases.

(3.15), because α is a positive real number, and the switching period Ts is less than the resonant period Tr

(which equals 2π/Ωr ):

Tr
tA < . (3.30)
4

In the below-resonance region, Tsc must be less than Ts /2 − tB , otherwise, the rising edges of vD2.logic at

the end of rectifier current can mis-trigger vgs.SR1 . According to (3.29), since the gain is greater or equal to

one in the below-resonance region,

ΩotB 1
tan( ) tan β ≥ √ . (3.31)
2 1+m

If Ts /2 − tB ≤ Tr /4, then tan β ≤ 1 following the definition of β (3.26). Based on (3.31), tan(ΩotB /2) then

54
 √
should be greater or equal to 1/ 1 + m, which can be easily disproved by the instance of tB equal to zero.

Therefore,
Ts Tr
− tB > . (3.32)
2 4

As a result, the time window Tsc for vLS.sync and vHS.sync is selected as Tr /4, which is applicable to both

below- and above-resonance regions following 3.30 and 3.32.

Based on the operating principles of the resonant tank and the logic signals generated from drain-source

voltage and the primary gate-drive signals, the criteria to turn on the SR in above- and below-resonance

regions are determined respectively. The turn-on of vgs.SR1 is synchronous with vD2.logic for the above-

resonance, while it is synchronous with vLS.sync for the below-resonance operation. By simply taking the

logic AND operation of vD2.logic and vLS.sync , these two signals take over the control of SR seamlessly with-

out the need for resonant frequency information.

The sensed drain-source voltage not only relates to the turn-on of SR but also contains the information

to control the turn-off instant. The core VSP SR algorithm determines the SR on-time for both below- and

above-resonance conditions using the sampled drain-source blocking voltage from the kth cycle (vDP1 [k])

and the rectifier current conduction time from the previous cycle (tcnd1 [k − 1]); both are extracted from the

drain-source voltage during the SR turn-off phase. The core VSP SR algorithm is a linear combination of

volt-second products defined as

(vden + vcm ) · (tSR1 [k] + DT ) = (vnum + vcm ) · tcnd1 [k − 1], (3.33)

where DT is the safe operation margin, vcm is a constant for compensation, and





(vDp1 [k], vT [k]), if vDp1 [k] ≤ vT [k];


(vnum , vden ) = (3.34)





(vT [k], vDp1 [k]), otherwise.


For a center-tapped rectifier, vDp1 [k] and vT [k] are respectively proportional to the output voltage and target

with the same ratio. According to the VSP SR core equation, in steady states, vnum and vden are equal,

so the SR on-time tSR1 [k] reaches the rectifier conduction time with a constant safe operation margin DT .

In transient response, the sampled drain-source blocking voltage is the key to adjusting the SR on-time

dynamically. With a proper selection of vcm , the proposed VSP SR algorithm maintains the safe margin

55
above DT during the transient, which will be analyzed in the following subsection.

3.2.2 Transient Analysis

For a frequency modulated LLC resonant converter, the switching frequency is modulated by the closed-loop

controller. When the frequency increases, the SR on-time must reduce accordingly, otherwise, the rectifier

current can flow reversely and cause large voltage spikes at the turn-off of the SR. It is particularly critical in

the above-resonance region because the rectifier current conduction time changes with the switching period.

Therefore, the following transient analysis focuses on the above-resonance operation.

As the system block diagram shows in Fig. 3.6, the closed-loop controller outputs the control signal vc

based on ∆vo , the error of the output voltage. The frequency modulator determines the switching frequency

of the primary driving signals vHS and vLS by comparing vc with a sawtooth signal vsaw . Considering a typical

PI controller with the proportional and integral gain Kp and KI , the relationship between vc and vsaw is shown

in Fig. 3.7. Based on the geometry, the change in the switching period (∆ts ) per half-cycle is defined as

Ts [k − 1] − Ts [k] KI · ∆vo · tcnd1 [k − 1] Kp · ∆vo

∆ts [k] := = + (3.35)
2 Ssaw + Sc Ssaw + Sc

where Sc and Ssaw are the slopes of the controller output and the internal sawtooth signal, respectively. In

the above-resonance region, ∆ts equals the change in the rectifier current conduction time, as the conduction

time is one-half of the switching period. Therefore, to maintain the safe operation margin (DT ) during the

dynamic response, as illustrated in Fig. 3.7, the time difference between the rectifier current conduction time

and SR on-time (δ T ) must be at least DT :

δ T [k] := tcnd1 [k] − tSR1 [k] = tcnd1 [k − 1] − tSR1 [k] − ∆ts ≥ DT. (3.36)

Taking the core VSP SR equation (3.33) into (3.36) yields

∆vo · tcnd1 [k − 1]
≥ ∆ts [k] (3.37)
vden + vcm

For the above-resonance operation, the inequality (3.37) is more critical than below-resonance because

the reduced switching period directly leads to a reduction of rectifier conduction time. Combining (3.35) and

56
 HS SR 
Vin n::
Lr

Lm
LS SR  Co Ro vo

Signal Cr
Isolation vD1
vD2
vHS vLS
Logic VSP SR
Gates Controller

Frequency vc Closed-loop Dvo vo*

Modulator Controller
vsaw Microcontroller

Figure 3.6: System block diagram of a typical closed-loop controlled LLC resonant converter with the
proposed VSP SR controller.

vc
vsaw D vc
Sc
D ts
Ssaw
T s [k-1] 2

vHS
vLS T s [k-1] 2 T s [k] 2 T s [k+1] 2

vD1 tSR1 = f ( vnum, vden, tcnd1)

vDp1 [k]
tcnd1[k-1] tcnd1[k] tcnd1[k+1]
vgs.SR1 dT
dT dT
DT DT DT

tSR1[k-1] tSR1[k] tSR1[k+1] t

Frequency increasing, dT > DT to maintain safe margin

Figure 3.7: The relationship between the change in the switching period (∆ts ) and the closed-loop
controller gain defines the rate of change in the rectifier current conduction time in the above-
resonance region.

(3.37) gives the criterion for selection of the compensation voltage vcm :

Ssaw · tcnd1 [k − 1]
vcm ≤ − vden (3.38)
Kp + KI · tcnd1 [k − 1]

The larger the compensation vcm is, the less the VSP SR is sensitive to the frequency change. To ensure

a sufficient safe margin, the maximum of vden and the minimum of tcnd1 can be considered. Due to the

symmetry, similar analyses can be applied to the other SR. As a result, the complete VSP SR algorithm is

summarized as follows:

57
 

set,
 vD2.logic & vLS.sync
vgs.SR1

reset, tSR1 reached

 (3.39)

set,
 vD1.logic & vHS.sync
vgs.SR2

reset, tSR2 reached


3.3 Implementation of VSP SR

The proposed VSP SR algorithm is implemented using a microcontroller with only a few external logic gates.

The system block diagram is shown in Fig. 3.6, where both the closed-loop controller and the VSP SR are

in the single microcontroller. It clearly shows that the voltage sensing of the VSP SR requires only a pair

of voltage dividers for each of the SR switches. Due to the nature of large-magnitude voltage sensing, the

PCB (printed circuit board) layout design has less constraints than conventional vds.on based methods. The

SR controller, that is, the microcontroller, does not have to be placed as close to the SR switches as possible,

which makes the PCB design more flexible.

This section focuses on the VSP SR controller part, of which the implementation is shown in Fig. 3.8.

According to the VSP SR algorithm (3.39), vgs.SR1 is set by taking the logical AND operation of vD2.logic and

vLs.sync , which is indicated as Sync1 in Fig. 3.8. vgs.SR1 is reset according to the core VSP SR algorithm (3.33)

and (3.34), where the blocking voltage vDp1 and the rectifier current conduction time tcnd1 are the required

input signals. The sampling of vDp1 is implemented by feeding vD1 to the ADC module ADC1 , whereas tcnd1

is captured at the rising edge of vD1.logic , denoted as Cap1 . The implementation of the other SR is mirrored.

The detailed timing sequence for below- and above-resonance operations is shown in Fig. 3.9. As shown

in the timing sequence, each SR is respectively controlled by an internal time-based counter signal, Saw1 and

Saw2 . These time-based counters are used for recording the rectifier conduction time, triggering the turn-off

of SR, and initiating ADC sampling in each cycle. Note that the VSP SR algorithm (3.39) applies to both

below- and above-resonance conditions; the following description focusing on the first SR is applicable to

both conditions.

In the timing sequence, the k − 1th cycle starts at t0 , and the kth cycle starts at t4 ; each cycle is initiated

by the ADC1 interrupt service routine (ISR), of which the flowchart is shown in Fig. 3.10. At t1 and t5 ,

Sync1 resets the counter Saw1 and sets vgs.SR1 . When the counter Saw1 reaches CMPB1 , a reset signal is

sent to vgs.SR1 at t2 and t6 , respectively. The threshold CMPB1 corresponds to the SR on-time calculated by

58
 vD1 ADC1
vgs.SR1 ,
vD1.logic Cap 1 vgs.SR2
vref PWM
vLS , vHS
Sync 1 Module
vLS.sync vLS.sync ,
vHS.sync
vD2 ADC2
vD2.logic Cap 2
vref
Sync 2
vHS.sync
Microcontroller

Figure 3.8: Block diagram for implementation of the proposed VSP SR using TMS320F28379D with
only a few external logic gates.

vD1
vD2 v vDp1 [k] vDp1 [k-1] vDp1 [k]
Dp1 [k-1]
vref
Sync 1
Cap 1
ADC1
tcnd1[k-1] tcnd1[k] tcnd1[k-1] tcnd1[k]
CMPA1
Saw1 tSR1[k-1] tSR1[k]
CMPB1 tSR1[k-1] tSR1[k]
Sync 2
Cap 2
ADC2

CMPA2
Saw2
CMPB2
vgs.SR1
vgs.SR2 tSR1[k-1] tSR1[k] tSR1[k-1] tSR1[k]

t0 t1 t2 t3 t4 t5 t6 t7 t t0 t1 t2 t3 t4 t5 t6 t7 t
Below-Resonance Region Above-Resonance Region

Figure 3.9: Timing sequence of the VSP SR controller for below- and above-resonance operations.
tSR1 [k] is computed at ADC1 where vDp1 [k] is sampled. Sync1 resets the time counter, while Cap1
captures tcnd1 .

(3.33), which is updated in the ADC1 ISR of each cycle. At the rising edge of vD1 , correspondingly t3 and

t7 in the k − 1th and kth cycle, the time-interval capture signal Cap1 is triggered, and the value of Saw1 is

captured. This value corresponds to tcnd1 , and the captured value in the k − 1th cycle is used to determine

tSR1 [k] following (3.33). Note that the triggering of Cap1 is latched until the following ADC2 to prevent false

triggering. This is particularly important for the below-resonance mode to avoid false triggering caused by

voltage ringing on vD1 during the zero-current time intervals. Since each tcnd1 is captured following an ADC2

event, the reset of Cap1 latch is handled by ADC2 ISR; the reset of Cap2 latch is handled by ADC1 ISR.

As shown by the flowchart of ADC1 ISR in Fig. 3.10, the blocking voltage of the present cycle and the

rectifier conduction time from the previous cycle are acquired. The acquired vDp1 [k] and tcnd1 [k − 1] are for

calculating tSR1 [k]. In addition, the latch of Cap2 is reset and ready for capturing the conduction time of the

59
 ISR: ADC1 [k]

vnum = vDp1 [k]

Acquire vDP1 [k]
vden = vT [k]
Acquire tcnd1[k-1]
Reset Cap 2 latch

Calculate tSR1[k] (15)

No
vDp1 [k] > vT [k] CMPB1 = tSR1[k]

Yes
vnum = vT [k]
vden = vDp1 [k] Return

Figure 3.10: Flowchart of ADC1 interrupt service routine (ISR). In the kth cycle, it executes the core
of the VSP SR algorithm to determine the SR on-time tSR1 [k] based on tcnd1 [k − 1], vDp1 [k], and
vT [k].

other SR at the next rising edge of vD2 . By the end of the ISR, tSR1 is assigned to CMPB1 , which compares

with Saw1 and determines the SR on-time.

3.4 Simulation and Experimental Results

The proposed VSP SR is verified by both simulation and experiments on a 650 W/ 24 V battery charger

under closed-loop control. The system block diagram is shown in Fig. 3.6 with the system parameters listed

in Table 3.1. To examine the selection of the time window Tsc , Fig. 3.11 shows the theoretical rectifier

current conduction time for below-resonance and tA for above-resonance operations using (3.13) and (3.29).

Considering the SR operating load range from 25 % to 100 %, Fig. 3.11 demonstrates that the selected time

Table 3.1: System Parameters

Parameter Values
input voltage, Vin 400 V
nominal power, Pout 650 W
maximum output current, Imax 27 A
nominal output voltage, Vnom 24 V
maximum output voltage, Vmax 30 V
minimum output voltage, Vmin 20 V
switching frequency, fs 150–250 kHz
resonant frequency, Fr 189 kHz
magnetizing inductance, Lm 103.4 µH
resonant inductance, Lr 37.7 µH
resonant capacitor, Cr 18.8 nF
transformer turns ratio, n 8.1
primary switches IPA65R400CE
SR switches STP240N10F7

60
 fs F r (below resonance)
0.75 0.8 0.85 0.9 0.95 1
0.5
Ro Decreases ( t s 2 - t B) T r

0.375

T sc T r

t Tr
0.25

0.125
tA T r
Ro Decreases
0
1 1.05 1.1 1.15 1.2 1.25
fs F r (above resonance)

Figure 3.11: Plot of the theoretical, normalized rectifier current conduction time, tA , and time window
Tsc , considering 25 %, 50 %, 75 %, and 100 % load. The selection of Tsc is around the center
with sufficient margin between the rectifier current conduction time and tA .

window Tsc meets the criteria (3.30) and (3.32) with sufficient margin.

In order to verify that the proposed VSP algorithm effectively adjusts the SR on-time and maintains the

safe margin in transient response, the difference between the SR on-time and the rectifier current conduction

time (δ T ) is simulated. The above-resonance operation is focused as the SR on-time changes significantly

with frequency in this region. As shown in Fig. 3.12 (a), the output voltage (vo ) starts rising due to a step-up

vo command, and the frequency decreases following the control loop. In this case, both the conventional

and the proposed SR keep the safe operation margin above DT . When vo command steps down, as shown

in Fig. 3.12 (b), the frequency increases as a result of closed-loop regulation. In this case, however, several

cycles of the conventional adaptive SR have insufficient safe margin, since the detection of δ T < DT has to

take place first before the SR on-time can be reduced in the next cycle. In contrast, the proposed VSP SR

algorithm uses both the voltage and time information to change the SR on-time dynamically, maintaining the

safe margin above DT .

The 650 W battery charger prototype for validating the VSP SR is shown in Fig. 3.13. The VSP SR

daughterboard located on the secondary side detects the drain-source voltages, synthesizes the SR triggering

signals, and transmits them to the microcontroller board. For the below-resonance operation, Fig. 3.14 shows

the converter operating at the maximum voltage and maximum power condition, where Fig. 3.14 (a) is the

result using a commercial vds.on based adaptive SR controller, and Fig. 3.14 (b) is the result of the proposed

VSP SR. Figure 3.14 (a) shows that the adaptive SR controller turns on the switch early. It is mis-triggered

when the SR body diode starts conduction due to the sub-resonance between the parasitic capacitors and the

equivalent inductor. Consequently, the rectifier has reverse current flow, which lowers the efficiency.

61
 24 25
vo [V]

vo [V]
22
23
20 21
40 40

iD1 [A]
iD1 [A]

20 20

0 0
dT [Clock] vgs.SR1[V]

dT [Clock] vgs.SR1[V]
10 10

0 0
80 Proposed VSP SR Adaptive SR 80 Proposed VSP SR Adaptive SR
60 60
40 40
20 20
DT dT > DT DT dT < DT
0 0
0 20 40 60 80 100 120 0 20 40 60 80 100 120
t [ms] t [ms]
(a) (b)

Figure 3.12: Simulation results of the VSP SR and the conventional adaptive SR under closed-loop
regulation: a) vo rising and b) vo falling. In both cases, the VSP SR maintains the dead time δ T
above the preset safe margin DT , whereas the conventional adaptive SR has multiple cycles with
insufficient safe margin during frequency rise, increasing the risk of cross conduction.

Primary Side
VSP SR
Daughterboard

Secondary Side

Microcontroller
Board

Figure 3.13: The prototype of the 650 W/ 24 V LLC resonant converter with the proposed VSP SR
controller.

In contrast, the proposed VSP SR, as shown in Fig. 3.14 (b), is not affected by the parasitic effects and

turns on the switch properly after the rectifier current starts conduction. The turn-on delay of the prototype is

around 240 ns, which can be further improved by reducing the propagation delay. By removing the reverse

current, the VSP SR improves the efficiency by 0.2%, which is around 3% of the total loss.

For above-resonance operation, the results are compared in Fig. 3.15 (a) and (b), where the operating

condition is at the minimum output voltage and maximum current. As shown in Fig. 3.15 (a), the vds.on

based adaptive SR turns off the SR prematurely due to drastic change in the current slope and voltage across

the leakage inductance, and the dead time is nearly as much as twice that in the below-resonance operation.

62
vgs.SR1 vgs.SR2 (10V/ Div.) irec (20A/ Div.) vDS(SR1) (20V/ Div.) vgs.SR1 vgs.SR2 (10V/ Div.) irec (20A/ Div.) vDS(SR1) (20V/ Div.)

1 ms / Div. 1 ms / Div.
vDS(SR1) (2V/ Div.) Zoom-in vDS(SR1) (2V/ Div.) Zoom-in
inversion current 180 ns 110 ns

Adaptive SR: early turn-on VSP SR: proper turn-on

due to parasitic effects 300 ns / Div. timing, no inversion current 300 ns / Div.

(a) (b)

Figure 3.14: Steady-state test results in constant voltage regulation at 30 V/ 650 W, fs = 167 kHz: a)
the conventional adaptive SR turns on the switch early due to voltage ringing-induced SR body
diode conduction, introducing reverse current; b) the proposed VSP SR controls SR on-time
properly.

vgs.SR1 vgs.SR2 (10V/ Div.) irec (20A/ Div.) vDS(SR1) (20V/ Div.) vgs.SR1 vgs.SR2 (10V/ Div.) irec (20A/ Div.) vDS(SR1) (20V/ Div.)

1 ms / Div. 1 ms / Div.
vDS(SR1) (2V/ Div.) Zoom-in vDS(SR1) (2V/ Div.) Zoom-in
330 ns 120 ns

Adaptive SR: early turn-off VSP SR: reduced on-time

due to parasitic effects 300 ns / Div. error, consistent turn-off timing 300 ns / Div.

(a) (b)

Figure 3.15: Steady-state test results in constant current regulation at 27 A/ 540 W, fs = 238 kHz: a) the
conventional adaptive SR turns off the switch prematurely due drastic change in the current slope
and voltage across the leakage inductance; b) the proposed VSP SR is tolerant to the parasitic
effects, maintaining consistent dead time.

Contrary to the conventional method, the proposed VSP SR is not affected by the parasitic effect, and it

maintains a consistent safe margin for both operating modes. As shown in Fig. 3.15 (b), the SR tracks the

rectifier current conduction time and turns off the SR 120 ns before the current reaches zero, which is close

to the margin left in the below-resonance operation. Compared with Fig. 3.15 (a), the dead time is reduced

by 64%, and this difference is reflected in the efficiency.

The efficiency results of the 650 W prototype using the conventional vds.on method and the proposed

VSP SR are compared in Fig. 3.16 (a) and (b) considering constant-voltage and constant-current regulation,

respectively. For constant-voltage regulation, the output voltage is regulated at Vmax (30 V ), and the operating

63
 96.2
Proposed VSP SR Proposed VSP SR
93.2 93.13
95.80 Adaptive SR Adaptive SR
95.8 92.92
93.11
95.76
Efficiency [%]

Efficiency [%]
95.32 92.8
95.4
92.49
95.32 92.52
94.79 92.4
95.0
92.00 92.28
94.6 94.76 More loss due to 94.43 92.0
Efficiency improvement due
reverse current
to reduction of on-time error
91.77
94.2 94.25 91.6
25 50 75 100 20.5 21.5 22.5 23.5
Load [%] Output Voltage [V]
(a) (b)

Figure 3.16: Efficiency test results under: a) constant voltage regulation, Vo = 30 V , and b) constant
current regulation, Io = 27 A.

vgs.SR1 vgs.SR2 (10V/ Div.) irec (20A/ Div.) vo (10V/ Div.) vgs.SR1 vgs.SR2 (10V/ Div.) irec (20A/ Div.) vo (10V/ Div.)

Zoom-in 50 ms / Div. Zoom-in 50 ms / Div.

VSP SR responds to system dynamics properly VSP SR responds to system dynamics properly

SR on-time increasing SR on-time decreasing

2 ms / Div. 2 ms / Div.

(a) (b)

Figure 3.17: The dynamic test waveforms under a large command change, a) from Vmin to Vmax , and b)
from Vmax to Vmin : the VSP SR tracks the rectifier current conduction time properly under severe
voltage and current dynamics.

frequencies are below the resonance. The efficiency test results are comparable because the SR on-time of

the proposed VSP SR and the conventional adaptive SR are similar. In the full-load condition, the adaptive

SR is less efficient due to the reverse current shown in Fig. 3.14 (a).

For constant-current regulation, the output current is regulated at Imax (27 A) and the efficiency is mea-

sured above the minimum output voltage Vmin (20 V ). As shown in Fig. 3.16 (b), the efficiency of the

conventional adaptive SR is lower, and the gap increases with frequency. It is because the conventional

method turns off the SR prematurely, and the dead time increases with frequency.

The closed-loop dynamic test results of the proposed VSP SR are shown in Fig. 3.17. The command

changes from Vmin to Vmax and vice versa, which emulates the largest step change in the system, covering

the full operating frequency range. Under such a severe transient, both the rectifier current (irec ) and the

output voltage (vout ) respond dramatically. The VSP SR successfully tracks the switching frequency and the

64
rectifier current conduction time in both the output voltage step-up and step-down conditions. As shown

in Fig. 3.17 (a), the output voltage increases as the frequency decreases; the operating mode transits from

above-resonance to below-resonance. The SR on-time increases accordingly with a reasonable amount of

safe margin. In Fig. 3.17 (b), the output command steps down and the operating frequency increases from

the minimum to the maximum. The SR on-time also tracks the rectifier current conduction and maintains

the safe margin.

3.5 Summary
This chapter introduces a Volt-Second Product (VSP) based SR control method for LLC resonant converters

in high-power, high-current battery charging applications. The VSP SR employs the SR drain-source voltage

during the turn-off phase, which is large-magnitude and noise-tolerant in contrast to the drain-source voltage

in the turn-on phase (vds.on ). The VSP SR is implemented digitally with only a few external logic gates.

It covers both below- and above-resonance operations, which is essential to battery charging applications.

Compared with the conventional vds.on based adaptive SR, the VSP SR reduces the on-time error. In the

below-resonance region, the VSP SR turns on the switch properly without any reverse current, which reduces

the loss by 3%. In the above-resonance region, the VSP SR is independent of the voltage drop on the stray

inductance and hence reduces the on-time error by 64%. In transient response, the VSP SR algorithm

actively adjusts the SR on-time to maintain a safe operation margin, which prevents potential reverse current

or cross-conduction. Therefore, the VSP SR offers a simple, noise-tolerant and effective solution to LLC SR

in battery charging applications.

Since Chapter 2 compares RCV SR with vds.on based non-adaptive SR and this chapter discusses the

comparison between VSP SR and vds.on based adaptive SR, it is worthwhile to summarize them. Table 3.2

compares the SR methods in terms of noise tolerance, operating range, circuit complexity, and SR on-time

error. The vds.on based non-adaptive SR is greatly affected by the noise across the parasitic components, and

thus the SR on-time error is the largest among the four, reducing the suitable operating range. The vds.on

Table 3.2: Comparisons of the proposed SR with vds.on based SR methods

Noise Operating Circuit On-Time

Category Subgroup
Tolerance Range Complexity Error
non-adaptive low medium low large
vds.on sensing
adaptive medium wide low medium
RCV SR high wide high small
proposed
VSP SR high wide medium small

65
based adaptive SR is more noise-tolerant than the non-adaptive, although the on-time error caused by the

parasitic effects remains significant in the above-resonance region. Commercialized integrated circuits (ICs)

for the vds.on based methods are available, and the application circuit is simple due to the highly integrated

circuits. The proposed RCV and VSP SR use discrete components for prototyping, which makes the circuit

appear to be more complex. However, the circuit complexity can be reduced by employing a customized IC.

The proposed RCV SR and VSP SR are both based on large voltage signals, and hence they are insensitive

to the parasitic effects, reducing the on-time error. RCV SR requires a couple of voltage integrators for each

of the SR, which complicates the circuit. VSP SR greatly simplifies the implementation compared with

RCV SR. It has fewer input signals and does not require voltage integrators. Although RCV SR has more

complex circuits, it closely tracks the rectifier current conduction time in transient as well as in steady-state.

Compared with VSP SR, RCV SR is more suitable for applications that continuously operate with dynamic

loads, such as computing products. For EV battery charging applications, where the load changes slowly

over time, VSP SR is simple and effective. Overall, compared with vds.on based methods, both the proposed

RCV SR and VSP SR improve the efficiency by reducing the SR on-time error, which makes them strong

candidates for the next-generation synchronous rectifiers.

66
Chapter 4

Enhanced Small-Signal Modeling of

Charge-Controlled Resonant Converters

While Chapters 2 and 3 covered the efficiency aspect, one major indicator of steady-state performance, this

chapter will discuss the dynamics of resonant converters, particularly resonant converters with charge mode

control. Charge mode control refers to the control of the integration of inductor current in every switching

period of the converter, which equivalently controls the amount of electric charge per switching cycle. The

command of the charge control loop is from the output of the voltage loop controller that controls the output

voltage. In this way, a cascade loop architecture is formed, where the charge feedback is the inner loop and

the voltage feedback is the outer loop. The inner charge loop shapes the plant of the outer voltage loop, and

a well-designed inner loop makes the outer loop easy to achieve higher loop bandwidth.

Although charge mode control has been developed for resonant converters, the existing small-signal

dynamic model for a charge-controlled resonant converter is oversimplified, which leads to prediction errors,

especially in high-frequency regions. This chapter develops a new dynamic model for charge-controlled

resonant converters that improves the prediction of the dynamics, assisting high-bandwidth design. This

chapter uses a CLLC resonant converter as the case study, since this topology is also becoming popular in

battery charging applications, and it has a higher order resonant tank, which is more complex than LLC

converters. In fact, LLC resonant converters can be considered as a special case of CLLC converters, and

the modeling methodology developed for CLLC converters is applicable to LLC converters. This chapter

starts with the open-loop model of a half-bridge CLLC resonant converters, of which the schematic diagram

is shown in Fig. 4.1.

67
 Cr1 Cr2
irec

L1 i1 it n:1 i2 L2
Vg Cf Ro Vo

Lm
Cr1 Cr2
im

V1 V2

Figure 4.1: The schematic diagram of a half-bridge CLLC resonant converter.

4.1 Small-Signal Modeling for Open-Loop CLLC Resonant Converters

For the small-signal modeling of resonant converters, First Harmonic Approximation (FHA) and Extended

Describing Functions (EDF) are broadly-accepted techniques due to the systematic procedures. This section

first reviews the open-loop EDF model of a CLLC resonant converter, which is used for developing the

charge-control model later.

The study of the small-signal model of resonant converters using EDF focuses on modeling the slowly

time-varying envelope of the resonant current and voltage. The procedure involves 1) Deriving the state

equations of the resonant circuit based on KVL and KCL; 2) Applying harmonic approximation to the

resonant current and voltages and deriving the corresponding envelope terms of the sine and cosine parts;

3) Deriving the EDF of the inverter and rectifier voltages and finding the corresponding envelope terms of

the sine and cosine parts; 4) Taking the results from the second and third steps into the equations defined in

the first step and equating the sine and cosine coefficients respectively, with the new set of state equations

being called modulation equations; 5) Solving for the state variables at the operating point; 6) Perturbing and

linearizing the modulation equations and deriving the small-signal model.

State Equations of the CLLC Resonant Converter

Referring to the AC equivalent circuit shown in Fig. 4.2, a transformer T-mode is applied to facilitate

the analysis. The secondary side components are referred to the primary side. In the equivalent circuit, vab

and vcd represents the AC component of the inverter and rectifier voltage, respectively. For a half-bridge

inverter, vab is a square wave with amplitude ±Vin /2, and for a half-bridge rectifier, vcd is a square wave with

amplitude ±Vo /2. By KVL,

di1 dim
vab = L1 + Lm + v1 , (4.1)
dt dt

and
dim di1 dim
Lm = n2 L2 − n2 L2 + vt + vcd , (4.2)
dt dt dt

68
 L1 i1 it n2L2 i2 n

im
vab Lm vcd

C1 C2 n2

v1 nv2

Figure 4.2: The AC equivalent circuit of the resonant tank using a transformer T-model.

where vt is nv2 . Taking (4.2) into (4.1) yields


 di1 = Lm +L2′ Lm +L2′ Lm
− LLmµ vcd

Lµ vab − Lµ v1 − Lµ vt

dt
(4.3)
 dim =
 L2′ L2′ L1 L1
Lµ vab − Lµ v1 + Lµ vt + Lµ vcd ,

dt

where L2′ is n2 L2 , and Lµ is defined as

Lµ := L1 Lm + L1 L2′ + L2′ Lm . (4.4)

By KCL,
dv1
i1 = C1 , (4.5)
dt

and
i2 C2 dvt
i1 − im = = 2 . (4.6)
n n dt

In the output filter stage,

vo dvo
irec − = Cf . (4.7)
Ro dt

Rearranging (4.5) to (4.7) yields 

 dv1 i1
dt = C1






dvt it , (4.8)
 dt = C2′



 dvo = 1 i pk − vo


dt π Cf RoC f

where C2′ is C2 /n2 , it is i2 /n, and i pk is the peak of i2 .

Applying Harmonic Approximation to the Resonant Voltages and Currents

The First Harmonic Approximation (FHA) is applied in this case. The first harmonic of i1 and im are

69
represented as the sum of their sine and cosine components, and the general form is represented as follows:


i1 = i1s sin ωst + i1c cos ωst

(4.9)

im = ims sin ωst + imc cos ωst


Taking the derivatives of (4.9) yields


 di1 = ( di1s − ωs i1c ) sin ωst + ( di1c + ωs i1s ) cos ωst


dt dt dt
(4.10)
 dim = ( dims − ωs imc ) sin ωst + ( dimc + ωs ims ) cos ωst


dt dt dt

Also, the secondary resonant current i2 is dependent on i1 and im , which is equal to n(i1 − im ) or nit . Hence,

the FHA of it is

it = its sin ωst + itc cos ωst = (i1s − ims ) sin ωst + (i1c − imc ) cos ωst. (4.11)

Note that i1s , i1c , ims , imc , its , and itc are functions of time. Since its and itc are the sine and cosine components

of it , the peak of which is i pk /n,

i pk
q
= 2 + i2 ;
its (4.12)
tc
n

this equation associates its and itc with i pk .

Similarly, the first harmonic of v1 and vt is



v1 = v1s sin ωst + v1c cos ωst

(4.13)

vt = vts sin ωst + vtc cos ωst


Taking the derivatives of (4.13) yields


 dv1 = ( dv1s − ωs v1c ) sin ωst + ( dv1c + ωs v1s ) cos ωst


dt dt dt
(4.14)
 dvt = ( dvts − ωs vtc ) sin ωst + ( dvtc + ωs vts ) cos ωst


dt dt dt

Applying Harmonic Approximation to the Inverter and Rectifier Voltages

Until now, each item in the KVL and KCL equation (4.3) and (4.8) can be replaced by the corresponding

first harmonic, except vab and vcd . The first harmonic of the inverter voltage vab is

2
vab1 = Vg sin ωst (4.15)
π

70
Note that the cosine part of vab1 is zero because vab is selected as the reference. As for the rectifier voltage vcd

(referred to the primary side), considering that the transformer is continuously coupled, vcd is nvo /2 when i1

is larger than im and −nvo /2 when i1 is less than im , and thus vcd is expressed as

nvo
vcd = sign(i1 − im ) . (4.16)
2

The first harmonic of vcd is derived as

2nvo nits nitc

vcd1 = ( sin ωst + cos ωst) (4.17)
π Ipk Ipk

Deriving the State Equations of the Modulation Terms

The modulation terms are the coefficients of sin ωst and cos ωst in the previous step. Those terms mod-

ulates the amplitude of the first harmonic components sin ωst and cos ωst, and change in lower frequency

than ωs . The small-signal modeling of the resonant converter focuses on the dynamics of the modulation

terms because the dynamics of the system is determined by the dynamics of the amplitude of the voltages

and currents.

To establish the state equations of the modulation terms, replace i1 , im , it , v1 , vt , vab , and vcd in (4.3)

and (4.8) with the corresponding FHA in (4.9) – (4.11), (4.13) – (4.15), and (4.17). And then, equate the

modulation terms of the sin ωst and cos ωst, respectively. The resultant state equations are

′ Lm +L2′
 di1s 2 Lm +L2 Lm 2 Lm n2 (i1s −ims )
dt = ωs i1c + π Lµ vg − Lµ v1s − Lµ vts − π Lµ vo



 i pk


Lm +L2′ 2 Lm n2 (i1c −imc )

 di1c Lm



 dt = −ω s i 1s − L µ
v1c − L µ
vtc − π Lµ i pk vo


′ L2′ 2 L1 n2 (i1s −ims )

 dims 2 L2 L1
dt = ωs imc + π Lµ vg − Lµ v1s + Lµ vts + π Lµ vo



 i pk


L2′ 2 L1 n2 (i1c −imc )

 dimc L1



 dt = −ω s i ms − L µ
v 1c + L µ
vtc + π Lµ i pk vo


dv1s i1s (4.18)
 dt = ωs v1c + C1



dv1c
= −ωs v1s + Ci1c1





 dt


dvts i1s ims

dt = ωs vtc + C2′ − C2′







dvtc i1c imc

dt = −ωs vts + C2′ − C2′







 dvo = 1 i pk − vo


dt π Cf Ro C f

This set of differential equations can be represented in a matrix form in the following large-signal and small-

71
signal state equations.

Solving for the State Variables at the Operating Point

Based on the differential equations (4.18), to solve for state variables at the operating point, replacing

each state variable x with X and set dX/dt to be zero. The steady-state equations can be simplified by

replacing the output voltage (Vo ) and the first harmonic component of secondary-side resonant peak current

(Ipk ) with the equivalent output load resistance. The equivalent load resistance is derived based on FHA as

follows. In steady sate, the RMS (root-mean square) value of Vcd1 is

√
2
Vcd1,rms = Vo . (4.19)
π

The output voltage (Vo ) is the product of the average output current (Io ) and output load resistor (Ro ), and Io

is associated with Ipk by taking the average value:

1
Io = Ipk Kbr , (4.20)
π

where Kbr is the coefficient that represents the effect of transformer decoupling time on the magnitude of the

envelope terms [85]. It equals one if the transformer is continuously coupled and is less than one if there are

decoupling periods in a switching cycle:



1
 Ωs ≥ Ωo
Kbr = , (4.21)

sin πΩs
 Ωs < Ωo
2Ωo

where Ωs is the steady-state switching frequency, and Ωo is the resonant frequency. Therefore, the RMS

value of the first harmonic component of the secondary current is represented as

π
I2,rms = √ Io . (4.22)
2Kbr

According to (4.19) and (4.22), the equivalent load resistance Re is derived by dividing Vcd1,rms by I2,rms ,

which results in
2n2 Ro Kbr
Re = . (4.23)
π2

Note that Re is already reflected to the primary side, considering the turns ratio n. Thus, the term Vo /Ipk is

72
replaced by
Vo πRe
= 2. (4.24)
Ipk 2n

As a result, the steady-state equation is downsized to eight independent equations. Define Xst as the state

vector in the steady state:

 T
Xst = I1s I1c Ims Imc V1s V1c Vts Vtc , (4.25)

where each of the state variables represents the steady-state peak value. When the transformer is contin-

uously coupled, the peak values are not changed. If there are decoupling periods in one switching cycle,

depending on the steady-state switching frequency (Ωs ) and the resonant frequency (Ωo ), the average value

is approximately sin πΩs

2Ωo times the peak value. Therefore, the steady-state equation is expressed as

Kbr Ast Xst = Bst , (4.26)

where the input matrix is

 T
B st = 2 ′
π Vg (Lm + L2 ) 0 2 ′
π Vg L2 0 0 0 0 0 , (4.27)

and the state matrix is defined as

 
 Re Lm −Ωs Lµ −Re Lm 0 Lm + L2′ 0 Lm 0
 
ΩL
 s µ Re Lm 0 −Re Lm 0 Lm + L2′ 0 Lm 

 
−Re L1 −Ωs Lµ L2′ −L1
 
0 Re L1 0 0
 
 
 0 Re L1 −Ωs Lµ −Re L1 0 −L2′ 0 L1 
Ast =  . (4.28)
 
 1/C1 0 0 0 0 0 0
 
Ωs
 
 
 0
 1/C1 0 0 −Ωs 0 0 0
 
 1/C′ 0 −1/C2′ 0 0 0 0 Ωs 
 2 
 
0 1/C2′ 0 −1/C2′ 0 0 −Ωs 0

The peak values of the state variables: I1s , I1c , Ims , Imc , V1s , V1c , Vts , and Vtc , can be derived by solving

(4.26) for Xst . The peak current in the secondary side (Ipk ) is solved by

q
Ipk = (I1s − Ims )2 + (I1c − Imc )2 , (4.29)

73
which leads to the solution of the average output current Io following (4.20). Finally, the steady-state output

voltage Vo is derived by multiplying Io with Ro :

Vo = Io Ro (4.30)

As a result, the voltage and current at the operating point can be solved with the given system parameters

along with the input voltage, operating frequency, and output load. This information is then applied to derive

the small-signal model.

Deriving the Small-Signal Model

The linearization of (4.18) is achieved by taking partial derivatives of each term with respect to each state

variable. For example, linearizing the term ωs i1c yields:

∂ ωs i1c ∂ ωs i1c ˆ ˆ,
d(ωs i1c ) = ω̂s + i1c = I1c ω̂s + Ωs i1c (4.31)
∂ ωs ∂ i1c

and
2n2 vo i1s − ims I2 ˆ I2 ˆ Its Itc ˆ Its Itc ˆ Re Its
d( ) = n2 Re ( 2tc i1s − 2tc ims − 2 i1c + 2 imc )+ vˆo (4.32)
π i pk Ipk Ipk Ipk Ipk Vo

As a result, the linearized (4.18) can be represented in a matrix form

ẋ = Aol x + Bol u
(4.33)
y = Cvo x,

where the input, output and state variables are defined as

 T
ˆ i1c
x = i1s ˆ ims
ˆ imc
ˆ vˆ1s vˆ1c vˆts vˆtc vˆo
 T
u = ω̂s vˆg (4.34)

y = vˆo .

74
The state matrix is defined as

Aol =
 
−Krm Itc Krm Itc −(Lm +L2′ ) −Lm −Krs Lm
 Its Ωs + Krm Its −Krm Lµ 0 Lµ 0 Lµ 
−(Lm +L2′ )
 
−Ω + K −Krm Its Krm Its −Lm −Krc Lm 
 s rm Itc −Krm Itc 0 Lµ 0 Lµ Lµ 
 
 Krl Itc −Krl Itc L2′ L1 Krs L1
−Krl Ωs + Krl 0 0


 Its Its Lµ Lµ Lµ 


 −Krl Krl Its −Krl Its −L2′ L1 Krc L1

Itc −Ωs + Krl Itc 0 Lµ 0 Lµ Lµ




 (4.35)
1

 C1 0 0 0 0 Ωs 0 0 0 

 
1
0 0 0 −Ωs 0 0 0 0
 

 C1 

1 −1
 

 C2′ 0 C2′ 0 0 0 0 Ωs 0 

 
1 −1

 0 C2′ 0 C2′ 0 0 −Ωs 0 0 

 
n2 Its n2 Itc −n2 Its −n2 Itc −1
πI pkC f πI pkC f πI pkC f πI pkC f 0 0 0 0 Ro C f

where
n2 Lm Its Itc Re Krm L1
Krm = 2
, Krl = (4.36)
Lµ Ipk Lm

Krm Lµ Rt Itc Rt Its

Rt = , Rs = , Rc = , (4.37)
Lm Its Itc
Its Re Itc Re
Krs = , Krc = . (4.38)
Vo Vo

The input matrix is defined as

 
Bol = Bωs Bvg , (4.39)

where
 T
Bωs = I1c −I1s Imc −Ims V1c −V1s Vtc −Vts 0 , (4.40)

 T
2(Lm +L2′ ) 2L2′
Bvg = πLµ 0 πLµ 0 0 0 0 0 0 . (4.41)

For the study of control-to-output transfer function, the output matrix is selected as

 
Cvo = 0 0 0 0 0 0 0 0 1 . (4.42)

As a result, the transfer function of an open-loop, direct frequency-controlled CLLC resonant converter is

75
 n2Its n2Itc
L1I1c ws WsL1 i1c v1s its L2’ Itc ws WsL2’ itc vts i i
L2’ p Ipk ts p Ipk tc
C1 Lm ims C2’ Rs
vg i1s L1 Cf Ro
p C1 V 1c ws C2’ Vtc ws
i1s LmImcws
Rtitc vo
2vg Ws C1v1c C2’ Wsvtc
p WsLmimc
Krsvo
Krcvo
Ws C1v1s WsLmims C2’ Wsvts
Rtits
L1 C1 V1s ws LmImsws C2’ Vts ws
i1c C1 imc C2’ Rc
Lm

L1 I1s ws WsL1 i1s v1c itc L2’ L2’ Its ws WsL2’ its vtc

Figure 4.3: Extended Describing Functions (EDF) model of an open-loop, direct frequency-controlled,
half-bridge CLLC resonant converter. Input current is proportional to the sine component of the
primary resonant current, which forms the basis of the proposed enhanced charge-control model.

derived:
vˆo
Gv f (s) := = Cvo (sI − Aol )−1 Bωs . (4.43)
ω̂s

The small-signal equivalent circuit of an open-loop half-bridge CLLC converter can be obtained by ana-

lyzing the linearized modulation equations (4.33). The result is shown in Fig. 4.3, where the inverter stage,

the resonant tank, and the rectifier stage are included. The resonant tank model shows that each of the

resonant inductor and capacitor is composed of three elements. The EDF model of a resonant inductor is

composed of the inductor in series with two voltage sources; one is coupled from the switching frequency,

and the other is coupled from the sine or cosine part of the inductor current. As for the EDF model of a

resonant capacitor, it consists of the capacitor and two current sources in parallel; one is coupled from the

switching frequency, and the other is coupled from the sine or cosine part of the capacitor voltage. The in-

verter stage model shows that the input current is proportional to the sine component of the primary resonant

current (i1s ). This information is essential to the proposed charge-control model that will be discussed in

Section 4.2.

4.2 Small-Signal Modeling of Charge-Controlled Resonant Converters

The open-loop small signal model of the half-bridge CLLC resonant converter is derived following the

procedure from the previous section. The next step is to derived the charge-controlled model by closing the

charge loop. Charge control for resonant converters has been discussed in [75–79], however, the small signal

76
 ws vo ws vo
Converter Converter
Model irec Model i1s

irec equivalent feedback: equivalent feedback:

secondary current sine part of i1
overlooks the includes the
vHS Cr1 Cr2
effect of im effect of im
Vg L1 i t n:1 i2
Cf Ro Conventional Proposed
vch vch
vLS Lm im L2 Vo Charge Model Charge Model
i1
Cr1 (b)
Cr2
V1 V2 conventional
proposed
measured
Charge Loop Voltage Loop vo ws 100 ws 10 ws
vch
successfully predicts
V1 Vch votlage loop the response
Latch vsaw
controller Vref prediction error

vo

charge control circuit vch

prediction
successfully predicts error
the response
(a) (c)

Figure 4.4: a) Schematic diagram of a CLLC resonant converter with charge mode control. b) Block
diagram of the charge loop: the conventional model approximates the charge loop by using irec ,
overlooking the effect of magnetizing current (im ). c) Conceptual illustration of the frequency
response of the charge loop: the proposed model removes the prediction error, which is useful for
high-bandwidth design.

model developed since then, including [97, 98] works only for the low-frequency range. As the advancement

in high-performance resonant converter accelerates, it is worthwhile to explore the model that predicts the

behavior in the mid- to high-frequency range as well.

Charge mode control regulates the charges in each switching cycle. Fundamentally, charges are the

integration of current. In the context of resonant converters, it refers to the integration of the primary-

side resonant current. Regarding the implementation of the charge sensing circuit, the mainstream charge

controllers either use a resistive current sensor and a resettable integrator, or directly sense the resonant

capacitor voltage since the voltage is the integration of resonant current in a series resonant tank. In this

work, a commercial charge controller using the resonant capacitor voltage is employed for the analysis of

the small-signal modeling. As shown in Fig. 4.4 (a), the charge controller senses the resonant capacitor

voltage V1 and compares it with the charge command Vch to control the switches. The sawtooth signal vsaw

is for slope compensation, which will be discussed later.

The charge command Vch limits the charges accumulated in every half-switching cycle. The switch turns

off when V1 reaches Vch , and it initiates the other complementary switch. The charge command comes from

77
the voltage loop controller; with the inner charge loop and outer voltage loop, the converter is controlled

by a dual loop, cascade control system. The existence of this inner charge loop changes the open-loop

model derived in Section 4.1, which changes the design of the voltage loop controller. The conventional

modeling method concludes an equivalent feedback loop from irec , as shown in Fig. 4.4 (b), which is counter

intuitive. The proposed model, on the other hand, models the charge feedback as i1s , the sine component of

the resonant current, which is related to the actual feedback loop in the schematic diagram. Figure 4.4 (c)

illustrates a conceptual presentation of typical frequency response with charge control. The conventional

model deviates from the measured response from the mid- to high-frequency range, whereas the proposed

model corresponds well; the actual response will be discussed later.

This section investigates the modeling of the charge controlled resonant converter, with the focus on the

control-to-output (Vch to Vo ) transfer function. First, a review of the conventional model is given, followed

by the explanation of the proposed enhanced model.

4.2.1 Conventional Charge Mode Model

The conventional methodology for modeling charge-controlled resonant converters [77, 98] is based on en-

ergy balance of the system input and output. The procedure includes: 1) Defining system energy conservation

by equalizing the input and output power; 2) Replacing the average input current with the charge control in-

put and switching frequency; 3) Replacing the output current using the output voltage and impedance; 4)

Perturbing and linearizing the equation to derive the small-signal model.

Following this procedure, the transfer function from the control input to output voltage yields

vˆo KA Gv f (s)
= , (4.44)
vˆch 1 + KA KB Gv f (s)Gy (s)

where KA and KB are constants determined by the operating point, and Gy (s) is a transfer function related

to the output admittance. The transfer function Gv f (s) in [77] is replaced with the DC gain of the transfer

function, whereas in [98], the complete frequency-to-output transfer function is applied. The block diagram

that interprets the conventional model (4.44) is shown in Fig. 4.5. In this block diagram, an equivalent
ˆ represents the AC component of the rectifier current.
feedback loop is formed from the output, where irec

This equivalent charge feedback loop can be considered as an estimation of the actual charge feedback

signal, that is, the resonant capacitor voltage. However, it is not the full representation because the amplitude

of irec is proportional to it , which excludes im . According to Fig. 4.4 (a), the charge controller senses V1 as

the feedback signal, which is the integration of i1 , containing the information of im . Therefore, the effect of

78
 vch ws vo
KA Gvf (s)

equivalent charge
feedback loop

irec
KB Gy(s)

conventional charge model

Figure 4.5: Block diagram of the conventional charge model. The equivalent feedback loop from the
output does not fully represent the actual charge loop.

the magnetizing inductor current is overlooked. As a result, prediction errors occur in the frequency domain,

which will be presented in Section 4.3.

4.2.2 Enhanced Charge Mode Model

Since the essence of charge control is to regulate the accumulated resonant current, which is equal to the

charge stored in the resonant capacitor in every half switching cycle, the small-signal modeling methodol-

ogy proposed in this work focuses on linearizing the dynamics of these two parts. To simplify the problem,

this section first considers Bang-Bang Charge Control (BBCC), which has no slope compensation, and sec-

ond Hybrid-Hysteretic Control (HHC), which includes slope compensation. As illustrated in Fig. 4.6, the

resonant capacitor energy stored from t0 to t1 is

Katt C1 ∆v1a = 2Katt C1 vch (4.45)

where v1a is the attenuated resonant capacitor voltage; Katt v1a equals v1 . In a practical implementation, the

voltage sensing gain serves as the attenuation. The charge stored in C1 , or the accumulated i1 in each half

cycle, is controlled by ±vch . Referring to Fig. 4.6, let t0 be zero; the charge stored in C1 from zero to t equals

the resonant current accumulated in the same time interval:

Z t
2Katt C1 vch = i1 (t)dt (4.46)
0

Based on harmonic approximation, the resonant current is defined as

i1 (t) := i1pk sin(ωst + φ ), (4.47)

79
 i1pk
i1

vch Vch vch

v1a Vch
vch
vch

Ts / 2 Ts / 2 + t
vHS Ws Ws+ ws
t0 t1 t2 t3 t

Figure 4.6: Timing sequence diagram for charge control without slope compensation along with the
perturbation applied for linearization.

so (4.46) leads to
2Katt C1 vch =
−i1pk (4.48)
[cos(ωst) cos φ − sin(ωst) sin φ − cos φ ] ,
ωs
which is the nonlinear equation of charge control.

As the sine and cosine components of the resonant current intrinsically determines the phase angle φ ,

(4.48) can be transformed for linearization. Applying EDF to i1 (t) yields

i1 (t) = i1s sin(ωst) + i1c cos(ωst), (4.49)

of which the relationship in time domain is illustrated in Fig. 4.7 (a). In the phasor diagram, as Fig. 4.7 (b)

shows,
iis iic
cos φ = , sin φ = , (4.50)
i1pk i1pk

and thus,

2Katt C1 vch ωs = i1s [1 − cos(ωst)] + i1c sin(ωst). (4.51)

Next, to linearize (4.51), apply Taylor series expansion and neglect the higher order terms, which yields

2Katt C1 (Vch Ωs + Ωs vˆch +Vch ω̂s ) =

  (4.52)
ˆ − I1c T s
2I1s + 2i1s ω̂s + Ωstˆ .
2

Figure 4.6 shows the operating points (Vch , Ωs , Ts /2) and the perturbation of each variable (vˆch , ω̂s , tˆ). The

80
 i1 i1pk ( sin wst f ) Im
i1ssin wst
i1s Re
f
t
i1c coswst
i1c
f i1pk

(a) (b)

Figure 4.7: Relationship between the sine and cosine components of the resonant current using Ex-
tended Describing Functions (EDF) in: a) time domain and b) complex plane.

perturbations tˆ and ω̂s are interchangeable:

−Ts ω̂s
tˆ = . (4.53)
2Ωs

As a result, the cosine term I1c is eliminated, and the large-signal part of (4.52) is

I1s
Ωs = , (4.54)
MVch

where M is the constant Katt C1 . The small-signal part is

1 ˆ I1s
ω̂s = i1s − vˆ .
2 ch (4.55)
MVch MVch

Starting with the definition of the charge in the resonant tank, the small-signal modeling procedure in-

corporates EDF, phasor analysis, and linearization to derive the relationship between the charge command

and the frequency; these results are useful for both large and small-signal analyses of a charge-controlled

resonant converter. Taking the computed result of I1s from (4.26) into (4.54) yields the charge command

Vch at the designated operating point. This is essential for engineers to design and evaluate the controller in

open-loop tests.

Based on this analysis, the constructed charge-control model is related to frequency ω̂s , the sine compo-
ˆ , and the control input vˆch . To illustrate the block diagram of the proposed
nent of the resonant current i1s
ˆ:
model, first define the open-loop transfer function from ω̂s to i1s

ˆ
i1s
Gi1s f (s) := = Ci1s (sI − Aol )−1 Bωs , (4.56)
ω̂s

81
 open-loop
converter model vo
Gvf (s)
using EDF

vch ws i1s
Fm Gi1sf (s)

Ri

(a)

vch ws i1s vo
Fm Gi1sf (s) Gvi1s(s)

proposed charge model

decoupled
Ri converter model

charge control-to-output model Gvc (s)

(b)

Figure 4.8: Proposed block diagram of the small-signal model of a charge-controlled resonant con-
verter: a) direct b) cascade form. The feedback signal is the sine component of the primary
resonant current.

where
 
Ci1s = 1 0 0 0 0 0 0 0 0 . (4.57)

Combining with the converter open loop model derived using EDF, the block diagram of the proposed model

is highlighted in Fig. 4.8 (a), where

I1s
Fm = − 2
,
MVch
(4.58)
Vch
Ri = .
I1s
Generally, a system with a nested control loop is shown in a cascade form, as Fig. 4.8 (b) illustrates,
ˆ to vˆo transfer function derived from Gv f (s)/Gi1s f (s). The full closed-
where Gvi1s (s) is the open-loop i1s

loop system model is completed by closing the vˆo feedback loop with an outer-loop controller that gives vˆch

command. The outer loop is not the focus of this paper; however, it will be shown in the next section for

validation purposes.

The small-signal equation (4.55) and the proposed charge control block diagram reveal that the charge

controller is essentially a proportional controller (P-controller), where the gain is defined by the modulation

gain (Fm ). Furthermore, the equivalent feedback signal is the sine component of the resonant current, even

though the charge control loop ostensibly feeds back the resonant capacitor voltage or the integrated resonant

current. The physical meaning of the sine component of the primary resonant current, based on the analysis

82
in Section 4.1, is a current that is proportional to the average input current. The derived block diagram of

the proposed charge-control model is therefore consistent with the essence of charge control: to control the

average input current.

Having established the model for charge control without slope compensation, also known as Bang-Bang

Charge Control (BBCC), we can go one step further by adding slope compensation. In this case, also known

as the Hybrid-Hysteretic Control (HHC), a sawtooth signal vsaw is added to the sensed resonant capacitor

voltage, or, equivalently, subtracted from the charge command ±vch . As indicated in Fig. 4.9, the slope of

the sawtooth signal is Se , so (4.51) is rewritten as

 
Ts
2Katt C1 ωs vch + Se ( − t)
2
(4.59)
= i1s [1 − cos(ωst)] + i1c sin(ωst).

Following the same linearization procedure, the large-signal equation is

I1s πSe
Ωs = + , (4.60)
MVch 2Vch

and the small-signal equation is

 
1 ˆ I1s πSe
ω̂s = i1s − 2
+ 2 vˆch . (4.61)
MVch MVch 2Vch

Therefore, with slope compensation,

 
I1s πSe
Fm = − 2
+ 2 ,
MVch 2Vch
(4.62)
Vch
Ri = .
I1s + πSe M/2

Comparing (4.62) with (4.58), Se provides the ability to adjust the charge loop gain. Without slope

compensation, as in BBCC, the modulation gain and the current sensing gain are basically determined by

the system. In (4.58), Vch and I1s depend on the system operating conditions, and the gain M is determined

by the attenuation of the resonant capacitor voltage sensing. Therefore, the charge controller design for

83
 vch
vch vsaw
vch Se
v1a Vch Vch vch

Se
vch
vch vsaw
Se
vsaw
Se
Ts 2 Ts 2 t
vHS Ws Ws+ ws

t0 t1 t2 t3 t

Figure 4.9: Timing sequence diagram for charge control with slope compensation along with the per-
turbation applied for linearization.

BBCC is almost fixed by the system parameters. With slope compensation, as in HHC, Se becomes the

parameter to adjust the charge controller. When Se equals zero, (4.54) − (4.58) are equivalent to (4.60) −

(4.62), respectively, so the former can be considered as a special case of the latter. When Se increases such

that Se ≫ 2I1s /πM, the fixed slope compensation (vsaw ) dominates the switching frequency, and the effect

of the charge control feedback (i1s ) is negligible. Hence, the controller becomes direct frequency control as

voltage mode. In this case, Fm is −Ωs /Vch , and the operating frequency Ωs is approximately πSe /2Vch . By

rearranging (4.60), it is easily derived that in a half switching cycle, the current-sense voltage is I1s /MΩs ,

while the slope compensation magnitude is πSe /2Ωs ; the ratio of these two components indicates whether

the converter will tend to operate in voltage mode or charge mode.

The full small-signal model considering the converter model can be derived by replacing ω̂s in (4.33)

with (4.61). As a result, the state-space equations for a charge-controlled resonant converter is defined as

ẋ = Ah x + Bh uh
(4.63)
y = Cvo x.

The state and the output vectors remain the same as (4.33), while the input vector becomes

 
uh = vˆch vˆg . (4.64)

84
The new state matrix derived as

Ah = Ah0 + Aol (4.65)

where  
 −I1c 0 0 · · · 0 0
 
 I
 1s 0 0 
 
−Imc
 

 
 
 Ims 
 
 .. .. .. 
Ah0 = Fm Ri 
−V1c . . ., (4.66)
 
 V1s
 

 
 
 −Vtc 
 
 
 V
 ts 0 0 
 
0 0 0 ··· 0 0

and the new input matrix is defined as

 
Bh = Bh0 Bvg , (4.67)

where

Bh0 = Fm Bωs (4.68)

Subsequently, the charge control-to-output transfer function for a charge-controlled resonant converter is

expressed as
vˆo
Gvc (s) := = Cvo (sI − Ah )−1 Bh0 . (4.69)
vˆch

ˆ feedback loop modifies the resonant tank model, while leaving the inverter and
The presence of the i1s

rectifier stages unaffected, remaining the same as the open-loop model. The equivalent circuit of the resonant

tank is illustrated in Fig. 4.10. With charge control, an equivalent resistor Rch appears in series with L1 and C1 ,

which implies that a damper is generated in the resonant circuit. The dependent voltage and current sources

containing the Fm or Ri coefficient are affected by Se if slope compensation is implemented. The lump

effects of introducing Rch and Fm -Ri dependent sources are difficult to see from the equivalent circuit model

alone but can be easily understood by plotting the frequency response of Gvc (s), which will be analyzed and

validated in the following Section 4.3.

Although charge control with and without slope compensation, such as BBCC and HHC, has been pre-

sented before, the exact model of the feedback loop was not discovered. So far, a new mathematical model of

85
 WsL1 i1c v1s its Fm L2’ Itc vch WsL2’ itc vts
FmRiL1 I1c L2’

Rch C1 C2’
FmL1 I1c vch Lm ims FmRiL2’ Itc i1s Rs
L1 FmRiC1V1ci1s FmRi C2’ Vtci1s
FmRiLmImc i1s
i1s
FmC1V1cvch Fm C2’ Vtc vch Rtitc
2vg FmLmImcvch
p
WsC1v1c WsC2’ vtc
WsLmimc Krsvo

WsLmims Krcvo
i1c WsC1v1s WsC2’ vts

L1 FmLmImsvch
FmC1V1svch FmC2’ Vtsvch Rtits

FmRiLmIms i1s
FmRi C1V1si1s FmRiC2’ Vtsi1s
FmRiL2’ Its i1s Rc
C1 Lm imc C2’

FmL1 I1s vch ( Ws FmRiI1s( L1 i1s v1c itc L2’ FmL2’ Itsvch WsL2’ its vtc

Figure 4.10: Proposed equivalent small-signal circuit of a charge-controlled CLLC converter: focused
on the resonant tank that is affected by the charge loop.

charge control is derived using EDF, phasor analysis, and linearization, and the full equivalent small-signal

circuit is proposed.

4.2.3 LLC Resonant Converters

In the case of LLC resonant converters, for example, the half-bridge center-tapped LLC resonant converter

shown in Fig. 2.1, the same modeling procedure can be applied with some adjustments in the coefficients.

First, considering that for a center-tapped transformer, the reflected output voltage is nVo instead of nVo /2.

Second, in the differential equation (4.18), since the LLC resonant converter does not have the secondary-

side resonant elements, L2 and C2 , the parameter L2′ and the voltage across C2 are set to be zero. As a result,

(4.18) is rewritten as:

86
 
 di1s 2 1 1 4 1 n2 (i1s −ims )
dt = ωs i1c + π L1 vg − L1 v1s − π L1 vo



 i pk


4 1 n2 (i1c −imc )

 di1c 1
dt = −ωs i1s − L1 v1c − π L1 vo



 i pk


4 1 n2 (i1s −ims )

 dims



 dt = ω s i mc + π Lm i pk vo


dimc 4 1 n2 (i1c −imc ) (4.70)
 dt = −ωs ims + π Lm i pk vo



 dv1s i1s
 dt = ωs v1c + C1






dv1c i1c

dt = −ωs v1s + C1







 dvo = 2 i pk − vo


dt π Cf Ro C f

It is clear that (4.70) shares the same form as (4.18) with reduced size (L2 and C2 eliminated). The

coefficients of vo and i pk are doubled due to the center-tapped configuration. Therefore, from the modeling

point of view, LLC converter is a special case of a CLLC resonant converter.

Following (4.70), the state vector in the steady state is defined as:

 T
Xst = I1s I1c Ims Imc V1s V1c . (4.71)

Then, Xst can be derived by solving (4.26) with the steady-state input and state matrices for LLC converters,

defined as
 T
st
B = 2
π Vg Lm 0 0 0 0 0 , (4.72)

 
 Re −Ωs L1 −Re 0 1 0
 
Ω L
 s 1 Re 0 −Re 0 1 
 
 −Re 0 Re −Ωs Lm 0 0
 
Ast =  . (4.73)
 
 0
 R e −Ω L
s m −R e 0 0 

 
 1/C 0 0 0 0 Ωs 
 1 
 
0 1/C1 0 0 −Ωs 0

The equivalent resistor Re for a center-tapped rectifier is

8n2 Ro Kbr
Re = . (4.74)
π2

It is derived from the term 4n2 vo /(πi pk ) in (4.70), where Ipk is related with Io with a coefficient 2Kbr /π for

87
a center-tapped rectifier:

2 2nKbr
q
Io = Ipk Kbr = (I1s − Ims )2 + (I1c − Imc )2 , (4.75)
π π

For the small-signal state equations, similarly, it can be solved by linearizing (4.70) or simply apply-

ing zero L2 , vts , and vtc in the small-signal state equations of the CLLC converter. For the LLC resonant

converter, (4.76) is redefined as

 T
ˆ i1c
x = i1s ˆ ims
ˆ imc
ˆ vˆ1s vˆ1c vˆo
 T
u = ω̂s vˆg (4.76)

y = vˆo .

The state matrix is defined as

 
−Krm Itc Krm Itc −1 −Krs
Its Ωs + Krm Its −Krm L1 0 L1 

−Krm Its −1 −Krc 
 Krm Its

−Ωs + Krm −Krm 0
 Itc Itc L1 L1 
 
 Krl Itc −Krl Itc Krs
 Its −Krl Its Ωs + Krl 0 0 Lm


 
Aol =  −Krl Krl Its −Krl Its Krc  (4.77)
−Ωs + Krl

 Itc Itc 0 0 Lm 

 
1

 C1 0 0 0 0 Ωs 0  
 
1
0 0 0 −Ωs 0 0 
 
 C1
 
2n2 Its 2n2 Itc −2n2 Its −2n2 Itc −1
πI pkC f πI pkC f πI pkC f πI pkC f 0 0 Ro C f

where
n2 Its Itc Re Krm L1
Krm = 2
, Krl = (4.78)
L1 Ipk Lm

Rt Itc Rt Its
Rt = Krm L1 , Rs = , Rc = , (4.79)
Its Itc
Its Re Itc Re
Krs = , Krc = . (4.80)
Vo Vo

The input matrix is defined as

 
Bol = Bωs Bvg , (4.81)

88
where
 T
Bωs = I1c −I1s Imc −Ims V1c −V1s 0 , (4.82)

 T
Bvg = 2
πL1 0 0 0 0 0 0 . (4.83)

The results (4.77) – (4.83) are obtained by letting L2 , vts , and vtc in the small-signal state equations of the

CLLC converter (4.35) – (4.41) be zero, which is the same as taking the partial derivatives of (4.70) for

linearization. For the study of control-to-output transfer function, the output matrix is selected as

 
Cvo = 0 0 0 0 0 0 1 , (4.84)

and the transfer function Gv f of an open-loop, direct frequency-controlled LLC resonant converter can be

obtained by applying (4.77), (4.82), and (4.84) to (4.43).

Based on the analysis of charge control loop in Section 4.2.2, the charge loop essentially takes i1s , the

sine component of the primary resonant current as the feedback signal. It means that the loop is closed in the

primary side, and the secondary-side circuit or configurations do not affect the modeling of the charge loop.

Therefore, the conclusions from Section 4.2.2 remains valid for a half-bridge LLC resonant converter. As a

result, the small-signal model of a charge-controlled half-bridge, center-tapped LLC resonant converter can

be derived following the procedure (4.45) – (4.69), with the state matrix for the LLC converter defined as:

Ah = Ah0 + Aol (4.85)

where  
−I 0 0 ··· 0 0
 1c 
 
 I1s 0 0
 
 
−I 
 mc 
 
Ah0 = Fm Ri  Ims , (4.86)
 
 
 .
−V1c .. . .. .
.. 

 
 
 V1s
 

 
0 0 0 ··· 0 0

while Fm and Ri are the same as (4.58) or (4.62) for the case without or with slope compensation. Again,

the matrix Ah0 can also be derived by directly letting the Vts and Vtc terms in (4.66) be zero. Since the small-

89
signal model of the LLC resonant converter is a special case of the CLLC resonant converter, the following

simulation and experiments focus on the verification of the CLLC resonant converter.

4.3 Simulation and Experimental Results

The proposed model for charge-controlled resonant converters is applied to a 400 V / 1 kW CLLC converter

with system parameters as shown in Table 4.1. This converter demonstrates power supply operation with

constant-voltage and constant-current regulation. With operating modes covering both below- and above-

resonance regions, this prototype is used for validation of the proposed model and demonstration of high-

bandwidth design. As shown in Fig. 4.11, the control-to-output frequency response, Gvc (s), of the proposed

model is compared with the conventional model and the circuit simulation as a tool for validation.

For operation above the resonant frequency, shown in Fig. 4.11 (a) and (b), the converter is biased at the

maximum current. The test condition for Fig. 4.11 (a) is the minimum output voltage with the maximum

switching frequency, while the condition for Fig. 4.11 (b) is around the nominal output voltage. The oper-

ating conditions in Fig. 4.11 (c) and (d) respectively correspond to full-load and light-load operation at the

maximum output voltage, where the switching frequencies are below resonance. Across all the operating

conditions, estimation errors appear in the conventional model; the red areas highlight the errors under the

frequency of concern. On the other hand, the proposed model significantly reduces the discrepancies, which

is more practical for control loop analyses.

Table 4.1: System Parameters

Parameter Value
input voltage, Vin 400 V
nominal power, Pout 1 kW
maximum output current, Imax 3.3 A
nominal output voltage, Vnom 330 V
maximum output voltage, Vmax 400 V
switching frequency, fsw 155 − 180 kHz
primary resonant inductance, L1 45 µH
primary resonant capacitor, C1 20 nF
magnetizing inductance, Lm 36 µH
secondary resonant inductance, L2 31 µH
secondary resonant capacitor, C2 29 nF
output capacitor, C f 1 µF
transformer turns ratio, n 1.2
voltage attenuation, Katt 303
slope compensation, Se 0.184 V/µs

90
 40 overestimated 40
gain

Gain [dB]

Gain [dB]
20 20

0 0
Conventional Model Conventional Model
Proposed Model Proposed Model
-20 Simulation -20 Simulation

0 0

Phase [degree]

Phase [degree]
-90 -90

-180 underestimated -180 underestimated

phase drop phase drop
-270 enhanced for control -270 enhanced for control
loop analyses loop analyses
-360 -360
10 3 10 4 10 5 10 3 10 4 10 5
Frequency [Hz] Frequency [Hz]
(a) (b)

40 40 underestimated
gain
Gain [dB]

20 20 Gain [dB]

0 0
Conventional Model Conventional Model
Proposed Model Proposed Model
-20 Simulation -20 Simulation

0 0
Phase [degree]

Phase [degree]

-90 -90

-180 underestimated -180

phase drop
-270 enhanced for -270 enhanced for
control loop analyses control loop analyses
-360 -360
10 3 10 4 10 5 10 3 10 4 10 5
Frequency [Hz] Frequency [Hz]
(c) (d)

Figure 4.11: Comparison of the conventional and proposed analytical models (charge control-to-output
transfer function, Gvc (s)) with circuit simulation results at a) 234 V / 3.3 A; b) 320 V / 3.3 A;
c) 400 V / 2.5 A; d) 400 V / 0.8 A. Estimation errors from the conventional model render it
unsuitable for control-loop analyses especially in a high-bandwidth design. The proposed model
successfully predicts the frequency response across all the conditions.

The frequency response shows that from the mid-frequency range and above, the conventional model

starts to deviate from both the proposed model and the circuit simulation results. This behavior is evident in

the above-resonance conditions seen in Fig. 4.11 (a) and (b). These discrepancies hinder determination of the

crossover frequency and phase margin for the outer loop. In the light-load condition, shown in Fig. 4.11 (d),

the proposed model successfully predicts the resonant peak caused by the complex pole. This resonant peak

is particularly important for a high-bandwidth design as it inevitably constrains the gain margin of the outer

91
 40
10dB
20

Gain [dB]
Se = Se0 10dB
9 Se0
0 27Se0 wc.max wc.max
81Se0 Se = Se0 Se = 27Se0

-20

Phase [degree] -90

105
60
-180

-270

-360
10 2 10 3 10 4 10 5
Frequency [Hz]

Figure 4.12: The effect of slope compensation on the charge loop gain Gvc (s) predicted by the proposed
model assists rapid selection of slope compensation.

loop. Overall, the proposed model successfully predicts the charge loop response, providing an analytical

basis for control loop design.

The proposed analytical model is useful for quickly determining the slope compensation. By plotting the

frequency response with a set of slope compensation Se , the appropriate value can be selected, facilitating

the subsequent design of the outer loop compensation. Performing a parameter sweep is time-consuming for

circuit simulation, whereas by applying the proposed analytical model, it can be done in a few seconds.

Applying the proposed model, Fig. 4.12 shows a set of Se at light-load operation, where the high-

frequency complex pole is the main constraint for a high-bandwidth design. The base slope compensation

Se0 is selected as 0.184 V/µs in this case study. As Se increases, the system becomes closer to a direct

frequency-controlled system as predicted by the model, where the dominant pole and the second pole move

towards each other and tend to form a low-frequency resonant peak: around 6 kHz in this case.

Proper slope compensation design suppresses the high-frequency resonant peak using the second pole.

As shown in Fig. 4.12, selecting 27Se0 can potentially achieve higher bandwidth than the case with Se0 ,

considering a PI compensator for the outer loop. To achieve higher bandwidth for designs with low values of

slope compensation, a high-frequency pole can be considered to suppress the resonant peak. This prediction

cannot be done by the conventional model, as it does not predict the complex pole in the high-frequency

range. The proposed analytical model facilitates rapid selection of an appropriate slope compensation for

the charge loop.

92
 vHS Cr1 Cr2
Vg L1
Cf Ro
vLS Lm L2 vo

Cr1
Cr2 Rcs
Cd1
Cd2 Cp1
Vss Cz2
R1
Charge Rb Cz1 Rv
Controller
UCC
256302
1.2 V R2
0.2 V
R3
Cz3 Ri
Cp2 Cz4

Figure 4.13: Simplified schematic diagram and key components of the test setup for verifying the pro-
posed model using a commercial charge controller.

In order to verify the proposed model, a 400 V / 1 kW prototype is built based on the system parameters

shown in Table 4.1. The charge controller employed is TI UCC256302; this device has slope compensation

for the charge loop, which is suitable for verifying the proposed model. The selection of the operational

amplifiers for closing the outer loop is flexible; ST TSM1052 is applied in this paper as an example. Table 4.2

lists the key component values. Figure 4.13 illustrates the simplified schematic diagram, where the outer

loop is closed with two operational amplifiers for constant voltage and current regulation, respectively. Both

constant voltage and current regulation are included to validate the proposed model at operating modes below

and above resonance.

The charge loop compensation is determined by the capacitive voltage divider formed by Cd1 and Cd2 .

The ratio determines the attenuation of resonant capacitor voltage sensing, Katt , whereas Cd1 and the internal

sourcing current of the device determine the slope compensation. Therefore, Cd1 is selected considering the

Table 4.2: Compensator Parameters

Parameter Value Parameter Value

R1 470 kΩ Cp1 2.2 nF
R2 1.4 kΩ Cp2 5.6 nF
R3 1.8 kΩ Cz1 47 nF
Ri 2.1 kΩ Cz2 100 pF
Rv 4.9 kΩ Cz3 47 nF
Rb 1.3 kΩ Cz4 22 nF
Rcs 60 mΩ Cd1 33 pF
Cd2 10 nF

93
 20

Gain [dB]
0

-20

-40
0

Phase [degree]
-90

-180 400 V/ 0.8 A Experimental

400 V/ 0.8 A Analytical
-270 400 V/ 2.5 A Experimental
400 V/ 2.5 A Analytical
-360
5 x 10 2 10 3 10 4 5 x10 4
Frequency [Hz]
(a)

20
Gain [dB]

-20

-40
0
Phase [degree]

-90
234 V/ 3.3 A Experimental
-180
234 V/ 3.3 A Analytical
320 V/ 3.3 A Experimental
-270
320 V/ 3.3 A Analytical
-360
5 x 10 2 10 3 10 4 5 x10 4
Frequency [Hz]
(b)

Figure 4.14: Analytical and experimental loop frequency response under a) constant-voltage and b)
constant-current regulation; the analytical results using the proposed model closely match the
experimental measurements.

effect of slope compensation shown in Fig. 4.12, and Cd2 is selected following Katt .

The outer loop compensator selection depends on individual design objectives. The proposed model,

however, successfully predicts the frequency response and can be integrated into the design procedure to

achieve high-bandwidth design, improving the dynamic performance. In this work, the compensator for the

constant-voltage regulation is designed based on the frequency response shown in Fig. 4.11 (c) and (d). In

particular, the resonant peak at light load causes a constraint in the gain margin, limiting the bandwidth. The

conventional model fails to account for this behavior.

As a result, the outer loop compensator is designed based on the proposed model, and a PI with lead

compensator is chosen for a high-bandwidth design. Along with the model of the outer loop compensator

and the proposed model for the charge loop, the loop gain is plotted and compared with the experimen-

94
 vo (5V/ Div.)

1 ms

io (1A/ Div.)

(a)

vo (5V/ Div.)

1 ms

io (1A/ Div.)

(b)

Figure 4.15: Experimental transient response under closed-loop regulation: a) 100 % – 80 % load; b)
60 % – 40 % load. The time domain response demonstrates stable operation, as predicted in the
frequency domain.

tal results. Figure 4.14 compares the analytical and experimental frequency response in constant-voltage

and constant-current regulation that respectively correspond to below- and above-resonance operation; the

proposed model successfully predicts the loop gain in both operating modes. Figure 4.15 shows the time

domain transient response of the converter under closed-loop regulation. This result demonstrates that the

closed-loop regulation is stable as predicted by the model. Therefore, the proposed model is practical for the

closed-loop design of a charge-controlled resonant converter.

4.4 Summary
In this chapter, a new, enhanced analytical model for a charge-controlled resonant converter is proposed. To

derive the small-signal model, the integration of the resonant current is first described using the Extended

Describing Functions (EDF). Then, through phasor analyses, the phase angle of the resonant current is

transformed, which enables linearization. The proposed model reveals that the charge controller essentially

controls the sine component of the primary resonant current, which is proportional to the average input

95
current. The proposed charge-control model successfully predicts the frequency response across multiple

operating modes, including the high-frequency complex pole neglected by the conventional model, enabling

a high-bandwidth control loop design. The frequency response is plotted without needing to run a time-

consuming parameter sweep with circuit simulation tools. The loop gain predicted by the proposed model

is validated by experimental results from a 400 V / 1 kW CLLC resonant converter, and the results are

consistent. Lastly, the dynamic load test results demonstrate that the converter under closed-loop regulation

is stable as predicted. Therefore, the proposed analytical model improves the conventional one, providing

practical and rapid frequency-domain evaluation for the design of charge control.

96
Chapter 5

Conclusion

5.1 Conclusions and Contributions

As resonant converters are broadly applied to high-power and high-efficiency designs, there is still room

for improving the efficiency. Synchronous Rectification (SR) is an effective solution to reducing the recti-

fier conduction loss, particularly for high-current power converters. Conventional vds.on based methods are

sensitive to parasitic effects, which results in more SR on-time error and reduced efficiency performance.

In terms of the system dynamic performance, charge-mode control has been established as a replacement of

current-mode control for resonant converters. However, the existing model only works for the low-frequency

range, which opens a window for the research in a more complete model for high-bandwidth design.

This work focuses on the efficiency and dynamics improvement. It proposes two advanced SR solutions

to LLC resonant converters and a small signal modeling methodology for charge-controlled resonant con-

verters. The Resonant Capacitor Voltage based SR (RCV SR) is developed by analyzing the relationships

of the resonant capacitor voltage and the input and output voltages. By comparing the voltage integrations,

the SR on-time can be determined. The RCV SR covers below- and above-resonance regions as well as

light-load and heavy-load conditions.

Next, the Volt-Second Product based SR (VSP) is proposed. The VSP SR algorithm determines the SR

on-time based on the product of rectifier current conduction time and the blocking voltage of SR MOSFETs.

The VSP SR tracks the rectifier current conduction time from the previous cycle in steady-state while main-

taining a safe margin during the transient. Both the RCV and VSP SR are large-magnitude voltage based and

have less on-time error and better efficiency performance, compared with conventional vds.on based methods.

Regarding the system dynamics aspect, the proposed small-signal dynamic model for charge-controlled

97
resonant converters concludes that the equivalent charge feedback signal is the sine component of the reso-

nant current, which is essentially the average input current. The average input current contains the dynamics

of the magnetizing current, and yet it is neglected by the conventional model, leading to prediction error.

The proposed dynamic model takes that part into consideration and successfully predicts the frequency re-

sponse from the low-frequency to high-frequency regions, which enables high-bandwidth design, improving

the dynamic performance.

The main contributions of this work are summarized as follows:

1. Large-Magnitude Voltage Based, Noise-Tolerant SR: Both of the proposed RCV and VSP SR are

based on large-magnitude voltages as opposed to the conventional vds.on based methods. Since the sensed

voltages are much larger than the voltage drops on the parasitic components, both proposed methods are

insensitive to the parasitic effects. As a result, the SR on-time error caused by the parasitic effects is removed,

improving the efficiency. The proposed SR and the conventional vds.on based SR methods are tested on a

650W/ 24V battery charger. Compared with the vds.on based non-adaptive SR, the RCV SR reduces the loss

by 6 % in the full-load condition. The VSP SR is further compared with the advanced, adaptive version of

the vds.on based SR and shows loss reduction by 3 % in the full-load condition.

2. Simplified, Highly-Integrated SR: The proposed VSP SR offers a simple solution to LLC SR using

a microcontroller. In high-power battery charging applications, it is common to have a microcontroller on

the output stage for communication with the battery management system, and potentially, to function as

the closed-loop controller. With only a few basic logic gates, the VSP SR can be easily integrated into the

microcontroller, achieving a highly-integrated design. In addition, VSP SR has less printed-circuit board

(PCB) layout constraints. Conventional vds.on based SR controllers are supposed to be placed as close to the

SR MOSFETs as possible to reduce the stray inductance in the voltage sensing loop. The proposed VSP SR

senses the blocking voltage of the SR MOSFET simply using a pair of voltage dividers, which makes the

PCB design more flexible.

3. Enhanced Small-signal Modeling for Charge-Controlled Resonant Converters: The proposed

small-signal modeling methodology based on Extended Describing Functions (EDF) and phasor analysis

is applicable to both CLLC and LLC resonant converters. This model not only successfully predicts the

frequency response, but also reveals the essence of the charge loop. This part of the work concludes that

the charge loop controls the sine component of the resonant current, which is essentially the average input

current. As a result, the charge loop has two split real poles in the mid- to low-frequency range, and their

positions are affected by the slope compensation. For a high-bandwidth design, the effect of the second

98
pole must be taken into consideration. This enhanced small-signal model predicts the frequency response

very well from the low-frequency to high-frequency regions, and thus is useful for a high-bandwidth design,

improving the dynamic performance.

The research outcomes of this work have been published in IEEE Transactions on Power Electronics and

IEEE Journal of Emerging and Selected Topics in Power Electronics as follows:

• J. -D. Hsu, M. Ordonez, W. Eberle, M. Craciun and C. Botting, “LLC Synchronous Rectification

Using Resonant Capacitor Voltage,” in IEEE Transactions on Power Electronics, vol. 34, no. 11, pp.

10970-10987, Nov. 2019.

• J. -D. Hsu, M. Ordonez, W. Eberle, M. Craciun and C. Botting, “Noise-Tolerant LLC Synchronous

Rectification Using Volt-Second Product,” in IEEE Journal of Emerging and Selected Topics in Power

Electronics, Early Access.

• J. -D. Hsu, M. Ordonez, W. Eberle, M. Craciun and C. Botting, “Enhanced Small-Signal Modeling

for Charge-Controlled Resonant Converters,” in IEEE Transactions on Power Electronics, vol. 37, no.

2, pp. 1736-1747, Feb. 2022.

5.2 Future Work

This work has explored synchronous rectification for LLC resonant converters using large-magnitude voltage

signals as well as established the fundamentals of small signal modeling for charge-controlled resonant

converters. The methodologies cover both steady-state and transient analyses for resonant converters. The

findings open new research and development opportunities including:

• Integrated VSP SR and charge-mode controller: In Chapter 3, this work has demonstrated the in-

tegration of VSP SR with a voltage-mode, closed-loop PI compensator together in a microcontroller

located on the secondary side. It is possible to integrate the charge-loop compensator with the same

microcontroller. The challenge is to pass the AC component of the resonant capacitor voltage to the

secondary side. For a half-bridge topology, since the resonant capacitor voltage contains a DC com-

ponent, a pulse transformer with a DC blocking capacitor can be used to transfer the AC component.

The transferred resonant capacitor voltage on the secondary side is then compared with the output of

the voltage loop compensator to control the primary switches. Details about the operating sequence

such as start-up and protection remain to be studied.

99
• SR for bidirectional resonant converters: Bidirectional resonant converters are popular topologies

for high-efficiency energy recycling or backward power transfer. Due to the active switching devices

on both the primary and the secondary sides, it is reasonable to enable SR to improve the efficiency

performance. The proposed VSP SR can be the first candidate for its simplicity. The operating prin-

ciples of VSP SR for bidirectional resonant converters such as CLLC converters are similar to those

of LLC resonant converters. Hence, VSP SR for bidirectional resonant converters can be a potential

research topic. For charge-controlled bidirectional resonant converters, since the resonant capacitor

voltages from both sides and the input and output voltages are all available, RCV SR can be consid-

ered to make the best use of those signals. The resettable integrators to perform RCV SR can be shared

by both sides to maximize the utilization. Detailed control logics need further investigation.

• Charge control for three-phase resonant converters: Three-phase resonant converters are known

for its capacity for high-power, high-voltage applications. By interleaving the three phases, the output

current ripple can be reduced, which is beneficial to the power density. However, due to the unavoid-

able component tolerance, the three-phase currents are rarely perfectly balanced, which deteriorates

the performance. Since charge control intrinsically controls the average input current, potentially it

can achieve current balancing. The phase-shift of the three legs can be adjusted according to the charge

feedback. The impact of the phase shift on the dynamics of the charge-controlled three-phase resonant

converter can be explored in the future research.

100
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