DATA SHEET

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Linear Voltage Regulator

3A for DDR1, DDR2, DDR3,
LPDDR3, DDR4 VTT DFN10
CASE 485C
DFNW10
CASE 507AM
Termination
NCP51200, NCV51200 MARKING DIAGRAMS

The NCP/NCV51200 is a source/sink Double Data Rate (DDR) 51200

XX
termination regulator specifically designed for low input voltage and ALYWG
low−noise systems where space is a key consideration. G
The NCP/NCV51200 maintains a fast transient response and only
requires a minimum output capacitance of 20 mF. The NCP/NCV51200 XX = Specific Device Code
A = Assembly Location
supports a remote sensing function and all power requirements for L = Wafer Lot (Optional character )
DDR VTT bus termination. The NCP/NCV51200 can also be used in Y = Year
low−power chipsets and graphics processor cores that require W = Work Week
dynamically adjustable output voltages. G = Pb−Free Package
The NCP/NCV51200 is available in the thermally−efficient DFN10
(Note: Microdot may be in either location)
Exposed Pad wettable flank package, and is rated both Green and
Pb−free.
PIN CONNECTION
Features
• For Automotive Applications +
VRI 1 10 VCC
• Input Voltage Rails: Supports 2.5 V, 3.3 V and 5 V Rails
2 9
• PVCC Voltage Range: 1.1 to 3.5 V PVCC PGOOD
VTT 3 GND 8 GND
• Integrated Power MOSFETs
PGND 4 7 EN
• Fast Load−Transient Response
VTTS 5 6 VRO
• PGOOD − Logic output pin to Monitor VTT Regulation
• EN − Logic input pin for Shutdown mode Exposed Pad

• VRI − Reference Input Allows for Flexible Input Tracking Either

Directly or Through Resistor Divider ORDERING INFORMATION
• Remote Sensing (VTTS) See detailed ordering, marking and shipping information in the
package dimensions section on page 8 of this data sheet.
• Built−in Soft Start, Under Voltage Lockout and Over Current Limit
• Thermal Shutdown
• Small, Low−Profile 10−pin, 3x3 DFN Package
• NCV51200MWTXG (SFS), NCV51200MLTXG (SLP); − Wettable
Flank Options for Enhanced Optical Inspection
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable*
• These Devices are Pb−Free and are RoHS Compliant
Applications
• DDR Memory Termination
• Desktop PC’s, Notebooks, and Workstations
• Servers and Networking equipment
• Telecom/Datacom, GSM Base Station
• Graphics Processor Core Supplies
• Set Top Boxes, LCD−TV/PDP−TV, Copier/Printers
• Chipset/RAM Supplies as Low as 0.5 V
• Active Bus Termination

© Semiconductor Components Industries, LLC, 2016 1 Publication Order Number:

July, 2024 − Rev. 15 NCP51200/D
 NCP51200, NCV51200

PIN FUNCTION DESCRIPTION

Pin Number Pin Name Pin Function
1 VRI VTT External Reference Input ( set to VDDQ / 2 thru resistor network ).
2 PVCC Power input. Internally connected to the output source MOSFET.
3 VTT Power Output of the Linear Regulator.
4 PGND Power Ground. Internally connected to the output sink MOSFET.
5 VTTS VTT Sense Input. The VTTS pin provides accurate remote feedback sensing of VTT. Connect VTTS to the
remote DDR termination bypass capacitors.

6 VRO Independent Buffered VTT Reference Output. Sources and sinks over 5 mA. Connect to GND thru
0.1 mF ceramic capacitor.
7 EN Shutdown Control Input. CMOS compatible input. Logic high = enable, logic low = shutdown. Connect
to VDDQ for normal operation.

8 GND Common Ground.

9 PGOOD Power Good (Open Drain output).
10 VCC Analog power supply input. Connect to GND thru a 1 − 4.7 mF ceramic capacitor.
THERMAL Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple
PAD vias for maximum power dissipation performance.

ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Unit
VCC, PVCC, VTT, VTTS, VRI, VRO (Note 1) −0.3 to 6.0 V
EN, PGOOD (Note 1) −0.3 to 6.0 V
PGND to GND (Note 1) −0.3 to +0.3 V
Storage Temperature TSTG −55 to 150 °C
Operating Junction Temperature Range TJ 150 °C
ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following method:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.

DISSIPATION RATINGS
Derating Factor above
Package TA = 255C Power Rating TA = 255C TA = +855C Power Rating
10−Pin DFN 1.92 W 19 mW/°C 0.79 W

THERMAL INFORMATION
NCP51200 (*)
DFN 3x3mm
Symbol Thermal Metric 10 pins Unit
RqJA Junction−to−ambient thermal resistance 53.9 °C/W
RqJC(top) Junction−to−case (top) thermal resistance 95.5 °C/W
RqJB Junction−to−board thermal resistance (1mm from package) 32.3 °C/W
YJT Junction−to−top thermal resistance 4.3 °C/W
YJB Junction−to−board thermal resistance (1mm from package) 32.3 °C/W
RqJC(bot) Junction−to−case (bot) thermal resistance 14.2 °C/W
*1S2P JEDEC JESD51−7 PCB with 240 sqmm, 2 oz copper heat spreader.

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 NCP51200, NCV51200

RECOMMENED OPERATING CONDITIONS

Rating Symbol Value Unit
Supply Voltage VCC 2.375 to 5.5 V
Voltage Range VRO −0.1 to 1.8 V
VRI 0.5 to 1.8
PVCC, VTT, VTTS, EN, PGOOD −0.1 to 3.5
PGND −0.1 to +0.1
Operating Free−Air Temperature TA −40 to +125 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.

ELECTRICAL CHARACTERISTICS
−40°C ≤ TA ≤ 125°C; VCC = 3.3 V; PVCC = 1.8 V; VRI = VTTS = 0.9 V; EN = VCC; COUT = 3 x 10 mF (Ceramic); unless otherwise noted.

Parameter Conditions Symbol Min Typ Max Units

Supply Current
VCC Supply Current TA = +25°C, EN = 3.3 V, No Load IVCC 0.7 1 mA
VCC Shutdown Current TA = +25°C, EN = 0 V, VRI = 0 V, No Load IVCC SHD 65 80 mA
TA = +25°C, EN = 0 V, VRI > 0.4 V, No Load 200 400
VCC UVLO Threshold Wake−up, TA = +25°C VUVLO 2.15 2.3 2.375 V
Hysteresis 50 mV
PVCC Supply Current TA = +25°C, EN = 3.3 V, No Load IPVCC 1 50 mA
PVCC Shutdown Current TA = +25°C, EN = 0 V, No Load IPVCC SHD 0.1 50 mA
VTT Output
VTT Output Offset Voltage VRO = 1.25 V (DDR1), ITT = 0 A VOS −15 +15 mV
VRO = 0.9 V (DDR2), ITT = 0 A −15 +15
AMN suffix, VRO = 0.6 V (DDR4), ITT = 0 A −15 +15
PVCC = 1.5 V, VRO = 0.75 V (DDR3), −15 +15
ITT = 0 A

VTT Voltage Tolerance to VRO −2 A ≤ ITT ≤ +2 A −25 +25 mV

Source Current Limit VTTS = 90% * VRO 3 4.5 A
Sink Current Limit VTTS = 110% * VRO 3.5 5.5 A
Soft−start Current Limit TSS 200 ms
Timeout

Discharge MOSFET VRI = 0 V, VTT = 0.3 V, EN = 0 V, TA = +25°C RDIS 18 25 W

On−resistance

VRI − Input Reference

VRI Voltage Range VRI 0.5 1.8 V
VRI Input−bias Current EN = 3.3 V IRI +1 mA
VRI UVLO Voltage VRI rising VRI UVLO 360 390 435 mV
Hysteresis VRI HYS 60
VRO − Output Reference
VRO Voltage VRI V
VRO Voltage Tolerance to VRI IRO = ±10 mA, 0.6 V ≤ VRI ≤ 1.25 V −15 +15 mV
AMN suffix, IRO = ±1 mA, VRI = 0.6 V −12 +12
VRO Source Current Limit VRO = 0 V 10 40 mA
VRO Sink Current Limit VRO = 0 V 10 40 mA

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 NCP51200, NCV51200

ELECTRICAL CHARACTERISTICS
−40°C ≤ TA ≤ 125°C; VCC = 3.3 V; PVCC = 1.8 V; VRI = VTTS = 0.9 V; EN = VCC; COUT = 3 x 10 mF (Ceramic); unless otherwise noted.

Parameter Conditions Symbol Min Typ Max Units

PGOOD − Powergood Comparator
PGOOD Lower Threshold (with respect to VRO) −23.5% −20% −17.5 V/V
%

PGOOD Upper Threshold (with respect to VRO) 17.5% 20% 23.5%

PGOOD Hysteresis 5%
PGOOD Start−up Delay Start−up rising edge, VTTS within 15% of 2 ms
VRO

PGOOD Leakage Current VTTS = VRI (PGOOD = True) 1 mA

PGOOD = VCC + 0.2 V

PGOOD = False Delay VTTS is beyond ±20% PGOOD trip thresholds 10 ms

PGOOD Output Low Voltage IGOOD = 4 mA 0.4 V

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 NCP51200, NCV51200

ELECTRICAL CHARACTERISTICS
−40°C ≤ TA ≤ 125°C; VCC = 3.3 V; PVCC = 1.8 V; VRI = VTTS = 0.9 V; EN = VCC; COUT = 3 x 10 mF (Ceramic); unless otherwise noted.

Parameter Conditions Symbol Min Typ Max Units

EN − Enable Logic
Logic Input Threshold EN Logic high VIH 1.7 V
EN Logic low VIL 0.3
Hysteresis Voltage EN pin VENHYS 0.5 V
Logic Leakage Current EN pin, TA = +25°C IILEAK −1 +1 mA
Thermal Shutdown
Thermal Shutdown TSD 150 °C
Temperature

Thermal Shutdown Hysteresis TSH 25 °C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

Figure 1. Typical DDR−3 Application Schematic

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NCP51200, NCV51200

Figure 2. Block Diagram

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 NCP51200, NCV51200

General limits of the PowerGood window. During initial VTT

The NCP51200 is a sink/source tracking termination startup, PGOOD asserts high 2 ms after the VTT enters power
regulator specifically designed for low input voltage and good window. Because PGOOD is an open−drain output, a
low external component count systems where space is a key 100 kW, pull−up resistor between PGOOD and a stable active
application parameter. The NCP51200 integrates a supply voltage rail is required.
high−performance, low−dropout (LDO) linear regulator The LDO has a constant over−current limit (OCL). Note
that is capable of both sourcing and sinking current. The that the OCL level reduces by one−half when the output
LDO regulator employs a fast feedback loop so that small voltage is not within the power good window. This reduction
ceramic capacitors can be used to support the fast load is non−latch protection. For VCC under−voltage lockout
transient response. To achieve tight regulation with (UVLO) protection, the NCP51200 monitors VCC voltage.
minimum effect of trace resistance, a remote sensing When the VCC voltage is lower than the UVLO threshold
terminal, VTTS, should be connected to the positive terminal voltage, both the VTT and VRO regulators are powered off.
of the output capacitors as a separate trace from the high This shutdown is also non−latch protection.
current path from VTT.
Thermal Shutdown with Hysteresis
VRI − Generation of Internal Voltage Reference If the NCP51200 is to operate in elevated temperatures for
The output voltage, VTT, is regulated to VRO. When VRI long durations, care should be taken to ensure that the
is configured for standard DDR termination applications, maximum operating junction temperature is not exceeded.
VRI can be set by an external equivalent ratio voltage divider To guarantee safe operation, the NCP51200 provides
connected to the memory supply bus (VDDQ). The on−chip thermal shutdown protection. When the chip
NCP51200 supports VRI voltage from 0.5 V to 1.8 V, junction temperature exceeds 150°C, the part will shutdown.
making it versatile and ideal for many types of low−power When the junction temperature falls back to 125°C, the
LDO applications. device resumes normal operation. If the junction
temperature exceeds the thermal shutdown threshold then
VRO − Reference Output
the VTT and VRO regulators are both shut off, discharged by
When it is configured for DDR termination applications,
the internal discharge MOSFETs. The shutdown is a
VRO generates the DDR VTT reference voltage for the
non−latch protection.
memory application. It is capable of supporting both a
sourcing and sinking load of 10 mA. VRO becomes active Tracking Startup and Shutdown
when VRI voltage rises to 435 mV and VCC is above the The NCP51200 also supports tracking startup and
UVLO threshold. When VRO is less than 360 mV, it is shutdown when EN is tied directly to the system bus and not
disabled and subsequently discharges to GND through an used to turn on or turn off the device. During tracking
internal 10 kW MOSFET. VRO is independent of the EN pin startup, VTT follows VRO once VRI voltage is greater than
state. 435 mV. VRI follows the rise of VDDQ memory supply rail
via a voltage divider. The typical soft−start time for the
Soft Start
VDDQ memory supply rail is approximately 3 ms, however
The soft−start function of the VTT pin is achieved via a
it may vary depending on the system configuration. The SS
current clamp. The current clamp allows the output
time of the VTT output no longer depends on the OCL
capacitors to be charged with low and constant current,
setting, but it is a function of the SS time of the VDDQ
providing a linear ramp−up of the output voltage. When
memory supply rail. PGOOD is asserted 2 ms after VTT is
VTT is outside of the power good window, the current
within ±20% of VRO. During tracking shutdown, VTT falls
clamp level is one−half of the full over−current limit (OCL)
following VRO until VRO reaches 360 mV. Once VRO falls
level. When VTT rises or falls within the PGOOD window, the
below 360 mV, the internal discharge MOSFETs are turned
current clamp level switches to the full OCL level.
on and quickly discharge both VRO and VTT to GND.
The soft−start function is completely symmetrical; it
PGOOD is de−asserted once VTT is beyond the ±20% range
works not only from GND to the VRO voltage but also from
of VRO.
PVCC to the VRO voltage.
VTT Output Capacitor
EN − Enable Control
The NCP51200 requires the output capacitor connected as
When EN is driven high, the NCP51200 VTT regulator
close as possible to the VTT and PGND pins. The regulator
begins normal operation. When EN is driven low, VTT is
has been designed to remain stable with output capacitor’s
discharges to GND through an internal 18−W MOSFET.
effective capacitance in range from 20 μF to 1000 μF. The
VREF remains on when EN is driven low.
ceramic X7R or X5R type is recommended due to its low
PGOOD − PowerGood capacitance variations over the specified temperature range
The NCP51200 provides an open−drain PGOOD output and low ESR and ESL. When selecting the capacitor value
that goes high when the VTT output is within ±20% of VRO. the changes with temperature and DC bias voltage needs to
PGOOD de−asserts within 10 ms after the output exceeds the be taken into account. Especially for small package size

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 NCP51200, NCV51200

capacitors, the effective capacitance drops rapidly with the limited). This capacitor provides needed energy during load
applied DC bias voltage (refer the capacitor’s datasheet for transients for output capacitor re−charging and from this
details). Larger capacitance and lower ESR improves the point of view, the higher value is better. The good starting
load transient response and PSRR. In the PCB layout, design value is the half of the output capacitor value. The rules
the traces short and wide and place the capacitor at the same mentioned at VTT capacitor paragraph are applicable for
PCB layer as the device (do not use layers changing for the PVCC capacitor as well.
traces).
VCC Input Capacitor
PVCC Input Capacitor Add a ceramic capacitor, connected as close as possible to
Power input capacitor, connected as close as possible to VCC and GND pins. The X7R or X5R capacitor should be
PVCC and PGND pins, is also necessary to ensure device used with a value in range from 1 μF to 10 μF is
stability and good transient response. The value of the input recommended.
capacitor should be 10 μF or greater (max. value is not

DEVICE ORDERING INFORMATION

Device Marking Code Package Feature Shipping†
NCP51200MNTXG 51200
NCV51200MNTXG* 51200 Non−Wettable Flank 3000 / Tape & Reel
MN DFN10
(Pb−Free)
NCV51200MWTXG* 51200 Wettable Flank
3000 / Tape & Reel
MW SFS Process

NCV51200MLTXG* 51200 DFNW10 Wettable Flank

3000 / Tape & Reel
ML (Pb−Free) SLP Process

NCP51200AMNTXG 51200 DFN10

Non−Wettable Flank 3000 / Tape & Reel
A (Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.

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 MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

DFN10, 3x3, 0.5P

CASE 485C
ISSUE F
SCALE 2:1 DATE 16 DEC 2021

GENERIC
MARKING DIAGRAM*

XXXXX
XXXXX
ALYWG
G
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
*This information is generic. Please refer to
Y = Year
device data sheet for actual part marking.
W = Work Week Pb−Free indicator, “G” or microdot “G”, may
G = Pb−Free Package or may not be present. Some products may
(Note: Microdot may be in either location) not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON03161D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: DFN10, 3X3 MM, 0.5 MM PITCH PAGE 1 OF 1

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2000 www.onsemi.com

 MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

DFNW10 3x3, 0.5P

CASE 507AM
ISSUE A
DATE 12 JUN 2018

GENERIC XXXXX = Specific Device Code

MARKING DIAGRAM* A = Assembly Location
L = Wafer Lot
*This information is generic. Please refer to
XXXXX Y = Year
device data sheet for actual part marking.
XXXXX W = Work Week Pb−Free indicator, “G” or microdot “ G”,
ALYWG G = Pb−Free Package may or may not be present. Some products
G (Note: Microdot may be in either location) may not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON85414G Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: DFNW10 3x3, 0.5P PAGE 1 OF 1

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2018 www.onsemi.com

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