: mes Digitol Togs and esse Codex EC {es)304 $} Amen f= If feyie. > Compose Asyachronous ‘and Syne hryonovs sequeattia | Featuses’ Asynchronous Banal Synchyonovs Sequential logic t logic t Clocking [Does not vse a clocksiqnal [Uses 0 clock signal to J to con trol tiening, 4 Synchronize ste change Timin Changes in the stote ave, [State chan onl J Hriggdeed by change in inpot lars Rime varia. bles. determined by ha clock polse- Complerity srtcelly simaples, but havder [Mose steuctored and eatler to design and analy ze. fo design and onalyre Reliability | Prone te Hening_problena such | Move velvoble due fu Ff as glitches ai ace condi fans | syrchyonl zation tt th . The clock a ral aus issues Vi ce conditicny, speed ’ Foster due fe no clock Ql ee vah o 0 nu dependency, peso with the clock pulse Application Used in small ond fast [Used in Longe, complex. civeults [lke Keyboords . - syctemy [lit procesmrysense etgee 2 Draw the state Slog ron and choracterittics equation OP ab and SR FF. So? D- Flip Flop State diogvam a RY)” Characteristics equation - Q. =D SR FlipFlop Reset Cheracleristic, €q vation- Qneet = $+ Qas- Le Po-3_, Flop 'S oO latch? Difference between Lateh ond Flip ace Latch 'S 6 besic bistable mult yi i isto tvibratos that ch is State based on the input whlle the enable s " Tt doesn't depend onaclock siqnal. Most common, types of latch Bree SR latch (set- Reset latch) Biotech (Dato Latch) DiPResences, Features Late i] Flip Flop i Clock Signal No clock signal veq une Operate with a clock ignel 1G active. Sensittvity | Level-senai tive Cd Edge sensitive(ch ovtpat} J outpet senate Cong onl) (rege : i + 5 on Go clec! ge etter Of the con tro I fi atsing oy Pollin signal) “em a Speed Foster but less contlk Slowes but move corttralled Powes | Gr \ Flip-Flops Consumption. mane ae erly ed paver dve sl clue fo the lack o $e the clock signal clocking clvcuitey - diving the ch gn oF sak Exompk BR, DIK Latch SRD, Jk, T Flip Flop [ |ene Fe FlipFlop using SR Flip Flop. Step I: Connect the T inpul divect Iy to both Sand R inpuk of th SR Flip-Flop ‘hough on tara XoR gate Logic- s=T@, R= TR Step 22 The T F lip Flop toggles tks skate on each clock Pulse wher T= I- Block diagram of T Fliprlp using SR-Plip?lep s o SR FlipFlop I Next | State Decoder & How doos He Tk Flip Plop cKPRer som an SR PlipPlep init bosle equotion? > i Handling Ho S=t, R21 Condition: "SR FE- ‘nis lhe euinvalil ond must be avoided. + TK FF- This condition couses the PlipPlep to Foggle its store. 2 Logic Expression’ -SREE- SR Fliplop Uses Sand R input a in its equation + TK FF- IK FlipPlep adds tags ling Punctionabi mM using J ond & Vewsolitys Verso.lity+ becaus it can ev Fore. -the Punetions -TkK FF is mew versatile Shon sk 0,27 ER depending on input con Piourationeee nee DS Convert Tk FF into SR FF: Sogn uth Tables [apt Prinest State [xt Shae — | FlipPlap ecco areca See epee jS |R | Qn | Gm tT IK oO | 6 Oo ° K o|0 rl fe x lo | o|[t 6 9 te loft | \ co ‘jt 4 Jeseeves 3 | ! x | 1 [o \ ! x | 07 eave ° x a_| & | vid \ : x |* Biogram: cP l2.Whatis wore owound condition? How de you eliminate ip DRoer Axound condition occurs in. Tk FF when the clock pulse is high for o duvation longer ‘than the propo ation. | delay. T+ aus fre output to Hoagle my LHple firma in ON cloc! cyck i i To else | edge feign insteod of level felggeving © Redvee cle pulse width: @ Vee o Moster-Slove FlipFlp con Figuration.3-Design the sy nchvorous coun’ uv 4 . stote Jiogrom J ee ner By the. Following 40 0-D1H0-DHO-P10 |S OOH 4 Mention two differences between the ed teig exin and level eggs e y i Sol Diffesences ove Edge Tatggering Opeworlss on clock edges Opesates closing high or low Level Taga clock levels, Postes, avoid Kite hes Slower 5 Susceptible to gt tohesBDDvow the state diag vor OP -Hhe MOD-10 counter Using FF. J Go ee Ooll? aE Sasert sae eae Clo Eee aie” \ aor al cixcuits? Give som examp les. ®Wwhatis Sequeat! DA sequential ciscult is a type of di ital ateep th where the aviput cLepends not only on the Me inputs bot alsoon Hw history at intp he T+ ine lode Late i elemonts to s tore stote of te system ablowilj it fo maintain infosmotion obout pas Fevens- Soma Excarmplos Ose MOD-N Countess Shift _ 5S Memory ni ts: I> Dwow a NAND based logic diog Tk FlipF lop- i>—-p D7 wom of Moater Slave @SR (set React) Flip Flop That occurs when both SR Flip-Flop): Truth Toble + k Qn DSEplein The Fliphbp | oper “Fauth toble- ? rr Le . A ae Flip sp is 0 ype of Fitp Pop with two inpols Sond kK, and one ovtpul’'Q.T1 1s on Lelie over d ox it ecliminales: hs invalid stote inputs oe high (S=t and Rel in om le] > DéP Pesentia Asynchsonous Coun tes TDT+ can operate of fem slower in operation. ean due to vipple eFFect HDA ceurulates with each Flip Flop, cousing coe in counting MD sed in low-speed app lication, such os simp binony counters le ag afion. Fide ona WA subsequent pre deloy is encountered Flip-Flop te another. : V> Higher power consumption. je Asynchronous and Synchronous counter: | Synchronous Counter TUTE can Operate at much higdhew clock. Freq uencias ser BD Minimal delay o all Flip-Flops seciee the clod signal ot once. zed applications, WY Used ia Frequeny divide. Vhe digitad wee WW) Thave is no inherent pro delay in syrchwonovg coun ti poy? Ly VD Lowes power consump tion:~peonost mw veo PSzso= | Srso shift segisher | 1S Fype of shift seqister whore ay is is a en (ona bik ota tine) ond ofs0 oatof erst on bit at ating). Dota ent oF inpot Yne and is shied thromhe Soe ie eg ister The bits owe shifted ‘one by om ree Risst Pip-Plop to the last-APler the, lost bit hos been shifted Oot, Phe. voqister Beacts oy continues fo Shift for he rect jopeh Sed chakt weqis has ave, Used Por applica tion where fade ta Pe istered oad shipted owt ino Serial Porm, such ag in sesial dota trommission, > STPO- A szpo shift wegister i isa pe ok shift veqistes ee Hato ts entesed steially on ond ft ted in p rollel - en keys An x a sevtally, one wit at a fides and is io tha -Hrveu: Once all bits ove shifted in , ave aval lable ot poral Peake simutiaasevsly STPO PISO— A ‘PIso ashi wegis ter allows oe to be ea in pavallel and output sev Date | ie Voaded info the shiPt sate ip peas an ty dota ts shifted out sevi sone bit ato time, ister’s ome Cees Fo eo Reece cle. PISO shift se povallel +0 sell “oy ave vsetol when inutligle fi Ye of dato agd to be Sent s tally over a copnmnunicado te chonnel, such af in Poreliel bus sys us where cata needs TO be Tsonsmitted sestodly aver a wire u>PTPO- A PEPO shift veqister allows | data to be catered andehaved into the ia ae oe lel. beth in. povallel: Jouis entered with eoch bit pleoced into its covsespon a bi aS ave ovtput is also olan Ln me grist ovo Flable simu Hansousl ottels. Pare shi kt reais ters one vas in op ico shee oto Meds fo, be stoxed and aceessed in pork Ror, such O% in mamoyy ¢ tovas its Sede doto- aisle, ond buf Per cisev'7 Drow FUp Flop. ‘SK FR Sole Present State— the shate Present State next state tab le 12 Pesign Ho Cisevit of table and exclia k fon table of T Pox T Flip Plop MOD 6 Synchronous Counter Using Next State For MOD t Synchronous Coun bs. Present State | Next State Excitation “Lnpels Hleleimlalai[m [kiln [kh ofofo | of of4 0 4 f° |d ole |r [oltlo Oe eld So tlo OF 0 ad ja 4 : ee on oe en eo 1 | o L}o|! d o |o|3 L}o o jroo a os ri} ilo |d{afa |e | la fa ae en ed a | fa+5V For Jy Nate OO Of 11 10_ a ae z 4 Te hte For Ke ee, ot (1 10 © [pet 1 (158) Kot cu,139 Explain 4 bikup-down. counter: SAYIE vp-down covnler is a Seq venbiak digital. cireult thet counts in binary either apie | (up counting) &% decrementin (down -eauallin ) its count ve ve Th ses Flip Flops Cosvably ww os Th Fl Flops) und some combinational logic +o contyol the coontin divection, 4 con count from 0 (6800 Ine Winery) do FS CILIL TH binary ), a it has Q=l6 possible states: TH+ Counts v word oy downwards bared ono contre | ‘inpet signal Commonly lobeled os UP/DOWN or DIR). Componants — Flip Flopst 4 Plip F tops store tha count Each Flip-Flop xeprerents one bit Con trol logics Determints whetwr to incveament ae “tha count coat on Hw UP/DOWN signak- Clock Stgnets Synchwonize te Counting process: Je crement IM Ex plain the Ring and Tahason Counter. Sok Ring Counter Aving counter isotype of sequential digital cisevit where he output of tn (at Flip Pop is fed back ts the input of the Fixst Flip-Flop, foxrning a civevlay Cxing- like) sequene of stoctes. Shift Reaisler Bored Feaeturess ; . Consisfo fa gevie “oF Flip-Flops connected ina chift aw Sartell TOV o0 dea, and Hw bik eivevlate Hovough, tha. Plip- Flops Cyclic Nodvre! For on n-bit Ring Counter, Preve oe 0 unt que stotes only one Flip-Flop is set O) ot atime, and the vest ocrexuil Advortoges: $i it mee he de each stot,or only one Plip-Plop is active ata Easy to deco he 9 tevms of state vsvage (only a is edvaneyss gels Pa Applications. Timing clveults quence genevotorsSohnson Counter ~ A johnson Counter, also known on a Twisted Ring Counter, is a modified version oF te Ring Counted? where the inverted output of te last Pio Flop is Red back to the input of Hhe Pivst F lip-Plops Key Features Tyeasaed Stotes: For an n-bit Johnson Counter,thave are 2n vnique states. “This is mare efficient thon o standard Ring Counter. Unique Sequence “The Sequence conaists ofa com bination f Is onb Os That civculate on dvepeat after In states. Adventogos: Ubliees twice 8 many states as Hho number of Cle tee. Simp ley decoding Por certain applications Disochoategp’ SI htly move complex to implement then o. Rig outer) Digital te Analog Conves fers (DACs). App licotions: ep Control systens. Sequence detectors. Is Whed ts Data lockout? > Data lochoot xefus to a. stluation where aceess ty dato is vextsicted oF unowal lable, typic due bs fecholcal, cod ly OF ad ministrortve eel THs feom ig often used ian tre context of systems, ratworls or application ohne vsers owe nab 1 setsieve ot 2 ot Common Covser of Dera Lochovls axe — othantcation issue, Encxyption pre ems, So Taare (Sytem Exrovs, Administrative Rosrsictios , Networb/ Sever Downti Consequencss; Prodyctivit sceurity volnerebility, N Prevention Moltatuin bochups Secure ovthentica tion enactho ds Regular sateen avdits Tmplemart vsex Access contyols | loss, Risk of data loss, Lneweased16) Write b notes on Analog to Digitot Be HEL porenaltg converter bach J oo Analog to Digital Converter (ADC) ital conver tes produces o diqvlal. output An ana di ia Snaleg ‘input vo \toge ‘aPter o“cex tain code Ph on Amount of Aiene- Bostic Opesation of ADC loap Cet te operation, is Inittated by stort command puls- % Clock contre! Hw xate ond ted vnit modifie certainly binary number and stored in ve is ter. 2 Binoxy no stoved in ~vegis tex is converted into anakeg Vo lta by DAC- 4 The" comparator in the cixevit compares the anale inputs: _ 5: The contol fog ie activates end of convertion signa iwhan- convertion is comple. 7 C. There one several type of ADC "9 Succemive opproximati Adc tie e ae TT Digital Rom bc S Glee aig ADC Digitol to Anolog Conver tex (DAC) Digital to Anoleq convessfon ig the process of pis oo vorlue eeeeeted in digital code and converting N to a Voltage on cons ant @hich is propovtional be digi tet Glut Tha Onaleg ovlput voltage “Vo at an N bi t straig binory D/A converte is Selated to the digital input b Fhe equation : ey Vo = k [2 'by.it qv byeat 2ba*2b, +2be] apropaxtonally Pac tor : b ae en free di ital inpu Fis L i. TP n-th bit of digital input {s 0. Lrypes oF DIA converter + R-2R ladder D/A cones ter: Type or eer. + Weighted vest stor D/A converter. + bit binary weighted Dac,el ee gee Ae Seen Ip i Sesolvron. Accurvacy, Pow hot is the ey Voltage of ony D/A and A/b tonve Sof Resolution Accuracy +E shows howu precise the converter {s a v1 ox A/ 7 converter, it clepends on the number of bits (e4- hit, to bit) Higher bis mean move accurate ovtpot. Set ling Time-“This is the time the converter tales to Jive a stable ovtput offer ac ange in input. Faster settling “time means quicker wes ponse, CRRset Voltoge~ “Lys the small evvo in pelea that appears even when qe input Vs Gevor Tde vit should be zero, bot in -vealdeviceits o Hing fixed ~¢svorw. L>Design an equivalent TTL NOT gate: The tronsistor Q is He input coup lin transistor and Di 1s +he protective diode. Trangis fx Qe iscalled o Phase sp (tev, and the combination of tyansistors Q; and Qu Posms hotem-pole outpu Claeul fs- yp Wee SRy ee Ou tput Qs Laput [ Qo Ee www Alf at i aNWhen o High GS) Volta 's opplied ta ‘ish G PPlied SF He taped (Ay He oae-emifler vn ction, ofa, beco 4 ~ fe ve Pata bode collet uate Sever Beverce- blaze d Vers | . Corsent tan Few firroug S Ry ond be . clea tes OF ®, into the base of Oy Tare ha the transistor Qa ives into saturation and Vol tage crop acvoss Ry tusna aha, honsis tox Qu So the outpot 1S nearer to low Poterttag. When the input ts low, the bese-een iter, junction OtQ is Poswoard- biased and the base collector Jvnc tion lased- There Poe, the curren} Plows sou: Rand se-emiHer function Ohi tole in uF As thee is “ , Servvent Plowing ints the bose of Qaitis OFF-The co sie At Qa cis Hivh thus turning Qs ON-A saturated Qs prov Obs my redone “path Prom ver to The outputs Hence He outpul 1s Hien, is ¥everse - the