Vol. 36, No.

1 Journal of Semiconductors January 2015

A 9–12 GHz 5-bit active LO phase shifter with a new vector sum method
Chen Changming(陈昌铭), Li Wei(李巍)Ž , Li Ning(李宁), and Ren Junyan(任俊彦)
State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China

Abstract: This paper presents a 5-bit active LO phase shifter with a new vector sum method for 9–12 GHz ap-
plications. The 5-bit phase shifter is composed of four 3-bit sub phase shifters by adopting the new vector sum
method, which reduces the requirements on the resolution of the variable gain amplifier (VGA). The variable gain
function is realized by switch on/off parallel input transistor pairs rather than changing the bias current of the VGA,
which avoids the linearity variation and drain-source voltage variation existing in the quadrature vector sum active
phase shifter. The 5-bit active LO phase shifter is fabricated in TSMC 0.13 m CMOS technology. The measured
results show that the phase shifter achieves 5-bit phase shift accuracy. The average conversion gain for 32 phase
states is 0:5 to 7 dB from 9 to 12 GHz. The RMS gain error and the RMS phase error are smaller than 0.8 dB and
4ı respectively. The current consumption is 27.7 mA from a 1.2 V supply voltage.

Key words: active; phase shifter; vector sum; LO; CMOS

DOI: 10.1088/1674-4926/36/1/015002 EEACC: 2570

sum active phase shifter. Thus, the variation needs to be elim-

1. Introduction
inated to achieve low phase shift error.
Phased array systems are adopted not only to satisfy the In this paper, in order to reduce the phase shift error, a
stringent link budget requirements but also to steer the antenna LO phase shifter using a new vector sum method is presented.
beam direction electrically to suppress undesired signals. Phase The LO phase shifter achieves 5-bit (11.25ı per LSB) phase
shifters are essential elements in the phased array system for shift resolution for 9–12 GHz applications. The chip is com-
beam-forming. The phase shifter can be implemented in var- posed of a RC-based poly-phase filter (PPF), four 3-bit (45ı
ious locations in the phased array system, including the RF per LSB) sub-phase shifters and a down-conversion mixer. The
signal path, LO path, IF path and basebandŒ1 . The main ad- chip is designed in TSMC 0.13-m RF CMOS technology. In
vantage of the LO phase shifting is that the phase shifter is not Section 2, the linearity and drain-source voltage variation in
placed on the signal path, so that the system performance does quadrature vector sum active phase shifter is analyzed first, and
not suffer from the poor gain, noise, or linearity of the phase then the new proposed vector sum method and the system ar-
shifter. chitecture are described. Section 3 presents the detailed circuit
LO phase shifting can be realized using a multi- level descriptions of all building blocks. Section 4 describes
phase LOŒ2 , injection-locked voltage-controlled oscillator (IL- the measured results, followed by the conclusion in Section 5.
VCO)Œ3 , delay cellŒ4 or vector sum active phase shifterŒ5 . Per-
forming the phase shifting using a multi-phase LO requires a
huge chip area and high power consumption, especially for 2. New vector sum method and system architec-
high phase shift resolution. An injection-locked VCO could ture
achieve a very low phase shift error using automatic phase tun-
ing algorithm, however, the tuning circuit limits the resolution 2.1. Quadrature vector sum active phase shifter
of the phase shift and takes up a large chip area. The phase
shifter based on delay cell could achieve very high resolution A quadrature vector sum active phase shifter is based on
but is not suitable for high frequency applications. Compared I/Q vector combination. The desired output is obtained by com-
to previous techniques, vector sum active phase shifter has ad- bining In-phase and Quadrature-phase signals with appropri-
vantages in terms of chip size, power consumption and the flex- ate magnitude and polarity. Figure 1 shows a schematic of the
ibility of the operating frequency. Previous work on the vector quadrature vector sum phase shifterŒ6 , which consists of two
sum active LO phase shifter has achieved limited performance. variable gain amplifiers (VGAs) to modulate the magnitude
Quadrature vector sum active phase shifters with high inte- and the polarity of the I- and Q-input signal, respectively, and
gration level, high resolution, and wide operating frequency a shared active inductor load where the output currents from
have been proven for RF phase shiftingŒ6 8 . It is convenient I- and Q-VGA are added. A current steering DAC is used to
to design a LO phase shifter based on quadrature vector sum change the bias current of the I- and Q-VGA so that the output
method. However, with large input power, the linearity varia- phase can be controlled digitally. Since the gain is dependent
tion caused by the tuning of the bias current during phase shift on the bias current, the voltage gain of this phase shifter is ap-
will deteriorate the phase shift error of the quadrature vector proximated as Equation (1), and the output phase is given as

* Project supported by the National Natural Science Foundation of China (No. 61376037) and the National Twelve-Five Project (No. 513***).
Ž Corresponding author. Email: [email protected]
Received 17 June 2014, revised manuscript received 25 August 2014 c 2015 Chinese Institute of Electronics

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Figure 1. Schematic of the quadrature vector sum active phase shifterŒ6 .

Equation (2).
q
AV D A2I-VGA C A2Q-VGA
r
W

D 2n Cox II-VGA C IQ-VGA Zload ; (1)
L
s
AQ-VGA IQ-VGA
 D arctan D arctan ; (2)
AI-VGA II-VGA
where AI-VGA and AQ-VGA are the voltage gains of the I-VGA
and Q-VGA, respectively, II-VGA and IQ-VGA are the bias cur-
rents of the I-VGA and Q-VGA, respectively, Zload is the active
inductor load shared by VGAs, n is the electron mobility, Cox Figure 2. The P1dB of the I-VGA with  D 0ı and  D 45ı .
is the oxide capacitance, and W=L is the size of input transis-
tors (M1–M8).
From Equation (2), it is known that the phase shift is ob- In Figure 2, L1 is the input-output response curve of the I-
tained by changing the bias current ratio of the I- and Q-VGA. VGA with  D 0ı , Pin0; 1dB is the 1 dB compression point. L2
Since the DAC’s output current (IDACC C IDAC / is constant, is the ideal response curve with  D 45ı , while L3 is the real
according to Equation (1), the voltage gain keeps constant response curve with  D 45ı . From Figure 2, it is known that
among different output phases, resulting of zero gain error the- the I-VGA’s voltage gain under 45ı phase shift represented by
oretically. L2 is 3 dB smaller than the voltage gain under 0ı phase shift
Since the linearity of the input differential pair is propor- represented by L1, leading to a constant output magnitude be-
tional to its bias currentŒ9 , the 1 dB compression points (P1dB / tween 0ı and 45ı phase shift. However, since the P1dB ’s drop
of the I- and Q-VGA vary among different output phases. The by 3 dB, the real voltage gain under 45ı phase shift represented
P1dB of I-VGA can be given as: by L3 is .3 C G/dB smaller than the voltage gain under 0ı
v phase shift represented by L1, leading to G dB gain error be-
u 1:16II-VGA
Pin; 1dB D u t : (3) tween 0ı and 45ı phase shift. Obviously, with the increase of
W the input power, the gain error could increase to several dB. In
n Cox
L addition, the changing of the bias current will cause the vari-
When  D 0ı , according
to Equation (2), the II-VGA ation of the drain–source voltage VDS of the input transistors
equals to k II-VGA C IQ-VGA and reaches its maximum value, M1–M8 and the tail transistors MI and MQ. In deep submicron
leading to the best P1dB of the I-VGA among all output technology, as the accuracy of the input transistor’s transcon-
phases. When  D
45ı , both II-VGA and IQ-VGA equal to ductance and the tail transistor’s current matching vary notably
0:5k II-VGA C IQ-VGA , resulting of P1dB ’s 3 dB smaller than at different VDS , the gain and phase error of this phase shifter
 D 0ı . Figure 2 shows the P1dB of the I-VGA with  D 0ı will further deteriorate.
and  D 45ı . Figure 3 shows the simulated gain and phase difference

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Figure 5. Generating an 11.25ı vector using (a) quadrature vector sum

and (b) new vector sum method.

Figure 3. Simulated gain and phase difference between 0ı and 45ı

versus input power.

Figure 6. Realizing the variable gain function (a) by adjusting bias

current and (b) by switching on/off parallel input transistors.

vector sum method consists of four 3-bit sub phase shifters, the
Figure 4. The sum of two vectors.
requirement on the resolution of the VGA is reduced, which is
helpful to eliminate the linearity variation.
To keep a constant linearity, the VGA structure in Fig-
between 0ı and 45ı versus input power of the quadrature vector ure 1, obtaining the variable gain function by adjusting bias
sum active phase shifter. With the increase of the input power, current, can be replaced by another VGA structure, which re-
both the gain and the phase difference are degraded gradually. alizes a variable gain by switching on/off parallel input tran-
Thus, the quadrature vector sum active phase shifter is not a sistors with constant gate-source voltage and drain-source volt-
good choice for LO path phase shift. age, as shown in Figure 6. In this VGA structure, the number of
parallel input transistors and switches is proportional to the res-
2.2. New vector sum method olution of the phase shifter. To implement a 5-bit phase shifter,
at least 32 parallel input transistors and switches are needed,
At first, let us consider the sum of two vectors, which have which will form a very large parasitic capacitance at the output
the same magnitude A0 and different phase 1 and 2 , respec- node. Since the parasitic capacitance Cpar is difficult to drive
tively, as shown in Figure 4, the output vector is given as: at high frequency, the new vector sum method is adopted to
1 C 2 j.1 C2 /=2 reduce the requirement on the resolution of the VGA, resulting
VOUT D A0 ej1 C A0 ej2 D 2A0 cos e : (4) in less parallel input transistors and a lower parasitic capaci-
2 tance in the sub 3-bit phase shifter. Therefore, the new vector
According to Equation (4), a high resolution vector can be sum method is used in this paper to implement a 5-bit active
generated by summing two low resolution vectors together. For LO phase shifter with constant linearity.
example, 11.25ı output of the 5-bit phase shifter could be ob- Assuming that the magnitudes of the four vectors in Fig-
tained by adding a 0ı vector and a 22.5ı vector together. For a ure 5(b) are 1/4, the combination of the four vectors is given
constant resolution of the phase shifter, as the number of vec- as:
4
tors to be summed is increased, the requirement on the resolu- 1 X jn 1p 2
VOUT D e D ˛ C ˇ 2 †; (5)
tion of the vector decreases. Thus, 5-bit output vectors of the 4 nD1 4
5-bit phase shifter could be generated by summing four 3-bit
vectors, which could be provided by four 3-bit phase shifters. ˛ D cos 1 C cos 2 C cos 3 C cos 4 ; (6)
Generating the 11.25ı vector of the 5-bit phase shifter
using quadrature vector sum method and new vector sum ˇ D sin 1 C sin 2 C sin 3 C sin 4 : (7)
method are presented in Figures 5(a) and 5(b), respectively.
In Equation (5), n is the output phase of the nth sub phase
In the quadrature vector sum method, a high resolution VGA
shifter. The output phase of the 5-bit phase shifter is given as:
is needed to adjust the magnitude of the I/Q signals to obtain
the 5-bit resolution. Compared to the quadrature vector sum ˇ
active phase shifter, since the 5-bit phase shifter using the new  D arctan : (8)
˛

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Table 1. The synthesis of the 9 phase states in the first quadrant.

Vectors adding together
Desired output 1 ı 1 ı 1 ı Theoretical output Gain error (dB) Phase error
4 †0 4 †45 4 †90
1†0ı 4 0 0 1†0ı 0 0
1†11:25ı 3 1 0 0:94†10:8ı 0.54 0.45
1†22:5ı 2 2 0 0:92†22:5ı 0.72 0
1†33:75ı 1 3 0 0:94†34:2ı 0.54 0.45
1†45ı 0 4 0 1†45ı 0 0
1†56:25ı 0 3 1 0:94†55:8ı 0.54 0.45
1†67:5ı 0 2 2 0:92†67:5ı 0.72 0
1†78:25ı 0 1 3 0:94†79:2ı 0.54 0.45
1†90ı 0 0 4 1†90ı 0 0

Figure 7. System architecture.

When 1 D 2 D 3 D 0ı and 4 D 45ı , the output can The system is composed of a quadrature signal generator,
be given as: four 3-bit sub phase shifters, a down-conversion mixer with
multiple LO switches, and a shift register (REG). The quadra-
1 1
VOUT D 3  †0ı C †45ı D 0:94†10:8ı : (9) ture signal generator converts the differential input LO signals
4 4 into quadrature LO signals, which are provided to the 3-bit sub
The result in Equation (9) is very close to the ideal 11.25ı phase shifters as their inputs. The down-conversion mixer is
vector in the 5-bit phase shifter. Thus, the proposed method can designed with four pairs LO switches. Four output signals of
achieve a 5-bit resolution. The synthesis of the 9 phase states the four 3-bit sub phase shifters are fed into the four pairs LO
in the first quadrant are shown in Table 1, and the remaining 23 switches, respectively, where four LO signals mix with the RF
phase states (32 phase states in total for a 5-bit phase shifter) signal, and then four IF signals are summed at the output load
can be achieved by simply changing the polarity of the vectors to accomplish the phase shift. The shift register is designed to
in Table 1. control the output phases of the four 3-bit sub phase shifter with
From Table 1, it is known that this new vector sum method an off-chip micro control unit (MCU).
will inherently bring some gain and phase errors. According
to the root mean square (RMS) error functionŒ6 , the inherent
RMS gain error and RMS phase error are 0.15 dB and 0.32ı ,
3. Circuit design
respectively. Since the new vector sum method could avoid the 3.1. Quadrature signal generator
problems mentioned above, the sacrifice of the gain and phase
error is acceptable. The passive PPF has the advantage of high integration and
The 5-bit active LO phase shifter is designed using the pro- straightforward implementation. Moreover, if we assume that
posed vector sum method. The system architecture is shown in the In-phase output port and the Quadrature-phase output port
Figure 7. have the same load, then the PPF’s amplitude and phase accu-

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To obtain the transfer function of the RC-based two stage PPF
with the consideration of its load shown in Figure 8. The chain
matrix for the single stage PPF in Equation (10) is cascaded
to achieve the chain matrix for two stage PPF and the Iout; k is
replaced by YL Vout; k to take the load into account. Considering
that the In-phase output port and the Quadrature-phase output
port has the same load and YL is the admittance of the load, the
In-phase VoiC and the Quadrature output VoqC of the PPF can
be given as:

1 C ! 2 R1 R2 C1 C2 j .!R1 C1 C !R2 C2 /
VoiC D Vin ;
˛
(11)
Figure 8. Topology of the RC-based two-stage poly phase filter.


1 C ! 2 R1 R2 C1 C2 C j .!R1 C1 C !R2 C2 /
VoqC D Vin ;
˛
(12)

˛ D .1 C sR1 C1 / .1 C sR2 C2 / C 2sR1 C2

C YL ŒR1 C R2 C sR1 R2 .C1 C C2 / ; (13)

where Vin is the magnitude of the input of the PPF. We can get
this as follows:

VoqC 1 C ! 2 R1 R2 C1 C2 C j .!R1 C1 C !R2 C2 /
D
VoiC .1 C ! 2 R1 R2 C1 C2 / j .!R1 C1 C !R2 C2 /

Figure 9. Decomposition of the differential-phase inputs into two parts !R1 C1 C !R2 C2
1Cj
of quadrature-phase inputs. 1 C ! 2 R1 R2 C1 C2
D : (14)
!R1 C1 C !R2 C2
1 j
racy are completely insusceptible to its load. The major chal- 1 C ! 2 R1 R2 C1 C2
lenge of using PPF is the loss, which will degrade with the in- Thus, ˇ ˇ
crease of the PPF stage for wideband operation. In this work, a ˇ VoqC ˇ
ˇ ˇ
RC-based two-stage PPF is adopted as illustrated in Figure 8. ˇ V C ˇ D 1; (15)
oi
To minimize its loss, two differential inductors are added at the
output of the RC-based two-stage PPF. ˚

As illustrated in Figure 9, the differential-phase input of  D arctan 2 1 C ! 2 R1 R2 C1 C2 .!R1 C1 C !R2 C2 /
the RC-based PPF could be decomposed into two parts of h i 

2 1
quadrature-phase input with positive and negative sequence,  1 C ! 2 R1 R2 C1 C2 .!R1 C1 /2 .!R2 C2 /2 :
respectively. After the decomposition, the circuit topology of (16)
the PPF with two input ports is transferred into a PPF with four
input ports. The chain matrix of the PPF with four input ports From Equation (15), it is obvious that the magnitude of
in the dash box in Figure 9 for the positive and the negative I and Q outputs are equal over all the frequency bands. From
inputs is given asŒ10 : Equation (16), it is known that exact 90ı phase shift can be gen-
erated at ! D 1=R1 C1 and ! D 1=R2 C2 , which is supremely
    competent for wideband quadrature generation. More impor-
Vin; k 1 1 C sRC R
D tantly, the accuracy of this PPF is completely unaffected from
Iin; k 1 C ej sRC 2sC 1 C sRC
its load YL . However, the increase of the load YL will degrade
 
Vout; k the loss of the PPF. To minimize YL in Equation (13), and
 : (10) to decrease the loss of the PPF, two differential inductors are
Iout; k
adopted at the PPF’s outputs, as shown in Figure 8.
In Equation (10), Vin; k and Vout; k is the kth input voltage Since the PPF is operating at X-band, the two poles of
and kth output voltage of the PPF, respectively, Iin; k and Iout; k the PPF are placed at 9 GHz and 11 GHz, respectively, to
is the kth input current and kth output current of the PPF, re- achieve the lowest mismatch over the X-band, resulting to
spectively. If the input sequence is positive, then  equals to f1 D 1=2R1 C1 D 9 GHz and f2 D 1=2R2 C2 D 11 GHz.
90ı . If the input sequence is negative, then  equals to –90ı . The resistances and capacitances are finely optimized to obtain

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Figure 10. The post simulation results of the PPF. (a) The loss with and without output inductors. (b) I/Q amplitude and phase difference.

Figure 11. Schematic of the 3-bit sub phase shifter.

the best performance of the impedance matching and the loss,

and they are chosen as R1 D R2 D 100 , C1 D 177 fF and Table 2. Parameters of the 3-bit sub phase shifter.
C2 D 145 fF. The inductances are set as L D 990 pH to res- Parameter Value
onate with parasitic capacitances (255 fF) at the output nodes M1, M2, M7, M8 15 m/0.13 m
M3, M4, M9, M10 6 m/0.13 m
at 10 GHz. Figure 10(a) shows that the loss of the PPF is im-
M5, M6, M11, M12 9.9 m/0.13 m
proved by 6.5 dB at 10 GHz with output inductors. Figure 10(b) M13–M28 9 m/0.13 m
presents the simulation results of I/Q amplitude and phase dif- M29, M30 24 m/0.13 m
ference of the PPF. The amplitude error is less than 0.035 dB R1 , R2 700 
over the X-band, and the phase error is less than 1ı over the
X-band.
set to be constant, avoiding the variation of the linearity and
3.2. 3-bit sub phase shifter
drain–source voltage in the quadrature vector sum active phase
Figure 11 shows a schematic of the 3-bit sub phase shifter, shifter.
which converts the I- and Q-input voltages from the PPF into The 3-bit output phases are obtained by manipulating the
currents by the I-VGA and the Q-VGA, respectively, and adds voltage gain and the polarity of the I- and Q-VGA, which are
them together at the output node. The I-VGA and Q-VGA decided by the main cell and auxiliary cell. When the output
are both composed of two quasi-differential pairs, which are phase is 0ı , both the main cell and the auxiliary cell in the
called the Main cell and Auxiliary cell, respectively. The vari- I-VGA (Q-VGA is disabled) are switched on. When the out-
able gain function is achieved by switching on/off parallel in- put phase is 45ı , only the main cell in the I-VGA and Q-VGA
put transistors in the main cell and auxiliary cell separately. is switched on. Assuming that the voltage gain of the main
The gate biases of input transistors M1–M4 and M7–M10 are cell and the auxiliary cell is Amain and Aaux , then the ratio of

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Figure 12. Simulated gain and phase difference between 0ı and 45ı
versus input power. Figure 13. Simulated eight output phases of the 3-bit sub phase shifter.

Figure 14. Schematic of the down-conversion mixer.

Amain =Aaux is set to 5 : 2 to keep a constant output magnitude. by the four 3-bit sub phase shifters in the LO switches and then
Thus, the size ratio between input transistors in main cell and four output currents of the LO switches are summed and con-
auxiliary is decided. An active inductor load composed of R1 – verted into the output voltage at the resistor load. The mixer is
R2 and M29–M30 is adopted to save the chip area. M5–M6 designed using folded double-balanced active topology, which
and M11–M12 are added to maintain a constant dc current of is well-known for low voltage and design flexibility. The mixer
the active inductor load among all of the eight output phases. consists of gm -stage, LO switches and resistor load. The gm -
Table 2 gives the parameters of the 3-bit sub phase shifter. stage, which consists of M1–M4, is based on common-gate
Figure 12 shows the post-simulated gain and phase dif- amplifier to achieve a wideband input impedance matching by
ference between 0ı and 45ı versus input power of the pro- setting its transconductance appropriately. The differential in-
posed phase shifter. With 3 dBm input power, the gain error ductor L, resonating with the parasitic capacitance of the node
and the phase error of the proposed phase shifter is 0.35 dB and x and y in gm -stage, is used as the RF choke to form a high
1.2ı , respectively, which are 1.7 dB and 2.6ı smaller than the impedance from 9 to 12 GHz. Thus, most of the ac current of
quadrature vector sum active phase shifter. Figure 13 depicts the gm -stage will flow into the LO switches. The LO switches
all the output phases of the phase shifter from 9 to 12 GHz. (M5–M20), where frequency mixing takes place, is composed
of four PMOS switch pairs, each of which is driven by a 3-bit
3.3. Down-conversion mixer sub phase shifter. The gate dc bias of the LO switches is set at
Vdd Vthp to make PMOS switch pairs work on sub-threshold
The schematic of the down-conversion mixer is shown in region so that a low bias current (72 A for each PMOS tran-
Figure 14. The RF signal is mixed with four LO signals offered

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Figure 15. Chip photograph of the proposed phase shifter.

Figure 16. Measurement setup of the LO phase shifter.

Table 3. Parameters of the down-conversion mixer.

Parameter Value
M1, M2 36 m/0.13 m
M3, M4 28 m/0.4 m
M5–M20 24 m/0.13 m
L 955 pH
R1 , R2 600 
C1 , C2 1 pF

sistor) is obtained. Meanwhile, the usage of low LO amplitude

to achieve a complete current computation is allowed. The low
bias current of the LO switches also allows the load resistor to
consume a large IR drop, such that the conversion gain of the
mixer can be increased by using a larger resistance. Thus, the
resistances of R1 and R2 are set to 600 . Table 3 gives the
parameters of the down-conversion mixer.
Figure 17. Measured result of the RF input return loss.
4. Measurement results
The proposed 5-bit active LO phase shifter using a new conversion gain is 0:5 to 7 dB from 9 to 12 GHz. The peak-
vector sum method is fabricated in TSMC 0.13 m CMOS to-peak gain variation among 32 phase states is 6˙2 dB. The
technology. The chip photograph of the phase shifter is shown main sources of the gain variation are PPF’s amplitude and
in Figure 15. The core chip size is 640  660 m2 , and the phase error, and the input transistor mismatch in the 3-bit sub
overall chip size including PAD is 1.26  1.16 mm2 . The chip is phase shifter.
tested using a printed circuit board (PCB) with a chip on board Figure 19 shows the measured 5-bit phase responses from
(COB) package. The conversion gain and the 5-bit phase re- 9 to 12 GHz. The 0ı phase response is set as the reference that
sponses are measured using Agilent Vector Analyzer N5242A. is subtracted from the rest of 31 phase states (11.25ı , 22.5ı ,


,
Figure 16 shows the measurement setup, which consist of a net- 348.75ı ), resulting in constant phase shifts from 9 to 12 GHz.
work analyzer, off-chip baluns, an MCU, power supplies and Figure 19 proves the 5-bit phase shift ability of the proposed
the PCB. During the test, the IF frequency is fixed at 10 MHz, phase shifter.
the RF frequency is swept from 9.01 to 12.01 GHz, and the LO Figure 20 shows the measured root mean square (RMS)
frequency is swept from 9 to 12 GHz. The measured dc current gain error and RMS phase errorŒ6 of the proposed phase shifter
consumption is 27.7 mA from a 1.2 V supply voltage. from 9 to 12 GHz. The RMS gain error is less than 0.8 dB from
Figure 17 presents the measured result of the RF input re- 9 to 12 GHz, and the RMS phase error is less than 4ı from 9 to
turn loss, which is below 8:5 dB from 9 to 12 GHz. Since the 12 GHz. From Figure 20, it is known that the measured RMS
RF input reflection coefficient depends on the gm -stage in the error curves basically correspond to the simulated results, and
mixer, a changing phase does not affect the S11 characteristic this fact proves the feasibility of the proposed phase shifter.
of the RF input port. The deviation between the measured results and the simulated
Figure 18 presents the measured conversion gain of the ones could be caused by the mismatch of the transistors, the
mixer driven by the LO phase shifter. The measure average resistors, and the capacitors. Meanwhile, the off-chip compo-

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Figure 18. Measured conversion gain for 32 phase states. Figure 20. Measured RMS gain error and RMS phase error.

employed to overcome the PVT variation. In this 5-bit phase

shifter, the active inductor load rather than passive inductor
load is adopted in the 3-bit sub phase shifter to tradeoff the
chip area and the gain. However, the poor performance of the
active inductor under CMOS technology and low supply volt-
age limits the gain of the 3-bit sub phase shifter, resulting in
high power consumption when providing enough LO power for
the mixer. To reduce the power consumption without sacrific-
ing large chip area, a 1 : 4 transformer based power combiner,
which has been implemented in power combining power am-
plifiersŒ16 (PA), could be adopted in the LO phase shifter. The
primary windings of the power combiner are connected to the
four 3-bit sub phase shifters as their loads, while the secondary
windings are connected to the mixer to drive the LO switches.
Figure 19. Measured 5-bit phase responses. With the inductor load, the sub phase shifter could achieve the
same gain with less power consumption. Since the combination
is completed in the power combiner, only one pair of the LO
nents used to test the chip are non-ideal devices, which further switches is required in the mixer, resulting in the lower power
deteriorate the performance. Since the maximum RMS phase consumption of the mixer.
error is smaller than 0.5 LSB (5.625ı ) of 5-bit phase shift, the
5-bit accuracy of the proposed phase shifter is guaranteed.
5. Conclusion
A summary of the measured results and the comparison
with the current state-of-the-art phase shifters is listed in Ta- This paper presents a 5-bit active LO phase shifter with a
ble 4. The design in Reference [3], which is implemented us- new vector sum method for 9–12 GHz applications. The 5-bit
ing ILVCO, achieves only 4-bit of the phase shift resolution. phase shifter is composed of four 3-bit sub phase shifters by
Due to the increasing of the complexity of the tuning algorithm adopting the new vector sum method, which reduces the re-
in ILVCO, much more power and chip area will be consumed quirements on the resolution of the VGA. The variable gain
to achieve 5-bit resolution. The designs in References [6, 12, function is realized by switch on/off parallel input transistor
13] which are implemented, respectively, in SOI and BiCMOS pairs rather than changing the bias current of the VGA, which
technology with quadrature vector sum method, suffer from avoids the linearity variation and drain-source voltage variation
high cost, high supply voltage, and large phase error. Although that exist in the quadrature vector sum active phase shifter. To
the design in Reference [14] consumes the lowest power, it suf- verify the method, a 5-bit active LO phase shifter is designed
fers from high insertion loss under low operating frequency. and fabricated in TSMC 0.13 m CMOS technology. The mea-
From Table 4, it is known that the proposed design achieves sured results show that the phase shifter achieves 5-bit phase
low gain error and low phase error with low cost and low sup- shift accuracy. The average conversion gain for 32 phase states
ply voltage. is 0:5 to 7 dB from 9 to 12 GHz. The RMS gain error and the
Some work could be done to further improve the perfor- RMS phase error are smaller than 0.8 dB and 4ı , respectively.
mance of the phase shifter. Since the 5-bit resolution is suf- The current consumption of the phase shifter is 27.7 mA with
ficient for a common phased array system, the improvement a 1.2 V supply voltage.
will mainly focus on the phase shift error and power consump-
tion. Since the PPF is vulnerable to the PVT (process, voltage References
and temperature) variations and, therefore, degrades the phase
shift error, a PPF with self-calibration techniqueŒ15 could be [1] Yu Y, Peter G, Arthur H. Integrated 60 GHz RF beamforming in

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Table 4. Performance summary and comparison.

Parameter Reference [3] Reference [6] Reference [12] Reference [13] Reference [14] This work
Technology 65 nm CMOS 180 nm BiCMOS 180 nm BiCMOS 45 nm SOI 180 nm CMOS 130 nm CMOS
Supply voltage (V) 1.0 3.3 1.8 1.5 1.8 1.2
Architecture ILVCO Quadrature Quadrature Quadrature Quadrature New vector sum
vector sum vector sum vector sum vector sum
Freq (GHz) 42.7–49.5 6–18 15–35 40–70 0.75–2.67 9–12
Resolution (bit) 4 5 4 4 5 5
Gain (dB) NA 16.5–19.5 13:5 to 5 15 to 5 17:4 to 3.5 0:5 to 7
RMS gain error (dB) 0.4 1.1 2.2 1.2 0.74 0.8
RMS phase error (ı ) 0.93 5.6 13 11 7.2 4
Pdc (mW) 21.2 61.7 25.2 23 6.39 33.24
Size (mm2 / 0.7* 0.45* 0.19* 0.51 0.89 0.42*

*Core chip size

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