Machine Structure II

Chapter II
Sequential Logic Circuits

Presented by

BEN SI SAID KARIM

[email protected]
Copyright © Karim Ben Si Said L1 – INFO -2024/2025 1
 Chapter objectives

By the end of this chapter, you should be able to:

✓ Understand Sequential Logic – Differentiate between combinational and sequential circuits

✓ Differentiate between synchronous and asynchronous circuit : latch and flip-flops circuits RS, T, D and JK

✓ Analyze sequential logic circuits- Using state table, state equations and state diagrams

✓ Design sequential synchronous logic circuits- Using Flipflops and logic gates

✓ Understand, Design and analyze Registers and Counters

Copyright © Karim Ben Si Said L1 – INFO -2024/2025 2

 Chapter III Outlines

1. Introduction
2. Latch and flipflops
3. synchronous flipflops (RS, D, JK, T)
4. Registers
5. Sequential circuits analysis
6. Synchronous circuit synthesis
a) Moore and Mealy machines
b) State table and state diagram
7. Synchronous circuit design
a) examples
b) State reduction
8. Counters
a) synchronous counters
b) Ripple counters
9. Data storage and memories

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Chapter- 3: Sequential Logic circuits
Sequential logic- introduction
• Sequential logic systems are a fundamental component of digital electronic circuits, they
can be defined as combinational logic systems characterized by the incorporation of
memory elements, which allow them to store and recall information about past inputs.

• The outputs of a sequential circuit depend upon the present state of the inputs and the
values of stored bits in the memory unit.

• Memory elements, such as flip-flops, store binary

information in the present. They work together with
combinational circuits to change and save information,
deciding what the circuit will do next. Thus allows the
circuits to understand and react to new information while
keeping track of what happened before.

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Chapter- 3: Sequential Logic circuits
Sequential logic- Types
Sequential logic can be categorized into two main types: synchronous and asynchronous
circuits:

Synchronous Sequential Logic

The operation is synchronized by a clock signal. The circuit responds to changes in inputs or
triggers events only at specific instants defined by the clock signal. The clock signal ensures
that different components of the circuit change their states or perform actions at specific and
synchronized moments.
Advantages: Synchronous circuits are generally easier to design and analyze. The
predictable timing provided by the clock simplifies the synchronization of different
components.

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Chapter- 3: Sequential Logic circuits
Sequential logic- Types
Asynchronous Sequential Logic:

Asynchronous sequential logic, in contrast, doesn't rely on a global clock signal. The circuit
responds to changes in inputs or events as they occur, without being tied to a specific clock
cycle.

Advantages: Asynchronous circuits can potentially be more responsive and have a simpler
structure, as they don't need a global clock. However, they can be more challenging to
design and analyze due to the lack of a centralized timing mechanism.

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Chapter- 3: Sequential Logic circuits
Clock signal
• A clock signal is a periodic electrical signal that serves as a timing reference for synchronous digital
circuits, oscillates between two voltage levels (high and low) in a regular and repeating pattern. It
characterized by:
• Period T : The time taken for one complete cycle (from a rising edge to the next rising edge)
• Frequency f : It is the number of clock cycles per second, typically measured in Hertz (Hz), it
determines the rate at which operations within the circuit take place.
F = 1/T
• The rising (transition from low to high) or falling edge (transition from high to low) of the clock signal is
often used as a reference point for triggering events within the circuit.
• Clock signals can be generated by dedicated clock generators, crystal oscillators, or other precision
timing devices.

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Chapter- 3: Sequential Logic circuits
Clock signal- types of triggering
Triggering in digital circuits can occur based on either edges or levels of a signal:
Edge Triggering:
Rising Edge (▲): Actions occur when the signal transitions from low to high.
Falling Edge (▼): Actions occur when the signal transitions from high to low.
Commonly used in synchronous systems where events are synchronized with specific points in the clock signal.
Level Triggering:
High Level (─): Actions occur when the signal is consistently high.
Low Level (─): Actions occur when the signal is consistently low.
Found in certain asynchronous systems where events are triggered based on the continuous state of the
signal.

High level Low level rising edge falling edge

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Chapter- 3: Sequential Logic circuits
Clock signal- types of triggering
• The edge-triggering detection is accomplished using the circuit depicted in the following diagram.
• The clock signal is fed into one input of an AND gate through a NOT gate.
• Due to the delay introduced by the NOT gate, the signals Clk and Clk' are slightly shifted by several
nanoseconds.
• Consequently, the output of the AND gate produces a pulse, as illustrated in the timing diagrams.

Detected
Rising Edge

Copyright © Karim Ben Si Said L1 – MI -2024/2025 9

 Chapter III: Sequential Logic circuits

→ Latch and Flip-Flop

Copyright © Karim Ben Si Said L1 – MI -2024/2025 10

Chapter- 3: Latch and Flip-Flop
• A latch or flip flop is a digital logic element used to store a binary data. An element capable of
storing data is often called a memory.
• Latch and flip-flop are divided on two categories: synchronous and asynchronous

• Storage elements that operate with signal levels (rather than

signal transitions) are referred to as latches; those controlled by a
clock transition are flip-flops.

• Synchronous flip-flop systems use a global clock signal to

synchronize operations.

• Asynchronous systems operate independently of a clock signal,

responding directly to input changes.

• Synchronous circuits ensure precise timing but can be more

complex, while asynchronous circuits may be simpler but require
careful handling to avoid timing issues.

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Chapter- 3: Latch and Flip-Flop

→ Asynchronous latch circuits

A flip flop is a digital logic element used to store a binary data. An element capable of storing
data is often called a memory or latch.

Example:
The circuit of the following figure is called a latch.

• For this circuit, if we suppose initially that 𝐿𝑎𝑡𝑐ℎ 𝐶𝑜𝑚𝑚𝑎𝑛𝑑 = 0 𝑎𝑛𝑑 𝑄 = 0 the output
remains at Low level (0)
• When the latch input is forced HI (𝐿𝑎𝑡𝑐ℎ 𝐶𝑜𝑚𝑚𝑎𝑛𝑑 = 1), the output Q will go HI ⇒ 𝑄 = 1.
The feedback loop from the output to the input will cause the output Q to remain at HI
logic level even if the input goes LOW (𝐿𝑎𝑡𝑐ℎ 𝐶𝑜𝑚𝑚𝑎𝑛𝑑 = 0)
• Thus this latch is now latched (state memorized) and the command has no further effect

Copyright © Karim Ben Si Said L1 – MI -2024/2025 12

Chapter- 3: Latch and Flip-Flop

→ Asynchronous latch circuits

• The previous circuit is not very practical as the only way to unlatch the circuit is to remove
its power supply.
• To overcome this issue, the circuit is improved by using a pair of NOR or NAND gates.
• With this modification, there are mainly 3 Latches with two inputs each having the
following graphic symbols :

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Chapter- 3: Latch and Flip-Flop

→ Asynchronous latch circuits − RS Latch circuit

RS latch contains a pair of NOR gates having 2 inputs and 2 outputs:
• In this case, the S (Set) input forces the output Q to HI state: 𝑄 = 1
• When the input R (Reset or Clear) is HI, the output goes LOW: 𝑄 = 0
• When both inputs are LOW, the output of the flip-flop keeps it previous state (memorization).
• Setting both inputs to HI is forbidden.
The output Q’ is the complement of the output Q

Note:
The table used to describe the inputs RS
combinations and their resultant outputs is
referred to as a characteristic table, it is
similar to a truth table.
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Chapter- 3: Latch and Flip-Flop

→ Asynchronous latch circuits − RS Latch circuit

• Another type of RS flip-flop is developed also using NAND gates, it allows to Set (S) and
clear (R: Reset) the output using LOW level inputs.

➢ In this case, the S (Set) input is activated with the LOW state (0) and
forces the output Q to HI state: 𝑄 = 1 RS
FF
➢ When the input R (Reset or Clear) is LO, the output goes LO: 𝑄 = 0
➢ When both inputs are HI, the output of the flip-flop keeps it previous state.
➢ Setting both inputs to LO is forbidden
The output Q’ is the complement of the output Q

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Chapter- 3: Latch and Flip-Flop

→ Asynchronous latch circuits − Gated RS Latch

• A gated S-R latch requires an enable input En in addition to the set S and reset R inputs.
• The S and R inputs control the state to which the latch will go when a HIGH level is applied
to the EN input
• The gated latch is a level-sensitive device. In this circuit, the invalid state occurs when
both S and R are simultaneously HIGH and EN is also HIGH.

Example of inputs and outputs timing diagram

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Chapter- 3: Latch and Flip-Flop

→ Asynchronous latch circuits − Gated D-Latch

• A gated D latch has only one data input D, and used an enable input allowing to activate
the D-Latch when a high level is applied to En input.
• The D input is connected directly to the set (S) input, and through a NOT gate to the Reset
(R) input.
• When this latch is enabled (En = 1), the output Q = D
➢ D=0➔Q=0
➢ D=1 ➔Q=1 Example of inputs and outputs timing diagram

Copyright © Karim Ben Si Said L1 – MI -2024/2025 17

 Chapter III: Sequential Logic circuits

→ Synchronous Flip-Flop

Copyright © Karim Ben Si Said L1 – MI -2024/2025 18

Chapter- 3: Synchronous Flip-Flops

→ Synchronous Flip-Flops (FF)– definition

• The term synchronous means that the output changes state only at a specified point relative to the
clock on the triggering input called the clock (CLK)
• Flip-flops are edge-triggered or edge-sensitive whereas gated latches are level-sensitive:
✓ When a clock input in flip-flop symbols is depicted with nothing, it indicates high-level sensitivity.
✓ If represented with a bubble, it signifies low-level sensitivity.
✓ A triangle symbol denotes sensitivity to the rising edge of the signal.
✓ when both a triangle and a bubble are present, it indicates sensitivity to the falling edge of the clock signal

• The following symbols are used to designate the triggering type on the clock input

High level Low level rising edge falling edge 19

Chapter- 3: Synchronous Flip-Flops
→ Synchronous Flip-Flops– Commonly used FF

• The most common types of synchronous flip-flops are:

a. D Flip-Flop: The D flip-flop has a single data input (D) and two outputs (Q and Q'). The output (Q) follows the input (D)
when the clock (CLK) transitions from low to high (rising edge).
b. JK Flip-Flop: The JK flip-flop has two inputs (J and K) and two outputs (Q and Q'). It behaves similarly to the D flip-flop,
but it also has a toggle mode. When J and K are both high during the clock transition, the output toggles.
c. T Flip-Flop: The T flip-flop has a single input (T) and two outputs (Q and Q'). Similar to the JK flip-flop, when the input
(T) is high during the clock transition (from high to low in the example), the output toggles.
d. SR Flip-Flop: The SR flip-flop has two inputs (S and R) and two outputs (Q and Q'). It behaves similarly to the D flip-
flop, but it has a forbidden input combination (S=R= 1). When both inputs are low, the flip-flop holds its state.

• The following figures depict symbols representing various synchronous flip-flops.

set set
D Q J Q T Q S Q J Q S Q

ഥ ഥ
Q ഥ K ഥ
Q R ഥ
Q
Q K ഥ
Q R Q clr clr
20
Chapter- 3: Latch and Flip-Flop
→ Characteristic table
• In sequential logic, a Characteristic table is a tabular representation that outlines the relationship between
the present state, inputs, and the next state of the memory elements, such as flip-flops or latches.

• This table enumerates all possible combinations of inputs and current states, detailing the resulting state
changes. It provides a systematic way to analyze and understand the behavior of sequential circuits by
mapping out how they respond to different input conditions.

• In a characteristic table, the clock condition (rising edge, falling edge, or clock level) is assumed to be
established. We solely consider the inputs and present states to determine the future states.

Example: draw the Characteristic table, then write the characteristic equation for the of the D flip-flop

a. Characteristic QN D Q N+1 b. Characteristic equation

table
0 0 0 𝐐𝐍+𝟏=𝐃
0 1 1
1 0 0
1 1 1
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Chapter- 3: Latch and Flip-Flop

→ Synchronous Flip-Flops− RS Flip Flop

• A clock signal is applied to the “Clk” input, the outputs of the flip-flop change states as per
the inputs only on the occurrence of a clock pulse according to the following truth table.

Characteristic table of RS flip-flop

S R Q N Q N+1
0 0 0 0
0 0 1 1 Characteristic equations
0 1 0 0
0 1 1 0
1 0 0 1
S
Q 1 0 1 1
Clk 1 1 0 X
1 1 1 X
R ഥ
Q
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Chapter- 3: Latch and Flip-Flop

→ Synchronous Flip-Flops− RS Flip Flop

• Example: Draw the timing diagram of the output Q for these waveforms of the inputs R and S
of the RS flip-flop.
• This D flip-flop is triggered on every high level of the clock signal. Thus the outputs changes
according to the input R and S during the High Level on clock input, and keep their previous
values (memorization) during LOW level on the clock

S R Q N Q N+1
0 0 0 0
0 0 1 1 S
0 1 0 0
R
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X Copyright © Karim Ben Si Said L1 – MI -2024/2025 23
Chapter- 3: Latch and Flip-Flop

→ Synchronous Flip-Flops− D Flip Flop

• The D input of the D-FF is a synchronous input because data
on the input are transferred to the flip-flop’s output only on
the triggering edge of the clock pulse.

• The output of the D flip-flop changes to match the input D

specifically during the rising edge transitions of the clock
signal. Otherwise, the output retains its existing value from
the previous state.

Characteristic table of D-FF

Characteristic equations
D Q N Q N+1
0 0 0
0 1 0
1 0 1
1 1 1 Copyright © Karim Ben Si Said L1 – MI -2024/2025 24
Chapter- 3: Latch and Flip-Flop

→ Synchronous Flip-Flops− D Flip Flop

• Example:
Draw the timing diagram of the output Q of the D flip-flop for the following waveforms:

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Chapter- 3: Latch and Flip-Flop
→ Synchronous Flip-Flops− JK Flip Flop
• The J and K inputs of the J-K flip-flop are synchronous inputs because data on the
inputs are transferred to the flip-flop’s output only on the triggering edge of the
clock pulse:
➢ When J is HIGH and K is LOW, the Q output goes HIGH.
➢ When J is LOW and K is HIGH, the Q output goes LOW. Characteristic
table of JK-FF
➢ When both J and K are LOW, the output does not change from its prior state.
➢ When J and K are both HIGH, the flip-flop changes state. This called the J K QN Q N+1
toggle mode. 0 0 0 0
0 0 1 1
Characteristic 0 1 0 0
equations 0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
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Chapter- 3: Latch and Flip-Flop

→ Synchronous Flip-Flops− JK Flip Flop

Example: Draw the timing diagram of the output Q of the JK flip-flop for the following waveforms.
• This flip-flop is triggered with a falling edge of the clock, thus the state of the output is updated
only when the clock’s falling edge occurs

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 Chapter- 3: Latch and Flip-Flop

→ Synchronous Flip-Flops− T Flip Flop

• The T flip-flop, also called a toggle flip-flop, changes its output state when its single input (T)
is high and a clock pulse is applied.
• If the input is low, it maintains its current state. This flip-flop is commonly used in applications
where a binary signal needs to alternate between two states based on clock pulses.
• T flip-flop can be designed using a JK flip-flop by tying the JK inputs.
The truth table can be constructed using either of these two formats:

Characteristic table of T-FF

Characteristic
QN T Q N+1 equations
0 0 0 T Q
0 1 1 ഥ
Q
1 0 1
1 1 0 Copyright © Karim Ben Si Said L1 – MI -2024/2025 28
Chapter- 3: Latch and Flip-Flop
QN T Q N+1
→ Synchronous Flip-Flops− Summary
0 0 0
D Q N Q N+1 0 1 1
T Q
0 0 0
1 0 1
0 1 0 ഥ
Q
1 1 0
1 0 1
1 1 1
J K QN Q N+1

S R Q N Q N+1 0 0 0 0

0 0 0 0 0 0 1 1

0 0 1 1 0 1 0 0

0 1 0 0 0 1 1 0

0 1 1 0 1 0 0 1

1 0 0 1 1 0 1 1

1 0 1 1 1 1 0 1

1 1 0 X 1 1 1 0

1 1 1 X 29
Copyright © Karim Ben Si Said L1 – MI -2024/2025
Chapter- 3: Latch and Flip-Flop

→ Asynchronous Preset and clear inputs

• Some flip-flops have in addition to synchronous data inputs, asynchronous
inputs such as preset and clear
• These inputs affect the state of the flip-flop independent of the clock, usually
labeled preset (PRE ) and clear (CLR ),
• An active level on the preset input will set the flip-flop, and an active level on
the clear input will reset it.
Example:

When the PRE input is activated (LOW), the output

Q is set to HIGH, independent of the clock and the
input D

When the CLR input is activated (LOW), the output

Q is cleared (LOW) independent of the clock and
the input D
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Chapter- 3: Latch and Flip-Flop

→ Asynchronous Preset and clear inputs

Example 2
• When the PRE input is activated (LOW), the output Q is set to HIGH, independent of the clock and the inputs
J and K
• When the CLR input is activated (LOW), the output Q is cleared (LOW) independent of the clock and the
inputs J and K
• When PRE and CLR inputs are disabled (HIGH), the output Q depends on the J and K inputs synchronized by
the falling edge of the clock signal.
Clk
J
PRE
K
PRE
CLR
CLR
Q
Copyright © Karim Ben Si Said L1 – MI -2024/2025 31
 Chapter III: Sequential Logic circuits

→ Sequential circuits analysis

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Chapter- 3: Sequential circuit design and analysis

→ Introduction– circuit analysis

• Analysis describes the behavior of a clocked circuit under certain conditions. This behavior is
determined from the inputs, outputs, and the states of the memory element (flip-flops).
• Analyzing a sequential circuit involves acquiring either a table or a diagram that illustrates the
chronological sequence of inputs, outputs, and internal states. Additionally, It is also possible to
write Boolean expressions to depict the behavior of the sequential circuit.

• A sequential circuit may have a Moore machine or Mealy machine behavior.

• Both Moore and Mealy machines are types of finite state machines (FSMs) used in digital logic
design. The choice between Moore and Mealy machine behavior depends on the specific
requirements and constraints of the circuit's functionality.

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Chapter- 3: Sequential circuit design and analysis

→ Introduction– circuit analysis

• Moore machines have outputs associated with
states, and output changes occur synchronously
with state transitions.
• Mealy machines have outputs associated with state
transitions, and output changes can depend on both
the current state and the inputs.

Moore machines are often preferred for simpler designs with less complex output behavior, while Mealy
machines are more flexible and can handle situations where output behavior depends on both state and input
conditions. In the remaining of this course, we will use Mealy machine.

When drawing the state diagram, output

values are incorporated as follow, depending
on type of the machine

Moore
Copyright © Karim Ben Si Said Machine
L1 – MI -2024/2025 Mealy Machine 34
Chapter- 3: Sequential circuit design and analysis

→ circuit analysis– example

• The analysis goes from a circuit diagram to state A
equations, then state table to state diagram

• To explain the steps of the analysis, let’s take the

following circuit diagram as example
B
Note: This circuit has two D-flipflops, one input X and one
combinational output Y

• Step1:
write the FF-input equation: The equations at the
inputs DA and DB in function of An, Bn, and X.

𝐷𝐴 = 𝐴𝑛. 𝑋 + 𝐵𝑛. 𝑋
𝐷𝐵 = 𝐴𝑛 . 𝑋

X, and Y are the input-output respectively

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Chapter- 3: Sequential circuit design and analysis

→ circuit analysis– example A

• Step2: Write the state equations:

The equations at the outputs of the FlipFlops (An+1), (Bn+1)

and the possible circuit outputs (Y) B
𝐴𝑛 + 1 = 𝐷𝐴 … . (3)
𝐵𝑛 + 1 = 𝐷𝐵 … . (4)
𝑌 = 𝑋 ’ (𝐴𝑛 + 𝐵𝑛) … . (5)
Substitute the values of DA and DB found in step1 in equations
Note:
(3) and (4); thus, the state equations are: We consider the presence of a rising edge clock:
• between two edges we have An,
𝐴𝑛 + 1 = 𝐴𝑛. 𝑋 + 𝐵𝑛. 𝑋 • An+1 coming in the next edge.
𝐵𝑁 + 1 = 𝐴𝑛 . 𝑋
𝑌 = 𝑋ഥ (𝐴𝑛 + 𝐵𝑛)

An An+1
Copyright © Karim Ben Si Said L1 – MI -2024/2025 36
Chapter- 3: Sequential circuit design and analysis
→ circuit analysis– example
• Step3: Elaborate the state Table: Method-1
Fill up (using the state equations) the table containing the inputs (X), the present states of the FF
(An and Bn), and the future states of the FF (An+1 and Bn+1) in addition to the circuit output (Y).
inputs Outputs
The table containing :
- as inputs (the input X, and the present state of the FF: An, Bn)
- As outputs: - The future states of the FF (An+1 and Bn+1)
- The circuit’s other outputs (Y)
An Bn X An+1 Bn+1 Y
Notes: - The values in columns AN+1, BN+1 and Y of the table are
computed using state equations found in step-2

𝐴𝑛 + 1 = 𝐴𝑛. 𝑋 + 𝐵𝑛. 𝑋
𝐵𝑁 + 1 = 𝐴𝑛 . 𝑋
𝑌 = 𝑋ഥ (𝐴𝑛 + 𝐵𝑛)

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Chapter- 3: Sequential circuit design and analysis 𝐴𝑛 + 1 = 𝐴𝑛. 𝑋 + 𝐵𝑛. 𝑋
→ circuit analysis– example 𝐵𝑁 + 1 = 𝐴𝑛 . 𝑋
𝑌 = 𝑋ഥ (𝐴𝑛 + 𝐵𝑛)
• Step3: Elaborate the state Table: Method-2
The state table can be completed without directly computing the state equations (An+1 and Bn+1). Instead,
by using the flip-flop inputs as intermediate columns, the next state values (An+1, Bn+1) can
be determined based on the current state (An, Bn)
inputs intermediate Outputs
and the corresponding flip-flop inputs (DA, DB). columns

Present FF Next
Thus, two characteristic tables for the D flip-flops are formed: input output
state Inputs state
➢ DA flip-flop values are highlighted in blue. AN BN X DA DB AN+1 BN+1 Y
➢ DB flip-flop values are highlighted in purple. 0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 0 0 0 0 1
Notes: - The characteristic table of D-FF: 0 1 1 1 1 1 1 0
An DA An+1 1 0 0 0 0 0 0 1
0 0 0 1 0 1 1 0 1 0 0
0 1 1 1 1 0 0 0 0 0 1
1 0 0 1 1 1 1 0 1 0 0
1 1 1 38
Copyright © Karim Ben Si Said L1 – MI -2024/2025
Chapter- 3: Sequential circuit design and analysis
→ circuit analysis– example
• Step3: Elaborate the state Table:

Another common approach is to group present and future states based on the input value (x = 0
and x = 1). Both forms of state tables are valid and can be used.

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Chapter- 3: Sequential circuit design and analysis

→ circuit analysis– example

Step4: Draw the state diagram
• state diagram is a graphical representation of the sequential
circuit with circles representing each a state, and arrows
representing the transition between states.
• There are two possible representation: Maely and Moore. Mealy
is more flexible, thus, we will use it.

• For the Maely representation, the value of states are written inside Example: state Diagram for a
the circles and above the arrows representing the transitions, we transition from 01 to 11 with
write the Inputs / outputs combinations. input x=1 and output y =0
• The number of states depends often on the number of flip-flops

AB

Moore Machine Copyright © Karim Ben Si Said L1 – MI -2024/2025 40

Mealy Machine
Chapter- 3: Sequential circuit design and analysis

→ circuit analysis– example

→ –Step4: Draw the state diagram

Thus, From the state table the state diagram is given bellow:

• The number of states depends on the numbers of FF

• Each arrow point toward one transition direction. The

number of arrows is equal to the number of transitions
(rows in the state table).

• When a memorization occur, an arrow around the same

state is drawn : example: The first state of the table; the
transition from present state 00 to the same state 00
when the input = 0 and the output = 0.
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Chapter- 3: Sequential circuit design and analysis

→ Introduction– circuit analysis- Example 2

Analyze the following circuit:
1- Write the FF input equations from the logic circuit 𝐷𝐴 = 𝐴𝑁  𝑥  𝑦 . . (1)

2- Write the outputs (state) equations: intermediate

inputs columns Outputs
– future states of the Flipflop outputs 𝐴𝑛 + 1 = 𝐷𝐴 = 𝐴𝑁  𝑥 𝑦 . . (2)
- Other output equations 𝑍 = 𝐴𝑛. 𝑋 + 𝑌 . . (3)
FF FF
FF
Present inputs Next outputs
3- Elaborate the state table: The table containing : Inputs
state state
- as inputs (the inputs e.g. X, Y, and the present state of the FF: An) AN X Y DA AN+1 Z
- as intermediate columns: The FF inputs 0 0 0 0 0 0
- As outputs: - The future states of the FF (An+1) 0 0 1 1 1 0
- the other outputs (Z)
0 1 0 1 1 0
0 1 1 0 0 0
Notes: - The values in columns DA, AN+1, and Z of the table are computed using 1 0 0 1 1 0
Equations (1), (2), and (3), respectively OR using the intermediate columns 1 0 1 0 0 1
and the D-FF characteristic table.
1 1 0 0 0 1
Copyright © Karim Ben Si Said L1 – MI -2024/2025 1 1 1 1 1 42 1
Chapter- 3: Sequential circuit design and analysis

→ Introduction– circuit analysis

4- Draw the state diagram from the state table
- With one FF, the previous logic circuit will switch between two
possible states of the FF-output (0 or 1)
- Draw these states as circles
- Draw arrows between present state AN and future state AN+1 FF
FF
FF
Present inputs Next outputs
- Each arrow represents a transition (row within the table) Inputs
state state
- Above each arrow, the values of inputs/outputs combinations are AN X Y DA AN+1 Z
written 0 0 0 0 0 0
- In this example, each transition is represented with a specific 0 0 1 1 1 0
color
0 1 0 1 1 0
0 1 1 0 0 0
1 0 0 1 1 0
1 0 1 0 0 1
1 1 0 0 0 1
1 1 1 1 1 1
Copyright © Karim Ben Si Said L1 – MI -2024/2025 43
Chapter- 3: Sequential circuit design and analysis b. State
b. State equation
equation:
𝐀𝐍 + 𝟏 = 𝐀𝐍  𝐱  𝐲
→ circuit analysis– example 3
Analyze the following circuit and draw its state diagram.
• A slash on the directed lines is not needed, because there is
no output from a combinational circuit.
• The two inputs can have four possible combinations for each
state.
• Above each arrow, two input combinations during each state
transition are separated by a comma to simplify the notation c. State table

d. State diagram
a. Circuit diagram Copyright © Karim Ben Si Said L1 – MI -2024/2025 44
Chapter- 3: Sequential circuit design and analysis

→ circuit analysis– Example4

Analyze the following circuit and draw its state diagram.
a. Circuit diagram

Copyright © Karim Ben Si Said L1 – MI -2024/2025 45

Chapter- 3: Sequential circuit design and analysis
a. Circuit diagram
→ circuit analysis– example 4
Let’s analyze this circuit and draw its state diagram.
b. State equation
• Characteristic equation of D-FF and JK-FF
𝐵𝑁 + 1 =
𝐷 … . (eq1)
ഥ 𝐴𝑁 … . (eq2)
𝐴𝑁 + 1 = 𝐽 𝐴 𝑁 + 𝐾 c. State table format 1

• The input equations of the FF are: Present Next state

state X=0 X=1
𝐽𝐴 = 𝑥 + 𝐵 𝑁 , 𝐾𝐴 = 𝐴𝑁. 𝐵𝑁 , 𝐷𝐵 = 𝑥 Bn An Bn+1 An+1 Bn+1 An+1
• By substituting the values of JA and KA from the input 0 0 0 0 1 1
equations in state equation 2 and 1, we obtain: 0 1 0 1 1 1
BN + 1 = D = x
1 0 0 1 1 1
AN + 1 = X + BN AN + 𝐴𝑁. 𝐵𝑁. AN 1 1 0 0 1 0
AN + 1 = AN. 𝑋 + (𝐴𝑁𝐵𝑁) Copyright © Karim Ben Si Said L1 – MI -2024/2025 46
Chapter- 3: Sequential circuit design and analysis a. Circuit diagram
→ circuit analysis– example 4
Including FF-inputs in the state table
• Instead of calculating the state equations, it is
preferable in certain cases to include the FF-inputs
in the state table to find the future outputs of the FF c. State table fomat2
Present Flip flops
input Next states
states Inputs
• The input equations of the FF are:
X BN AN DB JA KA BN+1 AN+1
𝐷𝐵 = 𝑥
0 0 0 0 0 0 0 0
𝐽𝐴 = 𝑥 + 𝐵𝑁 , 𝐾𝐴 = 𝐴𝑁. 𝐵𝑁 0 0 1 0 0 0 0 1
0 1 0 0 1 0 0 1

 0
1
1
0
1
0
0
1
1
1
1
0
0
1
0
1
1 0 1 1 1 0 1 1
1 1 0 1 1 0 1 1
1 1 1 1 1 1 1 0
c. State table format 1
Copyright © Karim Ben Si Said L1 – MI -2024/2025 47
Chapter- 3: Sequential circuit design and analysis c. State table
→ circuit analysis– example 4
From the state table, the state diagram is drawn.

d. State diagram

Note: Looking at this state diagram, it’s obvious that:

• There are two stable states: 00 and 01 when the input x=0.

• There is a denied transition from states 00 to 01 and vice versa.

• This circuit alternates between states 10 and 11 for an input x=1.

Simulation Copyright © Karim Ben Si Said L1 – MI -2024/2025 48

Chapter- 3: Sequential circuit design and analysis

→ circuit analysis– Exercise

Analyze the following circuits

Copyright © Karim Ben Si Said L1 – MI -2024/2025 49

 Chapter III: Sequential Logic circuits

→ Sequential circuits design

Copyright © Karim Ben Si Said L1 – MI -2024/2025 50

Chapter- 3: Sequential circuit design

→ Sequential circuit design–introduction

• A sequential circuit can be defined by a word description, its circuit diagram, its state table or its
state diagram.
• The goal of designing a synchronous sequential circuit is to determine the logic circuit using flip-
flops and logic gates.
• Sequential circuit design or synthesis goes through certain steps:
1. From the word description and specifications of the desired operation, derive a state diagram for the
circuit.
2. Reduce the number of states if necessary.
3. Assign binary values to states (pure binary, Gray, or one-hot) if not already assigned.
4. Obtain the binary-coded state table.
5. Choose the type of flip-flops to be used and add excitation tables to the state table.
6. Derive the simplified flip-flop input equations and output equations.
7. Draw the logic diagram.
Copyright © Karim Ben Si Said L1 – MI -2024/2025 51
Chapter- 3: Sequential circuit design
→ Sequential circuit design–Example1
Design the sequential circuit defined by the following state diagram using JK-FF, then D-FF.
1. State table:
• This sequential circuit contains 4 bubbles (each bubble represents a state), 1 input and 1 output.
• With 4 states, such circuit needs 2 Flip-Flops (A and B)

• The FF combinations 00, 01, 10 and 1 1

Reminder:
Mealy Machine

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Chapter- 3: Sequential circuit design
→ Sequential circuit design–Example1
1. State table:(design with D-FF)
The state table of this circuit contains the input X, the output Y in addition to the present and next
states of the flipflops
- Each row in the table represents a transition (arrow)
in the state diagram. Present
input
Next
output
state state
AN BN X AN+1 BN+1 Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 0 0
1 0 0 0 0 1
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1

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Chapter- 3: Sequential circuit design
→ Sequential circuit design–Example1
2. Excitation table (design with D-FF)
After drawing the state table containing the present and next flip-flop outputs, the next step is to
determine the flip-flop inputs that allow these transitions from present to next states. It is called
“Excitation table”
Present Next
The excitation table of DA-FF indicates the state
input
state
output Excitation table
values of flip-flop inputs that led to this output AN BN X AN+1 BN+1 Y DA DB
transition from state AN to AN+1. 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 1
0 1 0 0 0 1 0 0

AN AN+1 DA 0 1 1 1 0 0 1 0
1 0 0 0 0 1 0 0
0 0 0
1 0 1 1 1 0 1 1
excitation table
0 1 1 1 1 0 0 0 1 0 0
Of D-Flipflop
1 0 0 1 1 1 1 1 1 1 1

1 1 1
54
Copyright © Karim Ben Si Said L1 – MI -2024/2025
Chapter- 3: Sequential circuit design
→ Excitation table-Definition
• In sequential logic, an excitation or transition table is a table that lists the present state, the desired next
state as inputs and the flip-flop inputs (J, K, D, etc.) required to achieve that as outputs.

• The goal here is to find the flip-flop inputs that led to this output transition from state QN to QN+1

• When the required input can be ‘1’ or ‘0’, we put an ‘X’ for the input

Example : Let’s draw the excitation table of the JK flip-flop

QN QN+1 J K QN QN+1 J K
0 0 0 0 or 1 => X 0 0 0 X
0 1 1 0 or 1 => X  0 1 1 X
1 0 0 or 1 => X 1 1 0 X 1
1 1 0 or 1 => X 0 1 1 X 0

Copyright © Karim Ben Si Said L1 – MI -2024/2025 55

Chapter- 3: Sequential circuit design
→ Excitation table
With the same procedure, the excitation table of the RS, D, and T flip-flops are drawn.

QN QN+1 S R QN QN+1 D QN QN+1 T QN QN+1 J K

0 0 0 X 0 0 0 0 0 0 0 0 0 X
0 1 1 0 0 1 1 0 1 1 0 1 1 X
1 0 0 1 1 0 0 1 0 1 1 0 X 1
1 1 X 0 1 1 1 1 1 0 1 1 X 0

S Q D Q

ഥ ഥ
Q
R Q

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Chapter- 3: Sequential circuit design
→ Sequential circuit design–Example1
3. FF-inputs equations table(design with D-FF)

From this table, the next step is to determine the

equations for the flip-flop inputs DA, DB, and
the output Y as functions of An, Bn, and X using k-map.

Bx Bx 00 01 11 10 Bx 00 01 11 10
A 00 01 11 10 A A
0 0 0 1 0 0 0 1 0 0 0 0 0 0 1
1 0 1 1 0 1 0 1 1 0 1 1 0 1 1

DA = Bn. X + An. X DB = Bn. X + An. X Y = An. ഥ

X + An. Bn + Bn. ഥ
X
DA = X (Bn + An) DB = X (Bn + An) Y=ഥ X An + Bn + An. Bn

57
Copyright © Karim Ben Si Said L1 – MI -2024/2025
Chapter- 3: Sequential circuit design
→ Sequential circuit design–Example1
4. Draw the circuit (design with D-FF)
Draw the logic sequential circuit using the FF-inputs equations DA and D𝐁 and the output equation Y
DA = X (Bn + An)
DB = X (Bn + An)
Y=ഥ
X An + Bn + An. Bn

In the next slide, design the circuit

using JK-FF
58
Copyright © Karim Ben Si Said L1 – MI -2024/2025
Chapter- 3: Sequential circuit design
→ Sequential circuit design–Example1
2. Excitation table (design with JK-FF)
To design the circuit using the JK-FF, the excitation table of JK-FF is used:

Present Next
input output Excitation table
state state
AN BN X AN+1 BN+1 Y JA KA JB KB
excitation table 0 0 0 0 0 0 0 X 0 X
Of JK-Flipflop 0 0 1 0 1 0 0 X 1 X
0 1 0 0 0 1 0 X X 1
QN QN+1 J K 0 1 1 1 0 0 1 X X 1
0 0 0 X 1 0 0 0 0 1 X 1 0 X
1 0 1 1 1 0 X 0 1 X
0 1 1 X
1 1 0 0 0 1 X 1 X 1
1 0 X 1 1 1 1 1 1 1 X 0 X 0
1 1 X 0
59
Copyright © Karim Ben Si Said L1 – MI -2024/2025
Chapter- 3: Sequential circuit design
→ Sequential circuit design–Example1
3. FF-inputs equations table(design with JK-FF)

From this table, the next step is to determine the

equations for the flip-flop inputs JA,KA, JB and KB
the output Y as functions of An, Bn, and X using k-map.

JA = B. x JB = X
Bx
Bx 00 01 11 10 A 00 01 11 10
A
0 0 0 1 0 0 0 1 X X Bx 00 01 11 10
A
1 X X X X 1 0 1 X X 0 0 0 0 1
1 1 0 1 1
KA = xത KB = ഥ ഥ
X+A

A
Bx 00 01 11 10 A
Bx 00 01 11 10 Y = An. ഥ
X + An. Bn + Bn. ഥ
X
0 X X X X 0 X X 1 1 Y=ഥ X An + Bn + An. Bn
1 1 0 0 1 1 X X 0 1
60
Copyright © Karim Ben Si Said L1 – MI -2024/2025
Chapter- 3: Sequential circuit design
→ Sequential circuit design–Example1
4. Draw the circuit (design with JK-FF)
Draw the logic sequential circuit using the FF-inputs equations JA,KA, JB and KB and the output
equation Y
JA = B. x
KA = xത

JB = X
KB = ഥ ഥ
X+A

Y=ഥ
X An + Bn + An. Bn

61
Copyright © Karim Ben Si Said L1 – MI -2024/2025
Chapter- 3: Sequential circuit design
→ Sequential circuit design–Example2
Design the sequential circuit defined by the following state diagram using D-FF, then JK-FF.
1. State table:
• This sequential circuit contains 4 bubbles (each bubble represents a state), 1 input and 1 output.
State
• With 4 states, such circuit needs 2 Flip-Flops (A and B)
diagram
• We assign to each state a FF output combination (Assign binary values to the states ): With
S0 = 0 0, S1 = 0 1, S2 = 1 0, and S3 = 1 1 assigned
states

Given
Reminder: state
Moore Machine diagram
>

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Chapter- 3: Sequential circuit design
→ Sequential circuit design–Example1
This circuit has one input x and two flip-flops A and B. Each circle represents a state / output,
✓ the value of the input x is represented for each directed line (arrow)
✓ The blue arrow represents the 2nd transition (01 to 00)
• Thus the state
statetable
table is as follow:
✓ The red arrow represents the 5th transition (00 to 01)
Present
Input Next state Output
state
X Y
A B A B
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 0
0 1 1 0 0 0
1 0 0 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
Copyright © Karim Ben Si Said L1 – MI -2024/2025 1 1 1 1 1 63 1
Chapter- 3: Sequential circuit design
→ Sequential circuit design–Example1
The state table can be drawn also with it’s second form:

Present Next state Output Y

state X=0 X=1 X=0 X=1
S0 S0 S1 0 0
S1 S0 S2 0 0
S2 S0 S3 0 0
Present Next state Y
S3 S0 S3 0 1
state X=0 X=1
X=0 X=1
A B A B A B
• Each state represent the state of 0 0 0 0 0 1 0 0
two FF A and B, thus the state table is as follow 0 1 0 0 1 0 0 0
1 0 0 0 1 1 0 0
1 1 0 0 1 1 0 1
Copyright © Karim Ben Si Said L1 – MI -2024/2025 64
Chapter- 3: Sequential circuit design D Excitation table

→ Sequential circuit design–Example1

state equations
State equations for flip-flop inputs (DA, and DB )
and the output (y) are derived from the state table,
utilizing D flip-flop excitation tables and simplifying
the expressions with K-maps.
Present state Input Next state Output
DA DB
A B X A B Y
0 0 0 0 0 0 0 0 State equations
0 0 1 0 1 0 0 1 • 𝐷𝐴 = 𝐴𝑁 𝑥 + 𝐵𝑁 𝑥
0 1 0 0 0 0 0 0 • 𝐷𝐵 = 𝐴𝑁 𝑥 + 𝐵𝑁 𝑥
0 1 1 1 0 0 1 0
• 𝑦 = 𝐴. 𝐵
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 0 0 1 0 0
1 1 1 1 1 1 1 1
65
Copyright © Karim Ben Si Said L1 – MI -2024/2025
Chapter- 3: Sequential circuit design

→ Sequential circuit design–Example1

The logic circuit using D flip flops:

• 𝐷𝐴 = 𝐴𝑁 𝑥 + 𝐵𝑁 𝑥
• 𝐷𝐵 = 𝐴𝑁 𝑥 + 𝐵𝑁 𝑥
• 𝑦 = 𝐴. 𝐵

See simulation under Digital-Software

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 JK Excitation table
Chapter- 3: Sequential circuit design
→ Sequential circuit design–Example1-Synthesis Using JK Flip-Flops
state
State equations for flip-flop inputs (JA, KA and JB, KB ) and the output (y)
are derived from the state table, utilizing JK flip-flop excitation tables
and simplifying the expressions with K-maps (see next page).

Present state Input Next state Output

JA KA JB KB
A B X A B Y
0 0 0 0 0 0 0 X 0 X State equations
0 0 1 0 1 0 0 X 1 X JA = B. x y = A. B
0 1 0 0 0 0 0 X X 1
0 1 1 1 0 0 1 X X 1
KA = xത
1 0 0 0 0 0 X 1 0 X JB = x
1 0 1 1 1 0 X 0 1 X
ഥB
KB = xത + A
1 1 0 0 0 1 X 1 X 1
1 1 1 1 1 1 X 0 X 0
67
Copyright © Karim Ben Si Said L1 – MI -2024/2025
Chapter- 3: Sequential circuit design Logic circuit with JK-FF
→ Sequential circuit design–Example1
K-map used to derive expressions
JA = B. x ഥB
KB = xത + A
Bx 00 01 11 10 Bx 00
A A 01 11 10
0 0 0 1 0 0 X X 1 1
1 X X X X 1 X X 0 1

KA = xത
Bx y = A. B
A 00 01 11 10
Bx
0 X X X X A 00 01 11 10
1 1 0 0 1 0 0 0 0 0 JA = B. x
1 0 0 1 1
KA = xത
JB = x
Bx 00 01 11 10 JB = x
A
0 0 1 X X ഥB
KB = xത + A
1 0 1 X X
y = A. B 68
Copyright © Karim Ben Si Said L1 – MI -2024/2025
Chapter- 3: Sequential circuit design
→ Sequential circuit design–
Exercise
Synthesize the circuit defined by the following state diagram using T-FF and JK-FF
• This circuit utilizes outputs generated by three flip-flops (FF), without any involvement
of combinational inputs or outputs.
1. Draw its transition table
2. Design its circuit using T flip-flops
3. Design the circuit using JK-FF.
4. What is the function realized by this circuit ?

69
Copyright © Karim Ben Si Said L1 – MI -2024/2025
Chapter- 3: Sequential circuit design

→ Sequential circuit design– state-reduction

The reduction in the number of flip-flops in a sequential circuit is referred to as the state-reduction
problem. To explain the steps, lets take the following sequential system defined by its state diagram.

• This circuit has one input X and one output y and 14 transitions between 7 states.

• The reduction process involves eliminating redundant (equivalent) transitions.

• To identify equivalent states, it is preferable to construct the state table.

Two states are said to be equivalent if : for the same input combination, the
transition from the present states to next states is equivalent and yields identical
outputs.

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Chapter- 3: Sequential circuit design

→ Sequential circuit design– states reduction

• The table is constructed from the state diagram.

• From the state table, for instance, states e and g are found to be equivalent as they lead to the
same next states and have identical outputs for both input combinations.

• Thus, the row with present state g is removed, and g state is replaced by state e each time it occurs
in the columns headed “Next State.”
Present Next state Output y
state X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g e f 0 1
g a f 0 1
Copyright © Karim Ben Si Said L1 – MI -2024/2025 71
Chapter- 3: Sequential circuit design

→ Sequential circuit design– states reduction

• After replacing the g states with e, we notice that states d and f are now equivalent as they lead to
the same next states and have identical outputs for both input combinations.

• Thus, following the same procedure as previous, the row with present state f is removed, and f
state is replaced by e state each time it occurs in the columns headed “Next State.”

Present Next state Output y Final State table after reduction

state X=0 X=1 X=0 X=1
Present Next state Output y
a a b 0 0 state X=0 X=1 X=0 X=1
b c d 0 0 a a b 0 0
c a d 0 0 b c d 0 0
d e f d 0 1 c a d 0 0
e a f d 0 1 d e d 0 1
f e f 0 1 e a d 0 1

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Chapter- 3: Sequential circuit design

→ Sequential circuit design– states reduction

• After all reduction the state table is shown bellow. Based on this table
the new state diagram is drawn

Present Next state Output y

state X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1

Exercise:
design the circuit of this reduced
state diagram using JK and D-FF
using One-hot states assignment
Copyright © Karim Ben Si Said L1 – MI -2024/2025 73