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DLC OBE Assignment Solution 22-49016-3

The document outlines a parking capacity monitoring system with a maximum capacity of 8 cars, detailing essential steps for a block and flow diagram, counter design, and a 555 timer circuit. It also includes a finite state machine (FSM) design with Verilog code for alternating outputs, and discusses limitations of the system along with suggested modifications for scalability and improved functionality. Key limitations include fixed capacity and lack of debouncing logic, while modifications propose wider counters and the use of microcontrollers for enhanced performance.

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29 views3 pages

DLC OBE Assignment Solution 22-49016-3

The document outlines a parking capacity monitoring system with a maximum capacity of 8 cars, detailing essential steps for a block and flow diagram, counter design, and a 555 timer circuit. It also includes a finite state machine (FSM) design with Verilog code for alternating outputs, and discusses limitations of the system along with suggested modifications for scalability and improved functionality. Key limitations include fixed capacity and lack of debouncing logic, while modifications propose wider counters and the use of microcontrollers for enhanced performance.

Uploaded by

ehteshamshaan32
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DLC OBE Assignment Solution - Spring

24-25
Student ID: 22-49016-3

Variables: a=2, b=2, c=4, d=9, e=7, f=1, g=3, h=3

Parking Capacity: a + g + h = 2 + 3 + 3 = 8 cars

Task (i): Block & Flow Diagram and Counter Design

Essential Steps (in sequence):


1. Initialize System
2. Set Maximum Capacity = 8
3. Monitor Entry Sensor
4. Monitor Exit Sensor
5. Use Counter to Count Cars In and Out
6. Compare Car Count with Maximum Capacity
7. If count == capacity → Display “FULL”
8. If count < capacity → Blink “SPACE AVAILABLE”
9. Repeat the cycle continuously

Block Diagram: Refer to provided conceptual layout with sensors, counter, comparator, and
displays.

Flow Diagram: System logic flow from initializing to display control based on count.

Counter Design: 4-bit Up/Down counter using D Flip-Flops with synchronous logic.

Task (ii): 555 Timer Circuit Design

- P = (a + c + d + e + f) × 2 = (2 + 4 + 9 + 7 + 1) × 2 = 46
- Duty Cycle D = 100 – P = 54%
- Frequency f = a + d + 2 = 13 Hz
- Chosen Capacitor: 250 µF
- Chosen Resistors: R1 = 500 Ω, R2 = 1.5 kΩ
"FULL" Display:
- Continuous ON using direct HIGH or monostable 555 timer configuration.

"SPACE AVAILABLE" Display:


- Blinking using 555 Timer in astable mode with calculated frequency and duty cycle.

Task (iii): FSM Design and Verilog Code

FSM: Alternates between A and B outputs every 4 ms.


- TH = 4 ms, TL = 4 ms (as per problem constraint)
- Clock = 1 ms → 4 clock cycles per state

State Table:
| Present State | Output | Next State | Duration |
|---------------|--------|------------|----------|
|A |1 |B | 4 ms |
|B |0 |A | 4 ms |

Verilog Code:

module blink_fsm (
input clk,
input reset,
output reg A, B
);

reg [2:0] count;


reg state; // 0 = A, 1 = B

always @(posedge clk or posedge reset) begin


if (reset) begin
count <= 0;
state <= 0;
A <= 1;
B <= 0;
end
else begin
count <= count + 1;

if (count == 3) begin // 4 clock cycles


count <= 0;
state <= ~state;
end

case(state)
0: begin A <= 1; B <= 0; end
1: begin A <= 0; B <= 1; end
endcase
end
end

endmodule

Task (iv): Limitations and Suggested Modifications

Limitations:
1. Fixed capacity (8 cars) – Not flexible for larger lots.
2. No debouncing logic for sensor noise.
3. Counter overflow possibility.
4. No manual override or emergency controls.

Modifications:
- Use wider counters for larger capacity.
- Add signal conditioning and debounce filters.
- Replace 7-segment with LCD for better display scalability.
- Use microcontroller or FPGA for flexible logic.

Impact of Scaling:
- More bits in counter logic.
- Adjust display logic for new thresholds.
- Increased circuit complexity and power demand.

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