IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO.

9, SEPTEMBER 2020 3685

SiC Trench MOSFET With Reduced Switching

Loss and Increased Short-Circuit Capability
Tongtong Yang , Yan Wang , Member, IEEE, and Ruifeng Yue

Abstract — In this article, a novel SiC trench MOSFET introduce p+ shielded regions around the gate trench, such
with deep p+ shielded regions and current spreading layers as the asymmetrical Cell Trench MOS [10], the bottom p+
(CSLs) (DPCSL-MOS) is proposed and studied by TCAD sim- shielded trench MOSFET (GP-MOS) [11], the integrated SiC
ulations. The results show that the introduction of the deep Trench/Planar MOSFET [12], and the Fin-shaped Gate SiC
p+ shielded region reduces the transfer capacitance Crss
(=Cgd ) and the saturation current, thus reducing the total Trench MOSFET [13]. However, the p+ regions shrink the
switching losses and increasing the short-circuit capability. available electron conducting path from the MOS channel
Besides, the deep p+ regions around the source trench into the drift layer, which increases the total device resis-
efficiently shields the shallow gate trench from the drain tance. Another method is Rohm’s double trench MOSFET
voltage, thus reducing the maximum oxide electric field. (DT-MOS) [14], which has a gate trench and a source trench.
In addition, the introduction of CSL with higher doping con- The DT-MOS could achieve a lower device ON-resistance.
centration than the drift layer brings down the JFET effect
and the resultant device ON-resistance. The dynamic figure
However, the electric field at the trench corner or bottom
of merit (FOM) (RON ∗ Qgd ) is significantly improved with no may cause reliability problem. And Crss is so large that
degradation in terms of the static FOM (V2br /RON ). Therefore, the switching losses are usually high. To better trade off,
the proposed DPCSL-MOS is a more robust and promising the device characteristics are the focus of present researches.
structure for power electronic systems, especially for the In this article, a SiC trench MOSFET with deep p+ shielded
high-frequency applications. regions and current spreading layers (CSLs) is proposed
Index Terms — Gate oxide electric field, gate oxide reliabil- and studied. Compared with two other prevalent structures,
ity, short circuit, SiC trench MOSFET, specific ON-resistance. the novel SiC trench MOSFET with deep p+ shielded regions
and CSL (DPCSL-MOS) demonstrates significantly reduced
I. I NTRODUCTION switching losses and increased short-circuit capability. In addi-
tion, both reduced maximum oxide electric field and device
S iC MOSFETs are preferred for high-frequency applica-
tions compared with the Si insulated gate bipolar transis-
tors (IGBTs) due to the advanced material properties of silicon
ON-resistance are obtained.

carbide [1]. However, the high interface charge density at the II. N EW S TRUCTURE AND S IMULATION R ESULTS
SiC/oxide interface leads to lower channel mobility, increasing
Fig. 1 shows the schematic cross-sectional views of (a) GP-
the channel resistance, a major part of the total device ON-
MOS, (b) DPCSL-MOS, and (c) DT-MOS. The DPCSL-MOS
resistance [2], [3]. Compared with the planar SiC MOSFETs,
features a shallow polysilicon gate trench and a deep source
the SiC trench MOSFETs could achieve both reduced cell
trench. The shallow poly gate trench depth in this work is set
pitch and high channel mobility, contributing to a low channel
to 0.7 µm for the DPCSL-MOS considering a channel length
resistance [4]–[6].
of 0.5 µm. The shallow gate trench that makes the trench area
However, the high oxide electric field developed at the
directly exposed to the drain electrode is rather small. Along
trench corner or trench bottom causes premature oxide break-
with the shielding effect of the deep p+ regions, the transfer
down, which becomes a major obstacle for the further devel-
capacitance Crss is further reduced, thus lowering the total
opment of the conventional SiC trench MOSFETs [7]–[9].
switching losses. In addition, the doping concentration of the
Another disadvantage of the trench MOSFET is the large
CSL is much lower than that of the deep p+ regions. The CSL
transfer capacitance Crss (=Cgd ), which degrades the switching
could be easily depleted at high drain voltage, making the deep
performance. In recent years, various methods have been
p+ regions still provide strong pinch-off effect and lower the
utilized to address these issues. One prevalent method is to
saturation current, which increases the short-circuit capability.
Manuscript received May 24, 2020; revised June 20, 2020; accepted In addition, the deep p+ regions around the deep source
June 26, 2020. Date of publication July 16, 2020; date of current version trench efficiently shield the shallow gate trench from the high
August 21, 2020. This work was supported by the Beijing Science drain voltage, thus reducing the oxide electric field. When the
and Technology Planning Project under Grant Z201100004020002. The SiC MOSFET operates in the ON-state, the drain voltage is
review of this article was arranged by Editor T. Kimoto. (Corresponding
author: Yan Wang.) supported by the p-n junction formed by the deep p+ regions
The authors are with the Institute of Microelectronics, Tsinghua Uni- and CSL. Due to the higher doping concentration of the CSL
versity, Beijing 100084, China (e-mail: [email protected]; than that of the drift layer, the depletion width is much smaller,
[email protected]; [email protected]).
Color versions of one or more of the figures in this article are available reducing the JFET effect caused by the adjacent deep p+
online at http://ieeexplore.ieee.org. regions, conducting the electrons downward to the drift layer.
Digital Object Identifier 10.1109/TED.2020.3005992 Consequently, the key structure parameters for optimizing the
0018-9383 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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3686 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 9, SEPTEMBER 2020

Fig. 1. Schematic cross-sectional views of (a) GP-MOS,

(b) DPCSL-MOS, and (c) DT-MOS. The parts in the dotted boxes
represent the cells used in the following simulations.

Fig. 3. Influences of width and the doping concentration of the CSL on

the (a) specific ON-resistance and (b) maximum electric field in the oxide
(extracted at a drain voltage of 1200 V). During the optimizations, Wpoly
and Lst are 0.6 and 1.5 µm, respectively.

Fig. 3 shows the influences of Wcsl and the doping con-

centration of CSL on the ON-resistance and maximum oxide
electric field (at a drain bias of 1200 V). Obviously, a larger
Wcsl and high doping concentration of the CSL could help
further reduce the device ON-resistance. Due to the shielding
effect of the deep p+ regions, the maximum oxide electric field
is still lower than 1.2 MV/cm when the doping concentration
and Wcsl are 8e16 cm−3 and 0.5 µm, respectively, which pro-
vide much room for further reducing the device ON-resistance.
However, with higher doping concentration and larger width
for the CSL, the electric field crowding phenomenon at the
Fig. 2. Influences of poly trench width and source trench depth on the corner for p+ shield region may lower the breakdown voltage.
(a) specific ON-resistance and (b) maximum electric field in the oxide
(extracted at a drain voltage of 1200 V).
B. Process Implementations and Parameter Variations
DPCSL-MOS are the poly trench width (Wpoly ), the source In order to show the feasibility of the proposed
trench depth (L st ), and the width and doping concentrations DPCSL-MOS, a possible fabrication process is illustrated,
of the CSL [as shown in Fig. 1(b)]. as shown in Fig. 4. First, an epitaxial drift layer with a doping
concentration of 8e15 cm−3 is grown on the top of the n+
A. Effect of Key Structure Parameters of DPCSL-MOS substrate. Then, multiple implantations are utilized to form
Fig. 2 gives the dependence of the specific ON-resistance the deep p+ shield and the CSL, which are formed by the
and maximum oxide electric field on the structure parame- aluminum and nitrogen implantations, respectively, as shown
ters Wpoly and L st . The device ON-resistance is extracted in Fig. 4(b) and (c). The self-aligned process is recommended
at a current density of 100 A/cm2 . A channel mobility of to simplify the fabrication process. After forming the p+ shield
50 cm2 /(V · s) is used. As expected, increasing Wpoly could regions and CSLs, a second epitaxial layer is grown on the
decrease the specific ON-resistance and increase the maximum surface with a doping concentration of 8e15 cm−3 [5]. Then,
oxide electric field for the same source trench depth. And with a mask layer, the gate trench is formed followed by the
the specific ON-resistance demonstrates nearly linear increase filling of mask layers (e.g., SiO2 ) in the trench. With the
with the increase of the source trench depth for the same mask layers in the gate trench, the multiple aluminum and
Wpoly . Because the JFET effect caused by adjacent deep p+ nitrogen implantations are used to form the p-base and n+
source regions is stronger when increasing the source trench source region [21], respectively, as shown in Fig. 4(f). Then,
depth, the JFET resistance is increased. This JFET effect the inductively coupled plasma reactive ion etching (RIE) is
could be well relieved with the introduction of the CSL, thus used to form the source trench, as illustrated in Fig. 4(g).
better trading off the ON-resistance against the maximum oxide After that, the gate oxide is formed by thermal oxidation with
electric field. a thickness of 50 nm. The polysilicon gate is then filled in
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YANG et al.: SiC TRENCH MOSFET WITH REDUCED SWITCHING LOSS AND INCREASED SHORT-CIRCUIT CAPABILITY 3687

Fig. 6. Dependence of device ON-resistance on Lv .

Fig. 4. Proposed fabrication process for the proposed DPCSL-MOS.

Only the key fabrication procedures are depicted. (a) Forming the
first epi layer. (b) Forming the CSL layer. (c) Forming the p+ shield
region. (d) Forming the second epi layer. (e) Forming the gate trench.
(f) Forming the Pbase and n+ source region. (g) Forming the source
trench. (h) Forming the ohm contact. (i) Forming the ILD layer. (j) Forming Fig. 7. Dependence of device ON-resistance and maximum oxide electric
the metal overlay. field on Lh .

Fig. 8. Changes of the ON-resistance and maximum oxide electric field

as a function of the mesa width for the DT-MOS.

Fig. 5. Enlarged view of the top part of the DPCSL-MOS. JFET effect, the ON-resistance is expected to increase. The
dependence of the ON-resistance on L v is shown in Fig. 6.
the gate trench. The following process is forming the ohm In the simulations, Wcsl and doping concentration of the
contact at the source electrode and drain electrode, as shown CSL are 0.3 µm and 6e16 cm−3 , respectively. As expected,
in Fig. 4(h). The final process included the deposition of the the device ON-resistance increases slightly with the increase
inter layer dielectric (ILD) layer and the metal overlay process, of L v . And when L v is smaller than 0.1 µm, the increase of
which are shown in Fig. 4(i) and (j), respectively. ON-resistance is negligible.
Owing to the unavoidable process variations in the real In addition, due to the unavoidable lithography misalign-
device fabrication, the effect of parameter variations is dis- ment between the gate trench and the p+/CSL, L h as shown in
cussed in this section. Fig. 5 should be considered as well. The simulated dependence
From the results in Figs. 2 and 3, it could be found that of the ON-resistance and maximum electric field is shown in
both device ON-resistance and the maximum oxide electric Fig. 7. Thanks to the proper design of the deep p+ shielded
field don’t show obvious changes with proper choice of the region and the CSL, both the ON-resistance and the maximum
structure parameters. When Wpoly is larger than 0.6 µm or electric field don’t demonstrate significant changes with para-
Wcsl is larger than 0.3 µm, the ON-resistance and maximum meter variations. It should be pointed out that the maximum
oxide electric field becomes less sensitive to the changes of electric field always exists at the middle of the bottom of the
the parameter values. gate trench.
The proposed DPCSL-MOS features a shallow gate trench.
Therefore, the distance between the bottom of the p-base layer C. Compared With Two Prevalent Structures
and that of the gate trench may vary depending on the etching Before the comparisons for the three structures shown
process and implantation process. The distance is labeled as in Fig. 1, optimization work should be done at first. For
L v , as shown in Fig. 5. When L v increases, the shielding the DT-MOS and GP-MOS, the mesa width demonstrates
effect for the gate trench becomes stronger. As discussed significant effect on the electrical device characteristics. On the
previously, increasing L v is beneficial to decreasing the oxide one hand, the increase of the mesa width widens the elec-
electric field and the switching losses. However, due to the tron current conduction path from the channel into the drift
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3688 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 9, SEPTEMBER 2020

Fig. 9. Changes of the ON-resistance and maximum oxide electric field

as a function of the mesa width for the GP-MOS.

TABLE I
S UMMARIZED D EVICE S TRUCTURE PARAMETERS

layer, which is beneficial to decreasing the JFET resistance. Fig. 10. (a) I − V characteristics varying the drain voltage from 0 to 800 V.
(b) I − V characteristics at low drain voltages. (c) Electric field contours
On the other hand, the cell pitch increases when increasing of the three structures with a drain bias of 1200 V.
the mesa width, thus increasing the ON-resistance. The final
TABLE II
optimization results for the DT-MOS and GP-MOS are shown S UMMARIZED D EVICE C HARACTERISTICS
in Figs. 8 and 9, respectively. The mesa width described here
is the width in the half cell pitch. For both device structures,
the maximum oxide electric field increases monotonically
with the increase of the mesa width. For the DT-MOS, the
ON-resistance shows a monotonous decrease. While for the
GP-MOS, the ON-resistance decreases when the mesa width is
lower than 1.1 µm, then increasing at larger mesa width. This
is believed to be caused by the two distinct effect of the mesa
width as discussed previously.
Compared with the GP-MOS, the introduction of the CSL
results in a much lower ON-resistance. In comparison with
the DT-MOS, the deep p+ regions should provide a stronger
shielding effect, leading to lower Crss and resultant switching
losses. For further clear comparisons, some typical parameters
are used here for the three structures. Based on the optimiza-
tion results, for the GP-MOS and the DT-MOS, the mesa width ON-resistances are summarized in Table II. The DPCSL-MOS
is set to 1.1 and 0.8 µm to better trade off the ON-resistance has lower ON-resistance than the other two structures. This is
and the maximum oxide electric field [7], [13]. The resultant attributed to the introduction of the CSL, which decreases the
half-cell pitch of GP-MOS is 2.1 µm. For the DT-MOS, the space charge region width of the p-n junction formed by the
half-cell pitch is 2.8 µm. For the DPCSL-MOS, Wcsl and p+ shielded regions and the CSL at low drain voltages, thus
doping concentration of the CSL are 0.3 µm and 6e16 cm−3 , widening the electron conducing path from the MOS channel
respectively. Wpoly and L st are 0.6 and 1.5 µm, respectively. to the drift layer. The electric field contours extracted at a
And the half-cell pitch of the DPCSL-MOS is 2.1 µm. The drain voltage of 1200 V are shown in Fig. 10(c). The DPCSL-
detailed structure parameters are summarized in Table I. MOS has the lowest oxide electric field among the three
Fig. 10(a) shows the I − V characteristics of the three structures. Due to the shielding effect provided by the p-
MOSFET structures. The I − V curves at low drain voltages base and p+ shield, the maximum electric field always exists
are also given in Fig. 10(b). The extracted device specific at the middle of the bottom of the gate trench. With the

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YANG et al.: SiC TRENCH MOSFET WITH REDUCED SWITCHING LOSS AND INCREASED SHORT-CIRCUIT CAPABILITY 3689

Fig. 11. Comparisons of the forward conducting characteristics of the

body diodes for the investigated structures.

Fig. 12. (a) Gate charging characteristics of the three structures.

(b) Extracted Crss at different drain voltages. The test circuit for measuring
the gate charging characteristics is shown in the inset of Fig. 12(a). The
active areas of the simulated structures are all set to 1 cm2 .

deep p+ shielded region, the gate trench is shielded from the

high drain voltage. Therefore, the combination of the deep
p+ shielded regions and the CSLs makes the DPCSL-MOS
achieve a better trade-off between the maximum oxide electric
field and ON-resistance. As shown in Table II, the DPCSL-
MOS demonstrates an obvious improvement in terms of the
static figure of merit (FOM) compared with the other two
structures. The forward conducting characteristics of the body
diodes of the three structures are shown in Fig. 11. Thanks
to the conductivity modulation in the parasitic body diode,
Fig. 13. (a) Double pulse test circuit used in this work. (b) Waveforms of
no significant difference is observed in terms of the third the drain voltage and drain current. (c) Power losses during the turn-off
quadrant body diode characteristics. process. (d) Waveforms of the drain voltage and drain current. (e) Power
Fig. 12(a) compares the gate charging of the three struc- losses during the turn-on process. The turn-off and turn-on switching
tures. The test circuit is shown in the inset. During the Miller losses are the areas of the shadow regions. (f) Comparison of total
power losses of the three structures at different operating frequencies.
plateau stage, both high drain current and high drain voltage
exist, which causes high power loss [16]. Most of the gate lower Crss reduces the switching loss. The comparisons of the
current is used to charge the transfer capacitance Crss . Due total power losses of the SiC MOSFETs at different operating
to the capacitive shielding effect of the deep p+ regions, Crss frequencies are shown in Fig. 13(f). Obviously, the advantages
of the DPCSL-MOS should be much smaller than the other of the DPCSL-MOS over the other two structures become
structures [15]. The extracted dependence of Crss on the drain more obvious with the increase of the operating frequency.
voltage is shown in Fig. 12(b). As expected, Crss of the In addition, the DPCSL-MOS also demonstrates increased
DPCSL-MOS is an order of magnitude lower than that of the short-circuit capability [18]–[20]. When the SiC MOSFET
other two structures. The smaller Crss reduces the total time operates in the conduction mode, due to the shorting of the
of the Miller plateau stage, which reduces the switching loss. load, the high-voltage source is directly biased at the drain
As shown in Table II, the dynamic FOM of the DPCSL-MOS electrode, which is called as the short circuit case. And a
shows significant decrease in comparison with those of the high drain current flows through the device with a high
GP-MOS and DT-MOS. drain voltage, generating high power loss and increasing the
The switching characteristics obtained along with the double temperature in the body. As shown in Fig. 10(a), the saturation
test circuit [as shown in Fig. 13(a)] are depicted in Fig. 13. current of the DPCSL-MOS is much lower than the other two
The results are summarized in Table II. The DPCSL-MOS structures due to the strong pinch-off effect provided by the
demonstrates significant reductions in terms of the total deep p+ regions. The short circuit performance of the struc-
switching losses. During the normal operations, the total power tures is simulated using the test circuit shown in Fig. 14(a).
losses of the SiC MOSFETs consist of the ON-state power The voltage waveforms applied at the gate electrode are also
loss and the power switching loss. For the DPCSL-MOS, provided to mimic the real short circuit case. The simulation
the lower ON-resistance reduces the ON-state power loss and the results are shown in Fig. 14(b). As expected, the DPCSL-MOS

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3690 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 9, SEPTEMBER 2020

achieves both reduced gate oxide electric field and device

ON-resistance. Therefore, the proposed DPCSL-MOS is a
promising candidate for the high-frequency applications.
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