EE477L

CMOS Digital Integrated Circuits

MOS Transistor Theory and Operation
Spring 2025

Instructors: Mehdi Kamal, Shahin Nazarian, Massoud Pedram

University of Southern California
Dept. of Electrical and Computer Engineering

Original Slides by Massoud Pedram

1
 MOSFET Transistor Theory
• MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
is a majority carrier device Note: Electron
– Electrons are the majority carrier for an N-channel FET; holes are the configuration of Si:
1s22s22p63s23p2
majority carrier for a P-channel FET.
– By contrast, a Bipolar Junction Transistor is a minority carrier device
• Electrons are the minority carrier in the base region of an NPN transistor
• Types of MOSFET Devices:
– N channel enhancement mode: normally OFF; VT > 0
– P channel enhancement mode: normally OFF; VT < 0, Ids < 0
– N channel depletion mode: normally ON; VT < 0
– P channel depletion mode: normally ON; VT > 0, Ids < 0

Note: In solid-state physics, the valence

band and conduction band are the bands
closest to the Fermi level and thus
determine the electrical conductivity of the
solid. The valence band is the highest
range of electron energies in which
electrons are normally present at absolute
zero temperature, while the conduction
band is the lowest range of vacant
electronic states. 2
 Electrons and Holes in Undoped
Semiconductors
• At room temperature the forbidden energy gap between Note: 1ev = 1.602e-19 J
the valence and conduction bands for silicon is 1.1eV.
Basically, carriers in undoped semiconductors (intrinsic
semiconductors) are generated in pairs by thermal
excitation of valence band electrons. Leaving the
valence band and entering the conduction band, each of
the thermally excited electrons generates a (mobile)
hole in the valence band.
• Both the electrons lifted into the conduction band and
the defect electrons (holes) left behind the valence band
will contribute to a current flow. Generally, this kind of
intrinsic conductivity is negligible compared to the
conductivity due to ionized impurities.

3
Current Conduction in Undoped
Silicon

4
 Electrons and Holes in Doped
Semiconductors

• Impurity atoms with a valence of five (so-called donors

like phosphorus (P) or arsenic (As)) may be introduced
to replace some silicon atoms in the crystal lattice.
• If the donors get ionized, each donor delivers an
electron to the conduction band.

5
 Electrons and Holes in Doped
Semiconductors

• Impurity atoms with a valence of three (called acceptors

e.g., boron (B)) may be introduced to replace some
silicon atoms in the crystal lattice.
• If the acceptors get ionized, each acceptor will capture
an electron from the valence band leaving a hole
behind.
6
Charge Neutrality Condition and Mass
Action Law
At room temperature all donors (density 𝑁𝑁𝐷𝐷 ) and acceptors (concentration
𝑁𝑁𝐴𝐴 ) are ionized. Consequently, in an n-type semiconductor doped with
donors, the electron density is approximately 𝑛𝑛 = 𝑁𝑁𝐷𝐷 where the intrinsic
concentration 𝑛𝑛𝑖𝑖 can be neglected (𝑛𝑛𝑖𝑖 << 𝑁𝑁𝐷𝐷 ). In contrast in an p-type
semiconductor doped with acceptors, the hole density is approximately
𝑝𝑝 = 𝑁𝑁𝐴𝐴

Charge neutrality condition: N D + p = N A + n

Under thermal equilibrium:
np = ni2 (ni ≈1.45 ×1010 cm −3 )
For example, if the substrate is uniformly doped @ NA, then
ni2
p p0 = N A → n p0 ≈
NA

7
 Two Terminal MOS Structure

The metal oxide semiconductor

(MOS) capacitor is at the core of
the complementary-metal-oxide-
silicon (CMOS) technology.
Silicon metal-oxide-silicon-field-
effect-transistors (MOSFETs)
rely on the extremely high
quality of the interface between
SiO2, the standard gate
dielectric, and silicon.

8
 Energy Band Diagram for p-Type Substrate
The Fermi level, 𝐸𝐸𝐹𝐹 , denotes the electrochemical potential of electrons inside q χ = electron affinity of Si in eV
a material (the energy level that has a 50% probability of being filled).
Note: The likelihood of a state of energy E being filled with 1 (energy released when an electron is added to Si)
an electron is given by the Fermi–Dirac distribution: Prob( E ) = ( E − EF )
where k denotes the Boltzmann constant = 8.617*10-5 eV/K 1+ e kT
Recall that 1eV = 1.6 × 10-19 Joules
Note: The free space energy EFp − Ei
level is used as the reference. φFp = in Volts
q
The energy band diagram is a
Note: The electron density representation of carrier energy in a
in Si is related to the Fermi semiconducting material, which is related
level as follows:
𝑞𝑞𝜙𝜙𝐹𝐹 to an orbital bonding representation.
𝑛𝑛 = 𝑛𝑛𝑖𝑖 𝑒𝑒 𝑘𝑘𝑘𝑘
Note: Under thermal
kT n Similarly, for n-Type substrate:
equilibrium (e.g., without
φFp ln i ( N A >> ni ) currents in the
semiconductor) the Fermi-
q NA kT N D edge is constant vs. the
= φFn ln ( N D >> ni ) position coordinate. In this
q n i
case, there is only one
energy level for electrons
ni 1.45 ×1010 cm −3
= and holes. In an unbalanced
thermo-dynamic state (e.g.,
kT with current flow due to
k 1.38 ×10−23 J / K
= = 26mV @room temperature supplied voltages), the

−19
q Fermi-level is split-up into a
quasi-Fermi-level for
q 1.6 ×10 C
= Note: The forbidden band gap generally refers to the energy electrons, and another one
for holes.
difference (in electron volts) between the top of the valence band and
the bottom of the conduction band in insulators and semiconductors. 9
 MOS System Energy Bands
Vacuum level

Note: 𝑞𝑞𝜒𝜒𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 denotes the

Note: The flatband voltage electron affinity of silicon,
corresponds to the voltage, qφs which is defined as the
which, when applied to the Eg energy obtained by moving
gate electrode, yields a flat an electron from the
energy band in the vacuum just outside the
semiconductor (see next semiconductor to the
page for more details). bottom of the conduction
Gate Electrode p-Type Substrate band just inside the
semiconductor.

𝐸𝐸𝑜𝑜 = energy of an electron in free space

𝐸𝐸𝑐𝑐 = conduction band edge = energy level of free electrons in the silicon
𝐸𝐸𝜐𝜐 = valence band edge = energy level of free holes in the silicon
𝐸𝐸𝑔𝑔 = 𝐸𝐸𝑐𝑐 − 𝐸𝐸𝑣𝑣 = band gap of silicon = 1.1 eV
𝐸𝐸𝑖𝑖 = intrinsic energy level = Fermi level for intrinsic silicon material = approximately the
center of the forbidden band gap
𝐸𝐸𝐹𝐹𝐹𝐹 = Fermi level in the p-type substrate material
𝐸𝐸𝐹𝐹𝐹𝐹 − 𝐸𝐸𝑖𝑖 = 𝑞𝑞𝜙𝜙𝐹𝐹𝑝𝑝 where 𝜙𝜙𝐹𝐹𝑝𝑝 is the Fermi potential in the p-type substrate material
𝑞𝑞𝜙𝜙𝑆𝑆 = Semiconductor work function = the minimum energy needed to remove an electron
𝐸𝐸𝑔𝑔
from the Fermi level to the vacuum level = 𝑞𝑞𝜒𝜒 + 𝐸𝐸𝑐𝑐 – 𝐸𝐸𝐹𝐹𝐹𝐹 = 𝑞𝑞𝜒𝜒 + − 𝑞𝑞𝜙𝜙𝐹𝐹𝑝𝑝
2
𝑞𝑞𝜙𝜙𝑀𝑀 = Metal work function = defined similarly
𝑞𝑞𝜙𝜙𝑀𝑀𝑀𝑀 = 𝑞𝑞𝜙𝜙𝑀𝑀 – 𝑞𝑞𝜙𝜙𝑆𝑆 = metal-to-semiconductor work function
𝑉𝑉𝐹𝐹𝐹𝐹 = 𝜙𝜙𝑀𝑀𝑀𝑀 = flatband voltage 10
Energy Band Diagram of MOS System
Eo Note: Consider a MOS capacitor at zero gate bias with 𝜑𝜑𝑀𝑀 < 𝜑𝜑𝑆𝑆 i.e.,
qφMS 𝑽𝑽𝑮𝑮 = 𝟎𝟎, 𝑽𝑽𝑭𝑭𝑭𝑭 < 𝟎𝟎. This means that the MOS system is in depletion region.
Electrons in the metal reside at energy levels above semiconductor’s
qφS conduction band. As a result, electrons flow from the metal into the
semiconductor (holes are depleted from the semiconductor surface) until a
potential that counterbalances the difference in the work functions is built up
qφM between the two plates. This induces a positive charge in the gate and a
negative charge in the semiconductor under the gate dielectric
qψs qφFp accompanied by a downward band bending on the silicon surface and
hence, a positive surface potential, 𝜓𝜓𝑠𝑠 (the surface potential denotes the
change in potential from bulk to surface of the semiconductor.) If an
external voltage equal to this difference is applied to the gate, the net
charge in the semiconductor disappears, and the bands return to their flat
position. This voltage is defined as the flatband voltage, VFB, (see below).
• Fermi levels in metal gate and semiconductor line up in equilibrium
– Bands necessarily bend downward at the semiconductor-oxide interface due to lining up of Fermi levels and built-in
positive oxide charge (surface states and traps)
𝑄𝑄𝑜𝑜𝑜𝑜
• Flat Band Voltage in the presence of oxide charges is: 𝑉𝑉𝐹𝐹𝐹𝐹 = 𝜙𝜙𝑀𝑀𝑀𝑀 −
𝐶𝐶𝑜𝑜𝑜𝑜
– VFB is the gate voltage required to create no charge in the Si (i.e., flatten the energy bands)
– Qox is the built-in (fixed) oxide charge (per cm2) that originate from processing, defects in the bulk or charges that exist at
the interface between Si and SiO2 whereas Cox denotes the gate oxide capacitance (per cm2). These charges are positive.
– Qox induces opposite charges in the semiconductor and the gate. This can cause the bands to bend up or down. Therefore, the
flatband voltage will have to be adjusted to consider this.
• Three operating regions are important:
– Accumulation: interface strongly p-type, i.e., applied gate voltage < 𝑉𝑉𝐹𝐹𝐹𝐹
– Depletion: interface depleted of mobile carriers or Weak inversion: interface resembles an intrinsic material i.e.,
𝑉𝑉𝐹𝐹𝐹𝐹 < applied gate voltage < 𝑉𝑉𝑇𝑇
– Strong inversion: interface strongly n-type i.e., applied gate voltage > 𝑉𝑉𝑇𝑇 11
Work Function (𝑞𝑞𝜙𝜙𝑀𝑀 ) of MOS Gate
Materials
valence band

12
 Polysilicon v. Metal Gate (Optional)
• There are a few reasons that poly was the preferred material until a few years ago;
metal gates were used when operating voltages were high (say 3V). As operating
voltages lowered, manufacturers transitioned to using polysilicon as the gate
material. After 45nm (for Intel) and 28nm (for TSMC), gates are again made with
metal in conjunction with high-k insulators.
• One reason for the initial switch from metal to polysilicon gate (which occurred two-
three decades ago) was that fabrication processes after the initial doping required
very high temperature annealing. Metal gates would melt under such conditions
whereas polysilicon would not. Using polysilicon allowed for a one-step process of
etching the gates compared to elaborate multi-steps that we see today in metal-gate
processes. The other reason is that the threshold voltage of the MOSFET is
correlated with the work-function difference between the gate and the channel.
Using metal would result in a higher VT compared to polysilicon since the work
function of a typical metal (such as Copper, Silver, and Gold) is larger than that of
highly doped n+ polysilicon.
• As we reach smaller and smaller scales, the need for a higher VT has become
important again due to problems of gate leakage. Higher conductivity in the gate has
also become important as the oxide dielectric layers cannot be shrunk any further to
increase speed. Thus, metal gates with a high-k dielectric are used in modern
CMOS transistors.
13
MOS Capacitor in Accumulation
𝑉𝑉𝐺𝐺 < 𝑉𝑉𝐹𝐹𝐹𝐹 Accumulation Condition:
• Application of sufficiently negative
voltage (i.e., a voltage that is less than the
flatband voltage) on the gate of the
capacitor on the P substrate induces holes
at the silicon-oxide interface
• Bands bend upward (beyond flat band
condition), making the channel strongly P
type

In a MOS capacitor charge neutrality is always preserved.

Therefore, a net positive charge, QC, must be generated in the
silicon substrate under an applied negative gate bias to
counterbalance the negative charge on the gate. This is achieved
by an accumulation of majority carrier holes under the gate. This
condition, where the majority carrier concentration is greater near
the Si-SiO2 interface than the bulk is called accumulation.
Under an applied negative gate bias, the Fermi level of the gate is
raised with respect to the Fermi level of the substrate by an amount
equal to qVGB. The energy bands in the semiconductor bend
upward, bringing the valence band closer to the Fermi level,
indicative of a higher hole concentration under the dielectric (and
resulting in a negative surface potential). It is important to note that
the Fermi level in the substrate remains invariant even under an
applied bias since no current can flow through the device due to the
presence of an insulator.
14
 MOS Capacitor in Depletion
Note: The band bending in Note: With a positive gate
𝑉𝑉𝐹𝐹𝐹𝐹 < 𝑉𝑉𝐺𝐺 < 𝑉𝑉𝑇𝑇 Si is consistent with the bias, the Fermi level of the
presence of a depletion gate is lowered with respect to
layer. the Fermi level of the
substrate. The bands bend
downward resulting in a
positive surface potential.
Under the gate, the valence
xd band moves away from the
Fermi level indicative of hole
depletion. When the band
bending at the surface is such
that the intrinsic level
Poisson equation:
coincides with the Fermi level,
Finds the electric potential ϕ for a given charge the surface resembles an
• Depletion Condition: distribution described by a charge density function, ρf intrinsic material (onset of the
weak inversion).
– Application of a small positive voltage (i.e., voltage that is more positive than the flatband
voltage) on the gate of capacitor on a p-type substrate causes the silicon-oxide interface to
be depleted of mobile charge carriers
– Width of the depletion region, xd, can be found 2ε Si φs − φFp
xd =
by integrating the Poisson equation for sheet charge qN A
from the surface (s) into the bulk, resulting in
– The depletion region charge is given by Qd = − 2qN Aε si | φs − φFp |
– Note that xd and Qd are maximum when φs = −φFp , which is in turn achieved at the onset of
strong inversion 15
 Deriving the Depletion Width and Charge
(Optional)
𝑉𝑉𝐹𝐹𝐹𝐹 < 𝑉𝑉𝐺𝐺 < 𝑉𝑉𝑇𝑇

φ is the voltage across

the depletion region
xd = f (φ ) x

dQ = −qN A dx ⇒ Mobile hole charge density in the thin layer

parallel to the Si surface
x qN A ⇒ Change in the surface potential required to displace
dφ =
− dQ =
x dx
ε si ε si dQ by distance x into bulk (Poisson equation)
φFp
xd qN A qN A 2
∫ dφ
=
φs
∫0
x
ε si
φFp − φs
dx →=
2ε si
xd

2ε si | φs − φFp |
xd = Q= − 2qN Aε si | φs − φFp |
−qN A xd =
qN A
16
 MOS Capacitor in Inversion
𝑉𝑉𝑇𝑇 < 𝑉𝑉𝐺𝐺

Note: At the Si-SiO2 interface, the Fermi energy gets closer to the
conduction band edge as expected when a high density of electrons is
• Inversion: present.
Top panels: An applied positive
gate voltage bends bands,
– A sufficiently large positive voltage applied to the gate of a MOS depleting holes from surface
(left). The charge inducing the
capacitor (with P substrate) induces mobile electrons in the oxide- bending is balanced by a layer
silicon interface and inverts the bands at the interface. of negative acceptor-ion charge
(right). Bottom panels: A larger
– The onset of weak inversion is defined as the gate voltage where the applied positive voltage further
Fermi level at the interface coincides with the intrinsic energy level Ei. depletes holes but conduction
band lowers enough in energy
– The total band bending = q|φFp| for weak inversion to populate a conducting
channel.
– The onset of strong inversion is defined as the gate voltage where the
Fermi level at the interface is above the intrinsic energy level Ei by the
same amount that it is below Ei in the bulk region
• This also means that the density of mobile electrons on the surface is equal
to that of holes in the bulk
• The total band bending = q|2φFp| for strong inversion 17
 Summary of Energy Band Diagrams
for the MOS Structure (p-type Silicon)
2 1 3 4

Holes
Exposed
acceptors

18
Total Charge Density in Si (Optional)

19
 Physical Structure of an n-Channel
Enhancement-Type MOSFET
The MOSFET shown in the adjacent figure
is an n-channel MOSFET, in which
electrons flow from source to drain in the
channel induced under the gate oxide.
Both n-channel and p-channel MOSFETs
are extensively used. In fact, CMOS IC
technology relies on the ability to use both
devices on the same chip. The table below
shows the dopant types used in each
region of the two structures.
Simplified Schematic of a MOSFET
n-channel p-channel
MOSFET MOSFET
Substrate (Channel) p n
Gate Electrode n+ p+

Source and Drain n+ p+

20
nMOS Transistor Under Different VGS
Values
Assuming 𝑉𝑉𝐹𝐹𝐹𝐹 = 0

(however, see next slide)

Metal–oxide–semiconductor
structure on p-type silicon
21
 Types of MOSFET Devices

Circuit symbols for n-channel and p-channel enhancement-type MOSFETs

22
 Threshold Voltage of MOS Transistors
Note: The same exact equations apply to both n-channel and p-channel devices, except
Consider an n-channel device: that one should use the fermi level of p-type substrate, 𝜙𝜙𝐹𝐹𝐹𝐹 , for nMOS transistors and the
fermi level of n-type substrate, 𝜙𝜙𝐹𝐹𝐹𝐹 , for pMOS transistors and sign of QBO changes.

For VSB=0, the threshold voltage is denoted as VT0

QBO Qox C
VT 0 =VFB − − 2φF where VFB =Φ MS − QBO = − 4qN Aε S i | φF | 2
, which
COX COX cm
VFB = flatband voltage 4ε si | φF |
is achieved at xd ,max =
QBO = depletion charge density at surface inversion qN A
QOX = (positive) fixed charge density at gate Si-oxide interface due to impurities and
lattice imperfections at the interface
Eg ε
= φM − χ −
Φ MS + φF COX = OX
Threshold voltage determinants: 2q tOX
- Gate conductor materials
- Gate oxide material & thickness 𝑉𝑉𝑇𝑇 can be changed by selective (shallow) ion implantation into the
channel. This is equivalent to adding a new term +𝑄𝑄𝐼𝐼 /𝐶𝐶𝑜𝑜𝑜𝑜 to the RHS
- Substrate doping
of the 𝑉𝑉𝑇𝑇 equation where QI is positive for acceptors and negative for
- Impurities in Si-oxide interface donors. More precisely, one can increase (make more positive) 𝑉𝑉𝑇𝑇 by
- Source-bulk voltage VSB adding extra p-type (acceptor) impurities and decrease (make more
- Temperature negative) 𝑉𝑉𝑇𝑇 by adding extra n-type (donor) impurities. The algebraic
sign of VT shift is independent of whether we have an n or p substrate.
23
 Threshold Voltage Cont’d
For VSB≠0, the threshold voltage is denoted as VT or VTn,p

− 2qN Aε S i | −2φF + VSB |

QB =

QB QOX
VT =Φ GC − 2φF − −
COX COX
Q Q Q − QB 0 Q − QB 0
=Φ GC − 2φF − B 0 − OX − B VT 0 − B
=
COX COX COX COX

QB − QB 0 2qN Aε Si
where =
− ( | −2φF + VSB | − | 2φF |) Band diagram showing the
COX COX body effect. VSB splits Fermi
levels Fn for electrons and Fp
VT = VT 0 + γ ( | −2φF + VSB | − | 2φF |) for holes, requiring larger
VGB to populate the
conduction band in an
2qN Aε Si nMOS MOSFET.
γ body
= effect coefficient
COX

24
Signs of Key Parameters

Parameter nMOS pMOS

𝜙𝜙𝐹𝐹 Negative Positive

QB0, QB Negative Positive

γ Positive Negative

VSB* Positive Negative

* For the reverse body biasing condition (resulting

in a larger magnitude of VT and a slower
switching speed for both transistor types)

25
 Examples of Reverse Body Biasing
𝑽𝑽𝑺𝑺𝑺𝑺, 𝒑𝒑𝒑𝒑𝒑𝒑𝒑𝒑 < 𝟎𝟎 𝑽𝑽𝑺𝑺𝑺𝑺, 𝒑𝒑𝒑𝒑𝒑𝒑𝒑𝒑 < 𝟎𝟎 during transition
s2
𝑉𝑉𝑆𝑆 = 𝑉𝑉𝐷𝐷𝐷𝐷
s1
𝑉𝑉𝑆𝑆 = 𝑉𝑉𝐷𝐷𝐷𝐷 → |𝑉𝑉𝑇𝑇,𝑝𝑝 |
𝑉𝑉𝐺𝐺 = 𝑉𝑉𝐷𝐷𝐷𝐷 → 0 s1
𝑉𝑉𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏 > 𝑉𝑉𝑉𝑉𝐷𝐷 𝑉𝑉𝐺𝐺 = 𝑉𝑉𝐷𝐷𝐷𝐷 → 0
𝑉𝑉𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏 = 𝑉𝑉𝑉𝑉𝐷𝐷
s2

𝑉𝑉𝐷𝐷 = 0 → 𝑉𝑉𝐷𝐷𝐷𝐷 𝑉𝑉𝐷𝐷 = 0

𝑽𝑽𝑺𝑺𝑺𝑺, 𝒏𝒏𝒏𝒏𝒏𝒏𝒏𝒏 > 𝟎𝟎 𝑽𝑽𝑺𝑺𝑺𝑺, 𝒏𝒏𝒏𝒏𝒏𝒏𝒏𝒏 > 𝟎𝟎 during transition

s2

𝑉𝑉𝐷𝐷 = 𝑉𝑉𝑉𝑉𝐷𝐷 → 0 𝑉𝑉𝐷𝐷 = 𝑉𝑉𝑉𝑉𝐷𝐷

s1
s1

𝑉𝑉𝐺𝐺 = 0 → 𝑉𝑉𝐷𝐷𝐷𝐷 𝑉𝑉𝐺𝐺 = 0 → 𝑉𝑉𝑉𝑉𝐷𝐷

𝑉𝑉𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏 < 0 𝑉𝑉𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏 = 0

s2

𝑉𝑉𝑆𝑆 = 0 𝑉𝑉𝑆𝑆 = 0 → 𝑉𝑉𝑉𝑉𝑉𝑉 − 𝑉𝑉𝑇𝑇,𝑛𝑛

26
 Example 1.1
Calculate the threshold voltage VT0 at 𝑉𝑉𝐵𝐵𝐵𝐵 = 0, for an aluminum gate, n-channel
MOS transistor with the following parameters. Assume there is no fixed charge
in the oxide or at the oxide-silicon interface.
Substrate doping density: N A = 1017 cm −3
Aluminum work function: qφM = 4.08eV
Silicon bandgap energy: Eg = 1.12eV
Gate oxide thickness: tox = 20nm
Silicon permittivity: ε si= 11.7 × ε 0= 11.7 × (8.85 ×10−14 )= 1.04 ×10−12 Fcm −1
Silicon oxide permittivity: ε ox= 3.9 × ε 0= 3.97 × (8.85 ×10−14 )= 0.34 ×10−12 Fcm −1
Electron affinity of Si: χ = 4.15V

kT ni  1.45 ×1010 
φFp = ln = 0.026 ln  17 =0.026(−7)(2.30) =
−0.42V
q NA  10 
E
φS = χ + g − φFp = 4.15 + 0.56 + 0.42 = 5.13V
2q
VFB = φMS =
Φ GC = φM − φS =4.08V − 5.13V =−1.05V
27
 Example 1.1, cont’d

− 2qN Aε S i | 2φF ( sub ) | =

QB 0 = − 2(1.6 ×10−19 C )(1017 cm −3 )(1.04 × 10−12 Fcm −1 )(2 × 0.42V )
−1.69 ×10−7 C / cm 2
=

ε OX
0.34 ×10−12 Fcm −1 −7 2
COX
= = = 1.7 × 10 F / cm
tOX 20 ×10−7 cm

QBO 1.69 ×10−7

VT 0 =Φ GC − 2φF ( sub ) − =−1.05V + 0.84 + =0.79V
COX 1.7 × 10−7

Notice that if we use TaSi2 gate with metal work function of 4.6eV, then the
threshold voltage will increase by 0.52V.

28
 Example 1.2
Calculate the threshold voltage VT0 at 𝑉𝑉𝐵𝐵𝐵𝐵 = 0, for an n-channel MOS transistor
with the following parameters:
Gate type: n+ Polysilicon
Substrate doping density: N A = 1016 cm −3
Gate oxide thickness: tox = 500 A
Oxide fixed positive charge density: N ox = 6 ×1010 cm −2

kT ni  1.45 ×1010 
φF ( sub ) = ln = 0.026 ln  16  = −0.35V Note that we could have also calculated 𝜙𝜙𝐺𝐺𝐺𝐺 for a n+
q NA  10  polysilicon gate as follows. Assuming: N D = 2 ×1020 cm −3
Eg φF ( gate )
=
kT N D
= ln
 2 ×1020 
0.026 ln  = 0.60V
φS = χ + − φF ( sub ) = 4.15 + 0.56 + 0.35 = 5.06V q ni  1.45 × 1010 

2q
Eg
φM= χ= 4.15V φM = χ + − φF ( gate ) = 4.15 + 0.56 − 0.6 = 4.11V
2q
φM − φS =
Φ GC = 4.15 − 5.06 =−0.91V Φ GC φM − φS =
= 4.11 − 5.06 = −0.95V

The results are very close and our approximate

calculation, setting 𝑞𝑞𝜙𝜙𝑀𝑀 for n+ polysilicon gate to the
bottom of the conduction band energy level, will be
sufficient for our hand calculations.
29
 Example 1.2 (cont.)
QOX QBO
VT 0 =Φ GC − − − 2φF ( sub )
COX COX
− 2qN Aε S i | 2φF ( sub ) | =
QB 0 = − 2(1.6 ×10−19 C )(1016 cm −3 )(1.04 ×10−12 Fcm −1 ) | 2 × 0.35V |

−4.87 ×10−8 C / cm 2
=

ε OX
0.34 ×10−12 Fcm −1
COX
= = −8
= 6.8 ×10−8 F / cm 2
tOX 500 ×10 cm

qN ox (1.6 × 10−19 C )(6 × 1010 cm −2 ) =

QOX == 9.6 × 10−9 C / cm 2

QBO −4.87 ×10−8 C / cm 2 QOX 9.6 ×10−9 C / cm 2

= −8 2
= −0.72
= V = −8 2
0.14V
COX 6.8 ×10 F / cm COX 6.8 ×10 F / cm

−0.91 − 0.14 + 0.72 + 0.70 =

VTO = 0.37V

30
 Example 1.3
Consider the n+ Polysilicon gate, n-channel MOS transistor with the
following process parameters:
Substrate doping density: N A = 1016 cm −3
Gate oxide thickness: tox = 500 A
Oxide-interface fixed charge density: N ox = 4 ×1010 cm −2

In digital circuit design, the condition 𝑉𝑉𝑆𝑆𝑆𝑆 = 0 cannot always be guaranteed for
all transistors. Plot the threshold voltage VT as a function of VSB.
VT =VT 0 + γ ( | 2φF − VSB | − | 2φF |)
2qN Aε si 2(1.6 ×10−19 C )(1016 cm −3 )(1.04 ×10−12 Fcm −1 )
=γ =
COX 6.8 × 10−8 F / cm 2

5.824 ×10−8 C / V −1/ 2 cm 2 1/ 2

= = 0.85V
6.8 ×10−8 C / Vcm 2

31
 Example 1.3 (cont.)

VT = VT 0 + γ ( 2 φF − VSB − 2 φF ) where
= VT 0 0.37
= V , γ 0.85V 1 2

32
Modes of Operations for an nMOS
Transistor

Operating in the linear region

Operating at the edge of saturation

Operating in saturation

33
 MOSFET Current-Voltage
Characteristics
• Consider the cross-sectional view of an n-MOS transistor
which is working in linear region

• Coordinate system:
– x direction: perpendicular to the surface pointing down
– y direction: parallel to the surface originating at source (y=0)

34
 Derivation of I-V Characteristics
(Optional)
• Assumptions:
– No body effect: VS=VB=0
– Inversion region is present between drain and source: VGS>VT0
– Electric field component Ey is dominant compared to Ex; therefore,
we can only consider current flow in the y-direction
• We must simplify the geometry of the channel region

35
 Derivation, Cont’d (Optional)
• Let Vc(y) denote the voltage of the channel at coordinate y
• Boundary conditions: Vc ( y = 0) = VS = 0
Vc ( y = L) = VDS
• This region where the channel behaves like a resistor is
referred to as the linear region of operation
• The entire channel region between source and drain is
inverted (linear region): VGS ≥ VT 0
VGD = VGS − VDS ≥ VT 0
• Mobile charge in the channel:
QI ( y ) = −Cox [VGS − VCS ( y ) − VT 0 ]

36
 Derivation, Cont’d (Optional)
• Now consider the resistance (dR) of channel segment dy:
dy
dR = −
W µnQI ( y )
where µn is the electron mobility (cm2/V.sec)
• Then ID
dVc = I D dR = − dy
W µnQI ( y )
• We can now integrate equation the above along the channel:
L VDS
∫0
I D dy = −W µn ∫
0
QI ( y ) dVc
VDS
=I D .L W µnCox ∫
0
[VGS − VCS − VT 0 ] dVc
• We get
µnCox W
=ID  2(VGS − VT 0 )VDS − VDS
2

2 L 37
 MOSFET I-V Characteristics in the
Linear Mode
• We have:

µnCox W
=ID  2(VGS − VT 0 )VDS − VDS
2

2 L

• The current equation may also be rewritten as:

ID =
k' W
2 L
[ 2
2(VGS − VT 0 )VDS − VDS ⇒ ]
k
[
I D = 2(VGS − VT 0 )VDS − VDS
2
2
]
where parameters k and k’ are defined as:
W
= k ' µ= n Cox & k k'
L 38
 Example 1.4
For an n-channel MOS transistor with µn=600 cm2/V.s, Cox=7x10-8
F/cm2, W=20 µm, L=2 µm and VT0=1.0 V, plot the relationship
between drain current and the terminal voltages.
20 µ m
=k 600cm 2 / V .s × 7 ×10−8 F / cm=
2
× 0.42 mA / V 2
2µ m
=I D 0.21 mA / V 2  2(VGS − 1)VDS − VDS2 

39
 MOSFET I-V Characteristics in the
Saturation Mode
• The ID-VDS equations were derived for the linear region of
transistor operation, i.e., VGS ≥ VT 0 , VGD = VGS − VDS ≥ VT 0
• For 𝑉𝑉𝐷𝐷𝐷𝐷 values larger than 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇 , the MOS transistor is in
the saturation region
• In this case, ID does not show much variation as a function of
the drain voltage, 𝑉𝑉𝐷𝐷𝐷𝐷, beyond the saturation voltage, i.e., for
𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝐷𝐷𝐷𝐷 ≤ 𝑉𝑉𝑇𝑇𝑇 . More precisely,
µnCox W 
2 (VGS − VT 0 )(VGS − VT 0 ) − (VGS − VT 0 )

2
I D ( sat )
=
2 L  
µnCox W
(VGS − VT 0 )
2
I D ( sat )
=
2 L

40
n-MOS ID-VDS and ID-VGS Curves

41
 Channel Length Modulation
• The inversion layer charge at the source and drain ends are:
QI ( y = 0) = −Cox (VGS − VT 0 )
QI ( y = L) = −Cox (VGS − VT 0 − VDS )
• At the edge of saturation, VDS=VDSAT:
QI ( y = L) ≈ 0
• This means that under this bias condition, the channel is
pinched-off at the drain end
• If 𝑉𝑉𝐷𝐷𝐷𝐷 is increased beyond 𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷, a larger portion of the
channel becomes pinched-off
• Thus, the effective channel length is reduced to:
L '= L − ∆L
where Δ𝐿𝐿 is the length of the channel with 𝑄𝑄𝐼𝐼 = 0
42
 Length Modulation Cont’d
• The pinch-off point moves from the drain end toward source
Vc (=
y L= ') VDSAT
• Drain current can be found by using the effective channel
length µnCox W 1 µnCox W
(VGS − V= ) ( )
2 2
( sat )
I D= V − V
2 L'
T0
∆L 2 L
GS T0
1−
L
• It can be shown that: ∆L ∝ VDS − VDSAT

43
 Length Modulation Cont’d
∆L
• We can make the following approximation: 1 − ≈ 1 − λVDS
L
where λ is the channel length modulation coefficient
• Assuming λVDS << 1, we calculate the saturation current as:
µnCox W 1
(VGS − VT 0 ) (1 + λVDS )
2
I D (=
sat ) 1− x
≈ 1 + x when x << 1
2 L

44
 Body Bias Effect
• Recall that applying a substrate voltage changes the
threshold voltage:
VT (VSB ) =VT 0 + γ 2ϕ F − VSB − 2ϕ F ( )
• We can simply replace the threshold voltage terms in
linear-mode and saturation-mode current equations with
𝑉𝑉𝑇𝑇(𝑉𝑉𝑆𝑆𝑆𝑆 )
µnCox W
I D (lin
= )  2 (VGS − VT (VSB ) ) VDS − VDS
2

2 L
µC W
I D ( sat )= n ox (VGS − VT (VSB ) ) (1 + λVDS )
2

2 L

45
 MOSFET Current-Voltage Equations

• For nMOS transistor (𝜆𝜆 ≥ 0):

I D (cutoff
= ) 0 VGS < VT
µnCox W
I D (lin)
=
2 L
( 2 (V GS − VT (VSB ) )VDS − VDS
2
) VGS ≥ VT and VDS < VGS − VT

µnCox W
(VGS − VT (VSB ) ) (1 + λVDS ) VGS ≥ VT
2
I D ( sat )
= and VDS ≥ VGS − VT
2 L

• For pMOS transistor (𝜆𝜆 ≤ 0):

I D (cutoff
= ) 0 VGS > VT
µ p Cox W
I D (lin)
=
2 L
( 2 (V
GS − VT (VSB ) ) VDS − VDS
2
)
VGS ≤ VT and VDS > VGS − VT

µ p Cox W
(VGS − VT (VSB ) ) (1 + λVDS ) VGS ≤ VT
2
I D ( sat )
= and VDS ≤ VGS − VT
2 L

46
 Measurement of Parameters
(𝑉𝑉𝑇𝑇𝑇 , 𝑉𝑉𝑇𝑇 , 𝛾𝛾, 𝜆𝜆, 𝑘𝑘𝑛𝑛 )
• Consider the following test circuit, the source to substrate
voltage is set to a constant value and the drain current is
measured for the different values of the gate-source voltage, 𝑉𝑉𝐺𝐺𝐺𝐺
• Since the drain and the gate of the transistor are connected
together, the saturation condition is always satisfied, i.e., 𝑉𝑉𝐷𝐷𝐷𝐷 >
𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇
• Ignoring the channel length
modulation effect, we can write:
kn
(VGS − VT 0 )
2
( sat )
I D=
2
kn
I D ( sat )
= (VGS − VT 0 )
2

47
 Measurement of Parameters (Cont’d)
• If the square root of the drain
current is plotted against the gate-
source voltage, the slope and the
voltage-axis intercept of the
resulting curve(s) can determine
parameters 𝑘𝑘𝑛𝑛 and 𝑉𝑉𝑇𝑇𝑇
• For different 𝑉𝑉𝑆𝑆𝑆𝑆 , we can find
𝑉𝑉𝑇𝑇(𝑉𝑉𝑆𝑆𝑆𝑆 ) and from there we can
calculate 𝛾𝛾
VT (VSB ) − VT 0
γ=
2φF − VSB − 2φF

48
 Measurement of Parameters (Cont’d)
• We need a different experimental setup to measure the channel
length modulation coefficient, 𝜆𝜆
• Here, the gate-source voltage 𝑉𝑉𝐺𝐺𝐺𝐺 is set to 𝑉𝑉𝑇𝑇𝑇 + 1𝑉𝑉 and the
drain-source voltage is chosen to be sufficiently large so that
the transistor operates in the saturation mode. The saturation
drain current is then measured for two different 𝑉𝑉𝐷𝐷𝐷𝐷 values
• 𝜆𝜆 is calculated as follows:
I D 2 1 + λVDS 2
=
I D1 1 + λVDS 1

49
 MOSFET Scaling
• Scaling of MOS transistor is concerned
with the systematic reduction of overall
dimensions of the devices as allowed
by the available technology, while
preserving the geometric ratios found
in the larger devices

• We observe that a new

manufacturing technology is
introduced every 18 to 24
months. Furthermore, the
physical scaling factor S is
between 1.2 and 1.5 50
 Full Scaling (Constant-Field Scaling)
• This scaling option attempts Quantity Before
Scaling
After
Scaling
to preserve the magnitude of Channel length 𝐿𝐿 𝐿𝐿’ = 𝐿𝐿 /𝑆𝑆
internal electric fields in the Channel width 𝑊𝑊 𝑊𝑊’ = 𝑊𝑊/𝑆𝑆
MOSFET, while the Gate oxide thickness 𝑡𝑡𝑜𝑜𝑜𝑜 𝑡𝑡𝑜𝑜𝑜𝑜’ = 𝑡𝑡𝑜𝑜𝑜𝑜 /𝑆𝑆
dimensions are scaled down Junction depth 𝑥𝑥𝑗𝑗 𝑥𝑥𝑗𝑗’ = 𝑥𝑥𝑗𝑗 /𝑆𝑆
by a factor of S Power supply voltage 𝑉𝑉𝐷𝐷𝐷𝐷 𝑉𝑉𝐷𝐷𝐷𝐷’ = 𝑉𝑉𝐷𝐷𝐷𝐷 /𝑆𝑆

• The scaling factor for Threshold voltage 𝑉𝑉𝑇𝑇𝑇 𝑉𝑉𝑇𝑇𝑇 ’ = 𝑉𝑉𝑇𝑇𝑇 /𝑆𝑆

different parameters in this Channel doping

concentrations
𝑁𝑁𝐴𝐴 , 𝑁𝑁𝐷𝐷 𝑁𝑁𝐴𝐴’ = 𝑆𝑆. 𝑁𝑁𝐴𝐴
𝑁𝑁𝐷𝐷’ = 𝑆𝑆. 𝑁𝑁𝐷𝐷
case is as follows:
1. All dimensions, including those
vertical to the surface, 1/S
2. Device voltages, 1/S
3. Concentration densities, S

51
 Full Scaling (Cont’d)
• For linear mode and saturation mode drain current we have:
kn'  S kn 1 I D (lin)
'
I (lin
D = )
2 
2 V ( '
GS − VT
'
V '
DS )− V='2
DS 

2 S2 
 2 (V GS − VT ) VDS − V=2

DS 
S
kn' S kn 1 I D ( sat )
( )
2
( )
' 2
I D ( sat =
) VGS' − VT' = VGS − VT =
2 2 S2 S

• For propagation delay of the transistor, we have:

CL ∆V
' '
C ∆V Delay
Delay ' ∝ L ' = S S =
I I S
S
• For power dissipation of the transistor, we obtain:
I V Power
=' I=
Power ' '
V =
S S S2
– With the device area reduction by S2, we find that the power density
(W/cm2) remains unchanged for the scaled device

52
 Constant-Voltage Scaling
• In this case power supply voltage as well as the terminal
voltages remain unchanged
• The scaling factor for different parameters in this case is as
follows:
1. All dimensions including those vertical to the surface, 1/S
2. Supply voltage and threshold voltages, 1
3. The concentration densities, S2
Quantity Before After Scaling
Scaling
Dimensions 𝑊𝑊, 𝐿𝐿, 𝑡𝑡𝑜𝑜𝑜𝑜, 𝑥𝑥𝑗𝑗 reduced by S
(𝑊𝑊’ = 𝑊𝑊/𝑆𝑆,…)
Voltages 𝑉𝑉𝐷𝐷𝐷𝐷, 𝑉𝑉𝑇𝑇 remain unchanged
Doping densities 𝑁𝑁𝐴𝐴 , 𝑁𝑁𝐷𝐷 increased by S2
(𝑁𝑁𝐴𝐴’ = 𝑆𝑆2. 𝑁𝑁𝐴𝐴 )
53
 Constant-Voltage Scaling (Cont’d)
• In this case for linear mode and saturation mode drain current,
we have: kn'
'
I D (lin=
)  2 (VGS − VT ) VDS − VDS 
' ' ' '2

2  
S .kn
=  2 (VGS − VT ) VDS −=2
VDS  S I D (lin)
2
kn' ' Skn
'
I ( sat )=
D
2
(VGS − VT ) =
' 2

2
(VGS − VT ) = S I D ( sat )
2

• And for the power dissipation of the transistor we have:

=P ' I=
' '
D VDS ( S I D=
)VDS SP

• Thus, the power density (power dissipation per unit area) is

found to increase by a factor of 𝑆𝑆3
54
 Short-Channel Effects (SCE)
• A MOS transistor is called a short-channel device if its channel length is on
the same order of magnitude as the depletion region thickness of the source
and drain junctions
• The short-channel effects are mainly attributed to two physical phenomena:
1. Limitation on the electron drift characteristics in the channel
2. Reduction of the threshold voltage due to shortening of the channel length

GATE LENGTH, L
GATE WIDTH, W OXIDE THICKNESS, Tox

Gate Important SCE include:

• Drain-induced
barrier lowering and
Source Drain punchthrough
• Surface scattering
• Velocity saturation
Substrate
M. Bohr, Intel Developer
JUNCTION DEPTH, Xj Forum, September 2004

55
 Short-Channel Effect on Electron Drift
Characteristics
• In short-channel MOS transistor, the carrier velocity in the
channel is also a function of the vertical electric field, Ex
• Since the vertical field influences the scattering of the carriers in
the surface, the surface mobility is reduced with respect to the
bulk mobility
• The surface electron mobility can be expressed as follows:
Recall that (absolute) permittivity is µ µ
the measure of resistance that is = µn ( y ) = n0 n0

1 + Θ Ex ( y ) 1 + Θε ox V − V ( y )
encountered when forming an
( GS c )
electric field in a particular medium.
toxε Si
where 𝜇𝜇𝑛𝑛𝑛 is the low-field surface mobility and Θ is an empirical
factor. A simple estimation of the above formulae by using
another empirical factor, ζ , is: µn (eff ) =
µn 0
1 + ζ (VGS − VT )
– ζ =1.2 is typical in a 65nm technology node

56
Velocity Saturation and Short Channel Device
Current Equations – Version I (Optional)
• In short-channel MOSFETs, when a strong enough electric field (𝐸𝐸𝐶𝐶 ) is
applied, the carrier velocity reaches a maximum value, saturation velocity, vsat ,n
• When this happens, short-channel MOSFETs are said to be in a velocity
saturation regime
• Some have suggested the following simplified equation for short-channel
MOSFET current in saturation (i.e., when 𝑉𝑉𝐺𝐺𝐺𝐺 ≥ 𝑉𝑉𝑇𝑇 and 𝑉𝑉𝐷𝐷𝐷𝐷 ≥ 𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 ):
I D ( sat ) Wvsat ,n Cox (VGS − VT − VDSAT )
= Typical values:
7
EC L µn EC vsat ,n = 10 cm / s
where VDSAT (VGS − VT )
= and vsat ,n =
(VGS − VT ) + EC L 2 Ec = 105V / cm

• By plugging 𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 and 𝑣𝑣𝑠𝑠𝑠𝑠𝑠𝑠 equation into the 𝐼𝐼𝐷𝐷(𝑠𝑠𝑠𝑠𝑠𝑠) equation, we get:
(VGS − VT ) 2 µnCox W 2 Ec L 
I D ( sat ) Wvsat Cox
= = (VGS − VT )  
(VGS − VT ) + EC L 2 L  (VGS − VT ) + EC L 
• Example: 𝑉𝑉𝐷𝐷𝐷𝐷 = 1.5𝑉𝑉, 𝑉𝑉𝑇𝑇 = 0.5𝑉𝑉, 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 = 1𝑉𝑉. For 𝐿𝐿 = 180𝑛𝑛𝑛𝑛, 𝐸𝐸𝐶𝐶 𝐿𝐿 = 1.8𝑉𝑉.
• Notice when VGS − VT << EC L , the above equation is reduced to the long channel
device current equation! In the above example, this condition is not met.
57
Short Channel Device Current Equations –
Version II
• More often, we use the Alpha-Power Device Current Equations to account
for the velocity saturation effect for short-channel MOSFETs, which are as
follows:
k
( )
α
I=
D ( sat ) ω sat VGS − VT where 1 < α ≤ 2
2
I D (lin) ωlin k (VGS − VT )
α 2
= VDS

where ωlin, ωsat are scaling parameters (which are typically set to 1) and α is
an empirical coefficient. For a 60nm bulk CMOS process, α = 1.45

Plot of actual drain current

vs. alpha-power current
predictions for a 60nm bulk
CMOS process

58
 Effect of Short Channels on the Threshold
Voltage
• In short-channel MOS, there is a large amount of depletion charge around the source
and drain (this is even before a gate voltage is applied i.e., channel is somewhat
depleted by the built-in potential between channel and S/D regions); therefore, the long
channel model overestimates the amount of depletion charge that must be supported by
the gate voltage, resulting in the over-estimation of VT0 in short channel devices:
VT 0, ROE
= VT 0 − ∆VT 0, ROE

1 xj 1 2x 2x  
∆VT 0, ROE 2qε Si N A 2φF   1 + dS + 1 + dD  − 1
Cox L  2  xj xj  
 

where Δ𝑉𝑉𝑇𝑇𝑇, 𝑅𝑅𝑅𝑅𝑅𝑅 denotes the magnitude of the threshold voltage reduction due to the short-
channel effect whereas 𝑥𝑥𝑗𝑗 is the junction depth for source and drain regions, and 𝑥𝑥𝑑𝑑𝑑𝑑
and 𝑥𝑥𝑑𝑑𝑑𝑑 denote the depth of the pn-junction depletion regions associated with the
source and drain regions
• This modification of the threshold voltage due to short-channel effect is also called the
“VT roll-off effect” or ROE for short
– This effect is stronger when the channel is shorter (Δ𝑉𝑉𝑇𝑇𝑇, 𝑅𝑅𝑅𝑅𝑅𝑅 is larger for shorter channel devices)
– This effect is even more prominent when the p-n junction between the S/D region and the channel is
strongly reverse-biased, giving rise to the DIBL effect (see next slide)
USC/EE 59
 Effect of Drain-Induced Barrier Lowering
on the Threshold Voltage
• DIBL is threshold voltage reduction with the drain voltage
– The meaning is that the drain current is influenced by drain
voltage, not just the gate voltage
– DIBL is most noticeable in short-channel devices - it is
especially important in the subthreshold regime of operation
– DIBL effect is qualitatively similar to VT roll-off in that it is
caused by the encroachment of the depletion region from the
drain into the channel – although here the issue has to do with a
change in the channel potential due to depletion region around
the drain
– Strong DIBL effect is an indication of poor short channel
behavior
VT 0, DIBL ≈ VT 0 − ∆VT 0, DIBL As channel length decreases, the
barrier φB to be surmounted by an
(ξ + ρVDS ) e−Λ
∆VT 0, DIBL = electron from the source on its way
to the drain reduces.
L
where Λ = is channel length in units of λ
λ
ξ and ρ are fixed coefficients

M. Pedram USC/EE 60
Example of DIBL

61
 Combined Impact of ROE and DIBL
on 𝑉𝑉𝑡𝑡𝑡

0.7

Threshold Voltage (V)

0.6
∆ VT
0.5
(ROE)
Low Drain Voltage
0.4
∆ VT High Drain Voltage
0.3
(DIBL)
0.2
0.1 ROE: Roll-off Effect
DIBL: Drain-induced Barrier Lowering
0
0.1 1 10
Channel Length ( µm)

VT 0, SCE ≈ VT 0 − ∆VT 0, ROE − ∆VT 0, DIBL

M. Pedram USC/EE 62
 Subthreshold Current Conduction
• In small-geometry MOSFET’s, the potential barrier for the electrons
in the channel is controlled by both gate-source voltage and drain-
source voltage
• In this case, if the drain-source voltage is increased, the potential
barrier decreases, and we have significant current even when 𝑉𝑉𝐺𝐺𝐺𝐺 <
𝑉𝑉𝑇𝑇𝑇
• The channel current that flows under these conditions (𝑉𝑉𝐺𝐺𝐺𝐺 < 𝑉𝑉𝑇𝑇𝑇 ) is
called the sub-threshold current (this is the main source of leakage
power consumption in most CMOS technology nodes):
VGS −VT +η VDS
W nν θ
 −VDS
 kT
I D ( sub) ≡
= I sub µeCox (n − 1)ν θ2 e 1 − e νθ νθ
 where=
L   q
 
−VT −VT
W W 
VGS= 0, VDS >> ν θ ,η= 0 ⇒ I sub= µeCox (n − 1)ν θ2 e nνθ ∝  10 S
L L
M. Pedram USC/EE 63
 Subthreshold Current Conduction,
Cont’d
• The subthreshold swing (a.k.a. the inverse subthreshold slope),
S, is equal to the voltage required to increase ID by 10X, i.e.,
−1
 ∂ (log10 I sub )  kT
=S  =  nν
= θ ln10 2.3n
 ∂V GS  q
– n ≥1 is called the body effect coefficient
𝑡𝑡𝑜𝑜𝑜𝑜
– 𝑛𝑛 = 1 + 3𝑥𝑥 if we ignore the channel-oxide interface states (see the
𝑑𝑑𝑑𝑑𝑑𝑑,𝑚𝑚
next page)
– If 𝑡𝑡𝑜𝑜𝑜𝑜 → 0 then n → 1, S → 60 mV/decade at 300 K
– We want S to be small to shut off the MOSFET quickly
– In well-designed bulk CMOS devices, S is 70-90 mV/decade at 300 K

M. Pedram USC/EE 64
 Derivation of n value (Optional)
Simple Model:

Relative Permittivity of Si: 11.7 ~ 12

Relative permittivity of SiO2= 3.9 ~ 4

4𝜖𝜖0
𝐶𝐶𝑜𝑜𝑜𝑜 +𝐶𝐶𝑑𝑑𝑑𝑑𝑑𝑑 𝐶𝐶𝑑𝑑𝑑𝑑𝑑𝑑 𝑥𝑥𝑑𝑑𝑑𝑑𝑑𝑑,𝑚𝑚 𝑡𝑡𝑜𝑜𝑜𝑜
𝑛𝑛 = =1+ =1+ 12𝜖𝜖0 =1+
𝐶𝐶𝑜𝑜𝑜𝑜 𝐶𝐶𝑜𝑜𝑜𝑜 3𝑥𝑥𝑑𝑑𝑑𝑑𝑑𝑑,𝑚𝑚
𝑡𝑡𝑜𝑜𝑜𝑜

65
 Modeling Subthreshold (Isub) and off (Ioff)
Currents
• Isub increases exponentially with reduction in VT
• Modulation of VT in a short channel transistor
– L ↓ ⇒ VT ↓: “Vth Rolloff”
– VDS ↑ ⇒ VT ↓:”Drain Induced Barrier Lowering”
– VSB ↑ ⇒ VT ↑: “Body Effect”
• If VDS = 0 ⇒ Isub = 0 VGS −VT
W
• If long-channel device w/ VDS > 3nν θ ⇒ I sub = µeν θ2Csth e nνθ
L
• With Csth Cdep + Cis
1+
n= 1+
=
Cox Cox
• Key dependencies of the subthreshold slope:
– tox ↓ ⇒ Cox ↑ ⇒ n ↓ ⇒ sharper subthreshold V
W − T
– NA ↑ ⇒ Csth ↑ ⇒ n ↑ ⇒ softer subthreshold I off= I sub (VGS= 0)= µeν θ2Csth e nνθ
L
– VSB ↑ ⇒ Csth ↓ ⇒ n ↓ ⇒ sharper subthreshold
– T ↑ ⇒ softer subthreshold
M. Pedram USC/EE 66
 Subthreshold Swing
• VT , Ioff 
• Subthreshold swing (S)  , Ioff 
• S  with increased doping density, reduced gate length (drain-induced
barrier lowering)
• Silicon on Insulator (SOI) technology is able to achieve S = 60 mV/decade
10-7 10-7
L=0.25 µm S=120 mV/decade
10-8 S=120 mV/decade 10-8 Intel Data
Ioff (A/µm)

Ioff (A/µm)
90 mV/dec
10-9 10-9
90 mV/dec
10-10 60 mV/dec 10-10

10-11 10-11
L=0.25 µm 60 mV/dec
10-12 10-12
0 0.2 0.4 0.6 0.8 1 0.2 0.4 0.6 0.8 1
VT (V) IDsat (mA/µm)

M. Pedram USC/EE 67
Ion vs. Ioff for 90nm CMOS

68
 MOSFET Capacitances
• To examine the transient (AC) response of MOSFET, we
have to determine the nature and the amount of parasitic
capacitances associated with the MOS transistor
• There are two different types of parasitic capacitances:
1. Device-related capacitances
2. Interconnect-related capacitances
• For now, we only consider device-related capacitances and
will postpone a discussion of the interconnect capacitances

69
 MOSFET Capacitances (Cont'd)
• The mask length and actual
length of the gate are indicated
by L and Leff, respectively.
The extents of both gate-
source and gate-drain overlap
are LD. So we have:

Leff= L − 2 LD

• Note that p+ regions around L

the source and drain, namely

the channel-stop implants, are
used to prevent the formation
of any unwanted channels
between two neighboring n+
diffusion regions

70
 MOSFET Capacitances (Cont'd)
• Most of the parasitic capacitances are not lumped, but
distributed, and their exact calculation is complex
• We will identify the parasitic capacitances associated with a
MOSFET as lumped equivalent capacitances observed
between the device terminals
• Such a lumped representation is easily used to analyze the
dynamic transient behavior of the device
• Parasitic capacitances are divided into
two major groups:
1. Oxide-related capacitances (Cgd, Cgs, Cgb)
2. Junction capacitances (Cdb, Csb)

71
 Gate Oxide-Related Capacitances
• Gate oxide-related capacitances comprise of overlap
and gate-channel capacitances
• Gate-channel capacitances are: 𝐶𝐶𝑔𝑔𝑔𝑔 , 𝐶𝐶𝑔𝑔𝑔𝑔 , 𝐶𝐶𝑔𝑔𝑔𝑔 (see next
slide)
• Overlap capacitances:
CGSO = WLD Cox ε ox
with Cox =
CGDO = WLD Cox tox

72
Oxide-Related Capacitances (Cont'd)

73
 Oxide-Related Capacitances (Cont'd)

We typically
ignore 𝐶𝐶𝐺𝐺𝐺𝐺0

• Variation of the distributed

(gate-to-channel) oxide
capacitances as functions
of gate-to-source voltage is
shown in the figure

Summary Result (worst-case value):

Cg = WLCox

74
Junction Capacitances (Cdb, Csb)

75
Junction Capacitances (Cont'd)

76
 Junction Capacitances (Cont'd)

-
V
+

Let V denote the forward-bias junction potential (i.e., p to n+ region potential), then
2ε Si N A + N D kT  N A N D 
xd (ϕ0 − V ) where the built-in junction potential is: ϕ0 = ln  
q N A ND q  ni2 

The depletion region charge around the junction (A is the junction area) is:

 N AND   N AND 
=Q j Aq
=  x
 d A 2ε q
Si   (ϕ 0 − V )
N
 A + N D  N
 A + N D 

77
 Junction Capacitances (Cont'd)
• The junction capacitance can be obtained by differentiating Qj
with respect to the bias voltage, V:
dQ j ε Si q  N A N D  1
Cj = C j (V ) = A  
dV 2  N A + N D  ϕ0 − V

• Or in more general form, to account for junction grading:

AC j 0
C j (V ) = m
 V 
1 − 
 ϕ0 
where m is called the grading coefficient. For abrupt junction
profiles m=1/2, and for linearly graded junction profile m=1/3
The zero-bias junction
ε Si q  N A N D  1
capacitance per unit area C j0 =  
(𝐶𝐶𝑗𝑗 = 𝐶𝐶𝑗𝑗0 for 𝑉𝑉 = 0) 2  N A + N D  ϕ0

78
 Equivalent Large Signal Capacitance
• The equivalent large-signal (bias-voltage independent)
capacitance can be defined as:
∆Q Q j (V2 ) − Q j (V1 ) 1 V2
C=
j , eq =
∆V V2 − V1
=
V2 − V1 ∫V1
C j (V ) dV

• The reverse bias voltage is assumed to change between two

known values V1 and V2
AC j 0ϕ0  V 1− m  V 1− m 
C j ,eq = −  1 − 2  −  1 − 1   = AC j 0 K eq
(V2 − V1 )(1 − m)  ϕ0  ϕ
  0  
C j ,eq = AC j 0 K eq
or ϕ0  V 1− m  V 1− m 
K eq =−  1 − 2  −  1 − 1  
(V2 − V1 )(1 − m)  ϕ0   ϕ0  

1
• For abrupt pn-junctions, we set 𝑚𝑚 = .
2
79
 Sidewall Junction Capacitances
• For n+, p+ junctions (sidewalls), we have:
kT  N A ( sw) N D  ε Si q  N A ( sw) N D  1
ϕ0 sw = ln   C j 0 sw =  
q  ni2  2  N A ( sw) + N D  ϕ0 sw

• Next define: 𝐶𝐶𝑗𝑗𝑗𝑗𝑗𝑗 = 𝐶𝐶𝑗𝑗𝑗𝑠𝑠𝑠𝑠 𝑥𝑥𝑗𝑗

• Then, C = PC K jsw , eq jsw sw , eq

ϕ0 sw  V2 
1− m
 V1  
1− m

K sw,eq =−  1 −  − 1 −  
(V2 − V1 )(1 − m)  ϕ0 sw   ϕ0 sw  


where parameter 𝑃𝑃 denotes the perimeter of the sidewall faces

(this is because 𝑥𝑥𝑗𝑗 is now absorbed into 𝐶𝐶𝑗𝑗𝑗𝑗𝑗𝑗 .) Again, for
1
abrupt pn-junctions, we set 𝑚𝑚 = .
2
80
 Example 1.5
An abrupt pn-junction is reversed bias with Vbias, the
junction area is A=20 μm×20 μm, ND=1019 cm-3, NA=1016 cm-3.
Find the average junction capacitance assuming that the bias
voltage shown below changes from 𝑉𝑉1 = 0𝑉𝑉 to 𝑉𝑉2 = 5𝑉𝑉.

81
 Example 1.5, Cont’d
• We first calculate Cj0: Notice that V1 and V2
in the equations for K
kT  N A N D   10161019  were defined as bulk to
=ϕ0 = ln  2  0.026 V =
ln  20 
0.88 V
q  ni   2.1×10  drain voltage for
nMOS, hence the flip in
ε Si q  N A N D  1
C j0 =   sign when we refer to
2  N A + N D  ϕ0 the corresponding VDB
11.7 × 8.85 ×10−14 F / cm ×1.6 ×10−19 C  1016 ×1019  1 values.
=  16 19 
2  10 + 10  0.88V Also, note that K values
−8 2
= 3.1×10 F / cm are the same for V1 to
2 ϕ0 V2 transition and V2 to
K eq =
−
V2 − V1
( ϕ0 − V2 − ϕ0 − V1 ) V1 transition.

2 0.88
=−
−5
( 0.88 − (−5) − 0.88 =0.56)
C j ,eq = AC j 0 K eq
= 400 ×10−8 cm 2 × 3.1×10−8 F / cm 2 × 0.56 = 69 fF
82
 Example 1.6
• An n-channel enhancement type
MOSFET as shown in the figure has:
– Substrate doping NA=2×1015 cm-3
– Source/drain doping ND=1019 cm-3
– Sidewall (p+) doping NA(sw)=4×1016 cm-3
– Gate oxide thickness tox=45 nm
– Junction depth xj=1.0 μm
Calculate the drain diffusion
capacitance, 𝐶𝐶𝑑𝑑𝑑𝑑 when 𝑉𝑉𝐷𝐷𝐵𝐵 changes
from V1=5V to V2=0.5V.

83
 Example 1.6, Cont’d
kT  N A N D   2 ×1015 ×1019 
ϕ0 =ln   0.026 V ln  =  0.837 V
q  ni2   2.1 × 10 20

kT  N A ( sw) N D   4 ×1016 ×1019 
ϕ0 sw =ln   0.026V=
ln   0.915 V
q  ni2   2.1 × 10 20


ε Si q  N A N D  1
C j0 =  
2  N A + N D  ϕ0

11.7 × 8.85 ×10−14 F / cm ×1.6 ×10−19 C  2 ×1015 ×1019  1

 15 19 
×
2  2 ×10 + 10  0.837 V
= 1.41×10−8 F / cm 2

ε Si q  N A ( sw) N D  1
C j 0 sw =  
2  N A ( sw) + N D  ϕ0 sw

11.7 × 8.85 ×10−14 F / cm ×1.6 ×10−19 C  4 ×1016 ×1019  1

 16 19 
×
2  4 ×10 + 10  0.915V
= 6.01×10−8 F / cm 2
84
 Solution 1.6 (Cont.)
C jsw = 6.01×10−8 F / cm 2 ×10−4 cm =
C j 0 sw x j = 6.01 pF / cm

2 0.837
K eq =
−
(−0.5) − (−5)
× ( )
0.837 + 0.5 − 0.837 + 5 =
0.51

2 0.915
K sw,eq =
−
(−0.5) − (−5)
× ( )
0.915 + 0.5 − 0.915 + 5 =
0.53

Area ≡ A = Abottom + Aside = (10 × 5) µ m 2 + (5 ×1) µ m 2 = 55 µ m 2

P 10 µ m × 2 + 5µ=
Perimeter ≡= m 25µ m

=Cdb AC j 0 K eq + PC jsw K sw,eq

=55 ×10−8 cm 2 ×1.41×10−8 F / cm 2 × 0.51
+ 25 ×10−4 cm × 6.01×10−12 F / cm × 0.53
11.9 ×10−15 F =
= 11.9 fF

85
 Diode-Connected MOSFET

Top terminal

NMOS FET

Diode (bottom terminal > -0.7V or so)

86
 Capacitance-Connected MOSFET
When we tie the source and drain terminals of a MOSFET together, we get a
simple capacitor to the gate terminal as seen below:
Bottom terminal

Signal line
Top terminal

NMOS FET NMOS FET

Capacitance (bottom terminal > -0.7V or so) Capacitance to Gnd

87
 Capacitance-Connected MOSFET
(Capacitance in Parallel with a Diode)
When we separate the drain terminal of a MOSFET from the bulk, we get a
capacitor in parallel with a diode (with positive terminal grounded) as seen
below:
Top terminal Top terminal

Helpful
connection but VDD
not required Bottom terminal
tied to GND

Bottom terminal
tied to GND

NMOS FET NMOS FET

Source/Drain to bulk capacitance Drain to bulk capacitance

88
 Resistance-Connected MOSFET
(Resistance in Parallel with a Diode)
When we tie the Gate Terminal of an NMOS to VDD (or of a PMOS to Gnd),
and thus obtain a resistance between its source and drain terminals along
with a parallel-connected diode (with the + cathode at the drain terminal):

VDD

NMOS FET

Transistor with on resistance RD/S(on)

1
rD𝑆𝑆(𝑜𝑜𝑜𝑜) =
𝑊𝑊
𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜
𝐿𝐿 (𝑉𝑉𝐺𝐺𝐺𝐺
− 𝑉𝑉𝑇𝑇 )
89
MOSFET Model for Analog Circuits
(Optional)

90
N-Type MOSFET Small-Signal Model
(Optional)

91