Scribd
Upload
35 views1 page

Mid Semester HPC Compact

The document outlines a mid-semester examination for High Performance Computing with a total duration of 2 hours and a maximum score of 20 marks. It includes objective questions, brief answer questions, and detailed answer questions covering topics such as graph search algorithms, CUDA programming, array processor architectures, Amdahl's Law, speedup in parallel systems, data parallel approaches, NUMA and UMA architectures, load balancing techniques, and multithreading. The examination assesses students' understanding of key concepts in high performance computing.

Uploaded by

मनीष सिंह
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
35 views1 page

Mid Semester HPC Compact

The document outlines a mid-semester examination for High Performance Computing with a total duration of 2 hours and a maximum score of 20 marks. It includes objective questions, brief answer questions, and detailed answer questions covering topics such as graph search algorithms, CUDA programming, array processor architectures, Amdahl's Law, speedup in parallel systems, data parallel approaches, NUMA and UMA architectures, load balancing techniques, and multithreading. The examination assesses students' understanding of key concepts in high performance computing.

Uploaded by

मनीष सिंह
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

BCE Bakhtiyarpur

Mid Semester Examination


Subject: High Performance Computing
Duration: 2 Hours Maximum Marks: 20

Q.1 Answer the following objective questions: (1 mark each)


a) During a graph search algorithm, a 'closed list' is maintained. What is the primary operation performed on
this list?
(i) Sorting (ii) Searching (iii) Lookup (iv) None

b) CUDA supports which programming model for parallel processing on GPUs?


(i) Thread termination (ii) Thread abstraction (iii) Thread division (iv) All of the above

c) Array processor architectures, characterized by a single instruction stream operating on multiple data
streams, are classified as:
(i) MISD (ii) SIMD (iii) SISD (iv) MIMD

d) Static interconnection network topologies include:


(i) Bus-based (ii) Switch-based (iii) Both A & B (iv) None of these

e) What is the purpose of Amdahl's Law in High Performance Computing?


(i) To define the communication speed between processors.
(ii) To predict the maximum speedup of a program with parallelism.
(iii) To measure memory access times.
(iv) To optimize compiler performance.

Q.2 Answer the following in brief: (2 marks each)


a) Define "speedup" in the context of parallel systems and explain its significance as a performance metric.

b) What is the key idea behind data parallel approach?

c) How parallelism is used in supercomputing?

Q.3 Answer the following in detail: (3 marks each)


a) Explain the concept of NUMA and UMA architectures.

b) Explain any one mapping technique that is used for load balancing.

c) Describe multithreading with respect to parallelism.

You might also like