EEC 302:Microprocessor and Interfacing

Module II

 Register organization of 8086

 Architecture
 Signal description of 8086
 Physical memory organization
 I/O addressing capability
 Minimum mode 8086 system and timings
 Maximum mode 8086 system and timings

1
 8086 Micro processor Features
1. It is a 16-bit μp.
2. 8086 has a 20 bit address bus can access up to 220
memory locations (1 MB).
3. It can support up to 64K I/O ports.
4. It provides 14, 16 -bit registers.
5. Word size is 16 bits.
6. It has multiplexed address and data bus AD0- AD15
and A16 – A19.
7. It requires single phase clock with 33% duty cycle to
provide internal timing.

2
1. 8086 is designed to operate in two modes, Minimum
and Maximum.

2. It can pre fetches up to 6 instruction bytes from

memory and queues them in order to speed up
instruction execution.

3. It requires +5V power supply.

4. A 40 pin dual in line package.

5. Address ranges from 00000H to FFFFFH

6. Memory is byte addressable - Every byte has a

separate address.
3
Intel 8086 Internal Architecture

4
 Internal architecture of 8086
1. 8086 has two blocks BIU and EU.
2. The BIU handles all transactions of data and
addresses on the buses for EU.

3. The BIU performs all bus operations such as

instruction fetching, reading and writing operands
for memory and calculating the addresses of the
memory operands. The instruction bytes are
transferred to the instruction queue.
4. EU executes instructions from the instruction
system byte queue.
5
1. Both units operate asynchronously to give the
8086 an overlapping instruction fetch and
execution mechanism which is called as
Pipelining. This results in efficient use of the
system bus and system performance.
2. BIU contains Instruction queue, Segment
registers, Instruction pointer, Address adder.
3. EU contains Control circuitry, Instruction
decoder, ALU, Pointer and Index register, Flag
register.

6
 EXECUTION UNIT

1. Decodes instructions fetched by the BIU

2. Generate control signals,
3. Executes instructions.

The main parts are:

1. Control Circuitry
2. Instruction decoder
3. ALU

7
EXECUTION UNIT – General Purpose Registers
16 bits

8 bits 8 bits

AH AL Accumulator
AX

BX
BH BL Base

CX
CH CL Count

DX DH DL
Data
SP Stack Pointer
Pointer
BP Base Pointer

SI Source Index
Index
DI Destination Index
8
 EXECUTION UNIT – General Purpose Registers
Register Purpose
AX Word multiply, word divide, word I /O
AL Byte multiply, byte divide, byte I/O, decimal arithmetic

AH Byte multiply, byte divide

BX Store address information

CX String operation, loops

CL Variable shift and rotate

DX Word multiply, word divide, indirect I/O

(Used to hold I/O address during I/O instructions. If the result is more
than 16-bits, the lower order 16-bits are stored in accumulator and
higher order 16-bits are stored in DX register)
9
 Pointer And Index Registers

1. used to keep offset addresses.

2. Used in various forms of memory addressing.
3. In the case of SP and BP the default reference to form a
physical address is the Stack Segment (SS-will be
discussed under the BIU)
4. The index registers (SI & DI) and the BX generally
default to the Data segment register (DS).
SP: Stack pointer
– Used with SS to access the stack segment
BP: Base Pointer
– Primarily used to access data on the stack
– Can be used to access data in other segments

10
SI: Source Index register
– is required for some string operations
– When string operations are performed, the SI register
points to memory locations in the data segment which is
addressed by the DS register. Thus, SI is associated with
the DS in string operations.

DI: Destination Index register

– is also required for some string operations.
– When string operations are performed, the DI register
points to memory locations in the data segment which is
addressed by the ES register. Thus, DI is associated with
the ES in string operations.

The SI and the DI registers may also be used to access

data stored in arrays
11
EXECUTION UNIT – Flag Register
1. A flag is a flip flop which indicates some
conditions produced by the execution of an
instruction or controls certain operations of the
EU .
2. In 8086 The EU contains
1. 16 bit flag register
2. 9 of the 16 are active flags and remaining 7 are
undefined.
1. 6 flags indicates some conditions- status flags
2. 3 flags –control Flags
U U U U OF DF IF TF SF ZF U AF U PF U CF

Sign Auxiliary Carry

Interrupt Trap Zero Parity
Over flow Direction

U - Unused
12
 EXECUTION UNIT – Flag Register
Flag Purpose
Carry (CF) Holds the carry after addition or the borrow after subtraction.
Also indicates some error conditions, as dictated by some
programs and procedures .
Parity (PF) PF=0;odd parity, PF=1;even parity.

Auxiliary (AF) Holds the carry (half – carry) after addition or borrow after
subtraction between bit positions 3 and 4 of the result
(for example, in BCD addition or subtraction.)
Zero (ZF) Shows the result of the arithmetic or logic operation.
Z=1; result is zero. Z=0; The result is 0
Sign (SF) Holds the sign of the result after an arithmetic/logic instruction
execution. S=1; negative, S=0
13
 Flag Purpose
A control flag.
Trap (TF) Enables the trapping through an on-chip debugging
feature.
A control flag.
Interrupt (IF) Controls the operation of the INTR (interrupt request)
I=0; INTR pin disabled. I=1; INTR pin enabled.
A control flag.
Direction (DF) It selects either the increment or decrement mode for DI
and /or SI registers during the string instructions.
Overflow occurs when signed numbers are added or
Overflow (OF) subtracted. An overflow indicates the result has exceeded
the capacity of the Machine

14
 Execution unit – Flag Register
1. Six of the flags are status indicators reflecting
properties of the last arithmetic or logical instruction.
2. For example, if register AL = 7Fh and the instruction
ADD AL,1 is executed then the following happen
AL = 80h
CF = 0; there is no carry out of bit 7
PF = 0; 80h has an odd number of ones
AF = 1; there is a carry out of bit 3 into bit 4
ZF = 0; the result is not zero
SF = 1; bit seven is one
OF = 1; the sign bit has changed
15
 BUS INTERFACE UNIT (BIU)
Contains
1. 6-byte Instruction Queue (Q)
2. The Segment Registers (CS, DS, ES, SS).
3. The Instruction Pointer (IP).
4. The Address Summing block (Σ)

16
 THE QUEUE (Q)
1. The BIU uses a mechanism known as an instruction
stream queue to implement a pipeline architecture.

2. This queue permits pre-fetch of up to 6 bytes of

instruction code. Whenever the queue of the BIU is
not full, it has room for at least two more bytes and at
the same time the EU is not requesting it to read or
write operands from memory, the BIU is free to look
ahead in the program by pre-fetching the next
sequential instruction.

17
1. These pre-fetching instructions are held in its
FIFO queue. With its 16 bit data bus, the BIU
fetches two instruction bytes in a single memory
cycle.

2. After a byte is loaded at the input end of the

queue, it automatically shifts up through the FIFO
to the empty location nearest the output.

3. The EU accesses the queue from the output

end. It reads one instruction byte after the other
from the output of the queue.

4. The intervals of no bus activity, which may occur

between bus cycles are known as Idle state.

18
 Physical Memory
Segmented Memory
00000

1. The memory in an 8086/88

based system is organized as
segmented memory. Code segment (64KB)

2. The CPU 8086 is able to Data segment (64KB)

1 MB
address 1Mbyte of memory.
Extra segment (64KB)

3. The Complete physically

available memory may be Stack segment (64KB)

divided into a number of

logical segments. FFFFF

19
1. The size of each segment is 64 KB
2. A segment is an area that begins at any location which
is divisible by 16.
3. A segment may be located any where in the memory
4. Each of these segments can be used for a specific
function.

1. Code segment is used for storing the instructions.

2. The stack segment is used as a stack and it is used to store
the return addresses.
3. The data and extra segments are used for storing data byte.

In the assembly language programming, more than one

data/ code/ stack segments can be defined. But only one
segment of each type can be accessed at any time.
20
1. The 4 segments are Code, Data, Extra and Stack
segments.
2. A Segment is a 64kbyte block of memory.
3. The 16 bit contents of the segment registers in the
BIU actually point to the starting location of a
particular segment.
4. Segments may be overlapped or non-overlapped

Advantages of Segmented memory Scheme

1. Allows the memory capacity to be 1Mb although the actual addresses to be
handled are of 16 bit size.
2. Allows the placing of code, data and stack portions of the same program in
different parts (segments) of the m/y, for data and code protection.
3. Permits a program and/or its data to be put into different areas of memory each
time program is executed, i.e. provision for relocation may be done .
4. The segment registers are used to allow the instruction, data or stack portion of a
program to be more than 64Kbytes long. The above can be achieved by using
more than one code, data or stack segments.
21
 Segment registers
1. In 8086/88 the processors have 4 segments registers

2. Code Segment register (CS), Data Segment register

(DS), Extra Segment register (ES) and Stack
Segment (SS) register.

3. All are 16 bit registers.

4. Each of the Segment registers store the upper 16 bit

address of the starting address of the corresponding
segments.

22
23
 MEMORY
00000

BIU
Segment Registers 34BA0
CODE (64k)
44B9F
CSR 34BA
44EB0
DATA (64K)

MB
1
DSR 44EB 54EAF
54EB0
ESR 54EB EXTRA (64K)
64EAF
SSR 695E 695E0
STACK (64K)
795DF

Each segment register store the

upper 16 bit of the starting
address of the segments 24
 Instruction pointer & summing block
1. The instruction pointer register contains a 16-bit offset
address of instruction that is to be executed next.
2. The IP always references the Code segment register
(CS).
3. The value contained in the instruction pointer is called
as an offset because this value must be added to the base
address of the code segment, which is available in the
CS register to find the 20-bit physical address.
4. The value of the instruction pointer is incremented after
executing every instruction.
5. To form a 20bit address of the next instruction, the 16 bit
address of the IP is added (by the address summing
block) to the address contained in the CS , which has
been shifted four bits to the left.
25
26
The following examples shows the CS:IP
scheme of address formation:
CS 34BA IP 8AB4 Code segment
34BA0
Inserting a hexadecimal 0H (0000B)
with the CSR or shifting the CSR 8AB4 (offset)
four binary digits left
3D645

3 4 BA 0 ( C S ) +
8A B 4 ( I P )
3 D 6 5 4 (next address)
44B9F

27
 Example For Address Calculation
(segment: offset)
If the data segment starts at location 1000h and a
data reference contains the address 29h
where is the actual data?

Offset 0000 0000 0010 1001

Segment Address 0001 0000 0000 0000 0000

Required Address 0001 0000 0000 0010 1001

28
 Segment and Address register
combination
1. CS:IP

2. SS:SP SS:BP

3. DS:BXDS:SI

4. DS:DI (for other than string operations)

5. ES:DI (for string operations)

29
 Summary of Registers &
Pipeline of 8086 µP
EU BIU

AX AH AL
BX BH BL IP

CX CH CL D Fetch &
store code CS DS ES SS
DX DH DL E
bytes in
C C
O PIPELINE C
O O IP BX DI SP
D PIPELINE
SP D D
E (or) DI BP
E O QUEUE E
BP SI
U I
SI R N
T
DI
Default Assignment
Timing
FLAGS
ALU control

30
8086 Pin diagram

8086 is a 40 pin DIP using

MOS technology. It has 2
GND’s as circuit
complexity demands a
large amount of current
flowing through the
circuits, and multiple
grounds help in dissipating
the accumulated heat etc.
8086 works on two modes
of operation namely,
Maximum Mode and
Minimum Mode.

31
 Power Connections

GND 1 40 VCC Pin Description:

GND – Pin no. 1, 20
8086 Ground
CLK – Pin no. 19 – Type I
CLK 19
Clock: provides the basic
GND 20
timing for the processor and
bus controller. It is
asymmetric with a 33% duty
cycle to provide optimized
internal timing.
VCC – Pin no. 40
VCC: +5V power supply pin
32
Address/ Data Lines
AD14 2
39 AD15
AD13 3
AD12 4
AD11 5
AD10 6
AD9 7
AD8 8 8086
AD7 9
AD6 10
AD5 11
AD4 12
AD3 13
AD2 14
AD1 15
AD0 16 Continued…

33
Pin Description

AD15-AD0 – Pin no. 2-16, 39 – Type I/O

Address Data bus: These lines constitute the time

multiplexed memory/ IO address (T1) and data (T2, T3, TW, T4)
bus. A0 is analogous to BHE* for the lower byte of the data
bus, pins D7-D0. It is low when a byte is to be transferred on
the lower portion of the bus in memory or I/O operations.
Eight –bit oriented devices tied to the lower half would
normally use A0 to condition chip select functions. These lines
are active HIGH

34
Address Lines

A14 2 39 A15
A13 3
A12 4
38 A16
A11 5
A10 6
37 A17
A9 7
A8 8 8086
A7 9 36 A18
A6 10
A5 11 35 A19
A4 12
A3 13
A2 14
A1 15
A0 16
Continued…

35
A19/S6, A18/S5, A17/S4, A16/S3 – Pin no. 35-38

Address / Status: During T1 these are the four most

significant address lines for memory operations. During I/O
operations these lines are low. During memory and I/O
operations, status information is available on these lines
during T2, T3, TW and T4. The status of the interrupt enable
FLAG bit (S5) is updated at the beginning of each CLK
cycle. A17/S4 and A16/S3 are encoded as shown.

Continued…

36
 A17/S4 A16/S3 Characteristics
0 (LOW) 0 Alternate Data
0 1 Stack
1(HIGH) 0 Code or None
1 1 Data
S6 is 0 (always
LOW)
This information indicates which relocation register is
presently being used for data accessing.

37
Status Pins S0-S7
38 S3
37 S4
36 S5

35 S6

34 S7
8086
28 S2 (M/ I O )

27 S1 (DT/ R )

S 0 ( DE N)
26

Continued…

38
Pin Description

S 2 , S1 , S 0 - Pin no. 26, 27, 28 – Type O

Status: active during T4, T1 and T2 and is returned to the

passive state (1,1,1) during T3 or during TW when READY
is HIGH. This status is used by the 8288 Bus Controller to
generate all memory and I/O access control signals. Any
change by , or during T4 is used to indicate the beginning
of a bus cycle and the return to the passive state in T3 or
TW is used to indicate the end of a bus cycle.

Continued…

39
These signals float to 3-state OFF in “hold acknowledge”.
These status lines are encoded as shown.

S2* S1* S0* Characteristics

0(LOW) 0 0 Interrupt acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
0 1 1 Halt
1(HIGH) 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive
Continued…

40
Status Details
S2 S1 S0 Indication
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive
Continued…

41
S4 S3 Indications
0 0 Alternate data
0 1 Stack
1 0 Code or none
1 1 Data

Continued…

42
S5 ----- Value of Interrupt Enable flag

S6 ----- Always low (logical) indicating 8086 is

on the bus. If it is tristated another bus
master has taken control of the system
bus.

S7 ----- Used by 8087 numeric coprocessor to

determine whether the CPU is a 8086
or 8088

43
 Interrupts

Pin Description:
NMI – Pin no. 17 – Type I
8086
Non – Maskable Interrupt: an edge
triggered input which causes a type 2
NMI 17
interrupt. A subroutine is vectored to via
INTR 18 an interrupt vector lookup table located
in system memory. NMI is not maskable
internally by software. A transition from
a LOW to HIGH initiates the interrupt at
the end of the current instruction. This
input is internally synchronized.
Continued…

44
INTR – Pin No. 18 – Type I
Interrupt Request: is a level triggered input which is sampled
during the last clock cycle of each instruction to determine if
the processor should enter into an interrupt acknowledge
operation. A subroutine is vectored to via an interrupt vector
lookup table located in system memory. It can be internally
masked by software resetting the interrupt enable bit. INTR
is internally synchronized. This signal is active HIGH.

45
Min mode signals

33 VCC MN/ MX

31 HOLD

30 HLDA
29 WR
28 M/I O
8086
27 DT/ R

26 DEN

25 ALE

24 INTA

Continued…

46
Pin Description
HOLD, HLDA – Pin no. 31, 30
HOLD: indicates that another master is requesting a
local bus “hold”. To be acknowledged, HOLD must be
active HIGH. The processor receiving the “hold” request
will issue HLDA (HIGH) as an acknowledgement in the
middle of a T1 clock cycle. Simultaneous with the
issuance of HLDA the processor will float the local bus
and control lines. After HOLD is detected as being LOW,
the processor will LOWer the HLDA, and when the
processor needs to run another cycle, it will again drive
the local bus and control lines.
The same rules as apply regarding when the local bus will
be released.
HOLD is not an asynchronous input. External
synchronization should be provided if the system can not
otherwise guarantee the setup time.
Continued…
47
WR* - Pin no. 29
Write: indicates that the processor is performing a write
memory or write I/O cycle, depending on the state of the
M/IO* signal. WR* is active for T2, T3 and TW of any write cycle.
It is active LOW, and floats to 3-state OFF in local bus “hold
acknowledge”.

M/IO* - Pin no. 28

Status line: logically equivalent to S2 in the maximum mode. It is
used to distinguish a memory access from an I/O access. M/IO*
becomes valid in the T4 preceding a bus cycle and remains valid
until the final T4 of the cycle (M=HIGH), IO=LOW). M/IO*
floats to 3-state OFF in local bus “hold acknowledge”.

Continued…

48
DT/R* - Pin no. 27
Data Transmit / Receive: needed in minimum system that
desires to use an 8286/8287 data bus transceiver. It is used
to control the direction of data flow through the
transceiver. Logically DT/R* is equivalent to S1* in the
maximum mode, and its timing is the same as for M/IO*.
(T=HIGH, R=LOW). This signal floats to 3-state OFF in
local bus “hold acknowledge”.
DEN* - Pin no. 26
Data Enable: provided as an output enable for the
8286/8287 in a minimum system which uses the transceiver.
DEN* is active LOW during each memory and I/O access
and for INTA cycles. For a read or INTA* cycle it is active
from the middle of T2 until the middle of T4, while for a
write cycle it is active from the beginning of T2 until the
middle of T4. DEN* floats to 3-state OFF in local bus “hold
acknowledge”.

Continued…
49
ALE – Pin no. 25
Address Latch Enable: provided by the processor to latch
the address into the 8282/8283 address latch. It is a HIGH
pulse active during T1 of any bus cycle. Note that ALE is
never floated.

INTA* - Pin no. 24

INTA* is used as a read strobe for interrupt acknowledge
cycles. It is active LOW during T2, T3 and TW of each
interrupt acknowledge cycle.

50
Max mode signals
33 GND
31 RQ/ GT0

30 RQ/ GT1

29 LOCK
28 S2
8086
27 S1

26 S0

25 QS0

24 QS1

Continued…

51
Pin Description:
RQ*/GT0*, RQ*/GT1* - Pin no. 30, 31
Request /Grant: pins are used by other local bus masters to
force the processor to release the local bus at the end of
the processor’s current bus cycle. Each pin is bidirectional
with RQ*/GT0* having higher priority than RQ*/GT1*.
RQ*/GT* has an internal pull up resistor so may be left
unconnected.The request/grant sequence is as follows:

Continued…

52
1. A pulse of 1 CLK wide from another local bus master
indicates a local bus request (“hold”) to the 8086 (pulse 1)
2. During a T4 or T1 clock cycle, a pulse 1 CLK wide from the
8086 to the requesting master (pulse 2), indicates that the
8086 has allowed the local bus to float and that it will enter
the “hold acknowledge” state at the next CLK. The CPU’s
bus interface unit is disconnected logically from the local bus
during “hold acknowledge”.
3. A pulse 1 CLK wide from the requesting master indicates to
the 8086 (pulse 3) that the “hold” request is about to end
and that the 8086 can reclaim the local bus at the next CLK.

Continued…

53
Each master-master exchange of the local bus is a sequence
of 3 pulses. There must be one dead CLK cycle after each
bus exchange. Pulses are active LOW.
If the request is made while the CPU is performing a
memory cycle, it will release the local bus during T4 of the
cycle when all the following conditions are met:
 Request occurs on or before T2.
 Current cycle is not the low byte of a word (on an odd
address)
 Current cycle is not the first acknowledge of an interrupt
acknowledge sequence.
 A locked instruction is not currently executing.

Continued…

54
LOCK* - Pin no. 29 – Type O
LOCK* : output indicates that other system bus masters are not
to gain control of the system bus while LOCK* is active LOW.
The LOCK* signal is activated by the “LOCK” prefix instruction
and remains active until the completion of the next instruction.
This signal is active LOW, and floats to 3-state OFF in “hold
acknowledge”.
QS1, QS0 – Pin no. 24, 25 – Type O
Queue Status: the queue status is valid during the CLK cycle
after which the queue operation is performed.
QS1 and QS0 provide status to allow external tracking of the
internal 8086 instruction queue.

Continued…

55
QS1 QS0 Characteristics
0(LOW) 0 No operation
0 1 First Byte of Op Code from Queue
1 (HIGH) 0 Empty the Queue
1 1 Subsequent byte from Queue

56
Common Signals

Continued…

57
Pin Description:

RD* - Pin no. 34

Read: Read strobe indicates that the processor is performing a memory
of I/O read cycle, depending on the state of the S2 pin. This signal is
used to read devices which reside on the 8086 local bus. RD* is active
LOW during T2, T3 and TW of any read cycle, and is guaranteed to
remain HIGH in T2 until the 8086 local bus has floated.
This signal floats to 3-state OFF in “hold acknowledge”.

READY – Pin no. 22

READY: is the acknowledgement from the addressed memory or I/O
device that it will complete the data transfer. The READY signal from
memory / IO is synchronized by the 8284A Clock Generator to form
READY. This signal is active HIGH. The 8086 READY input is not
synchronized. Correct operation is not guaranteed if the setup and hold
times are not met.

Continued…
58
TEST* - Pin No 23
TEST* : input is examined by the “Wait” instruction. If the TEST* input
is LOW execution continues, otherwise the processor waits in an “idle”
state. This input is synchronized internally during each clock cycle on
the leading edge of CLK.

RESET – Pin no. 21

Reset: causes the processor to immediately terminate its present activity.
The signal must be active HIGH for at least four clock cycles. It restarts
execution, as described in the instruction set description, when RESET
returns LOW. RESET is internally synchronized.

Continued…

59
BHE*/S7- Pin No. 34
Bus High Enable / Status: During T1 the Bus High Enable signal
(BHE*) should be used to enable data onto the most significant half of
the data bus, pins D15-D8. Eight bit oriented devices tied to the upper
half of the bus would normally use BHE* to condition chip select
functions. BHE* is LOW during T1 for read, write, and interrupt
acknowledge cycles when a byte is to be transferred on the high portion
of the bus. The S,7 status information is available during T2, T3 and T4.
The signal is active LOW and floats to 3-state OFF in “hold”. It is LOW
during T1 for the first interrupt acknowledge cycle.
BHE* A0 Characteristics
0 0 Whole word
0 1 Upper byte from / to odd address
1 0 Lower byte from / to even address
1 1 None
Continued…

60
MN/MX* - Pin no. 33
Minimum / Maximum: indicates what mode the
processor is to operate in.

If the local bus is idle when the request is made the two
possible events will follow:
 Local bus will be released during the next clock.
 A memory cycle will start within 3 clocks. Now the
four rules for a currently active memory cycle apply with
condition number 1 already satisfied.

61
Minimum Mode 8086 System
MRD
MWR
DMUX IORD
IOWR

62
A minimum mode of 8086 configuration depicts a
stand alone system of computer where no other
processor is connected. This is similar to 8085 block
diagram with the following difference.
The Data transceiver block which helps the signals
traveling a longer distance to get boosted up. Two
control signals data transmit/ receive are connected
to the direction input of transceiver
(Transmitter/Receiver) and DEN* signal works as
enable for this block.

63
Read Cycle timing Diagram for Minimum
Mode

64
In the bus timing diagram, data transmit / receive
signal goes low (RECEIVE) for Read operation. To
validate the data, DEN* signal goes low. The
Address/ Status bus carries A16 to A19 address lines
during BHE* (low) and for the remaining time carries
Status information. The Address/Data bus carries A0
to A15 address information during ALE going high
and for the remaining time it carries data. The RD*
line going low indicates that this is a Read operation.
The curved arrows indicate the relationship between
valid data and RD* signal.
The TW is Wait time needed to synchronize the fast
processor with slow memory etc. The Ready pin is
checked to see whether any peripheral needs more
time for data transmission.
Continued…65
Write Cycle timing Diagram for Minimum
Operation

66
This is the same as Read cycle Timing Diagram
except that the DT/R* line goes high indicating it is a
Data Transmission operation for the processor to
memory / peripheral.
Again DEN* line goes low to validate data and
WR* line goes low, indicating a Write operation.

67
Bus Request & Bus Grant Timings in
Minimum Mode System

The HOLD and HLDA timing diagram indicates in

Time Space HOLD (input) occurs first and then the
processor outputs HLDA (Hold Acknowledge).
68
Maximum Mode 8086 System

69
In the maximum mode of operation of 8086, wherein
either a numeric coprocessor of the type 8087 or another
processor is interfaced with 8086.
The Memory, Address Bus, Data Buses are shared
resources between the two processors.
The control signals for Maximum mode of operation are
generated by the Bus Controller chip 8788.
The three status outputs S0*, S1*, S2* from the processor
are input to 8788. The outputs of the bus controller are the
Control Signals, namely DEN, DT/R*, IORC*, IOWTC*,
MWTC*, MRDC*, ALE etc.
These control signals perform the same task as the
minimum mode operation.
However the DEN is an active HIGH signal which has to be
converted to active LOW by means of an inverter.

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 Memory Read timing in Maximum Mode
Here MRDC* signal is used instead of RD* as in case of Minimum
Mode S0* to S2* are active and are used to generate control signal.

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 Memory Write Timing in Maximum Mode
Here the maximum mode write signals are shown. Please note that the T states
correspond to the time during which DEN* is LOW, WRITE Control goes LOW,
DT/R* is HIGH and data output in available from the processor on the data bus.

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RQ*/ GT* Timings in Maximum Mode

Request / Grant pin may appear that both signals are active
low. But in reality, Request signal goes low first (input to
processor), and then the processor grants the request by
outputting a low on the same pin.

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8284 Clock Generator

The clock Generator 8284 performs the

following tasks in addition to generating the
system clock for the 8086/8088.
 Generating the Ready active high signal
for 8086/8088
 Generating the Reset active high signal
for 8086/8088

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8284 Block Diagram
TANK
F/C CSYNC

X1 OSC
X2 CLOCK
PCLK
LOGIC
EFI CLK

RDY1
AEN1 READY
READY
RDY2 LOGIC
AEN 2

RESET LOGIC
RES RESET

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