Instruction Set Architecture

The portion of the machine visible to the programmer or compiler writer and this includes: 1. 2. 3. 4. 5. 6. Types of machine instructions Types and sizes of operands Addressing modes Byte Ordering (Endianness) Programmer visible CPU registers Instruction Formats (Instruction encoding)
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Instruction Set Classification

1. 2. 3. 4. 5. Register-Register architecture Register-Memory architecture Memory-Memory architecture Stack-based architecture Accumulator-based architecture

Register-Register Architecture
1. 2. Memory is accessed by LOAD/STORE instructions only Arithmetic and logical instructions accept operands from CPU registers only 3. Results of ALU operations go to CPU registers only 4. Also known as LOAD-STORE architecture 5. Simple fixed length instruction encoding 6. Instructions take nearly same number of cycles for execution 7. Simple code generation model 8. Compiler writers job is relatively easy 9. High instruction count i.e. larger programmes 10. Some instructions are short and bit encoding may be wasteful 11. Helps in pipelined execution of instructions 3

Register-Memory Architecture
1. 2. 3. 4. 5. 6. 7. Operands may be in memory and CPU registers Result of ALU operation may go to memory location or CPU register One operand may be lost if accumulator is used Data may be accessed without loading first Clocks per instruction vary according to operand location Encoding a register number and a memory address in each instruction may restrict the use of registers Instruction encoding is easy

Memory-Memory Architecture
1. Allows operands and result to reside in same memory 2. Large variations in instruction sizes 3. Large variation in work per instruction 4. Memory accesses create memory bottleneck 5. Most compact code

Instruction Types
(with respect to number of operands referred) 1. 2. 3. 4. Three-address instructions Two-address instructions One-address instructions Zero-address instructions ADD A,B,C ADD A,B ADD A ADD

Example
X = (A + B) * (C + D)
The computer has two data registers R1 and R2. A, B, C and D are memory addresses.

1. Three-address instructions
ADD R1, A, B ADD R2, C, D MUL X, R1, R2 MOV R1, A ADD R1, B MOV R2, C ADD R2, D MUL R1, R2 MOV X, R1 R1 [A]+[B] R2 [C]+[D] M[X] R1*R2 R1 R1 R2 R2 R1 M[X] M[A] R1 + M[B] M[C] R2 + M[D] R1 * R2 R1

2. Two-address instructions

3. One-address instructions
One of the operand is implied and is in the accumulator register (AC). Also, the result of an operation goes to The accumulator. LOAD A AC M[A] ADD B AC AC + M[B] STORE T M[T] AC LOAD C AC M[C] ADD D AC AC+ M[D] MUL T AC AC * M[T] STORE X M[X] AC Comments The operand in AC is overwritten by the result. Total number of instructions increases. Instruction encoding takes less number of bits.
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4. Zero-address instructions
Computational instructions do not need addresses for The operands. PUSH and POP instructions do need the address fields to specify the operands. PUSH PUSH ADD PUSH PUSH ADD MUL POP A B C D TOS TOS TOS TOS TOS TOS TOS M[X] M[A] M[B] M[A] + M[B] M[C] M[D] M[C] + M[D] (M[C]+M[D])*([A]+[B]) TOS
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Types of Instructions
(with respect to operations) 1. 2. 3. 4. 5. 6. Data transfer Arithmetic Logical Transfer of control Input output Conversion

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Common Instruction Set Operations

1. Data Transfer Operations
Operation Name Description Move (transfer) Transfer word or block from source to destination Store Transfer word from processor to memory Load (fetch) Transfer word from memory to processor Exchange Swap contents of source and destination Clear (reset) Transfer word of 0s to destination Set Transfer word of 1s to destination Push Transfer word from source to top of stack Pop Transfer word from top of stack to 11 destination

2.
Add Subtract Multiply Divide Absolute Negate Increment Decrement

Arithmetic Operations
Compute sum of two operands Compute difference of two operands Compute product of two operands Compute quotient of two operands Replace operand by its about value Change sign of operand Add 1 to operand Subtract 1 from operand

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3.
AND, OR, NOT, Exclusive-OR Test Compare

Logical Operations

Performs specified logical operation bitwise Test specified condition; set flag(s) based on outcome Make logical or arithmetic comparison of two or more operands; set flag(s) based on outcome Class of instructions to set controls for protection purposes, interrupt handling, timer control, etc. Left (right) shift operand, introducing constants at end Left (right) shift operand, with wraparound end
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Set Control Variables Shift Rotate

4.
Jump (branch)

Transfer of Control Operations

Unconditional transfer; load PC with specified address Test specified condition; either load PC with specified address or do nothing, based on condition Place current program control information in known location; jump to specified address Replace contents of PC and other register from known location Increment PC to skip next instruction
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Jump conditional

Jump to Subroutine

Return

Transfer of Control Operations

Skip Skip Conditional Halt Wait (hold) Increment PC to skip next instruction Test specified condition; either skip or do nothing based on condition Stop program execution Stop program execution; test specified condition repeatedly; resume execution when condition is satisfied No operation is performed, but program execution is continued

No operation

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5.
Input (read) Output (write) Start I/O Test I/O Translate Convert

Input/Output and Conversion Operations

Transfer data from specified I/O port or device to destination (e.g;, main memory or processor register) Transfer data from specified source to I/O port or device Transfer instruction to I/O processor to initiate I/O operation Transfer status information from I/O system to specified destination Translate values in a section of memory based on a table of correspondences Convert the contents of a word from one form to another (e.g., packed decimal to binary etc)
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Types of Operands
1. 2. 3. 4. 5. 6. 7. 8. 9. Addresses (treated as unsigned numbers) Integers (usually in 2s complement form) Single-precision floating point numbers Double-precision floating point numbers Packed decimal numbers (BCD for decimal arithmetic) Unpacked decimal numbers (numeric character) Characters (usually in ASCII) Logical data (n-bit word is taken as n 1-bit data) Any other special data type

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Addressing Modes
How architecture specifies the address of objects they access

Addressing Modes
1. Immediate addressing 2. Register direct addressing 3. Direct addressing 4. Indirect addressing 5. Register indirect addressing 6. Based addressing 7. Indexed addressing 8. PC-relative addressing 9. Modulo or circular addressing 10. Bit-reverse addressing

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Instruction Format
(Instruction Encoding) It defines the layout of bits of machine instructions in terms of their: Length Opcode fields Address Fields
Operand specifier1 Operand specifier2 Operand specifier3

Opcode

n-1 An n-bit instruction

0
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Instruction Length
Instruction length affects and is affected by
1. 2. 3. 1. 2. 3. 4. Memory size Memory organization Bus structure (number of bits in system bus vs. instruction length) CPU complexity (CPU registers) Complexity of instructions Number of operands referred Addressing modes/range

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Number of bits for address field depend on

1. 2. 3. 4. 5. 6. Number of addressing modes Number of operands referred in the instruction Register versus memory operands Number of CPU registers Address range of CPU Address granularity

Instruction Types
(with respect to fixed or variable length/format) 1. Fixed length/format instructions 2. Variable length/format instructions
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Fixed Length/format Instructions

1. 2. 3. 4. 5. Regular structure Simple instructions CPU complexity is reduced Few addressing modes Less powerful instruction set (Number instructions in programs is high). 6. Compiler writer job is easy 7. Less number of operands can be referred 8. Instruction execution is faster Example Systems: PDP 8, PDP 10 , Power PC and others

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Variable Length/format Instructions

1. 2. 3. 4. 5. 6. 7. 8. Can have more opcode! More flexible addressing with various combinations of Register and Memory addressing modes. Address space can be more. Powerful instruction set - more efficient and compact code can be written. Increased CPU complexity more cost. Compiler writers job becomes more difficult. More main memory space is required. Programming complexity is increased. Intel 8086, Pentium II, VAX and others
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Examples

Complex Instruction Set Computers (CISC)

1. 2. 3. 4. 5. 6. 7. 8. 9. Use large and complex instruction set (120-350) More functions are built in hardware to support HLLs Variable length instruction/data formats (16-64 bits) Small set of registers (8 - 24). Large number of memory referenced instructions. Large number of addressing modes (> 14 ). Lower clock rate. High average CPI (2 15). Most CISC architectures use micro coded control units which employ control ROM. Modern CISC also use hardwired control units. 10. Most CISC architectures use unified cache memory.
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Reduced Instruction Set Computers (RISC)

1. Use small set of instructions with fixed (32-bits) length/format ( < 100 instructions). 2. 3 5 simple addressing modes are used. 3. Most instructions are register based. 4. Memory access is done by Load/Store instructions only. 5. Large file of General Purpose Registers (GPRs) is used. More than 32 registers. 6. Most instructions execute in one cycle. Average CPI is less than 1.5. 7. Higher clock rate. 8. RISC architectures use hardwired control units. 9. RISC architectures use separate data and instruction cache memories. 10. Extensive use of pipelining to increase throughput.
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