Dhaval Gothi
Lead Physical Design Engineer
Address Vadodara, India 390024 WWW https://www.linkedin.com/in/dhaval-gothi-
Phone 9725346736 663907187
E-mail
[email protected] A Highly motivated, enthusiastic and hard working physical design engineer currently working with
NXP Semiconductors on Automotive Chips as a Lead Physical Design Engineer. I have overall around
4.5 years of experience in Physical Design with 3 tape-outs across 5nm, 16nm tech nodes. Looking
forward to exploring the latest technology and enhancing my overall skills as a physical design
engineer and using my technical knowledge for the organization's growth.
Skills
• Hands on with EDA design tools, flows and methodology
using Genus, Innovus, Design Compiler, ICC2, Fusion
Compiler, Conformal, Calibre and Redhawk.
• Knowledge on each design step of entire RTL to GDS flow
along with timing analysis and logical equivalence check.
• Programming and scripting skills in TCL and text processing
awk, sed basics.
Work History
Aug 2023 - Lead Physical Design Engineer
Current NXP Semiconductors, Noida (Remote)
RTL to GDS implementation for a block of 5nm Auto chip.
• Implemented a block in Cadence Genus & Innovus having 3 different IPs
(working at 400MHz & 300MHz) , CM7_CORE and NOC (working at
600MHz), having around 6M instances.
• Did multiple floorplan experiments to reduce the die size of the block. This
includes different type of macro placements and different cuts of
memories.
• Did Custom implementation for Ring Oscillator(placement & routing) and
for Ethernet RGMII Interface protocol (placement & building data as
clock).
• Resolved setup critical memory read timing paths by bounding memory
interface, controller logic, endpoints and by pulling memory. Resolved
other timing issues by staggering pipeline stage registers.
• Resolved shift_clk latency & skew degradation by strategic placement of
mini macros(clkdivmux & clk_shaper) and specific pairs of clock muxes &
CGs.
• Resolved congestion issue by methods like module padding, instance
padding, partial blockages etc.
• Implemented multiple Functional ECOs through conformal ECO and
resolved DFT scan chain issues arising due to it.
• Efficiently used past project learnings which resulted in very few IR
violations in the very first IR analysis.
• Helped other block owner in resolving critical DRC violations.
Aug 2022 - Sr. Physical Design Engineer
Jun 2023 NXP Semiconductors, Noida
RTL to GDS implementation of a block for the first 5nm Auto chip of NXP.
• Successfully implemented a block having three IPs (NETC, CAAM & AES)
and an instance count of 4M using Cadence Genus & Innovus.
• Fixed Interface Timing Violations by bounds & manual intervention which
appeared due to splitted bus port placement.
• Fixed IR violations for memories by PG Augmentation and for core by cell
padding, VT swap, DRC aware M1 PG Augmentation in clustered regions.
• Fixed EM violations by inserting via ladders and Antenna violations by layer
hopping & antenna diode insertion.
• Successfully overcome all the design challenges due to frame size
reduction (0.1mm2 area reduction) in the final phase of implementation
cycle like DRC violations, Data DRVs, etc.
• Implemented multiple RTL ECOs in the final phase of implementation.
Jun 2020 - Physical Design Engineer
Jul 2022 NXP Semiconductors, Noida
• Physical design for CPU blocks to evaluate PPA in 5nm tech node.
• Multiple flow experiments to converge timing & routablity.
• Frequency sweep experiments to achieve required power target.
• Multiple experiments for new 5nm flow enchancement.
Synthesis to GDS implementation for a block & an IP of Radar chip in 16nm.
• Resolved Congestion by gradient placement blockages & routing guides.
• Manually cleaned up DPT violations in M2 layer forming long loops.
• Resolved Antenna Violations by inserting Antenna diode.
• Did Custom implementation for an IP(placement of delay chains &
bounding of instances near tap points of delay chain to obtain minimum
delay).
Aug 2019 - Physical Design Intern
Jun 2020 NXP Semiconductors, Noida
RTL to GDS implementation of a block. It Includes Floorplan, Power Planning,
Placement, Clock tree Synthesis, Routing, DRC, LVS, EM & IR.
Education
Jun 2020 Master Of Technology: VLSI & Embedded Systems
Indraprastha Institute of Information Technology - New Delhi
Accomplishments
• Defensive Publication :: NXP Ref Record ID: 82406546 :: Novel logic design to leverage
scan chains repeater delay for timing closure of power sensitive SoCs and/or cost
optimized tapeout revisions.
• Multiple team bravo awards and recognition awards from peers.
