MIPS opcodes

ctrl transfer J 0x02 Arith Logic o

Bgez bltz 0x01 Add 0x20
bgtz 0x07 Addu 0x21
blez 0x06 Addi 0x08
bne 0x05 Addiu 0x09
beq 0x04 Sub 0x22
jalr 0x09 Subu 0x23
jal 0x03 Ans 0x24
jr 0x08 Or 0x25
Data trsfr LW 0x23 Xor 0x26
sw 0x2B Nor 0x27
lh 0x21 Slt 0x2a
lhu 0x25 Sltu 0x2b
sh 0x29 Slti 0x0a
lb 0x20 Sltiu 0x0b
lbu 0x24 Sll 0x00
sb 0x28 Srl 0x02
ll 0x30 sra 0x03
sc 0x38 syscall 0x0c
Break 0x0d
nop 0x00

INFORMATION EXTRACTED FROM SOLUTIONS:

-Assembly language is nothing but a direct textual representation of binary code

-Levels of abstraction actually means place some interfaces that remove the detail of what is behind them.
-A CPU register that keeps the track of execution of the program and contains the instructions currently being executed is called the
instruction register. It is filled as part of the fetch of the fetch-execute cycle and loaded with the data pointed to by the program counter.
-A programming language where there is a very strong correspondence between the language and the architecture of the machine code is
called Assembly language.
-A central processing unit fabricated on a single chip of semiconductors is called Microprocessor.
-The program counter always moves to the next instruction in the fetch-execute cycle, in MIPS this means incrementing the PC by 4.
-The instruction blt $t0, $t1, for_exit is equivalent to the following two instructions slt $at, $t0, $t1 followed by bne $at, $zero, for_exit.
THEORY 1
A computer with a von Neumann architecture stores program data and instruction data in the same memory, a computer with a Harvard
architecture has separate memories for storing program and data. In vonn neumann we have: memory (stores programs and instruction
data) central processing unit CPU or processor (loads instructions, interprets them, loads the data, processes it and then rewrites it)

CPU has: Control Unit (takes instructions from the memory, decodes them and directs them to the memory, indicating what operations must
be performed) ALU, Arithmetic logic unit (calculation unit of the computer, connected to the storage elements via data buses.) and registers.
A CPU register that keeps the track of execution of the program and contains the instructions currently being executed is called
the instruction register

Registers vs RAM→ Storage elements (memory) are registers and Random Access Memory. //The registers store parameters and results
from operations, and control data/ Registers are faster to access than memory/ Operating with memory data requires ‘loads’
and ‘stores’/ The compiler must use the variables’ registers as much as possible /Only store in the memory the least used
variables /Optimizing registers is very important/ Some registers are protected for safety, like only specific instructions affect the
program counter/ Register are only a few and typically the size is only one word Memory of the computer can range from some
GB to TB/ RAM can usually be extended after the first configuration (good).
Interpreter Vs compiler→ in compiler, the executable code is highly optimised and thus runs faster, the compilation into
machine language is performed only once/ in compiler, because the entire code is analysed, the programs are safer, more errors
are detected at compilation time rather than at run-time/ A compiler takes more time to process the input files that constitute a
program because a more detailed analysis is made of the entire code/Sometimes compilation is too rigid for development,
programmers want rapid feedback as they evolve their code.
Of RISC versus CISC:
Adv 1: RISC architecture has reduced set, so the ISA is more stable, rapidly new
CPUs can be produced without affecting the ISA. Adv 2: Technology for
compilers has improved dramatically, so the effort can be shifted into the
compiler. That is, the compiler can be cleaver at using the fewer instructions
(even though some more instructions are required). But the same as the earlier
advantage, the compiler has a longer life.
Disadv 1: The fewer addressing modes may result of inefficient communication
between RAM and CPU.
Disadv 2: With RISC, the code at machine language may be laborious and
inefficient.
RISC: Reduced Instruction Set Computer: Smaller and simpler set of instructions// Uniform instructions (same size) → Easier
decoding and addressing// Decoded and executed directly into hardware// Examples: MIPS, ARM, Alpha, PowerPC, etc.

RISC Compiler: Optimization done by the compiler. Less instructions → optimized work. Less instructions → less mistakes.
Computer : machine that can be instructed to carry out sequences of arithmetic/logical operations automatically via computer programming
computer architecture : describes the computer’s elements and the relations between them.
Von Neumann architecture : CPU, memory, peripherals, stored-program
THEORY 2:
Algorythm: The effective procedure that defines (without ambiguity) how to take the hardware from one state to the next state until the
desired final output is achieved and always terminate in a finite number of steps

If A and B are of the same sign, but the result of A + B is of the opposite (different) sign, then an overflow error has occurred //If A and B are
of different signs, then A + B will never overflow

Binary representation : Numbers expressed in the base-2 numeral system or binary numeral system.

Binary arithmetic : arithmetic with binary representations of numbers.

2’s complement : In two’s-complement, there is only one zero, represented as 00000000. Negating a number (whether negative or positive) is
done by inverting all the bits and then adding one to that result. In two’s complement, negative numbers are represented by the bit pattern
which is one greater (in an unsigned sense) than the ones’ complement of the positive value

THEORY 3:

The ASCII table (American Standard Code for Information Interchange) is a 7-bit character code where each individual bit represents a unique
character. We use the extended ASCII table, based on the windows character set and has 256 elements represented with 1 byte (or 8 bits). 0
to 127 are only standard and only 32 to 126 are printable.

An Instruction Set Architecture (ISA) is part of the abstract model of a computer that defines how the CPU is controlled by the software. ISA is
the parts that are different in computer architecture and affect how the software controls the CPU. It specifies: What instructions the CPU can
understand and execute // CPU components visible to the programmer (The set of instructions (arithmetic, logic, jumps, comparisons,
movements, memory access), data types, CPU registers, the memory, input and output drivers, etc)

Any machine that implements an ISA can run a coded program, and those that have the same ISA have binary compatibility. Machines with
the same ISA can have different power characteristics, performance and cost, and we say that they are from the same family.

The words of a computer’s language are called instructions, and its vocabulary is called instruction set. When designing a CPU, the goal is to
ease the hardware and compiler’s construction, while maximizing the output and minimizing the costs and power. Simplicity favors regularity,
it enables higher performance at lower cost.

MIPS (Microprocessor without interlocked pipelined stages) is a family of reduced instruction set computers (RISC) ISA. Characteristics: 32 bits
RISC architecture //1 word = 32 bits //1 halfword =16 bits //1 byte=8 bits //1 doubleword=64 bits // Unified memory for data and instructions.
(Capacity for 230 words) //32 registers of 32 bits each. These are few registers//instructions are encoded in binary as 32-bit instruction codes

The program counter (PC) is a register which manages the following instruction in memory: As the PC always points at the “next instruction”,
this direction/address (in hardware) must be easily to update /// The usual method is adding 4 to the current address (since the instruction is
a word of 32 bits and each word of 32 bits has an address 4 times higher than the last word).

The MIPS memory stores: main memory → complex data (Arrays (vectors), structures, dynamic data) // To apply arithmetic operations - Load
values of the memory in registers,, -Store the result register value in the memory // Memory is byte addressed - Each address identifies a byte
of 8 bits //Words are aligned in the memory -The address should be a multiple of 4

The MIPS control unit decodes the six bits in the left extreme of the operation code (the opcode field) from a coded operation of 32 bits, to
determine each instruction in sequence of instructions.

The operand is the input or output values for an operation

C/MIPS 8bit=1byte
8 bits→char/.byte
16 bits→short/.half
32 bits→int/.word
64 bits→long/.dword

Data type .asciii/asciiz →string of vectors or chars

.space→reserves the space in bytes in memory

MIPS MEMORY ACCESS INSTRUCTIONS:

la (load address) la target_register, label #target register ← address in memory by label
li (load immediate) li target_register, label #target register ← constant of 32-bits
move (from one register to another) move target_register, source register #target register ← source register
load/store at word level: The register must previously contain a memory address These instructions require memory addresses multiples of 4.
lw target_register, constant(register)→Reads from memory the word contained in the memory address indicated by the sum of the constant
and the register, and leaves it in the destination register Res: target_register ← data contained in the memory address constant + register
sw source_register, constant(register) →Writes the word, contained in the source register, at the memory address indicated by the sum of the
constant and the register Result : Calculated memory address: const + register ← source register
load/store at byte level MIPS provides LOAD and STORE instructions to read (respectively write) 1 byte of memory: lb: read a signed number //
lbu: read a natural number // sb: write a byte (Byte store: saves the 8 bits in memory lower weight from the source register The memory
address does not need to be aligned)
load/store at half level sh $t1, 0($t2) (store half word) store half word in $t1 in the memory address pointed by $t2// lh $t1, 0($t2) (load half
word) load half word stored in the memory address pointed by $t2, in the register $t1, with sign extension lhu $t1, 0($t2) (load half word) load
half word stored in the memory address pointed by $t2, in the register $t1, without sign extension

THEORY 4:

It is necessary to indicate the sign of the value

when using immediate value in operations.

Detects overflow: If the sum or subtraction produce arithmetic overflow in 2’s complement in 32bit representation, an exception is generated
- Sum (detects overflow) add rd, rs, rt (Assigns the result of the sum of registers rs and rt to the register rd)
- Immediate Sum (detects overflow) addi rt, rs, imm (Assigns the result of the sum of register rs and the immediate value (16 bits sign
extended ) to the register rt [Immediate value is stored within the instruction])
- Subtraction (detects overflow) sub rd, rs, rt Assigns the result of the subtraction of rs and rt to the register rd.

Arithmetic Overflow undetected with unsigned values: If the sum or subtraction produce and arithmetic overflow in 2’s complement in 32bit
representation, NO exception is generated and the programmer is responsible for detecting the error
 - Sum (no overflow detection) addu rd, rs, rt (Assigns the result of the sum of registers rs and rt to the register rd)
- Immediate Sum (no overflow detection) addiu rd, rs, imm (Assigns the result of the sum of register rs and the immediate value (16
bits sign extended ) to the register rt [Immediate value is stored within the instruction])
- Subtraction (no overflow detection) subu rd, rs, rt (Assigns the result of the subtraction of rs and rt to the register rd)

Division:

- div rs, rt Dividend: rs Divisor: rt The values in rs and rt are sign extended integer numbers. The quotient is stored in register lo and
the remainder is stored in the register hi.
- divu rs, rt Dividend: rs Divisor: rt The values in rs and rt are unsigned integer numbers. The quotient is stored in register lo and the
remainder is stored in the register hi.

Multiplication:

- mult rs, rt Calculate the product of registers rs and rt. The values of rs and rt are sign extended integer numbers. The lower part of
the result is stored in the register lo, and the higher part of the result is stored in the register hi.
- multu rs, rt Calculate the product of registers rs and rt. The values of rs and rt are unsigned integer numbers. The lower part of the
result is stored in the register lo, and the higher part of the result is stored in the register hi

example usage:

addu $t1, $t2, $t3 Sums the content of $t2 and $t3 and stores the result in $t1.

subu $t1, $t2, $t3 Subtracts the content of $t2 and $t3 and stores the result in $t1.

li $t1, immediate value Stores the immediate value in the register $t1. It can be interpreted as assigning a constant value to the register.

logic operations (AND) and rd, rs, rt (Evaluates the logic AND, bit by bit, of the two registers rs and rt, and the result is stored in register rd)
//immediate andi rt, rs, imm (Evaluates the logic AND , bit by bit, of the register rs and a constant imm, and the result is stored in register rd.)

(OR) or rd, rs, rt (Evaluates the logic OR, bit by bit, of the two registers rs and rt, and the result is stored in register rd) // immediate ori rt, rs,
imm (Evaluates the logic OR , bit by bit, of the register rs and a constant imm, and the result is stored in register rt)

In a logical shift, zeros are inserted to replace the discarded bits. Hence, left logical and arithmetic shift produce the same result
However since right logical shift inserts 0 in the most significant bit, (instead of copying the sign) this instruction cannot be used
as division of numbers represented in 2’s complement.
MIPS shifts:

THEORY 5:

Arrays or vectors: group of elements of the same type in one dimension

Matrices: group of elements of the same type in multiple dimensions
(All elements are stored in consecutive memory addresses. Every element can be accessed using an index)
2 basic operations: Retrieve (get) data stored in a specified position (read) //Store data in a specified position (write)
To know the address of some data we do: @V[i] = @V + (i * element size in bytes)
.align n This directive aligns the next data definition in an address multiple of 2n .
.half, .word and .dword perform automatic alignment for addresses multiple of of
2, 4 and 8 respectively. .align 0 deactivates the automatic alignment. Avoid using
it, unless you know what you are doing.
Arrays are a common data structure, all items are of the same type. Array : a data structure consisting of a collection of elements (values or
variables), each identified by at least one array index or key.

- One-dimensional array: A linear array with only a range of integers as the index.
- Array element size: The size in bytes shared by all elements of the array

In assembly language, the address of an element of an array is computed by multiplying the size in bytes of the elements by the index and
adding that to the base address of the array.

The memory is analogous to a large array of bytes. In it, different arrays may need to be allocated (placed).

Strings is not the same data type as an array of chars

THEORY 6:

MIPS has a special instruction: syscall These are calls to the OS to perform a specific action. We will use it to print data in the console / read
data from the console For using it:

- System (instruction) code is loaded in register $v0

- Arguments if needed are loaded in registers $a0, $a1, etc.
- Execute (invoke) syscall
- Returns values, if they exist, in the registers

Comparison instructions For example : slt (Set Less Than) Comparisons are usually used to decide which part of code must be executed next.
After it is necessary to label an instruction for indicating where the program must continue

Jump instructions→ Two types:

- Branch: it compares the value of the operand-registers according to different conditions If the comparison is true, it jumps to
execute the given instruction Otherwise it follows executing the next instruction (does nothing) (Jumps to a specified instruction, if
the condition is satisfied. The address of the instruction to jump is close to the current address in the PC (relative jump of the PC)
Used for control flow instructions: loops, if-then-else (branching))
- Jump: It jumps to execute a different part of the program, not the next instruction. Jumps to a specified instruction unconditionally.
The address of the instruction to jump is not necessarily close to the current address in the PC. Used for procedural abstraction:
subroutine calls. In a program code , the position ( memory address ) of the destination instruction is indicated using a label The
label takes the value of the memory address.

Branch: beq rf1, rf2, label (Jump to the label if the values of the two registers (rf1 and rf2) are equal) bne rf1, rf2, label (Jump to the label if
the values of the two registers (rf1 and rf2) are not equal)