American International University- Bangladesh Faculty of Engineering (EEE)

Digital Logic and Circuits Laboratory

Experiment no: 08

Name of the Experiment:

Construction Logic Gates using various MOS transistors

Group no: 05

Submitted By

Name of student ID

Hasan Mahmud Shanto 22-49453-3

Tarmin Islam Meem 22-48339-3

Arman Hossain Foej 22-49440-3

Marufa Islam 22-49431-3

Morzia Momo 23-50013-1

20-42311-1
MD.Abrar Dudaib

Supervised by: DR. MD. KABIRUZZAMAN

Date of Submission: 21/09/2024

Title: Construction Logic Gates using various MOS transistors

Introduction:

The experiment aims to construct logic gates using MOS transistors, specifically focusing on
NMOS and CMOS technology. The Metal-Oxide Semiconductor Field-Effect Transistor
(MOSFET) plays a critical role in digital electronics, serving as a fundamental building block for
logic circuits. In this experiment, both NMOS and CMOS logic circuits will be constructed,
evaluated, and compared.

Theory and Methodology (Part 1) :

MOSFET:
MAWS-feht is the correct pronunciation. Metal-oxide semiconductor field-effect transistor is an
acronym. These are utilized in a variety of situations when voltage conversion is required. To
create CPU, memory, and AGP voltages, for example, on your motherboard. Mosfets are typically
employed in groups of two. Three-phase power is indicated by the presence of six mosfets around
the CPU socket.

CMOS:
CMOS (complementary metal–oxide–semiconductor) is an integrated circuit fabrication method.
Microprocessors, microcontrollers, static RAM, and other digital logic circuits all utilise CMOS
technology. CMOS technology is also used for several analog circuits such as image sensors
(CMOS sensor), data converters, and highly integrated transceivers for many types of
communication. In 1963, Frank Wanlass received a patent on CMOS (US patent 3,356,858).
Complementary-symmetry metal–oxide–semiconductor is another name for CMOS (or COS-
MOS). The term "complementary-symmetry" refers to how CMOS logic functions are often
implemented using complementary and symmetrical pairings of p-type and n-type metal oxide
semiconductor field effect transistors (MOSFETs).
 Figure1: CMOS inverter

High noise immunity and low static power consumption are two significant properties of CMOS
electronics. Because one of the pair's transistors is permanently off, the series combination only
drains substantial power while transitioning between on and off states. As a result, CMOS devices
produce less waste heat than other types of logic, such as transistor–transistor logic (TTL) or
NMOS logic, which typically have some standing current even when not in use. In addition,
CMOS enables for a high density of logic functions on a single chip. It was primarily for this
reason that CMOS became the most widely utilized technology for VLSI chips.

Here Some the advantages of CMOS over TTL are:

1. Because MOSFETs are voltage-controlled rather than current-controlled

semiconductors, CMOS gate inputs draw significantly less current than TTL inputs.

2. CMOS gates can operate over a far larger range of voltages than TTL gates:
typically, 3 to 15 volts against 4.75 to 5.25 volts for TTL gates.

3. CMOS transistors are smaller than NMOS transistors and have lower power
dissipation.

CMOS Logic:
CMOS transistors are smaller than NMOS transistors and have lower power dissipation. Thus,
they became the obvious choice of replacing NMOS transistors at the integrating circuit level
design in all applications. CMOS consists of one p-channel MOSFET or PMOS and one NMOS.
The two MOSFETs have been engineered to have similar properties. Thus, they are
complementary to each other. When OFF, their resistance is effectively infinite; when ON, their
channel resistance is quite low (around 200 Ω). Since the gate is essentially an open circuit it
draws no current and the output voltage will be equal to either ground or to the power supply
voltage, depending on which transistor is conducting.
CMOS Inverter:
When the input is grounded (logic 0), the N-channel MOSFET is unbiased, and therefore has no
channel enhanced within itself. It is an open circuit, and therefore leaves the output line
disconnected from ground. At the same time, the P-channel MOSFET is forward biased, so it has
a channel enhanced within itself. This channel has a resistance of about 200 Ω, connecting the
output line to the +V supply. This pulls the output up to +V (logic 1). When input A is at +V (logic
1), the P-channel MOSFET is off and the N-channel MOSFET is on, thus pulling the output down
to ground (logic 0). Thus, this circuit correctly performs logic inversion, and at the same time
provides active pull-up and pull-down, according to the output state.

Fig:2 CMOS Inverter

CMOS NAND Gate:

Fig:3 CMOS NAND Gate

CMOS NOR Gate:

Fig:4 CMOS NOR gate

NMOS Logic:

N-type metal-oxide-semiconductor logic uses n-type (-) MOSFETs (metal-oxide- semiconductor

field-effect transistors) to implement logic gates and other digital circuits. These NMOS
transistors operate by creating an inversion layer in a p-type transistor body. This inversion layer,
called the n-channel, can conduct electrons between n-type "source" and "drain" terminals. The n-
channel is created by applying voltage to the third terminal, called the gate. Like other MOSFETs,
NMOS transistors have four modes of operation: cut-off (or subthreshold), triode, saturation
(sometimes called active), and velocity saturation.

NMOS Inverter with Ohmic/ Resistive Load:

Considering an ideal scenario, when a HIGH (+5V) is applied to the input, the NMOS transistor
turns ON and current flows from Vdd to ground; thus output voltage, Vo= 0V. Similarly, if a LOW
(0V) is applied to the input, the NMOS remains in its OFF state. As a result, the current from Vdd
has no path to ground. The output voltage is +5V

Fig 5: NMOS Inverter with Ohmic/Resistive Load

NMOS NAND Gate:

Fig.6 NMOS NAND Gate

NMOS NOR Gate:

Fig:7 NMOS NOR Gate

NMOS Inverter with NMOS Enhancement Transistor load:
One disadvantage of designing NMOS logic circuits with ohmic load is that even when the NMOS
is OFF, there is static power dissipation due to the resistor. A better design is to use an
enhancement-type NMOS as load. They are “normally-off” devices and it takes an applied voltage
between gate and drain of the correct polarity to bias them on. Thus static power consumption is
avoided

Fig:8 NMOS Inverter with NMOS Load

Apparatus:
(1) 10KΩresistor
(2) CMOS and Nmos
(3) Connecting wires.
(4) Trainer Board
Theory and Methodology (Part 2) :

To design any logic circuit first the truth table is needed to be established using different
combinations of logic ‘0’ and ‘1’ to get the desired output. After that the gate level design is
found from which transistor level design is done using desired transistors. Here CMOS is used
for the transistor level design of the Half Adder. The whole process is given step wise below:

Half Adder:
Gate Level Design:

Fig-9 Logic diagram of a Half Adder.

Equation of Sum = A (XOR) B
= +
This equation can be rewritten as =
=
Equation of Carry= AB

Apparatus:

5. PMOS,
6. NMOS,
7. IC 7404(Inverter).
8. Connecting wires.
9. Trainer Board
Simulation and Measurement:

NMOS Inverter with Ohmic/ Resistive Load:

Figure 10: Simulation output of a NMOS Inverter with Ohmic/ Resistive Load

Truth table of NMOS inverter

input LED1
0 on(1)
1 off (0)

Figure 11: NMOS Inverter with Ohmic/ Resistive Load

NMOS Inverter with NMOS Enhancement Transistor load:

Figure 12: Simulation output of NMOS Inverter with NMOS Enhancement Transistor load
Truth table of NMOS inverter
input LED1
0 on(1)
1 off (0)

Figure 13: NMOS Inverter with NMOS Enhancement Transistor load

NMOS NAND Gate:

Figure 14: Simulation output of the NMOS NAND Gate

Truth table of NMOS NAND Gate
input1 input2 LED1
0 0 on(1)
0 1 on(1)
1 0 on(1)
1 1 off (0)

Figure 15: NMOS NAND Gate

NMOS NOR Gate:

 Figure 16: Simulation output of the NMOS NOR Gate

Truth table of NMOS NOR Gate

input1 input2 LED1
0 0 On (1)
0 1 off (0)
1 0 off (0)
1 1 off (0)

Figure 17: Simulation output of the NMOS NOR Gate

CMOS Inverter:

Figure 18: Simulation output of the CMOS Inverter

Truth table of CMOS inverter

input LED1
0 On (1)
1 off (0)

Figure 19: CMOS Inverter

CMOS NAND Gate:

Figure 20: Simulation output of the CMOS NAND Gate

Truth table of CMOS NAND Gate

input1 input2 LED1
0 0 On (1)
0 1 On (1)
1 0 On (1)
1 1 off (0)

Figure 21: CMOS NAND Gate

CMOS NOR Gate:

Figure 22: Simulation output of the CMOS NOR Gate

Truth table of NMOS NOR Gate

input1 input2 LED1
0 0 On (1)
0 1 off (0)
1 0 off (0)
1 1 off (0)

Figure 23: CMOS NOR Gate

Half Adder using CMOS:

Figure 24: Simulation output of the Half Adder using CMOS

Figure 25: Half adder using CMOS

 Discussion:
The main objectives of this experiment were to be familiar with NMOS and CMOS logic to know
the how to design the inverter, NAND and NOR gate by NMOS and CMOS Mosfet.
In the hardware implementation part, we faced difficulties to implement the CMOS NOR Gate
that’s why it took a much extra time. Anyway, the overall outcome was excellent and matched
the truth table value. In the simulation part, we have used NI Multisim version -14.2. we
successfully assembled all of the components on the Multisim bread board without any faults.
Successfully we have confirmed to build the connection between the circuit wires without any
problem.

Conclusion:
All the simulation circuit were run and the output were matched with the theoretical knowledge.
No error was found in the output values. So, we can say that our hardware implementation was
verified by simulations result and truth table.

Reference:

1. Thomas L. Floyd, Digital Fundamentals, 9th Edition, 2006, Prentice Hall.

2. Link: http://www.techpowerup.com/articles/overclocking/voltmods/21
3. https://www.google.com/search?q=Construction+of+MOSFET+Logic+Gates+(P
art+I)&rlz=1C1GCEA_enBD903BD903&oq=Construction+of+MOSFET+Logic
+Gates+(Part+I)&aqs=chrome.0.69i59.1311j0j7&sourceid=chrome&ie=UTF-8
4. https://pages.jh.edu/aandreo1/216/Archives/2014/Handouts/POP_Ch3-4.pdf

5. https://www.google.com/search?q=cmosfet&rlz=1C1GCEA_enBD903BD903&o
q=cmosfet+&aqs=chrome..69i57j0i10i433j0i10i131i433j0i10l7.2865j0j7&source
id=chrome&ie=UTF-8