Registration No:
Total Number of Pages: 02 Course: B.Tech
Sub_Code: REC5D002
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02 4
5th Semester Regular / Back Examination: 2023-24
SUBJECT: Computer Architecture and Organisation
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BRANCH(S): ECE, ETC
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Time: 3 Hour
09 - Max Marks: 100
Q.Code : N264
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Answer Question No.1 (Part-1) which is compulsory, any eight from Part-II and any two
from Part-III.
The figures in the right hand margin indicate marks.
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Q1
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Answer the following questions:
Part-I
(2 x 10)
a)
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What is an instruction cycle? Write the phases of Instruction cycle.
b) 4 /
Why is RTL preferred for describing internal organization of digital computers?
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c)
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Differentiate between static RAM and Dynamic RAM.
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d)
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Register A holds the binary values 10011101. What is the register value after
arithmetic shift right? Starting from the initial number 10011101, determine the
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register value after arithmetic shift left, and state whether there is an overflow.
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e) 1/
How many 128 X 8 memory chips are needed to provide a memory capacity of
4096 X 16?
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What are the advantages and disadvantages of Associative memory?
109
f)
g) Differentiate between Synchronous and Asynchronous modes of data transfer.
h) What is interrupt? Give the steps for handling interrupt.
i)
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Find (1001101 – 10101001) using 2’s complement.
j)
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Draw the neat diagram of a 4-bit ripple carry adder using full adder.
0 1 /2 Part-II
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Only Focused-Short Answer Type Questions- (Answer Any Eight out of
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(6 × 8)
Twelve)
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a) State and explain any six addressing modes with suitable example.
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Explain with the help of flow diagram how an instruction is fetched, decoded, and
b)
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executed?
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What is CISC? How it is different from RISC? Explain the characteristics of RISC
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c)
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and CISC architecture. /0 1
d)1/ 0 4
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A digital computer has a common bus system for 8 registers of 16 bit each. The
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I. How many select input are there in each multiplexer?
10 II. What is the size of multiplexers needed?
III. How many multiplexers are there in the bus?
e) Describe the purpose of subroutine in a program. Write a program which moves a
block of data from one location to another.
f) Minimize the following Boolean function using K-map.
F(A, B, C, D) = Σm(0, 1, 3, 5, 7, 8, 9, 11, 13, 15)
g) Computer employs RAM chips of 256 x 8 and ROM chips of 1024 x 8. The
computer system needs 2K bytes of RAM, 4K bytes of ROM, and four interface
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units, each with four registers. A memory mapped I/O Configuration is used. The
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two highest-order bits of the address bus are assigned 00 for RAM, 01 for ROM,
10 for interface registers.
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(i) How many RAM and ROM chips are needed?
(ii) Draw a memory-address map for the system.
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(iii) Give the address range in hexadecimal for RAM, ROM, and interface.
h)
i)
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Explain in detail multiple bus organization with a neat diagram.
List the differences between hardwired and micro programmed control unit. Write
the sequence of control steps for the following instruction for single bus
architecture.
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j)
R1 ← R2* (R3)
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How is the Virtual address mapped into physical address? What are the different
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methods of writing into cache?
k)
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The logical address space in a computer system consists of 128 segments. Each
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segment can have up to 32 pages of 4K words each. Physical memory consists of
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4K blocks of 4K words each. Formulate the logical and physical address formats.
l)
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What are the different methods of asynchronous data transfer? Explain in detail.
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Part-III
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0Any Two out of Four)
Only Long Answer Type Questions (Answer
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Q3
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Write a program to evaluate the arithmetic statement: (16)
10 with three operand instructions
X = A * (B + C) + D / E * F + G
1. Using a general register computer
2. Using a general register computer with two operand instructions
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3. Using an accumulator type computer with one operand instructions
instructions)
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4. Using a stack organized computer with zero address instructions (stack
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Do not modify the values of A, B, C, D, E, F or G. Use a temporary location T to
store the intermediate results if is necessary.
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Q4
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Design hardware for signed magnitude addition and subtraction. Show the (16)
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(+13) X (–16) are multiplied.
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multiplication process using Booth algorithm, when the following binary numbers,
Classify4
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and describe the possible modes of data transfer to /and
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2 from peripherals.
Q5
2 0 how DMA bypasses CPU and speeds up the4/memory
Elaborate
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0 operation? With a (16)
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neat schematic, Explain about DMA controller and
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its mode of data transfer.
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0Q64 What is Locality of Reference? Explain about 9 memory in detail. Illustrate the
9 - 10Cache (16)
1 0 mapping process involved in transformation of data from main to Cache memory.
A computer has a 4 GByte memory with 32 bit word sizes. Each block of memory
stores 32 words. The computer has a direct-mapped cache of 64 blocks. The
computer uses word level addressing. What is the address format? If we change
the cache to an 8-way set associative cache, what is the new address format?
