CD40100BMS

CMOS 32-Stage Static

December 1992
Left/Right Shift Register

Features Description
• High Voltage Type (20V Rating) CD40100BMS is a 32-Stage shift register containing 32
D-type master-slave flip-flops.
• Fully Static Operation
The data present at the SHIFT RIGHT INPUT is transferred
• Shift Left/Shift Right Capability
into the first register stage synchronously with the positive
• Multiple Package Cascading CLOCK edge, provided the LEFT/RIGHT CONTROL is at a
low level, the RECIRCULATE CONTROL is at a high level,
• Recirculate Capability and the CLOCK INHIBIT is low. If the LEFT/RIGHT
• LIFO of FIFO Capability CONTROL is at a high level and the RECIRCULATE
CONTROL is also high, data at the SHIFT LEFT INPUT is
• 100% Tested for Quiescent Current at 20V transferred into the 32nd register stage synchronously with
• 5V, 10V and 15V Parametric Ratings the positive CLOCK transition, provided the CLOCK INHIBIT
is low. The state of the LEFT/RIGHT CONTROL,
• Maximum Input Current of 1µA at 18V Over Full Pack- RECIRCULATE CONTROL, and CLOCK INHIBIT should not
age Temperature Range; 100nA at 18V and +25oC be changed when the CLOCK is high.
• Noise Margin (Over Full Package/Temperature Range) Data is shifted one stage left or one stage right depending on
- 1V at VDD = 5V the state of the LEFT/RIGHT CONTROL, synchronously with
- 2V at VDD = 10V the positive CLOCK edge. Data clocked into the first or 32nd
- 2.5V at VDD = 15V register states is available at the SHIFT LEFT or SHIFT
RIGHT OUTPUT respectively, on the next negative CLOCK
• Standardized, Symmetrical Output Characteristics transition (see Data Transfer Table). No shifting occurs on the
positive CLOCK edge if the CLOCK INHIBIT line is at a high
• Meets All Requirements of JEDEC Tentative Standard
level. With the RECIRCULATE CONTROL low, data in the
No. 13B, “Standard Specifications for Description of
32nd stage is shifted into the first stage when the LEFT/
‘B’ Series CMOS Devices”
RIGHT CONTROL is low and from the first stage to the 32nd
stage when the LEFT/RIGHT CONTROL is low, and from the
Applications first state to the 32nd stage when the LEFT/RIGHT control is
• Serial Shift Registers high. The CD40100BMS is supplied in these 16-lead outline
packages:
• Time Delay Circuits
Braze Seal DIP H4T
• Expandable N-Bit Data Storage Stack (LIFO Operation) Frit Seal DIP H2R
Ceramic Flatpack H6W

Pinout Functional Diagram

CD40100BMS
TOP VIEW
LEFT/RIGHT
CONTROL
NC 1 16 VDD
13
CLOCK INHIBIT 2 15 NC SHIFT RIGHT SHIFT RIGHT
IN OUT
11 12
CLOCK 3 14 NC
LEFT/RIGHT CLOCK
SHIFT LEFT OUT 4 13
CONTROL 4
NC 5 12 SHIFT RIGHT OUT
CLOCK INHIBIT SHIFT LEFT
SHIFT LEFT IN 6 11 SHIFT RIGHT IN OUT
2 4
NC 7 10 NC SHIFT LEFT
RECIRCULATE IN VSS = 8
VSS 8 9 6
CONTROL 9 VDD = 16

RECIRCULATE NC = 1, 5, 7, 10, 14, 15

NC = NO CONNECTION CONTROL

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 3349
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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 Specifications CD40100BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
(Voltage Referenced to VSS Terminals) Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Maximum Package Power Dissipation (PD) at +125oC
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
Package Types D, F, K, H For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Linearity at 12mW/oC to 200mW
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for For TA = Full Package Temperature Range (All Package Types)
10s Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 10 µA
2 +125oC - 1000 µA
VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
(Note 2)
Input Voltage High VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
(Note 2)
Input Voltage Low VIL VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC - 4 V
(Note 2) VOL < 1.5V
Input Voltage High VIH VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC 11 - V
(Note 2) VOL < 1.5V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented. is 0.050V max.
2. Go/No Go test with limits applied to inputs.

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 Specifications CD40100BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) SUBGROUPS TEMPERATURE MIN MAX UNITS
o
Propagation Delay TPHL VDD = 5V, VIN = VDD or GND 9 +25 C - 720 ns
Clock to Shift Left/Right TPLH
10, 11 +125oC, -55oC - 972 ns
Output
Transition Time TTHL VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
TTLH o o
10, 11 +125 C, -55 C - 270 ns
o
Maximum Clock Input FCL VDD = 5V, VIN = VDD or GND 9 +25 C 1 - MHz
Frequency o o
10, 11 +125 C, -55 C .74 - MHz
NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55o C, +25 Co
- 5 µA

+125 C o
- 150 µA

VDD = 10V, VIN = VDD or GND 1, 2 o

-55 C, +25 C o
- 10 µA

+125 C o
- 300 µA

VDD = 15V, VIN = VDD or GND 1, 2 o

-55 C, +25 C o
- 10 µA

+125 C o
- 600 µA
o o
Output Voltage VOL VDD = 5V, No Load 1, 2 +25 C, +125 C, - 50 mV
-55oC

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, - 50 mV

-55oC

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, 4.95 - V

-55oC

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, 9.95 - V

-55oC
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

-55oC 0.64 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

-55oC 1.6 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

-55oC 4.2 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

-55oC - -0.64 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

-55oC - -2.0 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

-55oC - -1.6 mA

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

-55oC - -4.2 mA

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 Specifications CD40100BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS

Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, - 3 V
-55oC

Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, +7 - V
-55oC

Propagation Delay TPHL1 VDD = 10V 1, 2, 3 +25oC - 330 ns

Clock to Shift Left/Right TPLH1
VDD = 15V 1, 2, 3 +25oC - 230 ns
Output

Transition Time TTHL VDD = 10V 1, 2, 3 +25oC - 100 ns

VDD = 15V 1, 2, 3 +25oC - 80 ns

Maximum Clock Input FCL VDD = 10V 1, 2, 3 +25oC 2.5 - MHz

Frequency
VDD = 15V 1, 2, 3 +25oC 3 - MHz

Minimum Data Setup TS VDD = 5V 1, 2, 3 +25oC - 100 ns

Time
VDD = 10V 1, 2, 3 +25oC - 20 ns

VDD = 15V 1, 2, 3 +25oC - 10 ns

Minimum Data Hold Time TH VDD = 5V 1, 2, 3 +25oC - 275 ns

VDD = 10V 1, 2, 3 +25oC - 100 ns

VDD = 15V 1, 2, 3 +25oC - 75 ns

Minimum Clock Pulse TWL VDD = 5V 1, 2, 3 +25oC - 450 ns

Width Low Level
VDD = 10V 1, 2, 3 +25oC - 230 ns

VDD = 15V 1, 2, 3 +25oC - 190 ns

Minimum Clock Pulse TWH VDD = 5V 1, 2, 3 +25oC - 280 ns

Width High Level
VDD = 10V 1, 2, 3 +25oC - 150 ns

VDD = 15V 1, 2, 3 +25oC - 140 ns

Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF

NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V
Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V
Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 3V, VIN = VDD or GND

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 Specifications CD40100BMS

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Propagation Delay Time TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC

PARAMETER SYMBOL DELTA LIMIT
Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading
ON Resistance RONDEL10 ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

MIL-STD-883
CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz
Static Burn-In 1 1, 4, 5, 7, 10, 12, 2, 3, 6, 8, 9, 11, 13 16
Note 1 14, 15
Static Burn-In 2 1, 4, 5, 7, 10, 12, 8 2, 3, 6, 9, 11,
Note 1 14, 15 13, 16
Dynamic Burn- 1, 5, 7, 10, 14, 15 2, 8, 13 9, 16 4, 12 3 6, 11
In Note 1
Irradiation 1, 4, 5, 7, 10, 12, 8 2, 3, 6, 9, 11,
Note 2 14, 15 13, 16

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 Specifications CD40100BMS

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS (Continued)

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

TABLE 9. DATA TRANSFER TABLE*

INITIAL STATE CLOCK RESULTING STATE

INTERNAL
DATA INPUT CLOCK INHIBIT INTERNAL STAGE LEVEL CHANGE STAGE Q OUTPUT

0 0 X 0 NC

X 0 0 NC 0

1 0 X 1 NC

X 0 1 NC 1

X 1 1 X NC NC

0 = Low Level 1 = High Level X = Don’t Care NC = No Change

* For Shift-Right Mode

Data Input = SHIFT RIGHT INPUT (Term. 11)
Internal Stage = Stage 1 (Q1)
Output = SHIFT LEFT OUTPUT (Term. 4)

For Shift Left Mode

Data Input = SHIFT LEFT INPUT (Term. 6)
Internal Stage = Stage 32 (Q32)
Output = SHIFT RIGHT OUTPUT (Term. 12)

TABLE 10. CONTROL TRUTH TABLE

LEFT/RIGHT RECIRCULATE
CONTROL CLOCK INHIBIT CONTROL ACTION INPUT BIT ORIGIN

1 0 1 Shift Left Shift Left Input

1 0 0 Shift Left Stage 1

0 0 1 Shift Right Shift Right Input

0 0 0 Shift Right Stage 32

X 1 X No Shift -

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FAX: (886) 2 2715 3029

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 CD40100BMS

Logic Diagram

CLOCK CL
3*
CL
CLOCK INHIBIT
2*
R S

SHIFT RIGHT SHIFT RIGHT

p p 12
11* CL
INPUT n n OUTPUT
p
R
S
n
p S CL CL S CL
n CL
p p p
STAGE 1
LEFT/RIGHT R n n n
13* S
CONTROL S S CL
S S CL CL S

p p
RECIRCULATE STAGE 2
n n
9* R
CONTROL
R S S

STAGES 3-30
(ALL IDENTICAL TO
STAGES 2 AND 31)

S CL CL S
VDD
p p
STAGE 31
n n

S S
CL CL CL S R

VSS p p p
STAGE 32
n n n
* ALL INPUTS ARE PROTECTED
CL
BY CMOS PROTECTION R
NETWORK CL S
p p
n n

CL R SHIFT RIGHT
12
SHIFT LEFT
OUTPUT
6*
INPUT

CL CL

p p
D Q
n n

CL CL
CL CL
p p
n n

CL CL

FIGURE 1.

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 CD40100BMS

Typical Performance Characteristics

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25 12.5

20 10.0

10V
15 7.5
10V

10 5.0

5 2.5
5V 5V

0 5 10 15 0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15 -10 -5 0 -15 -10 -5 0
0 0
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10 -5

-15

-10V -10V
-20 -10

-25

-15V -15V
-30 -15

FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS CHARACTERISTICS
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

AMBIENT TEMPERATURE (TA) = +25oC

AMBIENT TEMPERATURE (TA) = +25oC
TRANSITION TIME (tTHL, tTLH) (ns)

600

SUPPLY VOLTAGE (VDD) = 5V 200

400 SUPPLY VOLTAGE (VDD) = 5V

150

100
200 10V 10V
15V
50
15V

0 20 40 60 80 100 0
0 20 40 60 80 100
LOAD CAPACITANCE (CL) (pF) LOAD CAPACITANCE (CL) (pF)

FIGURE 6. TYPICAL PROPAGATION DELAY TIME (CLOCK TO FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF
SHIFT LEFT/RIGHT) AS A FUNCTION OF LOAD LOAD CAPACITANCE
CAPACITANCE

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 CD40100BMS

Typical Performance Characteristics (Continued)

AMBIENT TEMPERATURE (TA) = +25oC

6
4 SUPPLY VOLTAGE (VDD) = 15V

LOAD CAPACITANCE (RL) = 200KΩ

POWER DISSIPATION (PD) (µW)
2
105
8 CL = 50pF
6 CL =15pF

INPUT RISE & FALL TIME

4
2
104
8
10V
6
4 10V

(tr, tf) = 20ns

2
103
8 5V
6
4
2
102
2 4 68 2 4 68 2 4 68 2 4 68 2 4 68
1 10 102 103 104
CLOCK INPUT FREQUENCY (fCL) (KHz)

FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY

Timing Diagram
tWL
tWH
CLOCK

tS
tH tPHL
INPUT

tPHL

OUTPUT

FIGURE 9. TIMING DIAGRAM DEFINING SETUP, HOLD, AND PROPAGATION DELAY TIMES

Chip Dimensions and Pad Layout

Dimensions in parenthesis are in millimeters and are derived from

the basic inch dimensions as indicated. Grid graduations are in mils
(10-3 inch).

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

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