PRADEEP KUMAR YADAV
[email protected]
PH no: 8421680331
Career Objective:
To achieve excellence in being a VLSI DESIGN professional in growing organization that will
challenge my skills, analytical and problem solving abilities & offering solutions to business
using the best available technology where my analytical abilities are used to maximum for
growth of the organization and to grow with the organization to excel in this progressive VLSI
DESIGN environment to the fullest of my potential.
Summary:
I have Total 3 years 8 months experience which include 3 years 2 Months
experience as NOC Engineer Worked with RELIANCE COMMUNICATION.
Professional Experience:
Company: - Reliance Communication
Duration: - March 2009 to MAY 2012
Position: - Network and Telecommunication Engineer
Company: - APW Private Limited.
Duration: - August 2008 to February 2009
Position: - System Engineer
Job Responsibilities:
To check hardware and networking device and their connectivity.
RTL DESIGN, FPGA DESIGN, VERILOG.
Providing the technical support and trouble-shooting standalone machines.
VLSI DOMAIN SKILL
HDL : VERILOG
EDA TOOL : ISE Xilinx
FPGA BOARD : SPARTAN 6
VLSI PROJECTS
DESIGNED A COUNTER (HDL: Verilog, EDA Tools: Xilinx XST, FPGA) this counter was
designed for the telecom equipment for checking the down time. Counter was designed and
checked on FPGA board.
ALU and FSM design was done for ring technology. (HDL: Verilog, EDA Tools: Xilinx
XST)
ACADEMIC PROJECT
OPTIMIZATION OF SCAN TIME OF SCAN TEST IN SYSTEM-ON-CHIP (SoC)
This project was about reducing the scan time in the system on chip the project was
successfully completed and was successfully tested on the FPGA board SPARTAN 6.
Area Of Interest:
Design in the field of VLSI DESIGN, RTL DESIGN.
FPGA, VERILOG, ASIC.
On various Electronics Equipment.
Education Qualifications:
ME in ELECTRONICS ENGINEERING:
Examination Institute University Year of GRADE
Passing
SEMISTER I TERNA ENGINEERING MUMBAI 2015 8.18
COLLEGE
SEMISTER II TERNA ENGINEERING MUMBAI 2015 8.36
COLLEGE
SEMISTER III & IV TERNA ENGINEERING MUMBAI 2018 8.97
COLLEGE
CGPA in ME ELECTRONICS is 8.97
B.E in Electronics and Telecommunication Engineering:
Completed BE in ELECTRONICS AND TELECOMMUNICATION from UNIVERSITY OF MUMBAI
from SSPM’s COLLEGE OF ENGINEERING in 2007 with aggregate of 64.01 %.
Secondary and Higher Secondary:
Percentag
Examination College/School Board Year of
e
Passing
H.S.C. A.E.J.C TARAPUR MAHARASHTRA 2002-2003 75.16
S.S.C. A.E.C.S TARAPUR C.B.S.E 2000-2001 69.20
Computer Technical Skill:
Languages : C, C++.
Operating System : Windows XP, Windows7, Windows10
Tools : MS Office 2003, 2007, MS VISIO 2003
Hobbies:
Athletics, Football, Visiting New Place.
Strengths:
Wonderful Team Player, Excellent in problem resource and troubleshooting, having a high
patient level at trouble-shooting problems, Good Communication and Motivational skills,
Quick learner, Punctual, Never Dying Fire to learn new things, always having Positive
attitude, Having Innovative ideas, Capable to work with team and take the responsibility.
Personal Profile:
Father's Name : Jairam Yadav
Data of Birth : 14-01-1986
Permanent Address : TYPE-B 30/1,T.A.P.S Colony, TARAPUR DIST: THANE
Pin: 401504
Email :
[email protected]Phone Number : 8421680331
(Pradeep Kumar Yadav)
