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A 76-81 GHz FMCW 2TX/3RX Radar Transceiver with Integrated

Mixed-Mode PLL and Series-Fed Patch Antenna Array
Taikun Ma1 , Wei Deng1,2 , Haikun Jia1,2 , Yejun He3 and Baoyong Chi1,2
1
School of Integrated Circuits, Tsinghua University, Beijing, China;
2
Research Institute of Tsinghua University in Shenzhen, Shenzhen, China;
3
College of Electronics and Information Engineering, Shenzhen University, Shenzhen, China;
Email: [email protected]

Abstract— This paper presented a 76-81 GHz outputs of (m − 1)th stage of X and mth stage of Y
FMCW MIMO Radar transceiver with mixed-mode equals zero. The dynamic range of the DAC is important
PLL. Utilizing series-fed patch antenna array, a for generating almost-ideal sawtooth FMCW chirp since
2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) | 978-1-6654-2135-5/22/$31.00 ©2022 IEEE | DOI: 10.1109/ASP-DAC52403.2022.9712506

prototype system is developed based on the proposed the DAC’s output represents the slope of the waveform.
transceiver. On-chip Measurements show that As illustrated in Fig. 2(b), a coarse-fine DAC with a 10
reconfigurable sawtooth chirps could be generated μA fine LSB and a 1.28 mA coarse LSB is presented,
with a bandwidth up to 4 GHz and a period as short supporting a chirp slope up to 4 GHz/5 μs.
as 30 μs. Real-time experiments demonstrate that C. Series-Fed Patch Antenna Array
the prototype MIMO radar has the ability of target
As shown in Fig. 3, based on the proposed FMCW radar
detection and achieves an angular resolution of 9◦
transceiver, a two-chip cascaded 4T6R radar prototype
I. Introduction is presented. PCB-based non-uniform excited series-fed
In recent years, with the development of automotive patch antenna array is employed. The gain and side lobe
technique, the demand for high performance millimeter level of one single antenna achieve 11.2 dB and -20 dB,
radar has grown rapidly. Several W-band FMCW radar respectively [4]. With a spacing of 2.2 mm, the theoretical
transceivers have been presented [1–3]. However, these field of view(FOV) of the antenna array achieves ±55◦
works suffer from inflexible PLL loop bandwidth and III. Measurement Results
limited angular resolution. Additionally, less attention The proposed radar transceiver is fabricated in a 65nm
has been paid on TX-leakage and short-range interference, CMOS technology with a chip area of 7.29 mm2 . Fig. 3(a)
which may deteriorate RX performance. shows the chip photo. Fig. 4 depicts the measured phase
In this work [4], a FMCW radar transceiver is presented noise of the PLL at 39.2 GHz carrier. Demodulated
by using a mixed-mode PLL with flexible loop bandwidth. FMCW chirps with different configurations are shown in
2 TX, 3 RX and cascadable LO scheme are presented for Fig. 5. Two corner reflectors placed 5 m away are used to
MIMO to improve angular resolution. High linearity RX measure the angular resolution and FOV of the prototype.
is utilized to deal with TX-leakage. A prototype system As shown in Fig. 6, a 9◦ angular resolution and a 106◦
is also developed with series-fed patch antenna array. FOV are achieved. Fig. 7 illustrated the environment
II. Proposed Radar Transceiver and Prototype and result of the real-time measurement in multi-target
A. System Architecture scenario. The result shows that Flag poles, trees and bikes
Fig. 1 shows the block diagram of the proposed FMCW are correctly detected.
radar transceiver. The system consists of a mixed- IV. Conclusion
mode PLL for chirp generating, a frequency doubled This paper presents a 76-81 GHz FMCW radar
LO network with input/output buffers for LO signal transceiver with mixed-mode PLL and a PCB-based radar
distribution and chip cascading. Two TXs and three prototype with series-fed patch antenna array [4]. The on-
RXs are integrated for MIMO operation. To resist TX- chip and real-time measurements show that the presented
leakage, high RX linearity is achieved by utilizing a low- radar system has the ability of multi-target detection and
gain LNA, a voltage-mode passive mixer and a high-pass the potential of practical application.
IF amplifier. Each TX consists of a PA with fast on/off
switch and a Bi-Phase modulation stage for OOK and Acknowledgements
BPSK MIMO operation This work was supported by the National Key R&D
B. Mixed-mode PLL Program of China under Grant No.2020YFB1807300,
the Shenzhen Science and Technology Program (No.
In the mixed-mode PLL, a digital loop filter is used
JCYJ20200109113601723), the Tsinghua-Samsung Joint
to reconfigure the loop bandwidth according to different
Research Project, and the Beijing Innovation Center for
chirp waveforms. A low-mismatch wide-range 2-D Venier
Future Chips (ICFC), Tsinghua University.
TDC is employed to detect the divided clock period. As
shown in Fig. 2(a), a delay lock loop(DLL) is utilized to References
[1] J. Lee, et al “A Fully-Integrated 77-GHz FMCW Radar
calibrated the delay mismatch between two delay chains. Transceiver in 65-nm CMOS Technology,” IEEE JSSC, vol. 45,
Assuming the unit delay time of two chain are τx = mΔ no. 12, pp. 2746-2756, Dec 2010.
and τy = (m − 1)Δ, the DLL configures the delay unit [2] H. K. Jia, et al “A 77 GHz Frequency Doubling Two-Path
Phased-Array FMCW Transceiver for Automotive Radar,”
of two chains till the delay time difference between the IEEE JSSC, vol. 51, no. 10, pp. 2299-2311, Oct 2016.

978-1-6654-2135-5/22/$31.00 ©2022 IEEE 3

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[3] B. P. Ginsburg, et al “A Multimode 76-to-81GHz Automotive
Radar Transceiver with Autonomous Monitoring,” 2018 IEEE
ISSCC, San Francisco, CA, 2018, pp. 158-160.
[4] T. Ma, et al “A CMOS 76-81GHz 2-TX 3-RX FMCW Radar
Transceiver Based on Mixed-Mode PLL Chirp Generator,”
IEEE JSSC, vol. 55, no. 2, pp. 233–248, Feb. 2020.

(a) (b)

(c) (d)
Fig. 5. Demodulated FMCW chirps and frequency error without
turning points under different configurations: (a) 300 μs & 4 GHz,
(b) 1 ms & 1 GHz, (c) 30 μs & 4 GHz, (d) 30 μs & 300 MHz. [4]
Fig. 1. System block diagram of the presented FMCW
transceiver. [4]

(a) (b)
Fig. 6. (a) Measured angle pattern with two corner reflectors. (b)
Measured FOV. [4]
(a) (b)
Fig. 2. (a) Conceptual block diagram of the 2-D Venier TDC and
the calibration loop. (b) Schematic of the current steering DAC. [4]

(a) (b)
(a) (b) Fig. 7. (a) Multi-target measurement scenario. (b) Measured 2-D
normalized power distribution of multi-target scenario. [4]
Fig. 3. (a) Chip Photograph (x2 = doubler, WC = Waveform
Controller). (b) Photograph of the RF board including TX/RX
antenna arrays and cascaded packaged chips. [4]
TABLE I
Performance Comparison
[1] [2] [3] This Work
65nm 65nm 45nm 65nm
Process CMOS CMOS CMOS CMOS
Channel 1T1R 1T2R 3T4R 2T3R
Chirp BW (GHz) 0.7 1.93 4 4
Chirp Slope (MHz/us) 1.4 1.93 100 13.3/133a
RMS error (kHz) 65 674 - 110/4620a
Phase noise (dBc/Hz) -85.53 -81 -94 -87
Area/channelb (mm2 ) 1.04 2.32 1.83 1.22
Power/channelb W 0.243 0.172 0.283 0.154

a The RMS frequency error of 4 GHz/300 μs and 4 GHz/30 μs

sawtooth chirp are 110 kHz and 4.62 MHz, respectively.
b The average area and consumption of the formed each MIMO
Fig. 4. Measured phase noise of the PLL locked at 39.2 GHz fixed virtual channel (N RX + M TX means N*M virtual channels).
frequency point. [4]

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