Power Supply Design Seminar

Introduction to the Trans-Inductor

Voltage Regulator (TLVR)

Reproduced from
2024 Texas Instruments Power Supply Design Seminar
SEM2600
Topic 3
Matthew Schurmann and Mohamed Ahmed
Literature Number: SLUP413

Power Supply Design Seminar resources

are available at:
www.ti.com/psds
Power Supply Design Seminar

Introduced in 2019, the trans-inductor voltage regulator (TLVR) topology offers major transient response, power density and solution cost
improvements (a >40% capacitor reduction for the design example reviewed in this topic) versus the traditional multiphase buck voltage
regulator topology. This topic covers the operating principles of the TLVR topology, performance and cost improvements over traditional
voltage regulators, design equations, and guidelines.

VIN
Introduction
SW1
Load transient regulation performance continues to be an
important challenge in the design of voltage regulators
for modern computing devices such as microprocessors,
graphics processors, application-specific integrated
circuits and field-programmable gate arrays. Technology
trends in the development of these computing devices,
VIN
such as rapidly increasing complexity, silicon process-
node evolution, physical limitations of transistor scaling SWn

and chiplet architectures continue to accelerate the

demands placed on the voltage regulators powering
Inductor type
them. In some cases, high-end core-rail voltage
Traditional
regulators have thermal design currents greater than
1,000 A, peak currents greater than 2,000 A, rise times Figure 1. Multiphase buck topology.
in the nanosecond range, and regulated output voltages VIN
of 0.7 V, ±3%.
SW1
The TLVR topology is derived from the multiphase half-
bridge buck converter topology, but replaces the single-
winding inductor of each phase with a two-winding
coupled inductor, as shown in Figure 1 and Figure 2.
Similar to the multiphase buck converter, the primary
side of each coupled inductor is connected between the VIN

switch node of each phase and the converter output

SWn
voltage. The added secondary windings are connected
in a series loop, with an additional inductor known
as the compensating inductor (LC). In the following
sections, we’ll discuss the limitations of the multiphase
buck converter in terms of load transient response,
LC Inductor type
fundamental operating principles of the TLVR topology, Coupled
trade-offs and practical considerations. Compensating

Figure 2. TLVR topology.

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Converter Transient Response Equation 1 shows the relationship between the total
output deviation ΔV, COUT, and the rate (slope) at which
Figure 3 shows a simple block diagram of a voltage
the converter can ramp its current up or down:
regulator system subject to a load transient condition.
ISUM represents the sum of the individual inductor 2
1 ×t 1 × Istep
currents from each phase in the converter. ILOAD ΔQ resp × I step 2 Slope
ΔV = C = 2 Cout = Cout (1)
out
represents the actual load current drawn by the load
device. Any time ILOAD changes, the voltage regulator For the traditional multiphase buck converter, this slope
responds by changing the effective duty cycle of is directly related to the output filter inductance used
switching in each phase in order for the ISUM to ramp for each phase. Reducing the inductance value would
up or down to track the new ILOAD value. indeed improve the transient response of the converter.
The output filter of the converter – in particular, the filter Simply reducing the output inductance of each phase
inductance – limits how quickly ISUM can ramp to the new has unintended consequences for the converter’s power
ILOAD value. During the time when ISUM is ramping up losses and its steady-state ripple, however. Reducing
or down, the filter capacitors must supply the difference the inductance value leads to a higher inductor current
between them over time; this is known as the charge ΔQ. ripple and consequently a higher voltage ripple on the
The output voltage of the converter will undershoot or output of the converter, which typically also has stringent
overshoot during this time, and the only ways to limit the requirements. It also increases the root-mean-square
voltage deviation (ΔV) are to either increase the rate at (RMS) current in each phase, reducing overall converter
which ISUM can ramp (by reducing the filter inductance, efficiency.
for example) or to increase the total output capacitance
In a multiphase buck converter topology, the inductance
(COUT) of the filter.
value is a constant, in both steady state and
ISUM
Voltage
ILOAD
during transient events. Therefore, the selection of
Load
Regulator
an inductance value is a balanced trade-off between
transient response, power loss, and voltage ripple and
current ripple. It is not practical to make the inductance
Figure 3. Converter load transient block diagram. very small; thus, a large amount of COUT may be required
to limit ΔV in order to meet the specifications.
Figure 4 shows the typical ISUM and output voltage
The TLVR topology addresses this problem by allowing a
waveforms in a traditional multiphase buck converter.
different effective filter inductance in different conditions.
ISUM(BUCK)
IOUT A high effective value of filter inductance during steady-
VOUT
state operation limits the converter ripple and RMS
ISTEP ΔQ ΔQ
power losses. A low effective inductance value during
transient conditions dramatically reduces the amount
of COUT required to meet a given transient regulation
specification. Figure 5 shows the typical load transient
response of a TLVR converter, having a much higher ISUM
slope during the converter response.
Time

Figure 4. Buck converter load transient.

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ISUM(TLVR)
IOUT Equation 4 and Equation 5 express the effect of RLL on
VOUT
the required COUT of the converter:

2
1 × ISTEP
ΔQunder 2 Slope
ISTEP ΔQ ΔQ
COUT min, step up = ΔV = ΔV + R × I (4)
under ac LL step

2
1 Istep
ΔQ ×
2 Slope
COUT min, step down = ΔVover = ΔV + R × I (5)
over ac LL step
ISUM
IOUT
VOUT = VNOM, RLL = 0 mΩ
VOUT > VNOM, RLL ≠ 0 mΩ

Time

Figure 5. TLVR load transient.

It is possible to achieve a further reduction in VOUT = VNOM

ΔVAC = ΔVOVER

capacitance with either the multiphase buck or TLVR ΔVAC = ΔVUNDER

topology using DC load line (DCLL), also known as VOUT > VNOM

ΔVAC

adaptive voltage positioning. Figure 6 demonstrates the

ΔVOVER
ΔVUNDER ΔVDROOP

concept. This technique applies to either the multiphase ΔVAC

Time

buck converter or TLVR topology and does not change Figure 6. DC load line, or adaptive voltage positioning.
fundamentally.
Magnetics
Given a specification, in terms of a load step size and
minimum and maximum allowable output voltage, the Because the TLVR topology achieves its transient

converter typically regulates the output voltage to a benefits by allowing different effective inductance values

constant value regardless of the load current – this is in steady-state and transient conditions, it is helpful to

known as zero load line, RLL = 0 mΩ. Then the allowed explore the behavior of the coupled inductor structure

output voltage overshoot (ΔVovershoot) and undershoot that it uses. This concept is not entirely unique to the

(ΔVundershoot ) each become equal to 50% of the total TLVR topology.

voltage specification window. Figure 7 shows a traditional two-phase coupled inductor

For a non-zero-load-line design, configure the converter structure in which the windings for individual phases in

to set its output voltage as a function of the sensed the converter share a common magnetic core. Current

load current. The voltage at zero load (V0) is configured in one winding directly induces current in the others, as

to a value near the maximum allowed output voltage. the magnetic flux in the core is additive. During a load

Equation 2 describes the output voltage when using the transient, a current change in one phase (one winding)

load line: directly causes a change in the same direction in the

other phases. This behavior allows the total converter
VOUT IOUT = V0 − RLL× IOUT (2) ISUM to ramp up or down to meet the load current
demand more quickly than if the phases were uncoupled.
Equation 3 defines the RLL value in terms of the allowed
voltage change ΔVDROOP: The coupling coefficient (K) between different windings of
this structure will typically be between 0.4 and 0.7. This
ΔV
RLL = ΔIDROOP (3) coupling is well controlled by the core design (in Figure
STEP
7, by the air gap in the middle leg). Very high coupling

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(K≅1.0) is not beneficial, as it increases the current ripple secondary-side current to all phases achieves coupling
of the converter in steady state. Very low coupling simply between cores (the phases), as they are connected in a
reduces the transient benefits achievable. loop.
A. B.

PRI SEC

1 2

IPRI1
IL1 IL2

LLKG

SEC
PRI ISEC
Phase
2

Phase
1

A. Primary side (connect to power stage)

B. Secondary side (provides coupling)

Source: Eaton Figure 8. Indirect-coupled two-phase inductor.

Figure 7. Traditional two-phase inverse-coupled inductor. Similar to a traditional coupled inductor, it is beneficial
to have the coupling coefficient (α) between phases in
Adoption of the traditional coupled inductor for high-
the range of 0.4 to 0.7. The secondary loop controls
phase-count designs (more than four phases) has been
this coupling. The inductance in the secondary loop may
limited for several reasons. Extending it to higher
be very low, leading to high coupling (and thus a large
phase counts requires a complex core geometry to
steady-state current ripple) or simply not well-controlled,
maintain coupling symmetry. This structure also requires
as a result of interconnect and physical construction
more customization of inductors for different designs,
tolerances.
limiting scalability; for example, you would need a
different inductor for two- and three-phase designs. To control the coupling between phases, the TLVR
Additionally, until recently, aggressive patent protection topology often uses a separate physical inductor on
limited multisourcing options; no such limitation exists for the secondary side, LC, shown in Figure 9. If the
the TLVR topology. leakage inductance in the secondary-side loop is large
enough compared to the magnetizing inductance of the
The TLVR topology relies on a similar principle but with
individual coupled inductors, and can be well-controlled
a different magnetic structure, known as an indirect-
by manufacturing, a separate physical LC is not needed,
coupled inductor, shown in Figure 8. Each phase
especially in high-frequency designs switching at higher
inductor has its own physical core with two windings,
than 1 MHz per phase.
so this structure is easily scalable to higher phase
counts simply by adding more cores. The magnetizing
inductance (LM) of each coupled inductor provides
energy storage and filtering. The K between two windings
on one core can be very high. Passing the same

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PRI SEC
TLVR Topology Operating Principles

Steady-State Operation
IPRI1
Figure 11 shows a typical TLVR converter schematic,
LLKG with important nodes, voltages and currents labeled.
LC
Figure 12 illustrates the steady-state operating
ISEC waveforms of a TLVR converter, with four phases shown.
In this example, the pulses from adjacent phases do
not overlap in time. There is no maximum duty-cycle
requirement for the TLVR topology. The same principles
apply for higher-duty-cycle applications where pulses do
Figure 9. Indirect-coupled two-phase inductor with a physical overlap in time.
compensating inductor.
Figure 12 shows the voltage and current waveforms of
Figure 10 shows the typical construction of a TLVR the LC of the secondary-side loop, switch nodes of all
inductor. The inductor size and shape are similar four phases, and the primary-side current of phase 4
to traditional high-current ferrite core inductors for (IPRI4). For clarity, this figure includes labels for the three
multiphase buck converters, with the secondary winding distinct states of operation.
inside the primary winding. The land pattern on the
The most important relationships are those of the LC loop
bottom of the package enables co-layout with both TLVR
and its influence on IPRI and ISUM.
and non-TLVR designs on the same physical printed
circuit board (PCB). VIN

SW1

Lm

ISUM

IPRI1 = ILm1 + ILC

VIN

B. A.
SW4
A. Primary winding

B. Secondary winding Lc

Source: Eaton

Figure 10. Typical TLVR inductor construction.

IPRI4 = ILm4 + ILC

+
LC ILC
–

Four-phase example, no pulse overlap

Figure 11. Steady-state topology.

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(VIN – VOUT)
Table 1 summarizes the state of each of the relevant
SW1 – VOUT

SW2
SW3 voltages and currents shown in Figure 12, with respect
SW4
to the derivation of IPRI4 shown in the plot.
(VIN – × VOUT)

VLC State 1 State 3

State 2
– × VOUT Phase 4 on, Phase 4 and two others
Parameter All phases
phases 1, 2 off, one of the other
off
ILC and 3 off phases is on
VSW1 0V 0V One phase is equal to VIN
ILM and the other two are equal
VSW2 0V 0V
to 0 V.
VSW3 0V 0V
IPRI

1 2 3 2 3 2 3 2 VSW4 VIN 0V –VOUT

Time
ΔVLM1 (1) –VOUT –VOUT
One phase is equal to VIN –
Four-phase, no pulse overlap ΔVLM2 (1) –VOUT –VOUT VOUT and the other two are
equal to –VOUT
Figure 12. Steady-state waveforms. ΔVLM3 (1) –VOUT –VOUT
ΔVLm4 VIN – VOUT –VOUT –VOUT
The magnetizing voltage for each phase is similar to that ILm4 Increasing(2) Decreasing(2) Decreasing(2)
of a buck converter. Equation 6 applies to phase on, ΔVLC Sum of VSW1 Sum of VSW1
Sum of VSW1 to VSW4 (5)
to VSW4 (5) to VSW4 (5)
and Equation 7 applies to phase off. The magnetizing
ILC Increasing(3) Decreasing(3) Increasing(3)
inductance always follows the fundamental inductor IPRI4 Decreasing
Increasing(4) Decreasing slower(4)
relationship shown in Equation 8: faster(4)

Table 1. Four-phase example, steady-state voltages and

ΔVLm, i = VIN (6) currents.
(1) Not in Figure 12.
ΔVLm, i = VIN − VOUT (7)
(2) ΔVLM4/LM
ΔV (3) ΔVLC/LC
ILM = L Lm (8) (4) ILM4 + ILC
m
(5) VIN – 4 × VOUT

The voltage across the LC is always equal to the sum Load Transient Step-Up
of the magnetizing voltages across all phases, as shown
Figure 13 and Figure 14 show a simulated comparison
in Equation 9. LC itself always follows the fundamental
between a multiphase buck converter and a TLVR
inductor relationship, expressed by Equation 10:
design under the same load step-up condition. Table
ΔVLC = VLm1 + VLm2 + … (9) 2 summarizes the simulation parameters. These are
closed-loop simulations using the TI TPS536C9T
ΔV
ILC = L LC (10) DCAP+™ constant on-time controller.
C

A few observations about Figure 13 and Figure 14:

The IPRI for each phase is equal to the sum of its
magnetizing current and ILC, expressed in Equation 11. • The TLVR design responds to the transient (ISUM
ISUM is the sum of the primary currents from all phases, catches up to ILOAD) much more quickly because the
expressed by Equation 12: ISUM rises at a faster rate. As a consequence, the
output voltage deviation is significantly lower.
IPRI, i = ILm, i + ILC (11)

ISUM = IPRI1 + IPRI2 + … (12)

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• During the transient response, the multiphase buck Parameter Description Value
VIN Input voltage 12 V
converter design required many more pulses to
VOUT Output voltage 0.8 V
respond than the TLVR design, meaning that the TLVR
Total operating phase
NTOTAL 4 phases
design delivers more energy per pulse during the number
transient event. fSW
Switching frequency per
600 kHz
phase
• Given the nature of constant-on-time control, pulses 25 A to 325 A,
ISTEP Load step size
overlapped during the transient response. The LC instantaneous
Magnetizing inductance LM
voltage increased to a level significantly higher than
LM/LBUCK for TLVR, filter inductor LBUCK 150 nH/150 nH
the input voltage during pulse overlap operation, then for buck

returned to normal operation at steady state. LC LC value for TLVR 180 nH

COUT Output capacitance 5.0 µF, idealized
Many pulses

PWM1
Table 2. Simulation parameters for transient load step-up and
PWM2 step-down examples.
PWM3
PWM4
Following the relationships described in the Steady-
IL1 State Operation section, it is evident why the TLVR is
to
IL4 able to ramp its ISUM up more quickly than the buck
converter, and why its transient response was superior.
IOUT
ISUM ISUM for the buck converter is simply the sum of its
individual inductor currents, as shown in Equation 13.
VOUT
Large For the TLVR design, ILC gets added once for each
undershoot

(100 mV/
phase, in addition to each magnetizing current (ILM), as
div)
shown in Equation 14:
Time (1µs/div)

Figure 13. Multiphase buck converter. ISUM buck = IL1 + IL2 + … (13)

Fewer pulses ISUM TLVR = IPRI1 + IPRI2 + … = ILm1 + ILc + (14)

PWM1 ILm2 + ILc + …
PWM2
PWM3
PWM4 All inductors in the system follow the fundamental
Ipri1
to inductor relationship. During the transient response to
Ipri4
the load step-up, the converter turns on NON phases
IOUT Small
Q
ISUM tresp ≅ 1µs
simultaneously. For various reasons, it may not be
possible to turn on all phases at once, so also consider
ILC
that NOFF phases remain off at any one time. Equation
Pulse overlap LC switches
causes large VLC at Ntotal × fsw
15 and Equation 16 show the rising ISUM slope for
△VLC
the multiphase buck converter. These equations do not
VOUT
Smaller undershoot account for the controller response time, but show only
(20 mV/
div)
the limitation from the converter topology.
Time (1µs/div)
ΔVL1 ΔVL2
Figure 14. TLVR. ↑Slope buck = L + L +… (15)

VIN − VOUT V
↑Slope buck ≅ NON L − NOFF OUT
L (16)

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Long PWM low period

Equation 17 and Equation 18 show the rising ISUM slope PWM1
for the TLVR design, assuming that the TLVR magnetizing PWM2
PWM3
inductance LM was equal to the buck filter inductor L for PWM4

comparison purposes: IL1

to
ΔVL1 ΔVLC ΔV ΔV IL4
↑Slope TLVR = LM + LC + L L2 + L Lc + … (17)
M C
Large
Q
IOUT tresp ≅ 10µs
↑Slope TLVR ≅ ↑Slope buck + NTOTAL × (18) ISUM

NON × VIN − NTOTAL × VOUT

LC
VOUT
Large undershoot
Written in this way, the additional terms clearly show the (100 mV/
div)
influence of ILC in enabling the TLVR design to respond Time (5µs/div)

more quickly to transients than a traditional multiphase Figure 15. Multiphase buck converter.
buck design. Shorter PWM low period
PWM1
Load Transient Step-Down PWM2
PWM3
Figure 15 and Figure 16 show a simulated comparison PWM4
Ipri1
between a multiphase buck converter and a TLVR to
design under the same load step-down condition. This Ipri4
Small
Q
tresp ≅ 3µs
simulation uses the same parameters as those in Table 2. IOUT
ISUM

A few observations about Figure 15 and Figure 16:

ILC

• The TLVR design responds to the transient (ISUM

△VLC
catches up to ILOAD) much more quickly because the
ISUM is falling at a faster rate. As a consequence, the VOUT

output voltage deviation is significantly lower. (100 mV/ Small overshoot

div)
• In this case, both designs had the same number of Time (5µs/div)
phases off, but the TLVR design ramped down the
Figure 16. TLVR.
ISUM at a faster rate.
Again, the relationship of ILC to ISUM explains the superior
transient response of the TLVR design. And again, all
inductors in the system follow the fundamental inductor
relationship. During the transient response to the load
step-down, the converter turns off all phases, NTOTAL,
simultaneously. Equation 19 shows the falling ISUM slope
for the multiphase buck converter:

VOUT
↓ Slope buck = – NTOTAL L (19)

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Using a similar analysis, Equation 20 shows the falling After building up a large current, the LC current naturally
ISUM slope for the TLVR design, assuming that the TLVR decays to zero, with a relatively high time constant, τLC,
magnetizing inductance LM is equal to the buck filter as described in Equation 23, formed by the LC and
inductor L for comparison purposes. The TLVR design the resistances in the LC loop. During high-frequency
ramps down its ISUM faster given the factor from the LC repetitive transients, ILC may not settle fully but will not
loop, which decreases proportionally to the square of the saturate, as load steps up and down push ILC in different
number of phases, NTOTAL. directions. Figure 17 and Figure 18 show a simulation of
this behavior:
N × VOUT
↓Slope TLVR ≅ ↓Slope buck – NTOTAL × TOTAL
LC (20)
C L
τLc = R (23)
DCR, Lc + Ntotal × RDCR, secondary + Rrouting
LC Inductor Selection
The LC has somewhat unique requirements compared
ISUM
to other inductors in a typical DC/DC design. The IOUT
inductance of LC is a trade-off between current ripple
and transient response benefits. Typically, start with
IPRI1
LC = LM as a balanced trade-off. Values between 0.8 to
IPRI4
to 1.5 times LM are common with discrete designs.
Lower values may be more common in highly integrated
designs, such as power modules.
ILC
At steady state, LC carries no DC current – only a small
0 100 200 300 400 500 600 700 800
AC current ripple – because it is switching at a high Time (µs)
frequency (at least NTOTAL × fSW when there is no pulse
fSW < 1 kHz
overlap). Its current ripple dominates its RMS current at
Figure 17. Low-frequency transient event.
steady state, described in Equation 21. Consider low
core-loss materials, such as ferrite cores, because of
the high fSW. Another option to further improve transient
ISUM
response may be soft-saturating cores. IOUT

ΔILc
Irms Lc ≈
3
(21) IPRI1
to
IPRI4
However, LC can continue to build large amounts
of current during transient events, as expressed by
Equation 22, where tRESP is the response time of the
controller, as highlighted in Figure 15 and Figure 16. ILC
Therefore, size the LC with a high saturation current, 0 5 10 15 20 25 30 35 40
Time (µs)
similar to the coupled inductors used in each phase.
fSW = 65 kHz
NON step × VIN − NTOTAL × VOUT
ISAT Lc ≫ tRESP × (22) Figure 18. High-frequency transient event.
Lc

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The voltage across the LC, ΔVLC, can exceed the input perfectly (with NTOTAL × D = 1, 2, …). However, for
voltage, VIN, during a load step response. Assuming that typical applications (highlighted in Figure 20 for typical
a controller turns on NON phases in response to the load output voltages of 1.0 V, 1.2 V and 1.8 V), TLVR designs
step, Equation 24 calculates ΔVLC: typically have a 25% to 50% larger ISUM ripple, and
consequently, a 25% to 50% larger output voltage ripple.
ΔVLC max = NON step × VIN − NTOTAL × VOUT (24)
For many cases this will not be an issue, because the
Creepage is not generally a concern, as the high voltage COUT required to meet the transient requirement is much
is not sustained for a long period of time. But the high larger than the capacitance required to meet the design’s
transient voltage across LC may be important to know ripple requirement.
for application safety and component reliability in some ZPCB ZPKG

cases.

Steady-State Ripple
ISUM
Load
TLVR-based designs tend to have larger output voltage
ripple than their multiphase buck converter counterparts. ZPCB ZPKG

Normally, multiphase converters have low voltage ripple

caused by interleaving and ripple cancellation. The Figure 19. Model for output voltage ripple.
converter achieves optimum ripple cancellation when
50
each inductor current has a phase offset of 360

12 V/ 1.0 V
12 V/ 1.2 V

12 V/ 1.8 V
TLVR
Buck
degrees/NTOTAL with respect to each other. For TLVR
Ripple Current Difference (A)

40

designs, however, ILC gets added once to ISUM for

30
each phase offset. So while the ISUM contribution from
each magnetizing inductance ILM does cancel because
20
of interleaving, the contribution from ILC does not, as
expressed by Equation 25: 10

ISUM TLVR = ILm1 + ILc + ILm2 + ILc + … (25)

0
0 5 10 15 20 25 30 35 40 45 50
Figure 19 illustrates the relationship between the ripple Duty Cycle (%)
on ISUM and the ripple on the converter output voltage.
8 phases LM = 150 nH
Typically, the converter and load are separated by a
LC = 120 nH LVR = Leq = 125 nH
power distribution network (PDN). ISUM is generated by
the converter in one location and fed to the PDN, at
Figure 20. Output voltage ripple.
some distance. The impedance of the PDN (including
output capacitors) then determines the output voltage A common technique to reduce the voltage ripple of a
ripple. For this reason, the additional ISUM ripple in TLVR TLVR design is to use more than one LC loop. Figure
designs translates directly to a larger output voltage 21 shows an example with two LC loops. The phase-
ripple. fire order for each phase is such that the ILC1 and ILC2
currents are 180 degrees out of phase, allowing the ILC1
An example in Figure 20 demonstrates the influence of
and ILC2 current ripple to cancel.
the converter duty cycle. The ILC ripple can still become
very small at certain duty cycles, when phases overlap

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VIN VIN
Power Loss and Efficiency
SW2
SW1
PWM1 PWM2 Figure 23 compares the power efficiency between a
multiphase buck converter and TLVR when designed

ISUM1
with the same component values. The curves are already
ISUM2
quite similar, but the TLVR design is a small amount
VIN VIN
lower (0.1%) in terms of efficiency.
SW4
SW3 While this plot is useful for demonstration purposes,
PWM11 PWM12 typically, multiphase buck and TLVR designs will not
have the same inductance values. The buck converter
will require a lower inductance value to meet the same
ILC1 ILC2 transient specifications, which further reduces its power
efficiency. In practice, when designing two converters to

Figure 21. Interleaved TLVR design. the same specifications, the multiphase buck and TLVR
converters have approximately equivalent efficiency. In
ILC1
ILC2
some cases, TLVR designs can have slightly higher
PWM1
efficiency.

PWM2 Two loss mechanisms differentiate the TLVR design from

the multiphase buck converter. Most obviously the LC
PWM3
loop losses are present only in TLVR designs. Earlier,
Equation 21 showed the RMS current in the LC loop,
PWM4
as a result of its current ripple. Thus, the losses in the
LC loop have a component of RMS conduction losses,
Time as well as core losses, which may be significant given
Figure 22. Two-loop interleaved TLVR waveforms. the high switching frequency of the LC. Equation 25
estimates the power losses in the LC loop:
Interleaving is also common in cases where space
constraints on the board layout prevent placing phases 2
PLc ≅ Irms L × RDCR, Lc + NTOTAL × RDCR, secondary (26)
c
near each other. Phases on each LC loop are co-located
+ Rrouting + Pcore Lc
with each other, but the LC loops may be separated by
some distance, sometimes even on different sides of Additionally, consider that the additional ripple from ILC
the load device. While less beneficial in terms of output will increase the RMS current in each power stage, and
voltage ripple, TLVR designs with asymmetric phase thus the conduction losses. Figure 24 demonstrates how
numbers on each LC loop are also possible. the addition of ILC increases the peak-to-peak current
ripple, ΔIPP, in the low-side switch of each phase. As the
ILC current ripple increases with lower phase numbers,
this additional component can become significant. That
is one reason why TLVR designs are typically reserved for
high-power, high-phase-count (greater than six phase)
designs.

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95%
TLVR It is also common to use dynamic phase shedding
Buck
94% (DPS) in high-phase-count designs to improve light-load

93%
efficiency. Switching a fewer number of phases when
the total output current is low enough to be supported
Efficiency

92% without all phases active reduces switching losses.

91%
Phases can be in one of three states: high-side MOSFET
on, low-side MOSFET off; high-side MOSFET off, low-
90%
side MOSFET on; or both MOSFETs off. Typically,
89% nonlinear control techniques add or drop phases quickly
0 50 100 150 200 250 300 350 400 450
Low-Side MOSFET Current (mA)
during load transient events, so the impact on the load
transient response is minimal. Figure 25 shows the
VIN = 12 V VOUT = 1.80 V
current flow in each state.
fSW = 600 kHz RLL = 0.5 mΩ
In a TLVR design, the LC loop continues to conduct
LM = LBUCK = 120 nH LC = 120 nH
current through the body-diode phases in the third state
Excludes PDN conduction losses (both MOSFETs off), which are not switching. There will
be additional power losses from nonswitching phases
Figure 23. Efficiency vs. output current.
caused by the voltage drop of the body diodes, Vdiode.

TLVR
Therefore, for phase shedding to make sense, the
Buck
switching losses saved by not switching a phase must
IPEAK be greater than that created by the body-diode losses.

IOUT . IOUT(avg) Equation 28 describes the power losses in nonswitching
phases:
IVALLEY

Pcond, HiZ = ILC rms ×Vdiode (28)

A measured plot of the same design with phase

–D)
shedding on and off, shown in Figure 26, demonstrates
Time
the TLVR design efficiency improvement at light load.
Figure 24. Addition of ILC to low-side metal-oxide semiconductor
field-effect transistor (MOSFET) current.

To understand this loss mechanism, Equation 27

expresses the relationship between the current ripple
and low-side MOSFET RMS current for a typical buck
converter design. An exact equation for the TLVR design
is more complex, but the buck converter equation
demonstrates the influence of ΔIPP.

ΔI 2
IRMS LSFET = IOUT × 1−D × 1 + 13 × 2 × PP
IOUT (27)

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VIN
ILC

Phase Multiplication
As power requirements continue to increase rapidly, it is
often necessary to design very high phase-count (more
VIN
than 16 phase) designs using controller devices that do
not have enough independent pulse-width modulation
(PWM) outputs to control each phase individually. It has
become common to phase double or phase multiply –
that is, to drive more than one power stage with the
VIN

same controller PWM output. This practice enables easy

scalability of multiphase designs – buck converter or
TLVR – to high power levels.
Phase
ON
OFF
Hi-Z
Figure 27 shows the connections of the LC loops in an
interleaved, phase-doubled TLVR design. Such a design
Figure 25. Dynamic phase shedding.
could, for example, extend a 12-phase design to 24 or
94%
36 phases, without requiring a different controller device.
92%

90%
For all phases (doubled or not) in the same LC loop,
the secondary sides are connected in series. The current
Efficiency

88%

86%
feedback lines from each phase (not shown in Figure
84%

82%
DPS 27) can be resistor-averaged for power stages with
Enabled
Disabled
80%
0 50 100 150 200 250 300 350 400
voltage-source-output current sensing, or simply added
Output Current (A)
for power stages with current-source-output current
VIN = 12 V VOUT = 1.80 V
sensing. It is possible to connect temperature sense
fSW = 90 kHz LM = LC = 100 nH outputs from each power stage (also not shown in Figure
8 phases Dual-side layout 27) together, regardless of which LC loop the power
stages are in.
TLVR CSD08860 (90-A SPS)

Figure 26. Efficiency vs. output current.

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VIN VIN
PWM1 PWM2

VIN VIN
PWM1 PWM2

VIN VIN
PWM11 PWM12

VIN VIN
PWM11 PWM12

Figure 27. Interleaved phase-doubling TLVR topology.

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PCB Layout Placing the phases as close to each other as possible

saves space. However, the phase-fire order is not
Figure 28 shows an example circuit board layout and
sequential. Changing the phase-fire order helps to
component placement for a TLVR design powertrain.
reduce crosstalk issues between phases by spreading
This design uses 4-mm-by-6-mm power-stage devices
their switching nodes out from each other in the time
and co-layout-compatible TLVR inductors, enabling
domain.
similar placement to a typical multiphase buck design.
Figure 29 is a zoomed-out example of a high-phase-
The LC loop runs through the middle of the primary-side
count layout design that uses two LC loops, placing
pads. The secondary-winding pads of the TLVR inductor
doubled phases next to one another and in the same LC
enable the running of this loop to occur on the top layer,
loop. The phases and LC in each loop follow the example
without requiring many vias or wide traces. Because the
in Figure 28. The loops are placed on opposite sides
LC loop can conduct high current during transient events,
(sometimes referred to as cardinal directions, east and
the traces are as wide as the clearance rules allow, but
west) of the load to minimize the PDN routing between
multilayer planes are not required. Inner ground planes
the output of each inductor and the pins of the load
close the LC loop from one side of the powertrain to
device. Two sides of the load device remain open, on the
another. Sensitive circuitry should have a wide clearance
top side, for high-frequency signal routing, as needed by
to the LC, and LC loop traces to avoid noise coupling and
the design.
interference.
Decoupling capacitors (not shown in Figure 29) are under
The LC inductor is placed to the side of the power
and, if possible, inside the footprint of the load device.
stages. Because the LC can be subjected to voltages
There are placeholders for polymer bulk capacitors, but
higher than VIN and will be switching at a high frequency,
some designs will not need them. Placing the controller
high transient voltages and electromagnetic interference
device far away from the powertrain avoids noise issues,
may become a concern as well. One possibility to
with long traces connecting it to the power stages
mitigate this (not shown in Figure 28) is to split the LC
in each LC loop. As with any high-power design, it’s
into two physical inductors – each with an inductance
important to maintain good signal integrity on the PWM
of one-half LC – and place them symmetrically on either
outputs, current-sense inputs and voltage-sense lines for
side of the power stages. This lowers the maximum
the controller.
voltage across each LC during transient events.

Lc pad is
high voltage
( 50V+)
Ph 1 Ph 3 Ph 5 Ph 7 Ph 9 Ph 2 Ph 4 Ph 6 Ph 8 Ph 10
Lc
L1 L3 L5 L7 L9 L2 L4 L6 L8 L10

Figure 28. Example TLVR powertrain layout.

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Figure 29. Example phase-doubled interleaved TLVR layout.

TLVR-Optimized Components the DCAP+ control architecture, a form of constant

on-time valley current-mode control. They may still
Recently, semiconductor vendors such as Texas
require second-order optimizations such as new gain and
Instruments (TI) have begun to offer multiphase
compensation parameters suited to the TLVR powertrain.
controllers and power stages optimized for TLVR
Higher-strength PWM output drivers are often needed
designs.
to support longer distances between multiple LC
Smart power stages optimized for TLVR designs require loops while maintaining good signal integrity. The
higher-bandwidth current-sensing architectures because implementation of a new protection mechanism for an
of the high-speed nature of the TLVR topology. The IOUT open or shorted LC loop should ease manufacturability
pin waveform of a TI smart power stage, for example, concerns.
tracks even the induced current ripple from the LC loop in
Table 3 and Table 4 summarize TLVR-optimized
a TLVR design. This requires current-sensing bandwidth
components available from TI at the time of this writing,
at least an order of magnitude higher than the fSW of the
with more under development.
design on a per-phase basis. The TLVR topology also
increases the bandwidth requirements for high-speed Package size
Part number Current rating (mm) IMON
overcurrent protection.
CSD95440 80-A peak, 40-A RMS 5×6 Voltage

Smart power stages optimized for TLVR designs must CSD95510 90-A peak, 50-A RMS 4×6 Voltage
CSD95560 90-A peak, 50-A RMS 4×6 Current
also be rated for increasingly high RMS currents and be
CSD95520 60-A peak, 30-A RMS 4×5 Voltage
able to support peak current pulses nearly two times
CSD95570 60-A peak, 30-A RMS 4×5 Current
their RMS rating for short durations, thermally as well as
Table 3. TLVR-optimized smart power stages.
electrically.

Controllers generally do not need re-architecting. TLVR

designs use the same control schemes designed for
multiphase buck designs. TI controllers continue to use

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Part number Phases Package size (mm) Interface

is the design that must change to meet the load
TPS53685 8 5×5 AMD
TPS536C5 12 6×6 AMD
requirements. As we’ve discussed, TLVR inductors
TPS53689T 8 5×5 Intel are footprint-compatible with standard single-winding
TPS536C9T 12 6×6 Intel inductors, enabling the testing of both designs with the
Table 4. TLVR-optimized controllers. same physical PCB layout.

Table 5 summarizes one such example. The TLVR design

Example Side-by-Side Design met the same specifications as the multiphase buck
The examples in earlier sections demonstrated the converter design with almost no impact on overall power
difference between a multiphase buck design and a losses, and an over 40% reduction in COUT required.
TLVR design with the same external components. This
Figure 30 and Figure 31 illustrate the worst-case
comparison is not often practical, however, because
overshoot waveforms for this design.
the requirements of the load do not change – it

Parameter Multiphase buck TLVR

Controller/standby power supply TPS53689, CSD95440
Input voltage (VIN) 12 V
Output voltage (VOUT) 1.8 V
Minimum output voltage (VMIN) 1.59 V
Maximum output voltage (VMAX) 1.85 V
Number of phases 8
Switching frequency 900 kHz
Load step 60 A-430 A, 1,000 A/µs, 1 kHz-1 MHz
Load line 0.5 mΩ
LM/LBUCK 70 nH 120 nH
LC N/A 100 nH
CBULK (polymer) 5 × 470 µF 0 × 470 µF
Multilayer ceramic capacitors (MLCCs) 80 × 22 µF, 0402 80 × 22 µF, 0402
45 × 47 µF, 0805 56 × 47 µF, 0603
15 × 100 µF, 0805 0 × 100 µF, 0805
8 × 0.1 µF, 0402 8 × 0.1 µF, 0402
Peak power efficiency (ηPEAK) 94.0% 93.9%
Full load efficiency (ηFull) 88.1% 88.1%
VMIN measured (worst case) 1.600 V (+10-mV margin), dominated by RLL 1.600 V (+10-mV margin), dominated by RLL
VMAX measured (worst case) 1.846 V (+4-mV margin) 1.839 V (+11-mV margin)
Total output capacitance (COUT) 7.7 mF 4.4 mF

Table 5. Design parameters.

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VMAX = 1.846 V D = 20% VMAX = 1.839 V D = 10%

fSW = 330 kHz fSW = 190 kHz

Figure 30. Worst-case overshoot (multiphase buck converter). Figure 31. Worst-case overshoot (TLVR).

Summary • Dong, Yan. 2009. “Investigation of Multiphase

Coupled-Inductor Buck Converters in Point-of-Load
The TLVR topology is an evolution of the traditional
Applications.” Ph.D. dissertation, Virginia Polytechnic
multiphase buck converter design for high-phase-
Institute and State University.
count, low-voltage nonisolated designs. It offers
significant output capacitor savings and has become • Qiu, Yang. 2007. “Coupled Inductors for Power

increasingly popular. In this paper, we introduced the Supplies: Advantages and Compromises.” EETimes,

concepts, operating principles, trade-offs, results from June 2007.

example designs, and practical considerations for TLVR • Lu, Zengyi, and Wei Chen. “Multi-Phase Inductor
designers. Coupling Scheme with Balancing Winding in VRM
Applications.” Published in Proceedings of the 22nd
Additional Resources Annual IEEE Applied Power Electronics Conference
• Technical Disclosure Commons. “Fast Multi-Phase and Exposition, Feb. 25-March 1, 2007, pp. 680-684.
Trans-Inductor Voltage Regulator.” Technical • Zhu, Feiyang. “Multi-Phase Coupled Inductor Analysis
Disclosure Commons Defensive Publications Series, for Multi-Phase Voltage Regulators.” Center for Power
May 9, 2019. Electronics Systems PMC Review, June 2021.
• Radhakrishnan, Kaladhar, and Jonathan Douglas, • Jiang, Shuai, Xin Li, Mobashar Yazdani, and
“Microprocessor Power Delivery Challenges.” APEC Chee Chung. “Driving 48V Technology Innovations
2022, March 22, 2022. Forward – Hybrid Converters and Trans-Inductor
• Parisi, Carmen. “Multiphase Buck Design From Start Voltage Regulator (TLVR).” Published in 34th Annual
to Finish (Part 1).” Texas Instruments application IEEE Applied Power Electronics Conference and
report, literature No. SLVA882B, April 2021. Exposition, March 15-19, 2020.
• Erickson, Robert W., and Dragan Maksimovic. 2020.
“Fundamentals of Power Electronics, Third Edition.”
New York: Springer AG.

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