Version Date

V1.0 7/29/2013
Initial Release
 Type 10 Rev. 2.1 Type 6 Rev. 2.1
Connector Model
Min / Max Min / Max
System I/O
A-B PCI Express Lanes 0 - 5 1/4 1/6
A-B LVDS Channel A 0/1 0/1
A-B eDP on LVDS Channel A 0/1 0/1
A-B LVDS Channel B NA 0/1
A-B VGA Port NA 0/1
A-B TV-Out NA NA
A-B Display Port InterfaceDDI 0 0/1 NA
A-B Serial Ports 1 -2 0/2 0/2
A-B CAN interface on SER1 0/1 0/1
A-B SATA / SAS Ports 1/2 1/4
A-B USB 3.0 Ports 0/2 NA
A-B AC’97 / HDA Digital Interface 0/1 0/1
A-B USB 2.0 Ports 4/8 4/8
A-B USB Client 0/1 0/1
A-B LAN 0 (10/100Base-T min) 1/1 1/1
A-B Express Card Support 0/2 1/2
A-B LPC Bus 1/1 1/1
A-B SPI 1/2 1/2
PCI Express Lanes 16-31 NA 0 / 16

PCI Express Graphics (PEG) NA 0/1

C-D SDVO Channels 1-2 (muxed on PEG) NA NA
PCI Express Lanes 6-15 NA 0/2
DVO Channels NA NA
HDMI/DVI-D Channels NA NA
DisplayPort Channels NA NA
C-D PCI Bus - 32 Bit NA NA
C-D PATA Port NA NA
C-D DisplayPort InterfaceDDI 1-3 NA 0/3
C-D USB 3.0 Ports NA 0/4
System Management
SDIO (muxed on GPIO) 0/1 0/1
A-B General Purpose Inputs 4/4 4/4
General Purpose Outputs 4/4 4/4
A-B SMBus 1/1 1/1
A-B I2C 1/1 1/1
A-B Watch Dog Timer 0/1 0/1
A-B Speaker Out 1/1 1/1
A-B External BIOS ROM support 0/2 0/2
A-B Reset Functions 1/1 1/1
Power Management
A-B Thermal Protection 0/1 0/1
A-B Battery Low Alarm 0/1 0/1
A-B Suspend NA NA
A-B Wake NA NA
A-B Suspend/Wake 0/3 0/3
A-B Power Button Support 1/1 1/1
A-B Power Good 1/1 1/1
A-B VCC_5V_SBY Contacts 4/4 4/4
A-B Sleep Inputs 0/1 0/1
A-B Lid Inputs 0/1 0/1
A-B Fan Control Signals 0/2 0/2
A-B Trusted Platform Modules 0/1 0/1
Power
A-B VCC_12V Contacts
COM Express® Required and Optional features are 12 / 12 12 / 12
C-D
summarized inVCC_12V Contacts
the following table. The features N/A 12 / 12
identified as Minimum (Min.) shall be implemented by all
modules. Features identified up to Maximum (Max) may
be additionally implemented by a module.
Change Key: Green = Generic R2.x, Orange = Type
10 only, Violet = Type 10 & Type 6 only, Red = Type
6 only
 SOM-5894 A101-1
Type 6 Rev. 2.1

6(LynxPoint-M)
1(LynxPoint-M)
0
1(LynxPoint-M)
1(LynxPoint-M)
NA
NA
2(IT8518E)
0
4(LynxPoint-M)
NA
1(LynxPoint-M)
8(LynxPoint-M)
0
1(I217)
2(IT8518E)
1(LynxPoint-M)
1(LynxPoint-M)
16(Haswell-Mbl+non
ECC)
1(Haswell-Mbl+non
ECC)
NA
1(LynxPoint-M)
NA
NA
NA
NA
NA
3(LynxPoint-M)
4(LynxPoint-M)

0
4(IT8518E)
4(IT8518E)
1(LynxPoint-M)
1(IT8518E)
1(IT8518E)
1(LynxPoint-M)
2(LynxPoint-M)
1(LynxPoint-M)

1(IT8518E)
1(IT8518E)
NA
NA
3(IT8518E/LynxPoint-M)
1(IT8518E)
1(IT8518E)
4
1(IT8518E)
 1(IT8518E)
2(IT8518E)
1(SLB9635TT1.2)

12
12
Row A Type 10 Rev. 2.1 Type 6 Rev. 2.1
A1 GND (FIXED) Option GND (FIXED)
A2 GBE0_MDI3- GBE0_MDI3-
A3 GBE0_MDI3+ GBE0_MDI3+
A4 GBE0_LINK100# GBE0_LINK100#
A5 GBE0_LINK1000# GBE0_LINK1000#
A6 GBE0_MDI2- GBE0_MDI2-
A7 GBE0_MDI2+ GBE0_MDI2+
A8 GBE0_LINK# GBE0_LINK#
A9 GBE0_MDI1- GBE0_MDI1-
A10 GBE0_MDI1+ GBE0_MDI1+
A11 GND (FIXED) GND (FIXED)
A12 GBE0_MDI0- GBE0_MDI0-
A13 GBE0_MDI0+ GBE0_MDI0+
A14 GBE0_CTREF GBE0_CTREF
A15 SUS_S3# SUS_S3#
A16 SATA0_TX+ SATA0_TX+
A17 SATA0_TX- SATA0_TX-
A18 SUS_S4# SUS_S4#
A19 SATA0_RX+ SATA0_RX+
A20 SATA0_RX- SATA0_RX-
A21 GND (FIXED) GND (FIXED)
A22 USB_SSRX0- SATA2_TX+
A23 USB_SSRX0+ SATA2_TX-
A24 SUS_S5# SUS_S5#
A25 USB_SSRX1- SATA2_RX+
A26 USB_SSRX1+ SATA2_RX-
A27 BATLOW# BATLOW#
A28 (S)ATA_ACT# (S)ATA_ACT#
A29 AC/HDA_SYNC AC/HDA_SYNC
A30 AC/HDA_RST# AC/HDA_RST#
A31 GND (FIXED) GND (FIXED)
A32 AC/HDA_BITCLK AC/HDA_BITCLK
A33 AC/HDA_SDOUT AC/HDA_SDOUT
A34 BIOS_DIS0# BIOS_DIS0#
A35 THRMTRIP# THRMTRIP#
A36 USB6- USB6-
A37 USB6+ USB6+
A38 USB_6_7_OC# USB_6_7_OC#
A39 USB4- USB4-
A40 USB4+ USB4+
A41 GND (FIXED) GND (FIXED)
A42 USB2- USB2-
A43 USB2+ USB2+
A44 USB_2_3_OC# USB_2_3_OC#
A45 USB0- USB0-
A46 USB0+ USB0+
A47 VCC_RTC VCC_RTC
A48 EXCD0_PERST# EXCD0_PERST#
A49 EXCD0_CPPE# EXCD0_CPPE#
A50 LPC_SERIRQ LPC_SERIRQ
A51 GND (FIXED) GND (FIXED)
A52 RSVD PCIE_TX5+
A53 RSVD PCIE_TX5-
A54 GPI0 SDIO_DAT0 GPI0
A55 RSVD PCIE_TX4+
A56 RSVD PCIE_TX4-
A57 GND GND
A58 PCIE_TX3+ PCIE_TX3+
A59 PCIE_TX3- PCIE_TX3-
A60 GND (FIXED) GND (FIXED)
A61 PCIE_TX2+ PCIE_TX2+
A62 PCIE_TX2- PCIE_TX2-
A63 GPI1 SDIO_DAT1 GPI1
A64 PCIE_TX1+ PCIE_TX1+
A65 PCIE_TX1- PCIE_TX1-
A66 GND GND
A67 GPI2 SDIO_DAT2 GPI2
A68 PCIE_TX0+ PCIE_TX0+
A69 PCIE_TX0- PCIE_TX0-
A70 GND (FIXED) GND (FIXED)
A71 LVDS_A0+ eDP_TX2+ LVDS_A0+
A72 LVDS_A0- eDP_TX2- LVDS_A0-
A73 LVDS_A1+ eDP_TX1+ LVDS_A1+
A74 LVDS_A1- eDP_TX1- LVDS_A1-
A75 LVDS_A2+ eDP_TX0+ LVDS_A2+
A76 LVDS_A2- eDP_TX0- LVDS_A2-
A77 LVDS_VDD_EN eDP_VDD_EN LVDS_VDD_EN
A78 LVDS_A3+ LVDS_A3+
A79 LVDS_A3- LVDS_A3-
A80 GND (FIXED) GND (FIXED)
A81 LVDS_A_CK+ eDP_TX3+ LVDS_A_CK+
A82 LVDS_A_CK- eDP_TX3- LVDS_A_CK-
A83 LVDS_I2C_CK eDP_AUX+ LVDS_I2C_CK
A84 LVDS_I2C_DAT eDP_AUX- LVDS_I2C_DAT
A85 GPI3 SDIO_DAT3 GPI3
A86 RSVD RSVD
A87 eDP_HPD eDP_HPD
A88 PCIE_CLK_REF+ PCIE_CLK_REF+
A89 PCIE_CLK_REF- PCIE_CLK_REF-
A90 GND (FIXED) GND (FIXED)
A91 SPI_POWER SPI_POWER
A92 SPI_MISO SPI_MISO
A93 GPO0 SDIO_CLK GPO0
A94 SPI_CLK SPI_CLK
A95 SPI_MOSI SPI_MOSI
A96 TPM_PP TPM_PP
A97 TYPE10# TYPE10#
A98 SER0_TX SER0_TX
A99 SER0_RX SER0_RX
A100 GND (FIXED) GND (FIXED)
A101 SER1_TX CAN_TX SER1_TX
A102 SER1_RX CAN_RX SER1_RX
A103 LID# LID#
A104 VCC_12V VCC_12V
A105 VCC_12V VCC_12V
A106 VCC_12V VCC_12V
 A107 VCC_12V VCC_12V
A108 VCC_12V VCC_12V
A109 VCC_12V VCC_12V
A110
should GND (FIXED) GND (FIXED)
be no
connect.
Type 6 Rev. 2.1 I/F SOM-5894 A101-1
Option PWR GND (FIXED)
GBE GBE0_MDI3-
GBE GBE0_MDI3+
GBE GBE0_LINK100#
GBE GBE0_LINK1000#
GBE GBE0_MDI2-
GBE GBE0_MDI2+
GBE GBE0_LINK#
GBE GBE0_MDI1-
GBE GBE0_MDI1+
PWR GND (FIXED)
GBE GBE0_MDI0-
GBE GBE0_MDI0+
GBE N/A
PSM SUS_S3#
SATA0 SATA0_TX+
SATA0 SATA0_TX-
PSM SUS_S4#
SATA0 SATA0_RX+
SATA0 SATA0_RX-
PWR GND (FIXED)
SATA2 SATA2_TX+
SATA2 SATA2_TX-
PSM SUS_S5#
SATA2 SATA2_RX+
SATA2 SATA2_RX-
PSM BATLOW#
SATA (S)ATA_ACT#
AC97 AC/HDA_SYNC
AC97 AC/HDA_RST#
PWR GND (FIXED)
AC97 AC/HDA_BITCLK
AC97 AC/HDA_SDOUT
MISC BIOS_DIS0#
PSM THRMTRIP#
USB6 USB6-
USB6 USB6+
USB_6_7 USB_6_7_OC#
USB4 USB4-
USB4 USB4+
PWR GND (FIXED)
USB2 USB2-
USB2 USB2+
USB_2_3 USB_2_3_OC#
USB0 USB0-
USB0 USB0+
PWR VCC_RTC
EXCD0 EXCD0_PERST#
EXCD0 EXCD0_CPPE#
LPC LPC_SERIRQ
PWR GND (FIXED)
PCIE PCIE_TX5+
PCIE PCIE_TX5-
SDIO_DAT0 GPIO GPI0
PCIE PCIE_TX4+
PCIE PCIE_TX4-
PWR GND
PCIE PCIE_TX3+
PCIE PCIE_TX3-
PWR GND (FIXED)
PCIE PCIE_TX2+
PCIE PCIE_TX2-
SDIO_DAT1 GPIO GPI1
PCIE PCIE_TX1+
PCIE PCIE_TX1-
PWR GND
SDIO_DAT2 GPIO GPI2
PCIE PCIE_TX0+
PCIE PCIE_TX0-
PWR GND (FIXED)
eDP_TX2+ LVDS LVDS_A0+
eDP_TX2- LVDS LVDS_A0-
eDP_TX1+ LVDS LVDS_A1+
eDP_TX1- LVDS LVDS_A1-
eDP_TX0+ LVDS LVDS_A2+
eDP_TX0- LVDS LVDS_A2-
eDP_VDD_EN LVDS LVDS_VDD_EN
LVDS LVDS_A3+
LVDS LVDS_A3-
PWR GND (FIXED)
eDP_TX3+ LVDS LVDS_A_CK+
eDP_TX3- LVDS LVDS_A_CK-
eDP_AUX+ LVDS LVDS_I2C_CK
eDP_AUX- LVDS LVDS_I2C_DAT
SDIO_DAT3 GPIO GPI3
RSVD (KBD_RST# if
RSVD
R240 stuffed)
RSVD eDP_HPD
PCIE PCIE_CLK_REF+
PCIE PCIE_CLK_REF-
PWR GND (FIXED)
SPI SPI_POWER
SPI SPI_MISO
SDIO_CLK GPIO GPO0
SPI SPI_CLK
SPI SPI_MOSI
MISC TPM_PP
MTD TYPE10#
GPSI SER0_TX
GPSI SER0_RX
PWR GND (FIXED)
CAN_TX GPSI SER1_TX
CAN_RX GPSI SER1_RX
PSM LID#
PWR VCC_12V
PWR VCC_12V
PWR VCC_12V
PWR VCC_12V
PWR VCC_12V
PWR VCC_12V
PWR GND (FIXED)
Row B Type 10 Rev. 2.1 Type 6 Rev. 2.1
B1 GND (FIXED) Option GND (FIXED)
B2 GBE0_ACT# GBE0_ACT#
B3 LPC_FRAME# LPC_FRAME#
B4 LPC_AD0 LPC_AD0
B5 LPC_AD1 LPC_AD1
B6 LPC_AD2 LPC_AD2
B7 LPC_AD3 LPC_AD3
B8 LPC_DRQ0# LPC_DRQ0#
B9 LPC_DRQ1# LPC_DRQ1#
B10 LPC_CLK LPC_CLK
B11 GND (FIXED) GND (FIXED)
B12 PWRBTN# PWRBTN#
B13 SMB_CK SMB_CK
B14 SMB_DAT SMB_DAT
B15 SMB_ALERT# SMB_ALERT#
B16 SATA1_TX+ SATA1_TX+
B17 SATA1_TX- SATA1_TX-
B18 SUS_STAT# SUS_STAT#
B19 SATA1_RX+ SATA1_RX+
B20 SATA1_RX- SATA1_RX-
B21 GND (FIXED) GND (FIXED)
B22 USB_SSTX0- SATA3_TX+
B23 USB_SSTX0+ SATA3_TX-
B24 PWR_OK PWR_OK
B25 USB_SSTX1- SATA3_RX+
B26 USB_SSTX1+ SATA3_RX-
B27 WDT WDT
B28 AC/HDA_SDIN2 AC/HDA_SDIN2
B29 AC/HDA_SDIN1 AC/HDA_SDIN1
B30 AC/HDA_SDIN0 AC/HDA_SDIN0
B31 GND (FIXED) GND (FIXED)
B32 SPKR SPKR
B33 I2C_CK I2C_CK
B34 I2C_DAT I2C_DAT
B35 THRM# THRM#
B36 USB7- USB7-
B37 USB7+ USB7+
B38 USB_4_5_OC# USB_4_5_OC#
B39 USB5- USB5-
B40 USB5+ USB5+
B41 GND (FIXED) GND (FIXED)
B42 USB3- USB3-
B43 USB3+ USB3+
B44 USB_0_1_OC# USB_0_1_OC#
B45 USB1- USB1-
B46 USB1+ USB1+
B47 EXCD1_PERST# EXCD1_PERST#
B48 EXCD1_CPPE# EXCD1_CPPE#
B49 SYS_RESET# SYS_RESET#
B50 CB_RESET# CB_RESET#
B51 GND (FIXED) GND (FIXED)
B52 RSVD PCIE_RX5+
B53 RSVD PCIE_RX5-
B54 GPO1 SDIO_CMD GPO1
B55 RSVD PCIE_RX4+
B56 RSVD PCIE_RX4-
B57 GPO2 SDIO_WP GPO2
B58 PCIE_RX3+ PCIE_RX3+
B59 PCIE_RX3- PCIE_RX3-
B60 GND (FIXED) GND (FIXED)
B61 PCIE_RX2+ PCIE_RX2+
B62 PCIE_RX2- PCIE_RX2-
B63 GPO3 SDIO_CD# GPO3
B64 PCIE_RX1+ PCIE_RX1+
B65 PCIE_RX1- PCIE_RX1-
B66 WAKE0# WAKE0#
B67 WAKE1# WAKE1#
B68 PCIE_RX0+ PCIE_RX0+
B69 PCIE_RX0- PCIE_RX0-
B70 GND (FIXED) GND (FIXED)
B71 DDI0_PAIR0+ LVDS_B0+
B72 DDI0_PAIR0- LVDS_B0-
B73 DDI0_PAIR1+ LVDS_B1+
B74 DDI0_PAIR1- LVDS_B1-
B75 DDI0_PAIR2+ LVDS_B2+
B76 DDI0_PAIR2- LVDS_B2-
B77 DDI0_PAIR4+ LVDS_B3+
B78 DDI0_PAIR4- LVDS_B3-
B79 LVDS_BKLT_EN eDP_BKLT_EN LVDS_BKLT_EN
B80 GND (FIXED) GND (FIXED)
B81 DDI0_PAIR3+ LVDS_B_CK+
B82 DDI0_PAIR3- LVDS_B_CK-
B83 LVDS_BKLT_CTRL eDP_BKLT_CTRL LVDS_BKLT_CTRL
B84 VCC_5V_SBY VCC_5V_SBY
B85 VCC_5V_SBY VCC_5V_SBY
B86 VCC_5V_SBY VCC_5V_SBY
B87 VCC_5V_SBY VCC_5V_SBY
B88 BIOS_DIS1# BIOS_DIS1#
B89 DDI0_HPD VGA_RED
B90 GND (FIXED) GND (FIXED)
B91 DDI0_PAIR5+ VGA_GRN
B92 DDI0_PAIR5- VGA_BLU
B93 DDI0_PAIR6+ VGA_HSYNC
B94 DDI0_PAIR6- VGA_VSYNC
B95 DDI0_DDC_AUX_SEL VGA_I2C_CK
B96 USB_HOST_PRSNT VGA_I2C_DAT
B97 SPI_CS# SPI_CS#
B98 DDI0_CTRLCLK_AUX+ RSVD
B99 DDI0_CTRLDATA_AUX- RSVD
B100 GND (FIXED) GND (FIXED)
B101 FAN_PWMOUT FAN_PWMOUT
B102 FAN_TACHIN FAN_TACHIN
B103 SLEEP# SLEEP#
B104 VCC_12V VCC_12V
B105 VCC_12V VCC_12V
B106 VCC_12V VCC_12V
B107 VCC_12V VCC_12V
 B108 VCC_12V VCC_12V
B109 VCC_12V VCC_12V
B110
should GND (FIXED) GND (FIXED)
be no
connect.
Type 6 Rev. 2.1 I/F SOM-5894 A101-1
Option PWR GND (FIXED)
GBE GBE0_ACT#
LPC LPC_FRAME#
LPC LPC_AD0
LPC LPC_AD1
LPC LPC_AD2
LPC LPC_AD3
LPC LPC_DRQ0#
LPC LPC_DRQ1#
LPC LPC_CLK
PWR GND (FIXED)
PSM PWRBTN#
PSM SMB_CK
PSM SMB_DAT
PSM SMB_ALERT#
SATA1 SATA1_TX+
SATA1 SATA1_TX-
PSM SUS_STAT#
SATA1 SATA1_RX+
SATA1 SATA1_RX-
PWR GND (FIXED)
SATA3 SATA3_TX+
SATA3 SATA3_TX-
PSM PWR_OK
SATA3 SATA3_RX+
SATA3 SATA3_RX-
MISC WDT
AC97 AC/HDA_SDIN2
AC97 AC/HDA_SDIN1
AC97 AC/HDA_SDIN0
PWR GND (FIXED)
MISC SPKR
MISC I2C_CK
MISC I2C_DAT
PSM THRM#
USB7 USB7-
USB7 USB7+
USB_4_5 USB_4_5_OC#
USB5 USB5-
USB5 USB5+
PWR GND (FIXED)
USB3 USB3-
USB3 USB3+
USB_0_1 USB_0_1_OC#
USB1 USB1-
USB1 USB1+
EXCD1 EXCD1_PERST#
EXCD1 EXCD1_CPPE#
PSM SYS_RESET#
PSM CB_RESET#
PWR GND (FIXED)
PCIE PCIE_RX5+
PCIE PCIE_RX5-
SDIO_CMD GPIO GPO1
PCIE PCIE_RX4+
PCIE PCIE_RX4-
SDIO_WP GPIO GPO2
PCIE PCIE_RX3+
PCIE PCIE_RX3-
PWR GND (FIXED)
PCIE PCIE_RX2+
PCIE PCIE_RX2-
SDIO_CD# GPIO GPO3
PCIE PCIE_RX1+
PCIE PCIE_RX1-
PSM WAKE0#
PSM WAKE1#
PCIE PCIE_RX0+
PCIE PCIE_RX0-
PWR GND (FIXED)
DDI0/LVDS LVDS_B0+
DDI0/LVDS LVDS_B0-
DDI0/LVDS LVDS_B1+
DDI0/LVDS LVDS_B1-
DDI0/LVDS LVDS_B2+
DDI0/LVDS LVDS_B2-
DDI0/LVDS LVDS_B3+
DDI0/LVDS LVDS_B3-
eDP_BKLT_EN LVDS LVDS_BKLT_EN
PWR GND (FIXED)
DDI0/LVDS LVDS_B_CK+
DDI0/LVDS LVDS_B_CK-
eDP_BKLT_CTRL LVDS LVDS_BKLT_CTRL
PWR VCC_5V_SBY
PWR VCC_5V_SBY
PWR VCC_5V_SBY
PWR VCC_5V_SBY
MISC BIOS_DIS1#
DDI0/VGA VGA_RED
PWR GND (FIXED)
DDI0/VGA VGA_GRN
DDI0/VGA VGA_BLU
DDI0/VGA VGA_HSYNC
DDI0/VGA VGA_VSYNC
DDI0/VGA VGA_I2C_CK
DDI0/VGA VGA_I2C_DAT
SPI SPI_CS#
DDI0 RSVD
DDI0 RSVD
PWR GND (FIXED)
PSM FAN_PWMOUT
PSM FAN_TACHIN
PSM SLEEP#
PWR VCC_12V
PWR VCC_12V
PWR VCC_12V
PWR VCC_12V
PWR VCC_12V
PWR VCC_12V
PWR GND (FIXED)
Row C Type 2 Rev. 2.0 Type 6 Rev. 2.0
C1 GND (FIXED) GND (FIXED) SDVO
C2 IDE_D7 GND
C3 IDE_D6 USB_SSRX0-
C4 IDE_D3 USB_SSRX0+
C5 IDE_D15 GND
C6 IDE_D8 USB_SSRX1-
C7 IDE_D9 USB_SSRX1+
C8 IDE_D2 GND
C9 IDE_D13 USB_SSRX2-
C10 IDE_D1 USB_SSRX2+
C11 GND (FIXED) GND (FIXED)
C12 IDE_D14 USB_SSRX3-
C13 IDE_IORDY USB_SSRX3+
C14 IDE_IOR# GND
C15 PCI_PME# DDI1_PAIR6+ SDVO1_FLDSTALL+
C16 PCI_GNT2# DDI1_PAIR6- SDVO1_FLDSTALL-
C17 PCI_REQ2# RSVD
C18 PCI_GNT1# RSVD
C19 PCI_REQ1# PCIE_RX6+
C20 PCI_GNT0# PCIE_RX6-
C21 GND (FIXED) GND (FIXED)
C22 PCI_REQ0# PCIE_RX7+
C23 PCI_RESET# PCIE_RX7-
C24 PCI_AD0 DDI1_HPD
C25 PCI_AD2 DDI1_PAIR4 + SDVO1_INT+
C26 PCI_AD4 DDI1_PAIR4- SDVO1_INT-
C27 PCI_AD6 RSVD
C28 PCI_AD8 RSVD
C29 PCI_AD10 DDI1_PAIR5+ SDVO1_TVCLKIN+
C30 PCI_AD12 DDI1_PAIR5- SDVO1_TVCLKIN-
C31 GND (FIXED) GND (FIXED)
C32 PCI_AD14 DDI2_CTRLCLK_AUX+
C33 PCI_C/BE1# DDI2_CTRLDATA_AUX-
C34 PCI_PERR# DDI2_DDC_AUX_SEL
C35 PCI_LOCK# RSVD
C36 PCI_DEVSEL# DDI3_CTRLCLK_AUX+
C37 PCI_IRDY# DDI3_CTRLDATA_AUX-
C38 PCI_C/BE2# DDI3_DDC_AUX_SEL
C39 PCI_AD17 DDI3_PAIR0+
C40 PCI_AD19 DDI3_PAIR0-
C41 GND (FIXED) GND (FIXED)
C42 PCI_AD21 DDI3_PAIR1+
C43 PCI_AD23 DDI3_PAIR1-
C44 PCI_C/BE3# DDI3_HPD
C45 PCI_AD25 RSVD
C46 PCI_AD27 DDI3_PAIR2+
C47 PCI_AD29 DDI3_PAIR2-
C48 PCI_AD31 RSVD
C49 PCI_IRQA# DDI3_PAIR3+
C50 PCI_IRQB# DDI3_PAIR3-
C51 GND (FIXED) GND (FIXED)
C52 PEG_RX0+ PEG_RX0+
C53 PEG_RX0- PEG_RX0-
C54 TYPE0# TYPE0#
C55 PEG_RX1+ PEG_RX1+
C56 PEG_RX1- PEG_RX1-
C57 TYPE1# TYPE1#
C58 PEG_RX2+ PEG_RX2+
C59 PEG_RX2- PEG_RX2-
C60 GND (FIXED) GND (FIXED)
C61 PEG_RX3+ PEG_RX3+
C62 PEG_RX3- PEG_RX3-
C63 RSVD RSVD
C64 RSVD RSVD
C65 PEG_RX4+ PEG_RX4+
C66 PEG_RX4- PEG_RX4-
C67 RSVD RSVD
C68 PEG_RX5+ PEG_RX5+
C69 PEG_RX5- PEG_RX5-
C70 GND (FIXED) GND (FIXED)
C71 PEG_RX6+ PEG_RX6+
C72 PEG_RX6- PEG_RX6-
C73 SDVO_DATA GND
C74 PEG_RX7+ PEG_RX7+
C75 PEG_RX7- PEG_RX7-
C76 GND GND
C77 RSVD RSVD
C78 PEG_RX8+ PEG_RX8+
C79 PEG_RX8- PEG_RX8-
C80 GND (FIXED) GND (FIXED)
C81 PEG_RX9+ PEG_RX9+
C82 PEG_RX9- PEG_RX9-
C83 RSVD RSVD
C84 GND GND
C85 PEG_RX10+ PEG_RX10+
C86 PEG_RX10- PEG_RX10-
C87 GND GND
C88 PEG_RX11+ PEG_RX11+
C89 PEG_RX11- PEG_RX11-
C90 GND (FIXED) GND (FIXED)
C91 PEG_RX12+ PEG_RX12+
C92 PEG_RX12- PEG_RX12-
C93 GND GND
C94 PEG_RX13+ PEG_RX13+
C95 PEG_RX13- PEG_RX13-
C96 GND GND
C97 RSVD RSVD
C98 PEG_RX14+ PEG_RX14+
C99 PEG_RX14- PEG_RX14-
C100 GND (FIXED) GND (FIXED)
C101 PEG_RX15+ PEG_RX15+
C102 PEG_RX15- PEG_RX15-
C103 GND GND
C104 VCC_12V VCC_12V
C105 VCC_12V VCC_12V
C106 VCC_12V VCC_12V
C107 VCC_12V VCC_12V
C108 VCC_12V VCC_12V
C109 VCC_12V VCC_12V
C110 GND (FIXED) GND (FIXED)
RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.
Type 6 Rev. 2.0 I/F SOM-5894 A101-1
DP HDMI/DVI PWR GND (FIXED)
IDE/PWR GND
IDE/USB USB_SSRX0-
IDE/USB USB_SSRX0+
IDE/PWR GND
IDE/USB USB_SSRX1-
IDE/USB USB_SSRX1+
IDE/PWR GND
IDE/USB USB_SSRX2-
IDE/USB USB_SSRX2+
PWR GND (FIXED)
IDE/USB USB_SSRX3-
IDE/USB USB_SSRX3+
IDE/PWR GND
PCI/DDI1 N/A
PCI/DDI1 N/A
PCI RSVD
PCI RSVD
PCI PCIE_RX6+
PCI PCIE_RX6-
PWR GND (FIXED)
PCI N/A
PCI N/A
DP1_HPD HDMI1_HPD PCI/DDI1 DDI1_HPD
PCI/DDI1 N/A
PCI/DDI1 N/A
PCI RSVD
PCI RSVD
PCI/DDI1 N/A
PCI/DDI1 N/A
PWR GND (FIXED)
DP2_AUX+ HDMI2_CTRLCLK PCI/DDI2 DDI2_CTRLCLK_AUX+
DP2_AUX- HDMI2_CTRLDATA PCI/DDI2 DDI2_CTRLDATA_AUX-
PCI/DDI2 DDI2_DDC_AUX_SEL
PCI RSVD
DP3_AUX+ HDMI3_CTRLCLK PCI/DDI3 DDI3_CTRLCLK_AUX+
DP3_AUX- HDMI3_CTRLDATA PCI/DDI3 DDI3_CTRLDATA_AUX-
PCI/DDI3 DDI3_DDC_AUX_SEL
DP3_LANE0+ TMDS3_DATA2+ PCI/DDI3 DDI3_PAIR0+
DP3_LANE0- TMDS3_DATA2- PCI/DDI3 DDI3_PAIR0-
PWR GND (FIXED)
DP3_LANE1+ TMDS3_DATA1+ PCI/DDI3 DDI3_PAIR1+
DP3_LANE1- TMDS3_DATA1- PCI/DDI3 DDI3_PAIR1-
DP3_HPD HDMI3_HPD PCI/DDI3 DDI3_HPD
PCI RSVD
DP3_LANE2+ TMDS3_DATA0+ PCI/DDI3 DDI3_PAIR2+
DP3_LANE2- TMDS3_DATA0- PCI/DDI3 DDI3_PAIR2-
PCI RSVD
DP3_LANE3+ TMDS3_CLK+ PCI/DDI3 DDI3_PAIR3+
DP3_LANE3- TMDS3_CLK- PCI/DDI3 DDI3_PAIR3-
PWR GND (FIXED)
PCIE PEG_RX0+
PCIE PEG_RX0-
 MTD TYPE0#
PCIE PEG_RX1+
PCIE PEG_RX1-
MTD TYPE1#
PCIE PEG_RX2+
PCIE PEG_RX2-
PWR GND (FIXED)
PCIE PEG_RX3+
PCIE PEG_RX3-
RSVD RSVD
RSVD RSVD
PCIE PEG_RX4+
PCIE PEG_RX4-
RSVD RSVD
PCIE PEG_RX5+
PCIE PEG_RX5-
PWR GND (FIXED)
PCIE PEG_RX6+
PCIE PEG_RX6-
SDVO/DDI1 GND
PCIE PEG_RX7+
PCIE PEG_RX7-
PWR GND
RSVD RSVD
PCIE PEG_RX8+
PCIE PEG_RX8-
PWR GND (FIXED)
PCIE PEG_RX9+
PCIE PEG_RX9-
RSVD RSVD
PWR GND
PCIE PEG_RX10+
PCIE PEG_RX10-
PWR GND
PCIE PEG_RX11+
PCIE PEG_RX11-
PWR GND (FIXED)
PCIE PEG_RX12+
PCIE PEG_RX12-
PWR GND
PCIE PEG_RX13+
PCIE PEG_RX13-
PWR GND
RSVD RSVD
PCIE PEG_RX14+
PCIE PEG_RX14-
PWR GND (FIXED)
PCIE PEG_RX15+
PCIE PEG_RX15-
PWR GND
PWR VCC_12V
PWR VCC_12V
PWR VCC_12V
PWR VCC_12V
 PWR VCC_12V
PWR VCC_12V
PWR GND (FIXED)
RSVD pins together.
Row D Type 2 Rev. 2.0 Type 6 Rev. 2.0
D1 GND (FIXED) GND (FIXED) SDVO
D2 IDE_D5 GND
D3 IDE_D10 USB_SSTX0-
D4 IDE_D11 USB_SSTX0+
D5 IDE_D12 GND
D6 IDE_D4 USB_SSTX1-
D7 IDE_D0 USB_SSTX1+
D8 IDE_REQ GND
D9 IDE_IOW# USB_SSTX2-
D10 IDE_ACK# USB_SSTX2+
D11 GND (FIXED) GND (FIXED)
D12 IDE_IRQ USB_SSTX3-
D13 IDE_A0 USB_SSTX3+
D14 IDE_A1 GND
D15 IDE_A2 DDI1_CTRLCLK_AUX+ SDVO1_CTRLCLK
D16 IDE_CS1# DDI1_CTRLDATA_AUX- SDVO1_CTRLDATA
D17 IDE_CS3# RSVD
D18 IDE_RESET# RSVD
D19 PCI_GNT3# PCIE_TX6+
D20 PCI_REQ3# PCIE_TX6-
D21 GND (FIXED) GND (FIXED)
D22 PCI_AD1 PCIE_TX7+
D23 PCI_AD3 PCIE_TX7-
D24 PCI_AD5 RSVD
D25 PCI_AD7 RSVD
D26 PCI_C/BE0# DDI1_PAIR0+ SDVO1_RED+
D27 PCI_AD9 DDI1_PAIR0- SDVO1_RED-
D28 PCI_AD11 RSVD
D29 PCI_AD13 DDI1_PAIR1+ SDVO1_GRN+
D30 PCI_AD15 DDI1_PAIR1- SDVO1_GRN-
D31 GND (FIXED) GND (FIXED)
D32 PCI_PAR DDI1_PAIR2+ SDVO1_BLU+
D33 PCI_SERR# DDI1_PAIR2- SDVO1_BLU-
D34 PCI_STOP# DDI1_DDC_AUX_SEL
D35 PCI_TRDY# RSVD
D36 PCI_FRAME# DDI1_PAIR3+ SDVO1_CK+
D37 PCI_AD16 DDI1_PAIR3- SDVO1_CK-
D38 PCI_AD18 RSVD
D39 PCI_AD20 DDI2_PAIR0+
D40 PCI_AD22 DDI2_PAIR0-
D41 GND (FIXED) GND (FIXED)
D42 PCI_AD24 DDI2_PAIR1+
D43 PCI_AD26 DDI2_PAIR1-
D44 PCI_AD28 DDI2_HPD
D45 PCI_AD30 RSVD
D46 PCI_IRQC# DDI2_PAIR2+
D47 PCI_IRQD# DDI2_PAIR2-
D48 PCI_CLKRUN# RSVD
D49 PCI_M66EN DDI2_PAIR3+
D50 PCI_CLK DDI2_PAIR3-
D51 GND (FIXED) GND (FIXED)
D52 PEG_TX0+ PEG_TX0+
D53 PEG_TX0- PEG_TX0-
D54 PEG_LANE_RV# PEG_LANE_RV#
D55 PEG_TX1+ PEG_TX1+
D56 PEG_TX1- PEG_TX1-
D57 TYPE2# TYPE2#
D58 PEG_TX2+ PEG_TX2+
D59 PEG_TX2- PEG_TX2-
D60 GND (FIXED) GND (FIXED)
D61 PEG_TX3+ PEG_TX3+
D62 PEG_TX3- PEG_TX3-
D63 RSVD RSVD
D64 RSVD RSVD
D65 PEG_TX4+ PEG_TX4+
D66 PEG_TX4- PEG_TX4-
D67 GND GND
D68 PEG_TX5+ PEG_TX5+
D69 PEG_TX5- PEG_TX5-
D70 GND (FIXED) GND (FIXED)
D71 PEG_TX6+ PEG_TX6+
D72 PEG_TX6- PEG_TX6-
D73 SDVO_CLK GND
D74 PEG_TX7+ PEG_TX7+
D75 PEG_TX7- PEG_TX7-
D76 GND GND
D77 IDE_CBLID# RSVD
D78 PEG_TX8+ PEG_TX8+
D79 PEG_TX8- PEG_TX8-
D80 GND (FIXED) GND (FIXED)
D81 PEG_TX9+ PEG_TX9+
D82 PEG_TX9- PEG_TX9-
D83 RSVD RSVD
D84 GND GND
D85 PEG_TX10+ PEG_TX10+
D86 PEG_TX10- PEG_TX10-
D87 GND GND
D88 PEG_TX11+ PEG_TX11+
D89 PEG_TX11- PEG_TX11-
D90 GND (FIXED) GND (FIXED)
D91 PEG_TX12+ PEG_TX12+
D92 PEG_TX12- PEG_TX12-
D93 GND GND
D94 PEG_TX13+ PEG_TX13+
D95 PEG_TX13- PEG_TX13-
D96 GND GND
D97 PEG_ENABLE# RSVD
D98 PEG_TX14+ PEG_TX14+
D99 PEG_TX14- PEG_TX14-
D100 GND (FIXED) GND (FIXED)
D101 PEG_TX15+ PEG_TX15+
D102 PEG_TX15- PEG_TX15-
D103 GND GND
D104 VCC_12V VCC_12V
D105 VCC_12V VCC_12V
D106 VCC_12V VCC_12V
D107 VCC_12V VCC_12V
D108 VCC_12V VCC_12V
D109 VCC_12V VCC_12V
D110 GND (FIXED) GND (FIXED)
RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.
Type 6 Rev. 2.0 I/F SOM-5894 A101-1
DP HDMI/DVI PWR GND (FIXED)
IDE/PWR GND
IDE/USB USB_SSTX0-
IDE/USB USB_SSTX0+
IDE/PWR GND
IDE/USB USB_SSTX1-
IDE/USB USB_SSTX1+
IDE/PWR GND
IDE/USB USB_SSTX2-
IDE/USB USB_SSTX2+
PWR GND (FIXED)
IDE/USB USB_SSTX3-
IDE/USB USB_SSTX3+
IDE/PWR GND
DP1_AUX+ HMDI1_CTRLCLK IDE/DDI1 DDI1_CTRLCLK_AUX+
DP1_AUX- HMDI1_CTRLDATA IDE/DDI1 DDI1_CTRLDATA_AUX-
IDE RSVD
IDE RSVD
PCI/PCIE PCIE_TX6+
PCI/PCIE PCIE_TX6-
PWR GND (FIXED)
PCI/PCIE N/A
PCI/PCIE N/A
PCI RSVD
PCI RSVD
DP1_LANE0+ TMDS1_DATA2+ PCI/DDI1 DDI1_PAIR0+
DP1_LANE0- TMDS1_DATA2- PCI/DDI1 DDI1_PAIR0-
PCI RSVD
DP1_LANE1+ TMDS1_DATA1+ PCI/DDI1 DDI1_PAIR1+
DP1_LANE1- TMDS1_DATA1- PCI/DDI1 DDI1_PAIR1-
PWR GND (FIXED)
DP1_LANE2+ TMDS1_DATA0+ PCI/DDI1 DDI1_PAIR2+
DP1_LANE2- TMDS1_DATA0- PCI/DDI1 DDI1_PAIR2-
PCI/DDI2 DDI1_DDC_AUX_SEL
PCI RSVD
DP1_LANE3+ TMDS1_CLK+ PCI/DDI1 DDI1_PAIR3+
DP1_LANE3- TMDS1_CLK- PCI/DDI1 DDI1_PAIR3-
PCI/DDI3 RSVD
DP2_LANE0+ TMDS2_DATA2+ PCI/DDI2 DDI2_PAIR0+
DP2_LANE0- TMDS2_DATA2- PCI/DDI2 DDI2_PAIR0-
PWR GND (FIXED)
DP2_LANE1+ TMDS2_DATA1+ PCI/DDI2 DDI2_PAIR1+
DP2_LANE1- TMDS2_DATA1- PCI/DDI2 DDI2_PAIR1-
DP2_HPD HDMI2_HPD PCI/DDI2 DDI2_HPD
PCI RSVD
DP2_LANE2+ TMDS2_DATA0+ PCI/DDI2 DDI2_PAIR2+
DP2_LANE2- TMDS2_DATA0- PCI/DDI2 DDI2_PAIR2-
PCI RSVD
DP2_LANE3+ TMDS2_CLK+ PCI/DDI2 DDI2_PAIR3+
DP2_LANE3- TMDS2_CLK- PCI/DDI2 DDI2_PAIR3-
PWR GND (FIXED)
PCIE PEG_TX0+
PCIE PEG_TX0-
 PCIE PEG_LANE_RV#
PCIE PEG_TX1+
PCIE PEG_TX1-
MTD TYPE2#
PCIE PEG_TX2+
PCIE PEG_TX2-
PWR GND (FIXED)
PCIE PEG_TX3+
PCIE PEG_TX3-
RSVD RSVD
RSVD RSVD
PCIE PEG_TX4+
PCIE PEG_TX4-
PWR GND
PCIE PEG_TX5+
PCIE PEG_TX5-
PWR GND (FIXED)
PCIE PEG_TX6+
PCIE PEG_TX6-
SDVO/DDI1 GND
PCIE PEG_TX7+
PCIE PEG_TX7-
PWR GND
IDE RSVD
PCIE PEG_TX8+
PCIE PEG_TX8-
PWR GND (FIXED)
PCIE PEG_TX9+
PCIE PEG_TX9-
RSVD RSVD
PWR GND
PCIE PEG_TX10+
PCIE PEG_TX10-
PWR GND
PCIE PEG_TX11+
PCIE PEG_TX11-
PWR GND (FIXED)
PCIE PEG_TX12+
PCIE PEG_TX12-
PWR GND
PCIE PEG_TX13+
PCIE PEG_TX13-
PWR GND
PCIE PEG_ENABLE#
PCIE PEG_TX14+
PCIE PEG_TX14-
PWR GND (FIXED)
PCIE PEG_TX15+
PCIE PEG_TX15-
PWR GND
PWR VCC_12V
PWR VCC_12V
PWR VCC_12V
PWR VCC_12V
 PWR VCC_12V
PWR VCC_12V
PWR GND (FIXED)
RSVD pins together.
 SOM-5894 A101-4
Pin No. Gigabit Ethernet Pin Type Pwr Rail / Tolerance Description Baseboard
Baseboard

According to LAN
A12 GBE0_MDI0- Checklist, general as:
10/100 - Connect to
Magnetics Module Connect to Magnetics
TXD+/-. Module MDI0+/-
1000 - Connect to N/C if not used.
Magnetics Module
A13 GBE0_MDI0+ MDI0+/-.
N/C if not used.

According to LAN
A9 GBE0_MDI1- Checklist, general as:
10/100 - Connect to
Gigabit Ethernet Controller 0: Media Dependent Interface Magnetics Module Connect to Magnetics
Differential Pairs 0,1,2,3. The MDI can operate in 1000, 100 RXD+/-. Module MDI1+/-
and 10 Mbit / sec modes. Some pairs are not used in some 1000 - Connect to N/C if not used.
modes, per the following: Magnetics Module
A10 GBE0_MDI1+ I/O MDI1+/-.
3.3V max Suspend
Analog 1000BASE-T 100BASE-TX 10BASE-T N/C if not used.
MDI[0]+/- B1_DA+/- TX+/- TX+/-
MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/-
According to LAN
A6 GBE0_MDI2- MDI[3]+/- B1_DD+/-
Checklist, general as:
10/100 - N/C. Connect to Magnetics
1000 - Connect to Module MDI2+/-
Magnetics Module N/C if not used.
A7 GBE0_MDI2+ MDI2+/-.
N/C if not used.

According to LAN
A2 GBE0_MDI3- Checklist, general as:
10/100 - N/C. Connect to Magnetics
1000 - Connect to Module MDI3+/-
Magnetics Module N/C if not used.
A3 GBE0_MDI3+ MDI3+/-.
N/C if not used.
 10/100 - Connect to LED
and current limiting
resistors 300 to 330 Ω to Connect to LED and
3.3VDUAL current limiting resistors
OD 3.3V / 3.3V Suspend
B2 GBE0_ACT# Gigabit Ethernet Controller 0 activity indicator, active low. 1000 - Connect to LED 250 to 330 Ω to 3.3VSB
CMOS 3.3V Suspend / 3.3V
and current limiting with bypass 470 pF
resistors 300 to 330 Ω to N/C if not used.
3.3VDUAL
N/C if not used.

10/100 - Connect to LED

and current limiting
resistors 300 to 330 Ω to Connect to LED and
3.3VDUAL current limiting resistors
OD 3.3V / 3.3V Suspend
A8 GBE0_LINK# Gigabit Ethernet Controller 0 link indicator, active low. 1000 - Connect to LED 250 to 330 Ω to 3.3VSB
CMOS 3.3V Suspend / 3.3V
and current limiting with bypass 470 pF
resistors 300 to 330 Ω to N/C if not used.
3.3VDUAL
N/C if not used.

10/100 - Connect to LED

and current limiting
resistors 300 to 330 Ω to Connect to LED and
3.3VDUAL current limiting resistors
OD 3.3V / 3.3V Suspend Gigabit Ethernet Controller 0 100 Mbit / sec link indicator,
A4 GBE0_LINK100# 1000 - Connect to LED 250 to 330 Ω to 3.3VSB
CMOS 3.3V Suspend / 3.3V active low.
and current limiting with bypass 470 pF
resistors 300 to 330 Ω to N/C if not used.
3.3VDUAL
N/C if not used.

10/100 - N/C
Connect to LED and
1000 - Connect to LED
current limiting resistors
OD 3.3V / 3.3V Suspend Gigabit Ethernet Controller 0 1000 Mbit / sec link indicator, and current limiting
A5 GBE0_LINK1000# 250 to 330 Ω to 3.3VSB
CMOS 3.3V Suspend / 3.3V active low. resistors 300 to 330 Ω to
with bypass 470 pF
3.3VDUAL
N/C if not used.
N/C if not used.
 Reference voltage for Carrier Board Ethernet channel 0
10/100 - N/C
magnetics center tap. The reference voltage is determined by
1000 - Connect 0Ω in Connect 0Ω in series to
the requirements of the module PHY and may be as low as
series to Magnetics Magnetics Module
GND min 0V and as high as 3.3V.
A14 GBE0_CTREF REF Module center trap and center trap and 0.1uF to
3.3V max
0.1uF to ground on ground on every pin
The reference voltage output shall be current limited on the
every pin N/C if not used.
module. In the case in which the reference is shorted to
N/C if not used.
ground, the current shall be limited to 250 mA or less.

According to LAN
Checklist, general as: Connect 0.1uF on every
10/100 - Connect RX+/- pin and 1uF bulk
center trap to 0.1uF(NL) decoupling capacitor
I/O GND min to ground. placed near the
CT Transformer Magnetics Module center taps
Analog 3.3V max 1000 - Connect 0.1uF to magnetics center tap
ground and 0Ω in series input to the transformer
to COME pin A14 to ground
GBE0_CTREF. N/C if not used.
N/C if not used.

4.3.2 Ethernet
Up to 3 Gigabit Ethernet ports are defined, designated GBE0 through GBE2. The ports may operate in 10, 100, or 1000 Mbit/sec modes.
Magnetics are assumed to be on the Carrier Board. All COM Express® Modules shall implement at least one 10/100 Ethernet port on
the GBE0 pin slot and this should be capable of at least 10/100 mode.
4.4.1 Ethernet
External Ethernet magnetics shall be implemented on the Carrier Board.

5.4.55.4.6 10/100/1000 Ethernet Insertion Loss Budget

 Figure 5-55-6: 10/100/1000 Ethernet Insertion Loss Budget

Table 5.205.155.16: 10/100/1000 Ethernet Insertion Loss Budget, 100 MHz

Segment Loss (dB) Notes
LA 0.08 Up to 3 inches of module trace @ 0.28 dB / GHz / inch
LB 0.02 COM Express® connector at 100 MHz measured value
LC 0.15 Up to 5 inches of Carrier Board trace @ 0.28 dB / GHz / inch
LD 24.00 Cable and cable connectors, integrated magnetics, per source spec.
Total 24.25
COM Express® Ethernet implementations should conform to insertion loss values less than or equal to those shown in the table above.
The insertion loss values shown account for frequency dependent material losses only. Cross talk losses are separate from material
losses in the Gb Ethernet specification.
“Device Down” implementations, in which the Ethernet target device is implemented on the Carrier Board (for instance, an Ethernet
switch), may add the insertion loss for the RJ45 Ethernet
jack and integrated magnetics to the Carrier Board budget. This insertion loss value is typically 1 dB. The Carrier Board insertion loss
budget then becomes LC + 1 dB, or 1.15 dB.

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 AC97 Audio / SOM-5894 A101-4
Pin No. Pin Type Pwr Rail / Tolerance Description Baseboard
High Definition Audio Baseboard

Module has integrated

series resistor
AC97 - Connect 0 Ω in Module has integrated
series to CODEC pin 11 series resistor
O 3.3V / 3.3V Suspend Reset output to AC97
A30 AC/HDA_RST# RESET# Connect to CODEC pin
CMOS 3.3V Suspend / 3.3V CODEC, active low.
HDA - Connect 0 Ω in 11 RESET#
series to CODEC pin 11 N/C if not used
RESET#
N/C if not used

Module has integrated

series resistor
AC97 - Connect 0 Ω in Module has integrated
48kHz fixed-rate, series to CODEC pin 10 series resistor
O
A29 AC/HDA_SYNC 3.3V / 3.3V sample-synchronization SYNC Connect to CODEC pin
CMOS
signal to the CODEC(s). HDA - Connect 0 Ω in 10 SYNC
series to CODEC pin 10 N/C if not used
SYNC
N/C if not used

AC97 - Connect 33-47 Ω

in series to CODEC pin
6 BIT_CLK Module has integrated
12.228 MHz serial data HDA - Module has series resistor
I/O
A32 AC/HDA_BITCLK 3.3V / 3.3V clock generated by the integrated series Connect to CODEC pin
CMOS
external CODEC(s). resistor. Connect 0 Ω in 6 BIT_CLK
series to CODEC pin 6 N/C if not used
BIT_CLK
N/C if not used
 Module has integrated
series resistor
AC97 - Connect 0 Ω in Module has integrated
series to CODEC pin 5 series resistor
O Serial TDM data output
A33 AC/HDA_SDOUT 3.3V / 3.3V SDATA_OUT Connect to CODEC pin
CMOS to the CODEC.
HDA - Connect 0 Ω in 5 SDATA_OUT
series to CODEC pin 5 N/C if not used
SDATA_OUT
N/C if not used

AC97 - Connect 33-47 Ω

in series to CODEC pin
8 SDATA_IN Connect 33 Ω in series
I 3.3V / 3.3V Suspend Serial TDM data inputs HDA - Connect 33-47 Ω to CODEC0 pin 8
B30 AC/HDA_SDIN0
CMOS 3.3V Suspend / 3.3V from CODEC 0. in series and PD SDATA_IN
10KΩ(NL) to CODEC N/C if not used
pin 8 SDATA_IN
N/C if not used

AC97 - Connect 33-47 Ω

in series to CODEC pin
8 SDATA_IN Connect 33 Ω in series
I 3.3V / 3.3V Suspend Serial TDM data inputs HDA - Connect 33-47 Ω to CODEC1 pin 8
B29 AC/HDA_SDIN1
CMOS 3.3V Suspend / 3.3V from CODEC 1. in series and PD SDATA_IN
10KΩ(NL) to CODEC N/C if not used
pin 8 SDATA_IN
N/C if not used

AC97 - Connect 33-47 Ω

in series to CODEC pin
8 SDATA_IN Connect 33 Ω in series
I 3.3V / 3.3V Suspend Serial TDM data inputs HDA - Connect 33-47 Ω to CODEC2 pin 8
B28 AC/HDA_SDIN2
CMOS 3.3V Suspend / 3.3V CODEC 2. in series and PD SDATA_IN
10KΩ(NL) to CODEC N/C if not used
pin 8 SDATA_IN
N/C if not used
4.3.1 AC97 Audio / High Definition Audio
The AC ’97 audio codec interface is limited to support a single AC ’97 link. High Definition Audio
may may be supported.
The HDA signal level from some chipsets might be 1.5V. Module designers must add any necessary
voltage translation circuitry to meet the COM Express 3.3V signaling requirement for AC-97/HDA
signals.
The AC'97 or HDA codec on a COM Express Carrier Board shall be connected as the primary
codec with the codec ID 00 using the data input line 'AC_SDIN0'. Up to two additional codecs with
ID 01 and ID 10 may be connected to the COM Express Module by using the other designated
signals AC_SDIN[1:2] / HDA_SDIN[1:2].

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 Pwr Rail /
Pin No. Serial ATA Pin Type Description Baseboard
Tolerance

Module has integrated

AC Coupling capacitor
A16 SATA0_TX+ Connect to SATA0 Conn
pin 2 TX+
N/C if not used.
O AC coupled on Serial ATA or SAS Channel 0 transmit differential
SATA module pair.
Module has integrated
AC Coupling capacitor
A17 SATA0_TX- Connect to SATA0 Conn
pin 3 TX-
N/C if not used.

Module has integrated

AC Coupling capacitor
A19 SATA0_RX+ Connect to SATA0 Conn
pin 6 RX+
N/C if not used.
I AC coupled on Serial ATA or SAS Channel 0 receive differential
SATA module pair.
Module has integrated
AC Coupling capacitor
A20 SATA0_RX- Connect to SATA0 Conn
pin 5 RX-
N/C if not used.

Module has integrated

AC Coupling capacitor
B16 SATA1_TX+ Connect to SATA1 Conn
pin 2 TX+
N/C if not used.
O AC coupled on Serial ATA or SAS Channel 1 transmit differential
SATA module pair.
Module has integrated
AC Coupling capacitor
B17 SATA1_TX- Connect to SATA1 Conn
pin 3 TX-
N/C if not used.
 Module has integrated
AC Coupling capacitor
B19 SATA1_RX+ Connect to SATA1 Conn
pin 6 RX+
N/C if not used.
I AC coupled on Serial ATA or SAS Channel 1 receive differential
SATA module pair.
Module has integrated
AC Coupling capacitor
B20 SATA1_RX- Connect to SATA1 Conn
pin 5 RX-
N/C if not used.

Module has integrated

AC Coupling capacitor
A22 SATA2_TX+ Connect to SATA2 Conn
pin 2 TX+
N/C if not used.
O AC coupled on Serial ATA or SAS Channel 2 transmit differential
SATA module pair.
Module has integrated
AC Coupling capacitor
A23 SATA2_TX- Connect to SATA2 Conn
pin 3 TX-
N/C if not used.

Module has integrated

AC Coupling capacitor
A25 SATA2_RX+ Connect to SATA2 Conn
pin 6 RX+
N/C if not used.
I AC coupled on Serial ATA or SAS Channel 2 receive differential
SATA module pair.
Module has integrated
AC Coupling capacitor
A26 SATA2_RX- Connect to SATA2 Conn
pin 5 RX-
N/C if not used.
 Module has integrated
AC Coupling capacitor
B22 SATA3_TX+ Connect to SATA3 Conn
pin 2 TX+
N/C if not used.
O AC coupled on Serial ATA or SAS Channel 3 transmit differential
SATA module pair.
Module has integrated
AC Coupling capacitor
B23 SATA3_TX- Connect to SATA3 Conn
pin 3 TX-
N/C if not used.

Module has integrated

AC Coupling capacitor
B25 SATA3_RX+ Connect to SATA3 Conn
pin 6 RX+
N/C if not used.
I AC coupled on Serial ATA or SAS Channel 3 receive differential
SATA module pair.
Module has integrated
AC Coupling capacitor
B26 SATA3_RX- Connect to SATA3 Conn
pin 5 RX-
N/C if not used.

Module has integrated

PU resistor to 3.3V
I/O ATA (parallel and serial) or SAS activity indicator, Connect to LED and
A28 (S)ATA_ACT# 3.3V / 3.3V
CMOS active low. current limiting resistors
250 to 330 Ω to 3.3V
N/C if not used.

4.3.4 Serial ATA

Serial ATA links for support of existing SATA-150 and emerging SATA-300 devices. Alternatively, this interface
may be used for Serial Attached SCSI (SAS).
The following signals shall be AC coupled on the Module.
• SATA[0:3]TX+/-
• SATA[0:3]RX+/-
5.4.3 SATA Insertion Loss Budget
The Serial ATA source specification provides insertion loss figures only for the SATA cable. There are several
cable types defined with insertion losses ranging from 6 dB up to 16 dB. Cross talk losses are separate from
material losses in the SATA specification.
The COM Express® SATA Insertion loss budgets presented below represent the material losses and do not
include cross talk losses. The COM Express® SATA Insertion loss budgets are a guideline: module and Carrier
Board vendors should not exceed the values shown in the tables below.
Figure 5-3: SATA Insertion Loss Budget

Table 5.175.12: SATA Gen 1 Insertion Loss Budget, 1.5 GHz

Segment Loss (dB) Notes
LA 1.26 Up to 3.0 inches of module trace @ 0.28 dB / GHz / inch
Coupling Caps 0.40
LB 0.25 COM Express® connector at 1.5 GHz measured value
LC 3.07 Up to 7.2 inches of Carrier Board trace @ 0.28 dB / GHz / inch
LD 6.00 Source specification cable and cable connector allowance
Total 10.98
Table 5.185.13: SATA Gen 2 Insertion Loss Budget, 3.0 GHz
Segment Loss (dB) Notes
LA 1.68 Up to 2.0 inches of module trace @ 0.28 dB / GHz / inch
Coupling Caps 0.40
LB 0.38 COM Express® connector at 3.0 GHz measured value
LC 2.52 Up to 3.0 inches of Carrier Board trace @ 0.28 dB / GHz / inch
LD 6.00 Source specification cable and cable connector allowance
Total 10.98

Pwr Rail /
Pin SATA Connector Pin Type Description SATA Device
Tolerance
1 GND Power Ground

2 TX+ Transmitter differential pair positive signal

I AC coupled on
SATA module
3 TX- Transmitter differential pair negative signal

4 GND Power Ground

5 RX- Receiver differential pair negative signal

O AC coupled on
SATA module
6 RX+ Receiver differential pair positive signal

7 GND Power Ground

SATA Power Pwr Rail /

Pin Pin Type Description SATA Device
Connector Tolerance
1,2,3 +3.3V Power 3.3V 3.3V power supply
4,5,6 GND Power Ground
7,8,9 +5V Power 5V 5V power supply
10,11,12 GND Power Ground
13,14,15 +12V Power 12V 12V power supply

Pwr Rail /
Pin eSATA Connector Pin Type Description SATA Device
Tolerance
1 GND Power Ground

2 TX+ Transmitter differential pair positive signal

I AC coupled on
SATA module
3 TX- Transmitter differential pair negative signal

4 GND Power Ground

5 RX- Receiver differential pair negative signal

O AC coupled on
SATA module
6 RX+ Receiver differential pair positive signal

7 GND Power Ground

 Pwr Rail /
Pin mSATA Connector Pin Type Description SATA Device
Tolerance
Side even
52 +3.3 V Power 3.3V 3.3 V Source
50 GND Power Return Current Path
48 +1.5 V Power 1.5V 1.5 V Source
46 Reserved No Connect
44 Reserved No Connect
42 Reserved No Connect
40 GND Power Return Current Path
38 Reserved No Connect
36 Reserved No Connect
34 GND Power Return Current Path
32 Two Wire Interface Two Wire Interface Data

30 Two Wire Interface Two Wire Interface Clock

28 +1.5 V Power 1.5V 1.5 V Source

26 GND Power Return Current Path
24 +3.3 V Power 3.3V 3.3 V Source
22 Reserved No Connect
20 Reserved No Connect
18 GND Power Return Current Path
Mechanical key
16 Reserved No Connect
14 Reserved No Connect
12 Reserved No Connect
10 Reserved No Connect
8 Reserved No Connect
6 +1.5 V Power 1.5V 1.5 V Source
4 GND Power Return Current Path
2 +3.3 V Power 3.3V 3.3 V Source
Side odd
51 Presence Detection Shall be pulled to GND by device PD to GND

Device Activity Signal / Disable Staggered Spin-

49 DA/DSS
up

47 Vendor Vendor Specific / Manufacturing Pin

45 Vendor Vendor Specific / Manufacturing Pin

43 Device Type No Connect N/C

41 +3.3 V Power 3.3V 3.3 V Source

39 +3.3 V Power 3.3V 3.3 V Source
37 GND Power Return Current Path
35 GND Power Return Current Path

Host Transmitter Differential Signal Pair This is

33 +A
an input of the SSD.

I AC coupled on
SATA module

Host Transmitter Differential Signal Pair This is

31 -A
an input of the SSD.

29 GND Power Return Current Path

27 GND Power Return Current Path

Host Receiver Differential Signal Pair This is an

25 -B
output of the SSD.

O AC coupled on
SATA module
 O AC coupled on
SATA module

Host Receiver Differential Signal Pair This is an

23 +B
output of the SSD.

21 GND Power Return Current Path

19 Reserved No Connect
17 Reserved No Connect
Mechanical key
15 GND Power Return Current Path
13 Reserved No Connect
11 Reserved No Connect
9 GND Power Return Current Path
7 Reserved No Connect
5 Reserved No Connect
3 Reserved No Connect
1 Reserved No Connect

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 SOM-5894 A101-4
Baseboard

Module has integrated

AC Coupling capacitor
Connect to SATA0 Conn
pin 2 TX+
N/C if not used.

Module has integrated

AC Coupling capacitor
Connect to SATA0 Conn
pin 3 TX-
N/C if not used.

Module has integrated

AC Coupling capacitor
Connect to SATA0 Conn
pin 6 RX+
N/C if not used.

Module has integrated

AC Coupling capacitor
Connect to SATA0 Conn
pin 5 RX-
N/C if not used.

Module has integrated

AC Coupling capacitor
Connect to SATA1 Conn
pin 2 TX+
N/C if not used.

Module has integrated

AC Coupling capacitor
Connect to SATA1 Conn
pin 3 TX-
N/C if not used.
Module has integrated
AC Coupling capacitor
Connect to SATA1 Conn
pin 6 RX+
N/C if not used.

Module has integrated

AC Coupling capacitor
Connect to SATA1 Conn
pin 5 RX-
N/C if not used.

Module has integrated

AC Coupling capacitor
Connect to SATA2 Conn
pin 2 TX+
N/C if not used.

Module has integrated

AC Coupling capacitor
Connect to SATA2 Conn
pin 3 TX-
N/C if not used.

Module has integrated

AC Coupling capacitor
Connect to SATA2 Conn
pin 6 RX+
N/C if not used.

Module has integrated

AC Coupling capacitor
Connect to SATA2 Conn
pin 5 RX-
N/C if not used.
Module has integrated
AC Coupling capacitor
Connect to SATA3 Conn
pin 2 TX+
N/C if not used.

Module has integrated

AC Coupling capacitor
Connect to SATA3 Conn
pin 3 TX-
N/C if not used.

Module has integrated

AC Coupling capacitor
Connect to SATA3 Conn
pin 6 RX+
N/C if not used.

Module has integrated

AC Coupling capacitor
Connect to SATA3 Conn
pin 5 RX-
N/C if not used.

Module has integrated

PU resistor
Connect to LED and
current limiting resistors
250 to 330 Ω to 3.3V
N/C if not used.
 Baseboard

Connect to GND
Connect to COME
SATAx_TX+
Connect to COME
SATAx_TX-
Connect to GND
Connect to COME
SATAx_RX-
Connect to COME
SATAx_RX+
Connect to GND

Baseboard

Connect to 3.3V
Connect to GND
Connect to 5V
Connect to GND
Connect to 12V

Baseboard

Connect to GND
Connect to COME
SATAx_TX+
Connect to COME
SATAx_TX-
Connect to GND
Connect to COME
SATAx_RX-
Connect to COME
SATAx_RX+
Connect to GND
 Baseboard

Connect to 3.3V
Connect to GND
Connect to 1.5V
N/C
N/C
N/C
Connect to GND
N/C
N/C
Connect to GND
Module has integrated
PU resistor to
3.3VDUAL
Connect 0Ω(NL) in
series to COME pin B14
SMB_DAT.

Module has integrated

PU resistor to
3.3VDUAL
Connect 0Ω(NL) in
series to COME pin B13
SMB_CLK.
Connect to 1.5V
Connect to GND
Connect to 3.3V
N/C
N/C
Connect to GND
N/C
N/C
N/C
N/C
N/C
N/C
Connect to 1.5V
Connect to GND
Connect to 3.3V

Connect to GPIO for

Presence Detection
Connect LED and
current limiting resistors
300 to 330 Ω to 3.3V
Connect to GPIO for
Vendor Specific /
Manufacturing or N/C
Connect to GPIO for
Vendor Specific /
Manufacturing or N/C
mSATA only - N/C
mSATA/PCIe Mini Card
Switch - PU 10KΩ to
3.3V and connect to
Differential Channel
Mux/Demux pin SEL for
mSATA
Connect to 3.3V
Connect to 3.3V
Connect to GND
Connect to GND

mSATA only - Connect

to COME SATAx_TX+
mSATA/PCIe Mini Card
Switch - Connect to
Differential Channel
Mux/Demux pin TX+ for
mSATA

mSATA only - Connect

to COME SATAx_TX-
mSATA/PCIe Mini Card
Switch - Connect to
Differential Channel
Mux/Demux pin TX- for
mSATA

Connect to GND
Connect to GND

mSATA only - Connect

to COME SATAx_RX-
mSATA/PCIe Mini Card
Switch - Connect to
Differential Channel
Mux/Demux pin RX- for
mSATA
mSATA only - Connect
to COME SATAx_RX+
mSATA/PCIe Mini Card
Switch - Connect to
Differential Channel
Mux/Demux pin RX+ for
mSATA

Connect to GND
N/C
N/C
N/C
Connect to GND
N/C
N/C
Connect to GND
N/C
N/C
N/C
N/C
 Pwr Rail /
Pin No. IDE Pin Type Baseboard
Tolerance

Connect 22-33Ω in
series near connector to
I/O
D7 IDE_D0 3.3V / 5V Bidirectional data to / from IDE device. IDE - pin 17 DD0
CMOS
CF - pin 21 D00
N/C if not used

Connect 22-33Ω in
series near connector to
I/O
C10 IDE_D1 3.3V / 5V Bidirectional data to / from IDE device. IDE - pin 15 DD1
CMOS
CF - pin 22 D01
N/C if not used

Connect 22-33Ω in
series near connector to
I/O
C8 IDE_D2 3.3V / 5V Bidirectional data to / from IDE device. IDE - pin 13 DD2
CMOS
CF - pin 23 D02
N/C if not used

Connect 22-33Ω in
series near connector to
I/O
C4 IDE_D3 3.3V / 5V Bidirectional data to / from IDE device. IDE - pin 11 DD3
CMOS
CF - pin 2 D03
N/C if not used

Connect 22-33Ω in
series near connector to
I/O
D6 IDE_D4 3.3V / 5V Bidirectional data to / from IDE device. IDE pin 9 DD4
CMOS
CF pin 3 D04
N/C if not used
 Connect 22-33Ω in
series near connector to
I/O
D2 IDE_D5 3.3V / 5V Bidirectional data to / from IDE device. IDE pin 7 DD5
CMOS
CF pin 4 D05
N/C if not used

Connect 22-33Ω in
series near connector to
I/O
C3 IDE_D6 3.3V / 5V Bidirectional data to / from IDE device. IDE pin 5 DD6
CMOS
CF pin 5 D06
N/C if not used

Module has integrated

PD resistor to GND.
Connect 22-33Ω in
I/O
C2 IDE_D7 3.3V / 5V Bidirectional data to / from IDE device. series near connector to
CMOS
IDE pin 3 DD7
CF pin 6 D07
N/C if not used

Connect 22-33Ω in
series near connector to
I/O
C6 IDE_D8 3.3V / 5V Bidirectional data to / from IDE device. IDE pin 4 DD8
CMOS
CF pin 47 D08
N/C if not used

Connect 22-33Ω in
series near connector to
I/O
C7 IDE_D9 3.3V / 5V Bidirectional data to / from IDE device. IDE pin 6 DD9
CMOS
CF pin 48 D09
N/C if not used
 Connect 22-33Ω in
series near connector to
I/O
D3 IDE_D10 3.3V / 5V Bidirectional data to / from IDE device. IDE pin 8 DD10
CMOS
CF pin 49 D10
N/C if not used

Connect 22-33Ω in
series near connector to
I/O
D4 IDE_D11 3.3V / 5V Bidirectional data to / from IDE device. IDE pin 10 DD11
CMOS
CF pin 27 D11
N/C if not used

Connect 22-33Ω in
series near connector to
I/O
D5 IDE_D12 3.3V / 5V Bidirectional data to / from IDE device. IDE pin 12 DD12
CMOS
CF pin 28 D12
N/C if not used

Connect 22-33Ω in
series near connector to
I/O
C9 IDE_D13 3.3V / 5V Bidirectional data to / from IDE device. IDE pin 14 DD13
CMOS
CF pin 29 D13
N/C if not used

Connect 22-33Ω in
series near connector to
I/O
C12 IDE_D14 3.3V / 5V Bidirectional data to / from IDE device. IDE pin 16 DD14
CMOS
CF pin 30 D14
N/C if not used
 Connect 22-33Ω in
series near connector to
I/O
C5 IDE_D15 3.3V / 5V Bidirectional data to / from IDE device. IDE pin 18 DD15
CMOS
CF pin 31 D15
N/C if not used

Connect to
O IDE pin 35 DA0
D13 IDE_A0 3.3V / 3.3V Address lines to IDE device.
CMOS CF pin 20 A00
N/C if not used
Connect to
O IDE pin 33 DA1
D14 IDE_A1 3.3V / 3.3V Address lines to IDE device.
CMOS CF pin 19 A01
N/C if not used
Connect to
O IDE pin 36 DA2
D15 IDE_A2 3.3V / 3.3V Address lines to IDE device.
CMOS CF pin 18 A02
N/C if not used
Connect to
O I/O write line to IDE device. Data latched on IDE pin 23 DIOW-
D9 IDE_IOW# 3.3V / 3.3V
CMOS trailing (rising) edge. CF pin 35 -IOWR
N/C if not used
Connect to
I IDE pin 25 DIOR-
C14 IDE_IOR# 3.3V / 3.3V I/O read line from IDE device.
CMOS CF pin 34 -IORD
N/C if not used

Module has integrated

PD resistor to GND.
I IDE Device DMA Request. It is asserted by the Connect to
D8 IDE_REQ 3.3V / 5V
CMOS IDE device to request a data transfer. IDE pin 21 DMARQ
CF pin 43 DMARQ
N/C if not used
 Connect to
O IDE pin 29 DMACK-
D10 IDE_ACK# 3.3V / 3.3V IDE Device DMA Acknowledge.
CMOS CF pin 44 -DMACK
N/C if not used
Connect to
O IDE pin 37 CS0-
D16 IDE_CS1# 3.3V / 3.3V IDE Device Chip Select for 1F0h to 1FFh range.
CMOS CF pin 7 -CS0
N/C if not used
Connect to
O IDE pin 38 CS1-
D17 IDE_CS3# 3.3V / 3.3V IDE Device Chip Select for 3F0h to 3FFh range.
CMOS CF pin 32 -CS1
N/C if not used

Module has integrated

PU resistor to 3.3V.
I IDE device I/O ready input. Pulled low by the IDE Connect to
C13 IDE_IORDY 3.3V / 5V
CMOS device to extend the cycle. IDE pin 27 IORDY
CF pin 42 IORDY
N/C if not used

Module has integrated

3.3V buffer and series
resistor.
O
D18 IDE_RESET# 3.3V / 3.3V Reset output to IDE device, active low. Connect to
CMOS
IDE pin 1 RESET-
CF pin 41 -RESET
N/C if not used

Module has integrated

PU resistor to 3.3V.
I Connect to
D12 IDE_IRQ 3.3V / 5V Interrupt request from IDE device.
CMOS IDE pin 31 INTRQ
CF pin 37 INTRQ
N/C if not used
 Input from off-module hardware indicating the Module has integrated
type of IDE cable being used. High indicates a PD resistor to GND.
I 40-pin cable used for legacy IDE modes. Low Connect to
D77 IDE_CBLID# 3.3V / 5V
CMOS indicates that an 80-pin cable with interleaved IDE pin 34 PDIAG-
grounds is used. Such a cable is required for CF pin 46 -PDIAG
Ultra-DMA 66, 100 and 133 modes. N/C if not used

4.3.3 IDE
Parallel ATA support for up to 2 devices in a master/slave configuration. This signaling interface is limited to
ATA100 speeds. Higher (ATA133) speeds are not defined. PATA signal pins are reused in Pin-out Type 3 and 5
Modules for 2 additional GB Ethernet interfaces; and for USB3.0 interfaces in Type 6.
The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V
with a 4.7kΩ resistor
• IDE_IORDY
Module termination of IDE_IRQ is dependent on the controller used. The Module shall provide the necessary
termination.

Pwr Rail /
Pin No. IDE Connector Pin Type Description IDE Device
Tolerance
I
1 RESET- 3.3V / 3.3V Reset input to IDE device, active low.
CMOS
2 Ground Power Return current path, Ground
 I/O
3 DD7 3.3V / 5V Bidirectional data to / from IDE device.
CMOS

I/O
4 DD8 3.3V / 5V Bidirectional data to / from IDE device.
CMOS

I/O
5 DD6 3.3V / 5V Bidirectional data to / from IDE device.
CMOS

I/O
6 DD9 3.3V / 5V Bidirectional data to / from IDE device.
CMOS

I/O
7 DD5 3.3V / 5V Bidirectional data to / from IDE device.
CMOS

I/O
8 DD10 3.3V / 5V Bidirectional data to / from IDE device.
CMOS

I/O
9 DD4 3.3V / 5V Bidirectional data to / from IDE device.
CMOS

I/O
10 DD11 3.3V / 5V Bidirectional data to / from IDE device.
CMOS

I/O
11 DD3 3.3V / 5V Bidirectional data to / from IDE device.
CMOS
 I/O
12 DD12 3.3V / 5V Bidirectional data to / from IDE device.
CMOS

I/O
13 DD2 3.3V / 5V Bidirectional data to / from IDE device.
CMOS

I/O
14 DD13 3.3V / 5V Bidirectional data to / from IDE device.
CMOS

I/O
15 DD1 3.3V / 5V Bidirectional data to / from IDE device.
CMOS

I/O
16 DD14 3.3V / 5V Bidirectional data to / from IDE device.
CMOS

I/O
17 DD0 3.3V / 5V Bidirectional data to / from IDE device.
CMOS

I/O
18 DD15 3.3V / 5V Bidirectional data to / from IDE device.
CMOS

19 Ground Power Return current path, Ground

20 (keypin)
O IDE Device DMA Request. It is asserted by the
21 DMARQ 3.3V / 5V
CMOS IDE device to request a data transfer.
22 Ground Power Return current path, Ground
I I/O write line to IDE device. Data latched on
23 DIOW- 3.3V / 3.3V
CMOS trailing (rising) edge.
24 Ground Power Return current path, Ground
 O
25 DIOR- 3.3V / 3.3V I/O read line from IDE device.
CMOS
26 Ground Power Return current path, Ground
O IDE device I/O ready output. Pulled low by the
27 IORDY 3.3V / 5V
CMOS IDE device to extend the cycle.

Cable select. If CSEL is enabled in the device,

the device is configured as either Device 0 or
I Integrated PU 10KΩ to
28 CSEL 3.3V / 5V Device 1 depending upon the value of CSEL:
CMOS 5V
If CSEL is negated, the device number is 0;
If CSEL is asserted, the device number is 1.

I
29 DMACK- 3.3V / 3.3V IDE Device DMA Acknowledge.
CMOS
30 Ground Power Return current path, Ground
O
31 INTRQ 3.3V / 5V Interrupt request from IDE device.
CMOS
IDE I/O channel select; asserted low for an
O
32 IOCS16# 3.3V / 5V access to the data port. The computer uses this N/A
CMOS
signal to indicate a 16-bit data transfer.
I
33 DA1 3.3V / 3.3V Address lines to IDE device.
CMOS

Output from off-module hardware indicating the

type of IDE cable being used. High indicates a
O 40-pin cable used for legacy IDE modes. Low Integrated PU 10KΩ to
34 PDIAG- 3.3V / 5V
CMOS indicates that an 80-pin cable with interleaved 5V
grounds is used. Such a cable is required for
Ultra-DMA 66, 100 and 133 modes.

I
35 DA0 3.3V / 3.3V Address lines to IDE device.
CMOS
I
36 DA2 3.3V / 3.3V Address lines to IDE device.
CMOS
I
37 CS0- 3.3V / 3.3V IDE Device Chip Select for 1F0h to 1FFh range.
CMOS
 I
38 CS1- 3.3V / 3.3V IDE Device Chip Select for 3F0h to 3FFh range.
CMOS

Time-multiplexed, open-collector output that

OD Integrated PU 10KΩ to
39 DASP# 3.3V / 5V indicates that a drive is active. It is also used for
CMOS 5V
Master/Slave negotiation on IDE channel.

40 Ground Power Return current path, Ground

Pwr Rail /
Pin No. CF Connector Pin Type Description CF Module
Tolerance
1 GND Power Return current path, Ground

I/O
2 D03 3.3V / 5V Bidirectional data to / from CF device.
CMOS
 I/O
3 D04 3.3V / 5V Bidirectional data to / from CF device.
CMOS

I/O
4 D05 3.3V / 5V Bidirectional data to / from CF device.
CMOS

I/O
5 D06 3.3V / 5V Bidirectional data to / from CF device.
CMOS

I/O
6 D07 3.3V / 5V Bidirectional data to / from CF device.
CMOS

I
7 -CS0 3.3V / 3.3V CF Device Chip Select for 1F0h to 1FFh range.
CMOS
In True IDE Mode, only A[2:0] are used to select
I the one of eight registers in the Task File, the
8 A10 3.3V / 5V
CMOS remaining address lines should be grounded by
the host.
I To enable True IDE Mode this input should be
9 ATA SEL# 3.3V / 5V
CMOS grounded by the host.
In True IDE Mode, only A[2:0] are used to select
I the one of eight registers in the Task File, the
10 A09 3.3V / 5V
CMOS remaining address lines should be grounded by
the host.
In True IDE Mode, only A[2:0] are used to select
I the one of eight registers in the Task File, the
11 A08 3.3V / 5V
CMOS remaining address lines should be grounded by
the host.
 In True IDE Mode, only A[2:0] are used to select
I the one of eight registers in the Task File, the
12 A07 3.3V / 5V
CMOS remaining address lines should be grounded by
the host.
13 VCC Power 3.3V / 5V +5 V, +3.3 V power
In True IDE Mode, only A[2:0] are used to select
I the one of eight registers in the Task File, the
14 A06 3.3V / 5V
CMOS remaining address lines should be grounded by
the host.

In True IDE Mode, only A[2:0] are used to select

I the one of eight registers in the Task File, the
15 A05 3.3V / 5V
CMOS remaining address lines should be grounded by
the host.
In True IDE Mode, only A[2:0] are used to select
I the one of eight registers in the Task File, the
16 A04 3.3V / 5V
CMOS remaining address lines should be grounded by
the host.
In True IDE Mode, only A[2:0] are used to select
I the one of eight registers in the Task File, the
17 A03 3.3V / 5V
CMOS remaining address lines should be grounded by
the host.
I
18 A02 3.3V / 3.3V Address lines to CF device.
CMOS
I
19 A01 3.3V / 3.3V Address lines to CF device.
CMOS
I
20 A00 3.3V / 3.3V Address lines to CF device.
CMOS

I/O
21 D00 3.3V / 5V Bidirectional data to / from CF device.
CMOS

I/O
22 D01 3.3V / 5V Bidirectional data to / from CF device.
CMOS
 I/O
23 D02 3.3V / 5V Bidirectional data to / from CF device.
CMOS

In True IDE Mode this output signal is asserted

low when this device is expecting a word data
O
24 -IOCS16 3.3V / 5V transfer cycle. N/A
CMOS
IOCS16# is shown for PIO modes 0, 1 and 2. For
other modes, this signal is ignored.

These Card Detect pins are connected to ground

on the CompactFlash Storage Card or CF+ Card.
O
25 -CD2 3.3V / 5V They are used by the host to determine that the PD to GND
CMOS
CompactFlash Storage Card or CF+ Card is fully
inserted into its socket.

These Card Detect pins are connected to ground

on the CompactFlash Storage Card or CF+ Card.
O
26 -CD1 3.3V / 5V They are used by the host to determine that the PD to GND
CMOS
CompactFlash Storage Card or CF+ Card is fully
inserted into its socket.

I/O
27 D11 3.3V / 5V Bidirectional data to / from CF device.
CMOS

I/O
28 D12 3.3V / 5V Bidirectional data to / from CF device.
CMOS

I/O
29 D13 3.3V / 5V Bidirectional data to / from CF device.
CMOS
 I/O
30 D14 3.3V / 5V Bidirectional data to / from CF device.
CMOS

I/O
31 D15 3.3V / 5V Bidirectional data to / from CF device.
CMOS

I
32 -CS1 3.3V / 3.3V CF Device Chip Select for 3F0h to 3FFh range.
CMOS
Voltage Sense Signals. VS1# is grounded on the
O Card and sensed by the Host so that the
33 -VS1 3.3V / 5V PD to GND
CMOS CompactFlash Storage Card or CF+ Card CIS
can be read at 3.3 volts.
O
34 -IORD 3.3V / 3.3V I/O read line from CF device.
CMOS
I I/O write line to CF device. Data latched on
35 -IOWR 3.3V / 3.3V
CMOS trailing (rising) edge.

I In True IDE Mode, this input signal is not used

36 -WE 3.3V / 5V N/A
CMOS and should be connected to VCC by the host.

O
37 INTRQ 3.3V / 5V Interrupt request from CF device.
CMOS
38 VCC Power 3.3V / 5V +5 V, +3.3 V power
This internally pulled up signal is used to
configure this device as a Master or a Slave when
configured in the True IDE Mode.
I Integrated PU 10KΩ to
39 -CSEL 3.3V / 5V When this pin is grounded, this device is
CMOS 5V
configured as a Master.
When the pin is open, this device is configured as
a Slave.
Voltage Sense Signals. VS2# is reserved by
O
40 -VS2 3.3V / 5V PCMCIA for a secondary voltage and is not N/A
CMOS
connected on the Card.
 I
41 -RESET 3.3V / 3.3V Reset input to CF device, active low.
CMOS
O CF device I/O ready output. Pulled low by the CF
42 IORDY 3.3V / 5V
CMOS device to extend the cycle.
O CF Device DMA Request. It is asserted by the
43 DMARQ 3.3V / 5V
CMOS CF device to request a data transfer.
I
44 -DMACK 3.3V / 3.3V CF Device DMA Acknowledge.
CMOS

In the True IDE Mode, this input/output is the Disk

OD Integrated PU 10KΩ to
45 -DASP 3.3V / 5V Active/Slave Present signal in the Master/Slave
CMOS 5V
handshake protocol.

In the True IDE Mode, this input / output is the

O Integrated PU 10KΩ to
46 -PDIAG 3.3V / 5V Pass Diagnostic signal in the Master / Slave
CMOS 5V
handshake protocol.

I/O
47 D08 3.3V / 5V Bidirectional data to / from CF device.
CMOS

I/O
48 D09 3.3V / 5V Bidirectional data to / from CF device.
CMOS

I/O
49 D10 3.3V / 5V Bidirectional data to / from CF device.
CMOS

50 GND Power Return current path, Ground

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
SOM-5894 A101-4
Baseboard
 N/C, SATA to IDE
Bridge like ACARD
ARC 772 is suggested
in Baseboard
 Baseboard
Connect to COME pin
D18 IDE_RESET#
Connect to GND
Connect 22-33Ω in
series near connector to
COME pin C2 IDE_D7

Connect 22-33Ω in
series near connector to
COME pin C6 IDE_D8

Connect 22-33Ω in
series near connector to
COME pin C3 IDE_D6

Connect 22-33Ω in
series near connector to
COME pin C7 IDE_D9

Connect 22-33Ω in
series near connector to
COME pin D2 IDE_D5

Connect 22-33Ω in
series near connector to
COME pin D3 IDE_D10

Connect 22-33Ω in
series near connector to
COME pin D6 IDE_D4

Connect 22-33Ω in
series near connector to
COME pin D4 IDE_D11

Connect 22-33Ω in
series near connector to
COME pin C4 IDE_D3
Connect 22-33Ω in
series near connector to
COME pin D5 IDE_D12

Connect 22-33Ω in
series near connector to
COME pin C8 IDE_D2

Connect 22-33Ω in
series near connector to
COME pin C9 IDE_D13

Connect 22-33Ω in
series near connector to
COME pin C10 IDE_D1

Connect 22-33Ω in
series near connector to
COME pin C12
IDE_D14

Connect 22-33Ω in
series near connector to
COME pin D7 IDE_D0

Connect 22-33Ω in
series near connector to
COME pin C5 IDE_D15

Connect to GND
N/C
Connect to COME pin
D8 IDE_REQ
Connect to GND
Connect to COME pin
D9 IDE_IOW#
Connect to GND
Connect to COME pin
C14 IDE_IOR#
Connect to GND
Connect to COME pin
C13 IDE_IORDY

PD 470Ω to GND

Connect to COME pin

D10 IDE_ACK#
Connect to GND
Connect to COME pin
D12 IDE_IRQ

N/C

Connect to COME pin

D14 IDE_A1

Connect to COME pin

D77 IDE_CBLID#

Connect to COME pin

D13 IDE_A0
Connect to COME pin
D15 IDE_A2
Connect to COME pin
D16 IDE_CS1#
Connect to COME pin
D17 IDE_CS3#

Connect LED and

current limiting resistors
300 to 330 Ω to 3.3V

Connect to GND

Baseboard
Connect to GND

Connect 22-33Ω in
series near connector to
COME pin C4 IDE_D3
Connect 22-33Ω in
series near connector to
COME pin D6 IDE_D4

Connect 22-33Ω in
series near connector to
COME pin D2 IDE_D5

Connect 22-33Ω in
series near connector to
COME pin C3 IDE_D6

Connect 22-33Ω in
series near connector to
COME pin C2 IDE_D7

Connect to COME pin

D16 IDE_CS1#

PD 0Ω to GND

PD 0Ω to GND

PD 0Ω to GND

PD 0Ω to GND
PD 0Ω to GND

Connect to 5V or 3.3V

PD 0Ω to GND

PD 0Ω to GND

PD 0Ω to GND

PD 0Ω to GND

Connect to COME pin

D15 IDE_A2
Connect to COME pin
D14 IDE_A1
Connect to COME pin
D13 IDE_A0

Connect 22-33Ω in
series near connector to
COME pin D7 IDE_D0

Connect 22-33Ω in
series near connector to
COME pin C10 IDE_D1
Connect 22-33Ω in
series near connector to
COME pin C8 IDE_D2

N/C

PD 1KΩ to GND

PD 1KΩ to GND

Connect 22-33Ω in
series near connector to
COME pin D4 IDE_D11

Connect 22-33Ω in
series near connector to
COME pin D5 IDE_D12

Connect 22-33Ω in
series near connector to
COME pin C9 IDE_D13
Connect 22-33Ω in
series near connector to
COME pin C12
IDE_D14

Connect 22-33Ω in
series near connector to
COME pin C5 IDE_D15

Connect to COME pin

D17 IDE_CS3#

PD 0Ω to GND and PU
10K(NL) to 3.3V

Connect to COME pin

C14 IDE_IOR#
Connect to COME pin
D9 IDE_IOW#

PU 10KΩ to 3.3V

Connect to COME pin

D12 IDE_IRQ
Connect to 5V or 3.3V

Master - PD 10KΩ
Slave - Floating

N/C
Connect to COME pin
D18 IDE_RESET#
Connect to COME pin
C13 IDE_IORDY
Connect to COME pin
D8 IDE_REQ
Connect to COME pin
D10 IDE_ACK#

Connect LED to current

limiting resistors 300 to
330 Ω to 3.3V

Connect to COME pin

D77 IDE_CBLID#

Connect 22-33Ω in
series near connector to
COME pin C6 IDE_D8

Connect 22-33Ω in
series near connector to
COME pin C7 IDE_D9

Connect 22-33Ω in
series near connector to
COME pin D3 IDE_D10

Connect to GND
 PCI Express Lanes Pwr Rail /
Pin No. Pin Type Description Baseboard
(General Purpose) Tolerance

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE0 x1 device
A68 PCIE_TX0+
PERp0.
Slot - Connect to PCIE0
x1 Conn pin B14 PETp0.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE0 x1 device
A69 PCIE_TX0-
PERn0.
Slot - Connect to PCIE0
x1 Conn pin B15 PETn0
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE1 x1 device
A64 PCIE_TX1+
PERp0.
Slot - Connect to PCIE1
x1 Conn pin B14 PETp0.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE1 x1 device
A65 PCIE_TX1-
PERn0.
Slot - Connect to PCIE1
x1 Conn pin B15 PETn0
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE2 x1 device
A61 PCIE_TX2+
PERp0.
Slot - Connect to PCIE2
x1 Conn pin B14 PETp0.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE2 x1 device
A62 PCIE_TX2-
PERn0.
Slot - Connect to PCIE2
x1 Conn pin B15 PETn0
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE3 x1 device
A58 PCIE_TX3+
PERp0.
Slot - Connect to PCIE3
x1 Conn pin B14 PETp0.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE3 x1 device
A59 PCIE_TX3-
PERn0.
Slot - Connect to PCIE3
x1 Conn pin B15 PETn0
N/C if not used.

O AC coupled PCI Express Differential Transmit Pairs 0 through

PCIE on module 7

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE4 x1 device
A55 PCIE_TX4+
PERp0.
Slot - Connect to PCIE4
x1 Conn pin B14 PETp0.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE4 x1 device
A56 PCIE_TX4-
PERn0.
Slot - Connect to PCIE4
x1 Conn pin B15 PETn0
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE5 x1 device
A52 PCIE_TX5+
PERp0.
Slot - Connect to PCIE5
x1 Conn pin B14 PETp0.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE5 x1 device
A53 PCIE_TX5-
PERn0.
Slot - Connect to PCIE5
x1 Conn pin B15 PETn0
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE6 x1 device
D19 PCIE_TX6+
PERp0.
Slot - Connect to PCIE6
x1 Conn pin B14 PETp0.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE6 x1 device
D20 PCIE_TX6-
PERn0.
Slot - Connect to PCIE6
x1 Conn pin B15 PETn0
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE7 x1 device
D22 PCIE_TX7+
PERp0.
Slot - Connect to PCIE7
x1 Conn pin B14 PETp0.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE7 x1 device
D23 PCIE_TX7-
PERn0.
Slot - Connect to PCIE7
x1 Conn pin B15 PETn0
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE0 x1
device PETp0.
B68 PCIE_RX0+
Slot - Connect to PCIE0
x1 Conn pin A16
PERp0.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE0 x1
device PETn0.
B69 PCIE_RX0-
Slot - Connect to PCIE0
x1 Conn pin A17
PERn0.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE1 x1
device PETp0.
B64 PCIE_RX1+
Slot - Connect to PCIE1
x1 Conn pin A16
PERp0.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE1 x1
device PETn0.
B65 PCIE_RX1-
Slot - Connect to PCIE1
x1 Conn pin A17
PERn0.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE2 x1
device PETp0.
B61 PCIE_RX2+
Slot - Connect to PCIE2
x1 Conn pin A16
PERp0.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE2 x1
device PETn0.
B62 PCIE_RX2-
Slot - Connect to PCIE2
x1 Conn pin A17
PERn0.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE3 x1
device PETp0.
B58 PCIE_RX3+
Slot - Connect to PCIE3
x1 Conn pin A16
PERp0.
N/C if not used.

I AC coupled off PCI Express Differential Receive Pairs 0 through

PCIE module 5
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE3 x1
device PETn0.
B59 PCIE_RX3-
Slot - Connect to PCIE3
x1 Conn pin A17
PERn0.
N/C if not used.
I AC coupled off PCI Express Differential Receive Pairs 0 through
PCIE module 5
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE4 x1
device PETp0.
B55 PCIE_RX4+
Slot - Connect to PCIE4
x1 Conn pin A16
PERp0.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE4 x1
device PETn0.
B56 PCIE_RX4-
Slot - Connect to PCIE4
x1 Conn pin A17
PERn0.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE5 x1
device PETp0.
B52 PCIE_RX5+
Slot - Connect to PCIE5
x1 Conn pin A16
PERp0.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE5 x1
device PETn0.
B53 PCIE_RX5-
Slot - Connect to PCIE5
x1 Conn pin A17
PERn0.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE6 x1
device PETp0.
C19 PCIE_RX6+
Slot - Connect to PCIE6
x1 Conn pin A16
PERp0.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE6 x1
device PETn0.
C20 PCIE_RX6-
Slot - Connect to PCIE6
x1 Conn pin A17
PERn0.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE7 x1
device PETp0.
C22 PCIE_RX7+
Slot - Connect to PCIE7
x1 Conn pin A16
PERp0.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE7 x1
device PETn0.
C23 PCIE_RX7-
Slot - Connect to PCIE7
x1 Conn pin A17
PERn0.
N/C if not used.

PCI Express Lanes Pwr Rail /

Pin No. Pin Type Description Baseboard
(General Purpose) Tolerance

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp0.
D52 PCIE_TX16+
Slot - Connect to PCIe
x16 Conn pin B14
PETp0.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn0.
D53 PCIE_TX16-
Slot - Connect to PCIe
x16 Conn pin B15
PETn0.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp1.
D55 PCIE_TX17+
Slot - Connect to PCIe
x16 Conn pin B19
PETp1.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn1
D56 PCIE_TX17-
Slot - Connect to PCIe
x16 Conn pin B20
PETn1
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp2.
D58 PCIE_TX18+
Slot - Connect to PCIe
x16 Conn pin B23
PETp2.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn2.
D59 PCIE_TX18-
Slot - Connect to PCIe
x16 Conn pin B24
PETn2.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn2.
D61 PCIE_TX19+
Slot - Connect to PCIe
x16 Conn pin B27
PETp3.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn3.
D62 PCIE_TX19-
Slot - Connect to PCIe
x16 Conn pin B28
PETn3.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp4.
D65 PCIE_TX20+
Slot - Connect to PCIe
x16 Conn pin B33
PETp4.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn4.
D66 PCIE_TX20-
Slot - Connect to PCIe
x16 Conn pin B34
PETn4.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp5.
D68 PCIE_TX21+
Slot - Connect to PCIe
x16 Conn pin B37
PETp5.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn5.
D69 PCIE_TX21-
Slot - Connect to PCIe
x16 Conn pin B38
PETn5.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp6.
D71 PCIE_TX22+
Slot - Connect to PCIe
x16 Conn pin B41
PETp6.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn6.
D72 PCIE_TX22-
Slot - Connect to PCIe
x16 Conn pin B42
PETn6.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp7.
D74 PCIE_TX23+
Slot - Connect to PCIe
x16 Conn pin B45
PETp7.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn7.
D75 PCIE_TX23-
Slot - Connect to PCIe
x16 Conn pin B46
PETn7.
N/C if not used.
PCI Express Differential Transmit Pairs 16
O AC coupled on
through 31
PCIE module
These are same lines as PEG_TX[0:15] + and -
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp8.
D78 PCIE_TX24+
Slot - Connect to PCIe
x16 Conn pin B50
PETp8.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp8.
D79 PCIE_TX24-
Slot - Connect to PCIe
x16 Conn pin B50
PETp8.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp9.
D81 PCIE_TX25+
Slot - Connect to PCIe
x16 Conn pin B54
PETp9.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn9.
D82 PCIE_TX25-
Slot - Connect to PCIe
x16 Conn pin B55
PETn9.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D85 PCIE_TX26+ PERp10.
Slot - Connect to PCIe
x16 Conn pin B58
PETp10.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D86 PCIE_TX26- PERn10.
Slot - Connect to PCIe
x16 Conn pin B59
PETn10.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D88 PCIE_TX27+ PERp11.
Slot - Connect to PCIe
x16 Conn pin B62
PETp11.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D89 PCIE_TX27- PERn11.
Slot - Connect to PCIe
x16 Conn pin B63
PETn11.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D91 PCIE_TX28+ PERp12.
Slot - Connect to PCIe
x16 Conn pin B66
PETp12.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D92 PCIE_TX28- PERn12.
Slot - Connect to PCIe
x16 Conn pin B67
PETn12.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D94 PCIE_TX29+ PERp13.
Slot - Connect to PCIe
x16 Conn pin B70
PETp13.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D95 PCIE_TX29- PERn13.
Slot - Connect to PCIe
x16 Conn pin B71
PETn13.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D98 PCIE_TX30+ PERp14.
Slot - Connect to PCIe
x16 Conn pin B74
PETp14.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D99 PCIE_TX30- PERn14.
Slot - Connect to PCIe
x16 Conn pin B75
PETn14.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D101 PCIE_TX31+ PERp15.
Slot - Connect to PCIe
x16 Conn pin B78
PETp15.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D102 PCIE_TX31- PERn15.
Slot - Connect to PCIe
x16 Conn pin B79
PETn15.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp0.
C52 PCIE_RX16+
Slot - Connect to PCIe
x16 Conn pin A16
PERp0.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn0.
C53 PCIE_RX16-
Slot -Connect to PCIe
x16 Conn pin A17
PERn0.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp1.
C55 PCIE_RX17+
Slot - Connect to PCIe
x16 Conn pin A21
PERp1.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn1.
C56 PCIE_RX17-
Slot - Connect to PCIe
x16 Conn pin A22
PERn1.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp2.
C58 PCIE_RX18+
Slot - Connect to PCIe
x16 Conn pin A25
PERp2.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn2.
C59 PCIE_RX18-
Slot - Connect to PCIe
x16 Conn pin A26
PERn2.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp3.
C61 PCIE_RX19+
Slot - Connect to PCIe
x16 Conn pin A29
PERp3.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn3.
C62 PCIE_RX19-
Slot - Connect to PCIe
x16 Conn pin A30
PERn3.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp4.
C65 PCIE_RX20+
Slot - Connect to PCIe
x16 Conn pin A35
PERp4.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn4.
C66 PCIE_RX20-
Slot - Connect to PCIe
x16 Conn pin A36
PERn4.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp5.
C68 PCIE_RX21+
Slot - Connect to PCIe
x16 Conn pin A39
PERp5.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn5.
C69 PCIE_RX21-
Slot - Connect to PCIe
x16 Conn pin A40
PERn5.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp6.
C71 PCIE_RX22+
Slot - Connect to PCIe
x16 Conn pin A43
PERp6.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn6.
C72 PCIE_RX22-
Slot - Connect to PCIe
x16 Conn pin A44
PERn6.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp7.
C74 PCIE_RX23+
Slot - Connect to PCIe
x16 Conn pin A47
PERp7.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn7.
C75 PCIE_RX23-
Slot - Connect to PCIe
x16 Conn pin A48
PERn7.
PCI Express Differential Receive Pairs 16 N/C if not used.
I AC coupled off through 31
PCIE module These are the same lines as PEG_RX[0:15] +
Device - Connect AC
and -
Coupling cap 0.22uF
near COME to PCIe x16
device PETp8.
C78 PCIE_RX24+
Slot - Connect to PCIe
x16 Conn pin A52
PERp8.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn8.
C79 PCIE_RX24-
Slot - Connect to PCIe
x16 Conn pin A53
PERn8.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp9.
C81 PCIE_RX25+
Slot - Connect to PCIe
x16 Conn pin A56
PERp9.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn9.
C82 PCIE_RX25-
Slot - Connect to PCIe
x16 Conn pin A57
PERn9.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp10.
C85 PCIE_RX26+
Slot - Connect to PCIe
x16 Conn pin A60
PERp10.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn10.
C86 PCIE_RX26-
Slot - Connect to PCIe
x16 Conn pin A61
PERn10.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp11.
C88 PCIE_RX27+
Slot - Connect to PCIe
x16 Conn pin A64
PERp11.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn11.
C89 PCIE_RX27-
Slot - Connect to PCIe
x16 Conn pin A65
PERn11.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp12.
C91 PCIE_RX28+
Slot - Connect to PCIe
x16 Conn pin A68
PERp12.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn12.
C92 PCIE_RX28-
Slot - Connect to PCIe
x16 Conn pin A69
PERn12.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp13.
C94 PCIE_RX29+
Slot - Connect to PCIe
x16 Conn pin A72
PERp13.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn13.
C95 PCIE_RX29-
Slot - Connect to PCIe
x16 Conn pin A73
PERn13.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp14.
C98 PCIE_RX30+
Slot - Connect to PCIe
x16 Conn pin A76
PERp14.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn14.
C99 PCIE_RX30-
Slot - Connect to PCIe
x16 Conn pin A77
PERn14.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp15.
C101 PCIE_RX31+
Slot - Connect to PCIe
x16 Conn pin A80
PERp15.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn15.
C102 PCIE_RX31-
Slot - Connect to PCIe
x16 Conn pin A81
PERn15.
N/C if not used.
 Module has integrated
series resistor
Device - Connect to
PCIe device REFCLK+.
Slot - Connect to PCIe
Conn pin A13
A88 PCIE_CLK_REF+ REFCLK+.
*Connect to PCIe Clock
Buffer(DB400/800) input
to provide PCIe clocks
output for more than one
PCIe devices or slots.
N/C if not used.

O
Reference clock output for all PCI Express and
CMOS PCIE
PCI Express Graphics lanes.
PCIE

Module has integrated

series resistor
Device - Connect to
PCIe device REFCLK-
Slot - Connect to PCIe
Conn pin A14 REFCLK-.
A89 PCIE_CLK_REF-
*Connect to PCIe Clock
Buffer(DB400/800) input
to provide PCIe clocks
output for more than one
PCIe devices or slots.
N/C if not used.

PCI Express Lanes Pwr Rail /

Pin No. Pin Type Description Baseboard
( x16 Graphics ) Tolerance
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp0.
D52 PEG_TX0+
Slot - Connect to PCIe
x16 Conn pin B14
PETp0.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn0.
D53 PEG_TX0-
Slot - Connect to PCIe
x16 Conn pin B15
PETn0.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp1.
D55 PEG_TX1+
Slot - Connect to PCIe
x16 Conn pin B19
PETp1.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn1
D56 PEG_TX1-
Slot - Connect to PCIe
x16 Conn pin B20
PETn1
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp2.
D58 PEG_TX2+
Slot - Connect to PCIe
x16 Conn pin B23
PETp2.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn2.
D59 PEG_TX2-
Slot - Connect to PCIe
x16 Conn pin B24
PETn2.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn3.
D61 PEG_TX3+
Slot - Connect to PCIe
x16 Conn pin B27
PETp3.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn3.
D62 PEG_TX3-
Slot - Connect to PCIe
x16 Conn pin B28
PETn3.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp4.
D65 PEG_TX4+
Slot - Connect to PCIe
x16 Conn pin B33
PETp4.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn4.
D66 PEG_TX4-
Slot - Connect to PCIe
x16 Conn pin B34
PETn4.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp5.
D68 PEG_TX5+
Slot - Connect to PCIe
x16 Conn pin B37
PETp5.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn5.
D69 PEG_TX5-
Slot - Connect to PCIe
x16 Conn pin B38
PETn5.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp6.
D71 PEG_TX6+
Slot - Connect to PCIe
x16 Conn pin B41
PETp6.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn6.
D72 PEG_TX6-
Slot - Connect to PCIe
x16 Conn pin B42
PETn6.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp7.
D74 PEG_TX7+
Slot - Connect to PCIe
x16 Conn pin B45
PETp7.
N/C if not used.

PCI Express Graphics transmit differential pairs.

Some of these are multiplexed with SDVO lines
(see SDVO section) in Type 2-5. In Type 6 SDVO
O AC coupled on
pins are on Digital Display InterfaceDDI 1.(refer to
PCIE module
Section 4.4.5 “SDVO (Types 2-5)“).
These are the same lines as PCIE_TX[16:31] +
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn7.
D75 PEG_TX7-
Slot - Connect to PCIe
x16 Conn pin B46
PCI Express Graphics transmit differential pairs. PETn7.
Some of these are multiplexed with SDVO lines N/C if not used.
(see SDVO section) in Type 2-5. In Type 6 SDVO
O AC coupled on
pins are on Digital Display InterfaceDDI 1.(refer to
PCIE module
Section 4.4.5 “SDVO (Types 2-5)“).
These are the same lines as PCIE_TX[16:31] + Module has integrated
and - in module pin-out types 4, 5 and 6. AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp8.
D78 PEG_TX8+
Slot - Connect to PCIe
x16 Conn pin B50
PETp8.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn8.
D79 PEG_TX8-
Slot - Connect to PCIe
x16 Conn pin B51
PETn8.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERp9.
D81 PEG_TX9+
Slot - Connect to PCIe
x16 Conn pin B54
PETp9.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device PERn9.
D82 PEG_TX9-
Slot - Connect to PCIe
x16 Conn pin B55
PETn9.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D85 PEG_TX10+ PERp10.
Slot - Connect to PCIe
x16 Conn pin B58
PETp10.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D86 PEG_TX10- PERn10.
Slot - Connect to PCIe
x16 Conn pin B59
PETn10.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D88 PEG_TX11+ PERp11.
Slot - Connect to PCIe
x16 Conn pin B62
PETp11.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D89 PEG_TX11- PERn11.
Slot - Connect to PCIe
x16 Conn pin B63
PETn11.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D91 PEG_TX12+ PERp12.
Slot - Connect to PCIe
x16 Conn pin B66
PETp12.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D92 PEG_TX12- PERn12.
Slot - Connect to PCIe
x16 Conn pin B67
PETn12.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D94 PEG_TX13+ PERp13.
Slot - Connect to PCIe
x16 Conn pin B70
PETp13.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D95 PEG_TX13- PERn13.
Slot - Connect to PCIe
x16 Conn pin B71
PETn13.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D98 PEG_TX14+ PERp14.
Slot - Connect to PCIe
x16 Conn pin B74
PETp14.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D99 PEG_TX14- PERn14.
Slot - Connect to PCIe
x16 Conn pin B75
PETn14.
N/C if not used.
 Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D101 PEG_TX15+ PERp15.
Slot - Connect to PCIe
x16 Conn pin B78
PETp15.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIe x16 device
D102 PEG_TX15- PERn15.
Slot - Connect to PCIe
x16 Conn pin B79
PETn15.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp0.
C52 PEG_RX0+
Slot - Connect to PCIe
x16 Conn pin A16
PERp0.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn0.
C53 PEG_RX0-
Slot -Connect to PCIe
x16 Conn pin A17
PERn0.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp1.
C55 PEG_RX1+
Slot - Connect to PCIe
x16 Conn pin A21
PERp1.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn1.
C56 PEG_RX1-
Slot - Connect to PCIe
x16 Conn pin A22
PERn1.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp2.
C58 PEG_RX2+
Slot - Connect to PCIe
x16 Conn pin A25
PERp2.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn2.
C59 PEG_RX2-
Slot - Connect to PCIe
x16 Conn pin A26
PERn2.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp3.
C61 PEG_RX3+
Slot - Connect to PCIe
x16 Conn pin A29
PERp3.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn3.
C62 PEG_RX3-
Slot - Connect to PCIe
x16 Conn pin A30
PERn3.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp4.
C65 PEG_RX4+
Slot - Connect to PCIe
x16 Conn pin A35
PERp4.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn4.
C66 PEG_RX4-
Slot - Connect to PCIe
x16 Conn pin A36
PERn4.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp5.
C68 PEG_RX5+
Slot - Connect to PCIe
x16 Conn pin A39
PERp5.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn5.
C69 PEG_RX5-
Slot - Connect to PCIe
x16 Conn pin A40
PERn5.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp6.
C71 PEG_RX6+
Slot - Connect to PCIe
x16 Conn pin A43
PERp6.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn6.
C72 PEG_RX6-
Slot - Connect to PCIe
x16 Conn pin A44
PERn6.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp7.
C74 PEG_RX7+
Slot - Connect to PCIe
x16 Conn pin A47
PERp7.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn7.
C75 PEG_RX7-
Slot - Connect to PCIe
PCI Express Graphics receive differential pairs. x16 Conn pin A48
Some of these are multiplexed with SDVO lines PERn7.
(see SDVO section) in Type 2-5. In Type 6 SDVO N/C if not used.
I AC coupled off
pins.are on Digital Display InterfaceDDI 1 (refer to
PCIE module
Section 4.4.5 “SDVO (Types 2-5)“). Device - Connect AC
These are the same lines as PCIE_RX[16:31] + Coupling cap 0.22uF
and - in module pin-out types 4, 5 and 6. near COME to PCIe x16
device PETp8.
C78 PEG_RX8+
Slot - Connect to PCIe
x16 Conn pin A52
PERp8.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn8.
C79 PEG_RX8-
Slot - Connect to PCIe
x16 Conn pin A53
PERn8.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp9.
C81 PEG_RX9+
Slot - Connect to PCIe
x16 Conn pin A56
PERp9.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn9.
C82 PEG_RX9-
Slot - Connect to PCIe
x16 Conn pin A57
PERn9.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp10.
C85 PEG_RX10+
Slot - Connect to PCIe
x16 Conn pin A60
PERp10.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn10.
C86 PEG_RX10-
Slot - Connect to PCIe
x16 Conn pin A61
PERn10.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp11.
C88 PEG_RX11+
Slot - Connect to PCIe
x16 Conn pin A64
PERp11.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn11.
C89 PEG_RX11-
Slot - Connect to PCIe
x16 Conn pin A65
PERn11.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp12.
C91 PEG_RX12+
Slot - Connect to PCIe
x16 Conn pin A68
PERp12.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn12.
C92 PEG_RX12-
Slot - Connect to PCIe
x16 Conn pin A69
PERn12.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp13.
C94 PEG_RX13+
Slot - Connect to PCIe
x16 Conn pin A72
PERp13.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn13.
C95 PEG_RX13-
Slot - Connect to PCIe
x16 Conn pin A73
PERn13.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp14.
C98 PEG_RX14+
Slot - Connect to PCIe
x16 Conn pin A76
PERp14.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn14.
C99 PEG_RX14-
Slot - Connect to PCIe
x16 Conn pin A77
PERn14.
N/C if not used.
 Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETp15.
C101 PEG_RX15+
Slot - Connect to PCIe
x16 Conn pin A80
PERp15.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn15.
C102 PEG_RX15-
Slot - Connect to PCIe
x16 Conn pin A81
PERn15.
N/C if not used.

Module has integrated

PCI Express Graphics lane reversal input strap.
PU resistor to 3.3V.
Pull low on the carrier board to reverse lane
I Normal - N/C
D54 PEG_LANE_RV# 3.3V / 3.3V order. Be aware that the SDVO lines that share
CMOS Reverse - PD 1KΩ to
this interface do not necessarily reverse order if
GND
this strap is low.
N/C if not used.

Module has integrated

Strap to enable PCI Express x16 external PU resistor to 3.3V.
I
D97 PEG_ENABLE# 3.3V / 3.3V graphics interface. Pull low to disable internal Internal - N/C
CMOS
graphics and enable the x16 PEG interface. PEG - PD 1KΩ to GND
N/C if not used.

4.3.5 General Purpose PCI Express Lanes

The number of available PCI Express lanes varies with the Module Pin-out Type (see refer to Section 5.2 'PCI
Express Link Configuration Guidelines' on page 78). If the Module supports off-Module x16 PCI Express Graphics,
then PCI Express Lanes 16-31 shall be used to implement this.
The PCIE_TX[0:31]+/- signals shall be AC coupled on the Module.
4.3.6 PEG PCI Express Lanes
These signals may be multiplexed with SDVO signals or defined as ordinary PCI Express signals on Module Types
2-5. Type 6 provides dedicated PEG and SDVO channels. The PEG lanes are the same lanes as PCI Express
lanes 16-31.
The PEG_TX[0:15]+/- signals shall be AC coupled on the Module.

5.4.1 PCI Express Insertion Loss Budget with Slot Card

 Figure 5-1: PCI Express Insertion Loss Budget with Slot Card

Table 5.155.8: PCI Express Insertion Loss Budget, 1.25 GHz with Carrier Board Slot Card
Loss (dB)
Segment max. Length Notes
[mm/inches]
3.46 Allowance for 5.15 inches of module trace 3.45 dB loss @ 0.28 dB / GHz /
LA
130/5.15 inch and 1.66 dB crosstalk allowance. Coupling caps not included.

Coupling 1.19 dB loss. From PCI Express Card Electromechanical Spec., Rev. 1.1,
1.19
Caps parameters (LST – LSR). Includes crosstalk allowance of 0.79 dB.

LB 0.25 COM Express® connector at 1.25 GHz measured value: 0.25 dB loss.
4.4 Allowance for 9 inches of Carrier Board trace 4.40 db loss @ 0.28 dB / GHz /
LC
228/9.0 inch and a 1.25 dB crosstalk allowance.
1.25 dB loss. PCI Express Card Electromechanical Spec Rev 1.1 “guard
LD 1.25
band” allowance for slot connector – includes 1.0 dB connector loss.
2.65 dB loss. From PCI Express Card Electromechanical Spec., Rev.
LE 2.65
1.1(without coupling caps; LAR). Implied crosstalk allowance is 1.25 dB.
Total 13.20 13.20 dB loss.
The module transmit and receive insertion loss budgets are different due to the presence of the coupling caps in the
module transmit path. The module transmit path insertion loss budget shall be 4.65 dB (3.46 dB + 1.19 dB). The
module receive path insertion loss budget shall be 3.46 dB. COM Express® connector loss is accounted for
separately.
The Carrier Board transmit and receive insertion loss budgets are the same in this case. The Carrier Board insertion
loss budget shall be 4.40 dB. COM Express® connector and slot card connector losses are accounted for
separately.
The slot card transmit and receive insertion loss budgets are different due to the presence of the coupling caps in
the slot card’s transmit path. The slot card’s transmit path insertion loss budget is 3.84 dB (2.65 dB + 1.19 dB) per
the PCI Express Card Electromechanical Specification Revision 1.1. The slot card’s receive path insertion loss
budget is 2.65 dB per the same specification. Slot card connector loss is accounted for separately.

Table 5.9: PCI Express Insertion Loss Budget, 2.5 GHz with Carrier Board Slot Card
max. Length
Segment Notes
[mm/inches]
Allowance for Module trace. Coupling cap effects included within simulation.
LA 127/5.0

LB COM Express™ connector simulated at 2.5 GHz.

LC 113/4.45 Allowance for Carrier Board.
LD PCI Express Card slot connector simulated at 2.5 GHz.
Slot Card trace length from PCI Express Card Electromagnetical Spec., Rev.
LE 80/3.15
1.1
Total 320/12.6 PCIe GEN2 Data clocked architecture
For “device up” PCIe Gen 2 operation, the Module PCIe maximum trace length is restricted to 5.0 inches and the
Carrier Board maximum trace to 4.45 inches. Shorter lengths will yield additional margin and are encouraged where
possible. Results assumed FR4 dielectrics.
Other dielectrics with lower losses could be considered, but were not simulated.

It should be noted that a use case exists that might result in reduced PCI Express bandwidth. This use case is tied
to Carrier boards with a PCI Express slot (device up). PCI Express Gen 1 and Gen 2 signaling rates use the same
PCI Express connector – there is no mechanical keying mechanism to identify the capabilities of the PCI Express
slot or the PCI Express board plugged into the slot. This can lead to the situation where the Module and PCI
Express board attempt a PCI Express Gen2 signaling rate connection over a Carrier that does not meet the routing
guidelines for Gen 2 signaling rates. In a worst case scenario the devices might connect at Gen2 signaling rate with
a high number of errors impacting the actual data throughput. It should be noted that there is a Carrier EEPROM
which would allow the Module to determine the Carrier board capabilities but this is not a requirement in COM.0.
5.4.2 PCI Express Insertion Loss Budget with Carrier Board PCIE Device
The insertion losses previously allowed for the slot card and slot card connector are re-allocated for use on the
Carrier Board, allowing longer Carrier Board trace lengths and more Carrier Board design flexibility. The module
and COM Express® connector loss budgets remain the same.
Figure 5-2: PCI Express Insertion Loss Budget with Carrier Board PCIE Device

Table 5.165.10: PCI Express Insertion Loss Budget, 1.25 GHz with Carrier Board PCIE Device
Loss (dB)
Segment max. Length Notes
[mm/inches]

3.46 Allowance for 5.15 inches of Module trace 3.46 dB loss @ 0.28 dB / GHz /
LA
131/5.15 inch and 1.66 dB crosstalk allowance. Coupling caps not included.

Coupling 1.19 dB loss. From PCI Express Card Electromechanical Spec., Rev. 1.1,
1.19
Caps parameters (LST– LSR). Includes crosstalk allowance of 0.79 dB.
LB 0.25 COM Express®connector at 1.25 GHz measured value: 0.25 dB loss
8.3 Allowance for 15.85 inches of Carrier Board trace 8.30 dB loss @ 0.28 dB /
LC
402/15.85 GHz / inch and a 2.75 dB crosstalk allowance.
Total 13.20 13.20 dB loss
The module transmit and receive insertion loss budgets are different due to the presence of the coupling caps in the
module transmit path. The module transmit path insertion loss budget shall be 4.65 dB (3.46 dB + 1.19 dB). The
module receive path insertion loss budget shall be 3.46 dB. COM Express® connector loss is accounted for
separately.

The Carrier Board transmit and receive insertion loss budgets are different due to the presence of the coupling caps
in the Carrier Board transmit path. The Carrier Board transmit path insertion loss budget shall be 9.49 dB (8.30 dB +
1.19 dB). The Carrier Board receive path insertion loss shall be 8.30 dB. COM Express® connector loss is
accounted for separately.
Table 5.11: PCI Express Insertion Loss Budget, 2.5 GHz with Carrier Board PCIE Device
max. Length
Segment Notes
[mm/inches]
Allowance for Module trace. Coupling cap effects included within simulation.
LA 127/5.0
LB COM Express™ connector simulated at 2.5 GHz.
LC 203/8.0 Allowance for Carrier Board trace.
Total 330/13.0 PCIe GEN2 Data clocked architecture
For “device down” PCIe Gen 2 operation, the Module PCIe maximum trace length is restricted to 5.0 inches and the
Carrier Board maximum trace to 8.0 inches. Shorter lengths will yield additional margin and are encouraged where
possible. Results assumed FR4 dielectrics. Other dielectrics with lower losses could be considered, but were not
simulated.

Pwr Rail /
Pin No. PCIe/PEG Slot Pin Type Description Add-in card
Tolerance
Side B
B1 +12V Power 12 V power Connect to 12V power
B2 +12V Power 12 V power Connect to 12V power
B3 +12V Power 12 V power Connect to 12V power
B4 GND Power Ground Connect to GND
 3.3VSB SMBus device
- Connect to SMBCLK of
SMBus device.
3.3V SMBus device -
Connect 3.3V isolation
circuit controlled by
+3.3V to SMBCLK of
SMBus device.
I/O OD 3.3V Suspend 5VSB SMBus device -
B5 SMCLK SMBus (System Management Bus) clock
CMOS / 3.3V Connect 5V Level
Shifter to SMBCLK of
SMBus device.
5V SMBus device -
Connect 5V isolation
circuit controlled by
+3.3V to SMBCLK of
SMBus device
N/C if not used.
 3.3VSB SMBus device
- Connect to SMBDAT of
SMBus device.
3.3V SMBus device -
Connect 3.3V isolation
circuit controlled +3.3V
to SMBDAT of SMBus
device.
I/O OD 3.3V Suspend 5VSB SMBus device -
B6 SMDAT SMBus (System Management Bus) data
CMOS / 3.3V Connect 5V Level
Shifter to SMBDAT of
SMBus device.
5V SMBus device -
Connect 5V isolation
circuit controlled by
+3.3V to SMBDAT of
SMBus device
N/C if not used.

B7 GND Power Ground Connect to GND

B8 +3.3V Power 3.3 V power Connect to 3.3V power

I Connect to JTAG
B9 JTAG1 3.3V / 3.3V TRST# (Test Reset) resets the JTAG interface
CMOS TRST# of Device

Connect to 3.3V standby

B10 3.3Vaux Power 3.3 V auxiliary power
power

O OD 3.3V Suspend Connect to WAKE# pin

B11 WAKE# Signal for Link reactivation
CMOS / 3.3V of device.

Mechanical key
B12 RSVD Reserved N/C
B13 GND Power Ground Connect to GND

I AC coupled on Connect to PERp0 of

B14 PETp0
PCIe module device.

Transmitter differential pair, Lane 0

I AC coupled on Connect to PERn0 of

B15 PETn0
PCIe module device.

B16 GND Power Ground Connect to GND

Connect to pin A1
O OD PRSNT1# for x1 add-in
B17 PRSNT2# 3.3V / 3.3V Hot-Plug presence detect
CMOS card.
N/C if not used

B18 GND Power Ground Connect to GND

End of the x1 connector

I AC coupled on Connect to PERp1 of

B19 PETp1
PCIe module device.

Transmitter differential pair, Lane 1

 Transmitter differential pair, Lane 1

I AC coupled on Connect to PERn1 of

B20 PETn1
PCIe module device.

B21 GND Power Ground Connect to GND

B22 GND Power Ground Connect to GND

I AC coupled on Connect to PERp2 of

B23 PETp2
PCIe module device.

Transmitter differential pair, Lane 2

I AC coupled on Connect to PERn2 of

B24 PETn2
PCIe module device.

B25 GND Power Ground Connect to GND

B26 GND Power Ground Connect to GND
 I AC coupled on Connect to PERp3 of
B27 PETp3
PCIe module device.

Transmitter differential pair, Lane 3

I AC coupled on Connect to PERn3 of

B28 PETn3
PCIe module device.

B29 GND Power Ground Connect to GND

B30 RSVD Reserved N/C

Connect to pin A1
O OD PRSNT1# for x4 add-in
B31 PRSNT2# 3.3V / 3.3V Hot-Plug presence detect
CMOS card.
N/C if not used.

B32 GND Power Ground Connect to GND

End of the x4 connector
 I AC coupled on Connect to PERp4 of
B33 PETp4
PCIe module device.

Transmitter differential pair, Lane 4

I AC coupled on Connect to PERn4 of

B34 PETn4
PCIe module device.

B35 GND Power Ground Connect to GND

B36 GND Power Ground Connect to GND

I AC coupled on Connect to PERp5 of

B37 PETp5
PCIe module device.

Transmitter differential pair, Lane 5

 Transmitter differential pair, Lane 5

I AC coupled on Connect to PERn5 of

B38 PETn5
PCIe module device.

B39 GND Power Ground Connect to GND

B40 GND Power Ground Connect to GND

I AC coupled on Connect to PERp6 of

B41 PETp6
PCIe module device.

Transmitter differential pair, Lane 6

I AC coupled on Connect to PERn6 of

B42 PETn6
PCIe module device.

B43 GND Power Ground Connect to GND

B44 GND Power Ground Connect to GND
 I AC coupled on Connect to PERp7 of
B45 PETp7
PCIe module device.

Transmitter differential pair, Lane 7

I AC coupled on Connect to PERn7 of

B46 PETn7
PCIe module device.

B47 GND Power Ground Connect to GND

Connect to pin A1
O OD PRSNT1# for x8 add-in
B48 PRSNT2# 3.3V / 3.3V Hot-Plug presence detect
CMOS card.
N/C if not used.

B49 GND Power Ground Connect to GND

End of the x8 connector

I AC coupled on Connect to PERp8 of

B50 PETp8
PCIe module device.

Transmitter differential pair, Lane 8

 Transmitter differential pair, Lane 8

I AC coupled on Connect to PERn8 of

B51 PETn8
PCIe module device.

B52 GND Power Ground Connect to GND

B53 GND Power Ground Connect to GND

I AC coupled on Connect to PERp9 of

B54 PETp9
PCIe module device.

Transmitter differential pair, Lane 9

I AC coupled on Connect to PERn9 of

B55 PETn9
PCIe module device.

B56 GND Power Ground Connect to GND

B57 GND Power Ground Connect to GND

I AC coupled on Connect to PERp10 of

B58 PETp10
PCIe module device.

Transmitter differential pair, Lane 10

I AC coupled on Connect to PERn10 of

B59 PETn10
PCIe module device.

B60 GND Power Ground Connect to GND

B61 GND Power Ground Connect to GND
 I AC coupled on Connect to PERp11 of
B62 PETp11
PCIe module device.

Transmitter differential pair, Lane 11

I AC coupled on Connect to PERn11 of

B63 PETn11
PCIe module device.

B64 GND Power Ground Connect to GND

B65 GND Power Ground Connect to GND

I AC coupled on Connect to PERp12 of

B66 PETp12
PCIe module device.

Transmitter differential pair, Lane 12

I AC coupled on Connect to PERn12 of

B67 PETn12
PCIe module device.

B68 GND Power Ground Connect to GND

B69 GND Power Ground Connect to GND

I AC coupled on Connect to PERp13 of

B70 PETp13
PCIe module device.

Transmitter differential pair, Lane 13

I AC coupled on Connect to PERn13 of

B71 PETn13
PCIe module device.
B72 GND Power Ground Connect to GND
B73 GND Power Ground Connect to GND

I AC coupled on Connect to PERp14 of

B74 PETp14
PCIe module device.

Transmitter differential pair, Lane 14

I AC coupled on Connect to PERn14 of

B75 PETn14
PCIe module device.

B76 GND Power Ground Connect to GND

B77 GND Power Ground Connect to GND

I AC coupled on Connect to PERp15 of

B78 PETp15
PCIe module device.

Transmitter differential pair, Lane 15

I AC coupled on Connect to PERn15 of

B79 PETn15
PCIe module device.

B80 GND Power Ground Connect to GND

Connect to pin A1
O OD PRSNT1# for x16 add-in
B81 PRSNT2#/PEG_ENABLE# 3.3V / 3.3V Hot-Plug presence detect
CMOS card.
N/C if not used.

B82 RSVD Reserved N/C

 End of the x16 connector
Side A
Connect to
Pin B17 PRSNT2# for
x1 add-in card.
Pin B31 PRSNT2# for
O OD
A1 PRSNT1# 3.3V / 3.3V Hot-Plug presence detect x4 add-in card.
CMOS
Pin B48 PRSNT2# for
x8 add-in card.
Pin B81 PRSNT2# for
x16 add-in card.
A2 +12V Power 12 V power Connect to 12V power
A3 +12V Power 12 V power Connect to 12V power
A4 GND Power Ground Connect to GND

I Connect to JTAG TCK

A5 JTAG2 3.3V / 3.3V TCK (Test Clock), clock input for JTAG interface
CMOS of Device

I Connect to JTAG TDI of

A6 JTAG3 3.3V / 3.3V TDI (Test Data Input)
CMOS Device

O Connect to JTAG TDO

A7 JTAG4 3.3V / 3.3V TDO (Test Data Output)
CMOS of Device

I Connect to JTAG TMS

A8 JTAG5 3.3V / 3.3V TMS (Test Mode Select)
CMOS of Device

A9 +3.3V Power 3.3 V power Connect to 3.3V power

A10 +3.3V Power 3.3 V power Connect to 3.3V power
 I 3.3V Suspend Connect to PERST# of
A11 PERST# Fundamental reset
CMOS / 3.3V device.

Mechanical key
A12 GND Power Ground Connect to GND

I Connect to REFCLK+ of
A13 REFCLK+ PCIE
PCIe device.

Reference clock (differential pair)

I Connect to REFCLK- of
A14 REFCLK- PCIE
PCIe device.

A15 GND Power Ground Connect to GND

Connect AC Coupling
O AC coupled off
A16 PERp0 cap 0.1uF to PETp0 of
PCIE module
device.

Receiver differential pair, Lane 0

 Receiver differential pair, Lane 0

Connect AC Coupling
O AC coupled off
A17 PERn0 cap 0.1uF to PETn0 of
PCIE module
device.

A18 GND Power Ground Connect to GND

End of the x1 connector
A19 RSVD N/C
A20 GND Power Ground Connect to GND

Connect AC Coupling
O AC coupled off
A21 PERp1 cap 0.1uF to PETp1 of
PCIE module
device.

Receiver differential pair, Lane 1

Connect AC Coupling
O AC coupled off
A22 PERn1 cap 0.1uF to PETn1 of
PCIE module
device.

A23 GND Power Ground Connect to GND

A24 GND Power Ground Connect to GND

Connect AC Coupling
O AC coupled off
A25 PERp2 cap 0.1uF to PETp2 of
PCIE module
device.

Receiver differential pair, Lane 2

 Receiver differential pair, Lane 2

Connect AC Coupling
O AC coupled off
A26 PERn2 cap 0.1uF to PETn2 of
PCIE module
device.

A27 GND Power Ground Connect to GND

A28 GND Power Ground Connect to GND

Connect AC Coupling
O AC coupled off
A29 PERp3 cap 0.1uF to PETp3 of
PCIE module
device.

Receiver differential pair, Lane 3

Connect AC Coupling
O AC coupled off
A30 PERn3 cap 0.1uF to PETn3 of
PCIE module
device.

A31 GND Power Ground Connect to GND

A32 RSVD Reserved N/C
End of the x4 connector
A33 RSVD Reserved N/C
A34 GND Power Ground Connect to GND

Connect AC Coupling
O AC coupled off
A35 PERp4 cap 0.1uF to PETp4 of
PCIE module
device.

Receiver differential pair, Lane 4

 Receiver differential pair, Lane 4

Connect AC Coupling
O AC coupled off
A36 PERn4 cap 0.1uF to PETn4 of
PCIE module
device.

A37 GND Power Ground Connect to GND

A38 GND Power Ground Connect to GND

Connect AC Coupling
O AC coupled off
A39 PERp5 cap 0.1uF to PETp5 of
PCIE module
device.

Receiver differential pair, Lane 5

Connect AC Coupling
O AC coupled off
A40 PERn5 cap 0.1uF to PETn5 of
PCIE module
device.

A41 GND Power Ground Connect to GND

A42 GND Power Ground Connect to GND

Connect AC Coupling
O AC coupled off
A43 PERp6 cap 0.1uF to PETp6 of
PCIE module
device.

Receiver differential pair, Lane 6

Connect AC Coupling
O AC coupled off
A44 PERn6 cap 0.1uF to PETn6 of
PCIE module
device.

A45 GND Power Ground Connect to GND

A46 GND Power Ground Connect to GND

Connect AC Coupling
O AC coupled off
A47 PERp7 cap 0.1uF to PETp7 of
PCIE module
device.

Receiver differential pair, Lane 7

Connect AC Coupling
O AC coupled off
A48 PERn7 cap 0.1uF to PETn7 of
PCIE module
device.

A49 GND Power Ground Connect to GND

End of the x8 connector
A50 RSVD Reserved N/C
A51 GND Power Ground Connect to GND
Connect AC Coupling
O AC coupled off
A52 PERp8 cap 0.1uF to PETp8 of
PCIE module
device.
Receiver differential pair, Lane 8
Connect AC Coupling
O AC coupled off
A53 PERn8 cap 0.1uF to PETn8 of
PCIE module
device.
A54 GND Power Ground Connect to GND
A55 GND Power Ground Connect to GND
Connect AC Coupling
O AC coupled off
A56 PERp9 cap 0.1uF to PETp9 of
PCIE module
device.
Receiver differential pair, Lane 9
Connect AC Coupling
O AC coupled off
A57 PERn9 cap 0.1uF to PETn9 of
PCIE module
device.
A58 GND Power Ground Connect to GND
A59 GND Power Ground Connect to GND
Connect AC Coupling
O AC coupled off
A60 PERp10 cap 0.1uF to PETp10 of
PCIE module
device.
Receiver differential pair, Lane 10
 Receiver differential pair, Lane 10
Connect AC Coupling
O AC coupled off
A61 PERn10 cap 0.1uF to PETn10 of
PCIE module
device.
A62 GND Power Ground Connect to GND
A63 GND Power Ground Connect to GND
Connect AC Coupling
O AC coupled off
A64 PERp11 cap 0.1uF to PETp11 of
PCIE module
device.
Receiver differential pair, Lane 11
Connect AC Coupling
O AC coupled off
A65 PERn11 cap 0.1uF to PETn11 of
PCIE module
device.
A66 GND Power Ground Connect to GND
A67 GND Power Ground Connect to GND
Connect AC Coupling
O AC coupled off
A68 PERp12 cap 0.1uF to PETp12 of
PCIE module
device.
Receiver differential pair, Lane 12
Connect AC Coupling
O AC coupled off
A69 PERn12 cap 0.1uF to PETn12 of
PCIE module
device.
A70 GND Power Ground Connect to GND
A71 GND Power Ground Connect to GND
Connect AC Coupling
O AC coupled off
A72 PERp13 cap 0.1uF to PETp13 of
PCIE module
device.
Receiver differential pair, Lane 13
Connect AC Coupling
O AC coupled off
A73 PERn13 cap 0.1uF to PETn13 of
PCIE module
device.
A74 GND Power Ground Connect to GND
A75 GND Power Ground Connect to GND
Connect AC Coupling
O AC coupled off
A76 PERp14 cap 0.1uF to PETp14 of
PCIE module
device.
Receiver differential pair, Lane 14
Connect AC Coupling
O AC coupled off
A77 PERn14 cap 0.1uF to PETn14 of
PCIE module
device.
A78 GND Power Ground Connect to GND
A79 GND Power Ground Connect to GND
Connect AC Coupling
O AC coupled off
A80 PERp15 cap 0.1uF to PETp15 of
PCIE module
device.
Receiver differential pair, Lane 15
 Receiver differential pair, Lane 15
Connect AC Coupling
O AC coupled off
A81 PERn15 cap 0.1uF to PETn15 of
PCIE module
device.
A82 GND Power Ground Connect to GND
End of the x16 connector

Pwr Rail /
Pin No. PCIe Mini Card Socket Pin Type Description PCIe Mini Card
Tolerance
Side even
Connect to 3.3V standby
52 +3.3Vaux Power 3.3 V source
power
50 GND Power Return current path Connect to GND
48 +1.5V Power 1.5V source Connect to 1.5V
 Connect to Wireless
OD
46 LED_WPAN# 3.3V / 3.3V PAN LED of PCIe
CMOS
device

Open drain, active low signals. These signals are

OD used to allow the PCI Express Mini Card add-in Connect to Wireless
44 LED_WLAN# 3.3V / 3.3V
CMOS card to provide status indicators via LED devices LAN LED of PCIe device
that will be provided by the system.

Connect to Wireless
OD
42 LED_WWAN# 3.3V / 3.3V WAN LED of PCIe
CMOS
device

40 GND Power Return current path Connect to GND

I/O 3.3V Suspend Connect to D+ of USB
38 USB_D+
USB / 3.3V device
USB serial data interface compliant to the USB
2.0 specification
I/O 3.3V Suspend Connect to D- of USB
36 USB_D-
USB / 3.3V device
34 GND Power Return current path Connect to GND

3.3VSB SMBus device

- Connect to SMBDAT of
SMBus device.
3.3V SMBus device -
Connect 3.3V isolation
circuit controlled 3.3V to
SMBDAT of SMBus
device.
I/O OD 3.3V Suspend SMBus data signal compliant to the SMBus 2.0 5VSB SMBus device -
32 SMB_DATA
CMOS / 3.3V specification Connect 5V Level
Shifter to SMBDAT of
SMBus device.
5V SMBus device -
Connect 5V isolation
circuit controlled by 3.3V
to SMBDAT of SMBus
device
N/C if not used.
 3.3VSB SMBus device
- Connect to SMBCLK of
SMBus device.
3.3V SMBus device -
Connect 3.3V isolation
circuit controlled by 3.3V
to SMBCLK of SMBus
device.
I/O OD 3.3V Suspend SMBus clock signal compliant to the SMBus 2.0 5VSB SMBus device -
30 SMB_CLK
CMOS / 3.3V specification Connect 5V Level
Shifter to SMBCLK of
SMBus device.
5V SMBus device -
Connect 5V isolation
circuit controlled by 3.3V
to SMBCLK of SMBus
device
N/C if not used.

28 +1.5V Power 1.5V source Connect to 1.5V

26 GND Power Return current path Connect to GND
Connect to 3.3V standby
24 +3.3Vaux Power 3.3 V source
power

I 3.3V Suspend Connect to PERST# of

22 PERST# Functional reset to the card
CMOS / 3.3V PCIe device.

Active low signal. This signal is used by the

system to disable radio operation on add-in cards
I
20 W_DISABLE# 3.3V / 3.3V that implement radio frequency applications. PU 10K to 3.3V
CMOS
When implemented, this signal requires a pull-up
resistor on the card.

18 GND Power Return current path Connect to GND

Mechanical key
 Variable supply voltage (e.g., programming
voltage) for class A devices. Refer to ISO/IEC
7816-3 for operating class definitions.
O Connect to SPU of
16 UIM_VPP 3.3V / 3.3V This signal is reserved for future use for devices
CMOS WWAN radio device
of other classes.
Compliant to the ISO/IEC 7816-3 specification
(VPP).
UIM reset signal.
O Connect to RST of
14 UIM_RESET 3.3V / 3.3V Compliant to the ISO/IEC 7816-3 specification
CMOS WWAN radio device
(RST).
UIM clock signal.
O Connect to CLK of
12 UIM_CLK 3.3V / 3.3V Compliant to the ISO/IEC 7816-3 specification
CMOS WWAN radio device
(CLK).
UIM data signal.
I/O Connect to I/O of
10 UIM_DATA 3.3V / 3.3V Compliant to the ISO/IEC 7816-3 specification
CMOS WWAN radio device
(I/O).
Connect to
5 V for class A UIM
Power source for the UIM. device.
O
8 UIM_PWR 3.3V / 3.3V Compliant to the ISO/IEC 7816-3 specification 3 V for class B UIM
CMOS
(VCC). device.
1,8 V for class C UIM
device.
6 +1.5V Power Connect to 1.5V
4 GND Power Return current path Connect to GND
Connect to 3.3V standby
2 +3.3Vaux Power 3.3 V source
power
Side odd
51 Reserved Reserved N/C
49 Reserved Reserved N/C
47 Reserved Reserved N/C
45 Reserved Reserved N/C
43 GND Power Return current path Connect to GND

Connect to 3.3V standby

41 +3.3Vaux Power 3.3 V source
power

Connect to 3.3V standby

39 +3.3Vaux Power 3.3 V source
power
37 GND Power Return current path Connect to GND
35 GND Power Return current path Connect to GND

I AC coupled on Connect to PERp0 of

33 PETp0
PCIe module device.

PCI Express x1 data interface: one differential

transmit pair

I AC coupled on Connect to PERn0 of

31 PETn0
PCIe module device.

29 GND Power Return current path Connect to GND

27 GND Power Return current path Connect to GND
 Connect AC Coupling
O AC coupled off
25 PERp0 cap 0.1uF to PETp0 of
PCIE module
device.

PCI Express x1 data interface: one differential

receive pair

Connect AC Coupling
O AC coupled off
23 PERn0 cap 0.1uF to PETn0 of
PCIE module
device.

21 GND Power Return current path Connect to GND

19 Reserved* (UIM_C4) Reserved N/C

17 Reserved* (UIM_C8) Reserved N/C

Mechanical key
15 GND Power Return current path Connect to GND

I Connect to REFCLK+ of
13 REFCLK+ PCIE
PCIe device.

PCI Express differential reference clock (100

MHz)
 PCI Express differential reference clock (100
MHz)

I Connect to REFCLK- of
11 REFCLK- PCIE
PCIe device.

9 GND Power Return current path Connect to GND

O OD 3.3V Suspend Connect to CLKREQ# of

7 CLKREQ# Reference clock request signal
CMOS / 3.3V PCIe device

I/O Definition of this pin is

5 COEX2 3.3V / 3.3V
CMOS Provide to allow for the implementation of for OEM Specification
wireless coexistence solutions between the
radio(s) on the Mini Card and other off-card
I/O radio(s). Definition of this pin is
3 COEX1 3.3V / 3.3V
CMOS for OEM Specification

Open Drain active Low signal. This signal is used

O OD 3.3V Suspend to request that the system return from a Connect to WAKE# pin
1 WAKE#
CMOS / 3.3V sleep/suspended state to service a function of device.
initiated wake event.

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 SOM-5894 A101-4
Baseboard

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE0 x1 device
PERp0.
Slot - Connect to PCIE0
x1 Conn pin B14 PETp0.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE0 x1 device
PERn0.
Slot - Connect to PCIE0
x1 Conn pin B15 PETn0
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE1 x1 device
PERp0.
Slot - Connect to PCIE1
x1 Conn pin B14 PETp0.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE1 x1 device
PERn0.
Slot - Connect to PCIE1
x1 Conn pin B15 PETn0
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE2 x1 device
PERp0.
Slot - Connect to PCIE2
x1 Conn pin B14 PETp0.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE2 x1 device
PERn0.
Slot - Connect to PCIE2
x1 Conn pin B15 PETn0
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE3 x1 device
PERp0.
Slot - Connect to PCIE3
x1 Conn pin B14 PETp0.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE3 x1 device
PERn0.
Slot - Connect to PCIE3
x1 Conn pin B15 PETn0
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE4 x1 device
PERp0.
Slot - Connect to PCIE4
x1 Conn pin B14 PETp0.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE4 x1 device
PERn0.
Slot - Connect to PCIE4
x1 Conn pin B15 PETn0
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE5 x1 device
PERp0.
Slot - Connect to PCIE5
x1 Conn pin B14 PETp0.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE5 x1 device
PERn0.
Slot - Connect to PCIE5
x1 Conn pin B15 PETn0
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE6 x1 device
PERp0.
Slot - Connect to PCIE6
x1 Conn pin B14 PETp0.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE6 x1 device
PERn0.
Slot - Connect to PCIE6
x1 Conn pin B15 PETn0
N/C if not used.

N/C
 N/C

Device - Connect AC
Coupling cap 0.1uF near
COME to PCIE0 x1
device PETp0.
Slot - Connect to PCIE0
x1 Conn pin A16
PERp0.
N/C if not used.

Device - Connect AC
Coupling cap 0.1uF near
COME to PCIE0 x1
device PETn0.
Slot - Connect to PCIE0
x1 Conn pin A17
PERn0.
N/C if not used.

Device - Connect AC
Coupling cap 0.1uF near
COME to PCIE1 x1
device PETp0.
Slot - Connect to PCIE1
x1 Conn pin A16
PERp0.
N/C if not used.
Device - Connect AC
Coupling cap 0.1uF near
COME to PCIE1 x1
device PETn0.
Slot - Connect to PCIE1
x1 Conn pin A17
PERn0.
N/C if not used.

Device - Connect AC
Coupling cap 0.1uF near
COME to PCIE2 x1
device PETp0.
Slot - Connect to PCIE2
x1 Conn pin A16
PERp0.
N/C if not used.

Device - Connect AC
Coupling cap 0.1uF near
COME to PCIE2 x1
device PETn0.
Slot - Connect to PCIE2
x1 Conn pin A17
PERn0.
N/C if not used.

Device - Connect AC
Coupling cap 0.1uF near
COME to PCIE3 x1
device PETp0.
Slot - Connect to PCIE3
x1 Conn pin A16
PERp0.
N/C if not used.
Device - Connect AC
Coupling cap 0.1uF near
COME to PCIE3 x1
device PETn0.
Slot - Connect to PCIE3
x1 Conn pin A17
PERn0.
N/C if not used.

Device - Connect AC
Coupling cap 0.1uF near
COME to PCIE4 x1
device PETp0.
Slot - Connect to PCIE4
x1 Conn pin A16
PERp0.
N/C if not used.

Device - Connect AC
Coupling cap 0.1uF near
COME to PCIE4 x1
device PETn0.
Slot - Connect to PCIE4
x1 Conn pin A17
PERn0.
N/C if not used.

Device - Connect AC
Coupling cap 0.1uF near
COME to PCIE5 x1
device PETp0.
Slot - Connect to PCIE5
x1 Conn pin A16
PERp0.
N/C if not used.
Device - Connect AC
Coupling cap 0.1uF near
COME to PCIE5 x1
device PETn0.
Slot - Connect to PCIE5
x1 Conn pin A17
PERn0.
N/C if not used.

Device - Connect AC
Coupling cap 0.1uF near
COME to PCIE6 x1
device PETp0.
Slot - Connect to PCIE6
x1 Conn pin A16
PERp0.
N/C if not used.

Device - Connect AC
Coupling cap 0.1uF near
COME to PCIE6 x1
device PETn0.
Slot - Connect to PCIE6
x1 Conn pin A17
PERn0.
N/C if not used.

N/C
 N/C

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp0.
Slot - Connect to PCIE
x16 Conn pin B14
PETp0.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn0.
Slot - Connect to PCIE
x16 Conn pin B15
PETn0.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp1.
Slot - Connect to PCIE
x16 Conn pin B19
PETp1.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device PERn1
Slot - Connect to PCIE
x16 Conn pin B20
PETn1
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp2.
Slot - Connect to PCIE
x16 Conn pin B23
PETp2.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn2.
Slot - Connect to PCIE
x16 Conn pin B24
PETn2.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn2.
Slot - Connect to PCIE
x16 Conn pin B27
PETp3.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn3.
Slot - Connect to PCIE
x16 Conn pin B28
PETn3.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp4.
Slot - Connect to PCIE
x16 Conn pin B33
PETp4.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn4.
Slot - Connect to PCIE
x16 Conn pin B34
PETn4.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp5.
Slot - Connect to PCIE
x16 Conn pin B37
PETp5.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn5.
Slot - Connect to PCIE
x16 Conn pin B38
PETn5.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp6.
Slot - Connect to PCIE
x16 Conn pin B41
PETp6.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn6.
Slot - Connect to PCIE
x16 Conn pin B42
PETn6.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp7.
Slot - Connect to PCIE
x16 Conn pin B45
PETp7.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn7.
Slot - Connect to PCIE
x16 Conn pin B46
PETn7.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp8.
Slot - Connect to PCIE
x16 Conn pin B50
PETp8.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp8.
Slot - Connect to PCIE
x16 Conn pin B50
PETp8.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp9.
Slot - Connect to PCIE
x16 Conn pin B54
PETp9.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn9.
Slot - Connect to PCIE
x16 Conn pin B55
PETn9.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp10.
Slot - Connect to PCIE
x16 Conn pin B58
PETp10.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn10.
Slot - Connect to PCIE
x16 Conn pin B59
PETn10.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp11.
Slot - Connect to PCIE
x16 Conn pin B62
PETp11.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn11.
Slot - Connect to PCIE
x16 Conn pin B63
PETn11.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp12.
Slot - Connect to PCIE
x16 Conn pin B66
PETp12.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn12.
Slot - Connect to PCIE
x16 Conn pin B67
PETn12.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp13.
Slot - Connect to PCIE
x16 Conn pin B70
PETp13.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn13.
Slot - Connect to PCIE
x16 Conn pin B71
PETn13.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp14.
Slot - Connect to PCIE
x16 Conn pin B74
PETp14.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn14.
Slot - Connect to PCIE
x16 Conn pin B75
PETn14.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp15.
Slot - Connect to PCIE
x16 Conn pin B78
PETp15.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn15.
Slot - Connect to PCIE
x16 Conn pin B79
PETn15.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp0.
Slot - Connect to PCIE
x16 Conn pin A16
PERp0.
N/C if not used.
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn0.
Slot -Connect to PCIE
x16 Conn pin A17
PERn0.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp1.
Slot - Connect to PCIE
x16 Conn pin A21
PERp1.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn1.
Slot - Connect to PCIE
x16 Conn pin A22
PERn1.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp2.
Slot - Connect to PCIE
x16 Conn pin A25
PERp2.
N/C if not used.
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn2.
Slot - Connect to PCIE
x16 Conn pin A26
PERn2.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp3.
Slot - Connect to PCIE
x16 Conn pin A29
PERp3.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn3.
Slot - Connect to PCIE
x16 Conn pin A30
PERn3.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp4.
Slot - Connect to PCIE
x16 Conn pin A35
PERp4.
N/C if not used.
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn4.
Slot - Connect to PCIE
x16 Conn pin A36
PERn4.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp5.
Slot - Connect to PCIE
x16 Conn pin A39
PERp5.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn5.
Slot - Connect to PCIE
x16 Conn pin A40
PERn5.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp6.
Slot - Connect to PCIE
x16 Conn pin A43
PERp6.
N/C if not used.
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn6.
Slot - Connect to PCIE
x16 Conn pin A44
PERn6.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp7.
Slot - Connect to PCIE
x16 Conn pin A47
PERp7.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn7.
Slot - Connect to PCIE
x16 Conn pin A48
PERn7.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp8.
Slot - Connect to PCIE
x16 Conn pin A52
PERp8.
N/C if not used.
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn8.
Slot - Connect to PCIE
x16 Conn pin A53
PERn8.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp9.
Slot - Connect to PCIE
x16 Conn pin A56
PERp9.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn9.
Slot - Connect to PCIE
x16 Conn pin A57
PERn9.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp10.
Slot - Connect to PCIE
x16 Conn pin A60
PERp10.
N/C if not used.
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn10.
Slot - Connect to PCIe
x16 Conn pin A61
PERn10.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp11.
Slot - Connect to PCIE
x16 Conn pin A64
PERp11.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn11.
Slot - Connect to PCIE
x16 Conn pin A65
PERn11.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp12.
Slot - Connect to PCIE
x16 Conn pin A68
PERp12.
N/C if not used.
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn12.
Slot - Connect to PCIE
x16 Conn pin A69
PERn12.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp13.
Slot - Connect to PCIE
x16 Conn pin A72
PERp13.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn13.
Slot - Connect to PCIE
x16 Conn pin A73
PERn13.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp14.
Slot - Connect to PCIE
x16 Conn pin A76
PERp14.
N/C if not used.
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn14.
Slot - Connect to PCIE
x16 Conn pin A77
PERn14.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp15.
Slot - Connect to PCIE
x16 Conn pin A80
PERp15.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIe x16
device PETn15.
Slot - Connect to PCIe
x16 Conn pin A81
PERn15.
N/C if not used.
Connect 0Ω in series to
Device - Connect to
PCIe device REFCLK+.
Slot - Connect to PCIe
Conn pin A13
REFCLK+.
*Connect to PCIe Clock
Buffer(DB400/800) input
to provide PCIE clocks
output for more than one
PCIe devices or slots.
N/C if not used.

Connect 0Ω in series to
Device - Connect to
PCIe device REFCLK-
Slot - Connect to PCIe
Conn pin A14 REFCLK-.
*Connect to PCIe Clock
Buffer(DB400/800) input
to provide PCIe clocks
output for more than one
PCIE devices or slots.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp0.
Slot - Connect to PCIE
x16 Conn pin B14
PETp0.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn0.
Slot - Connect to PCIE
x16 Conn pin B15
PETn0.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp1.
Slot - Connect to PCIE
x16 Conn pin B19
PETp1.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device PERn1
Slot - Connect to PCIE
x16 Conn pin B20
PETn1
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp2.
Slot - Connect to PCIE
x16 Conn pin B23
PETp2.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn2.
Slot - Connect to PCIE
x16 Conn pin B24
PETn2.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn3.
Slot - Connect to PCIE
x16 Conn pin B27
PETp3.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn3.
Slot - Connect to PCIE
x16 Conn pin B28
PETn3.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp4.
Slot - Connect to PCIE
x16 Conn pin B33
PETp4.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn4.
Slot - Connect to PCIE
x16 Conn pin B34
PETn4.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp5.
Slot - Connect to PCIE
x16 Conn pin B37
PETp5.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn5.
Slot - Connect to PCIE
x16 Conn pin B38
PETn5.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp6.
Slot - Connect to PCIE
x16 Conn pin B41
PETp6.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn6.
Slot - Connect to PCIE
x16 Conn pin B42
PETn6.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp7.
Slot - Connect to PCIE
x16 Conn pin B45
PETp7.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn7.
Slot - Connect to PCIE
x16 Conn pin B46
PETn7.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp8.
Slot - Connect to PCIE
x16 Conn pin B50
PETp8.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn8.
Slot - Connect to PCIE
x16 Conn pin B51
PETn8.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp9.
Slot - Connect to PCIE
x16 Conn pin B54
PETp9.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn9.
Slot - Connect to PCIE
x16 Conn pin B55
PETn9.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp10.
Slot - Connect to PCIE
x16 Conn pin B58
PETp10.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn10.
Slot - Connect to PCIE
x16 Conn pin B59
PETn10.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp11.
Slot - Connect to PCIE
x16 Conn pin B62
PETp11.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn11.
Slot - Connect to PCIE
x16 Conn pin B63
PETn11.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp12.
Slot - Connect to PCIE
x16 Conn pin B66
PETp12.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn12.
Slot - Connect to PCIE
x16 Conn pin B67
PETn12.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp13.
Slot - Connect to PCIE
x16 Conn pin B70
PETp13.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn13.
Slot - Connect to PCIE
x16 Conn pin B71
PETn13.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp14.
Slot - Connect to PCIE
x16 Conn pin B74
PETp14.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn14.
Slot - Connect to PCIE
x16 Conn pin B75
PETn14.
N/C if not used.
Module has integrated
AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERp15.
Slot - Connect to PCIE
x16 Conn pin B78
PETp15.
N/C if not used.

Module has integrated

AC Coupling Capacitor.
Device - Connect to
PCIE x16 device
PERn15.
Slot - Connect to PCIE
x16 Conn pin B79
PETn15.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp0.
Slot - Connect to PCIE
x16 Conn pin A16
PERp0.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn0.
Slot -Connect to PCIE
x16 Conn pin A17
PERn0.
N/C if not used.
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp1.
Slot - Connect to PCIE
x16 Conn pin A21
PERp1.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn1.
Slot - Connect to PCIE
x16 Conn pin A22
PERn1.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp2.
Slot - Connect to PCIE
x16 Conn pin A25
PERp2.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn2.
Slot - Connect to PCIE
x16 Conn pin A26
PERn2.
N/C if not used.
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp3.
Slot - Connect to PCIE
x16 Conn pin A29
PERp3.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn3.
Slot - Connect to PCIE
x16 Conn pin A30
PERn3.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp4.
Slot - Connect to PCIE
x16 Conn pin A35
PERp4.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn4.
Slot - Connect to PCIE
x16 Conn pin A36
PERn4.
N/C if not used.
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp5.
Slot - Connect to PCIE
x16 Conn pin A39
PERp5.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn5.
Slot - Connect to PCIE
x16 Conn pin A40
PERn5.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp6.
Slot - Connect to PCIE
x16 Conn pin A43
PERp6.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn6.
Slot - Connect to PCIE
x16 Conn pin A44
PERn6.
N/C if not used.
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp7.
Slot - Connect to PCIE
x16 Conn pin A47
PERp7.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn7.
Slot - Connect to PCIE
x16 Conn pin A48
PERn7.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp8.
Slot - Connect to PCIE
x16 Conn pin A52
PERp8.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn8.
Slot - Connect to PCIE
x16 Conn pin A53
PERn8.
N/C if not used.
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp9.
Slot - Connect to PCIE
x16 Conn pin A56
PERp9.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn9.
Slot - Connect to PCIE
x16 Conn pin A57
PERn9.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp10.
Slot - Connect to PCIE
x16 Conn pin A60
PERp10.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn10.
Slot - Connect to PCIE
x16 Conn pin A61
PERn10.
N/C if not used.
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp11.
Slot - Connect to PCIE
x16 Conn pin A64
PERp11.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn11.
Slot - Connect to PCIE
x16 Conn pin A65
PERn11.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp12.
Slot - Connect to PCIE
x16 Conn pin A68
PERp12.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn12.
Slot - Connect to PCIE
x16 Conn pin A69
PERn12.
N/C if not used.
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp13.
Slot - Connect to PCIE
x16 Conn pin A72
PERp13.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn13.
Slot - Connect to PCIE
x16 Conn pin A73
PERn13.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp14.
Slot - Connect to PCIE
x16 Conn pin A76
PERp14.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn14.
Slot - Connect to PCIE
x16 Conn pin A77
PERn14.
N/C if not used.
Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETp15.
Slot - Connect to PCIE
x16 Conn pin A80
PERp15.
N/C if not used.

Device - Connect AC
Coupling cap 0.22uF
near COME to PCIE x16
device PETn15.
Slot - Connect to PCIE
x16 Conn pin A81
PERn15.
N/C if not used.

Module has integrated

PU resistor to 3.3V.
Normal - N/C
Reverse - PD 1KΩ to
GND
N/C if not used.

Module has integrated

PU resistor to 3.3V.
Internal - N/C
PEG - PD 1KΩ to GND
N/C if not used.
 Baseboard

Connect to 12V power

Connect to 12V power
Connect to 12V power
Connect to GND
Module has integrated
PU resistor to
3.3VDUAL
Connect to COME pin
B13 SMB_CLK.
Module has integrated
PU resistor to
3.3VDUAL
Connect to COME pin
B14 SMB_DAT.

Connect to GND
Connect to 3.3V power

Connect to JTAG
TRST# of TAP(Test
Access Port) Controller.
PD 4.7K to GND if not
used.

Connect to 3.3V standby

power
Module has integrated
PU resistor to
3.3VDUAL
PCIe - Connect to
COME pin B66
WAKE0#.
PEG - N/C

N/C
Connect to GND

Module has integrated

AC Coupling Capacitor.
PCIe x1/x4/x8 - Connect
to COME pin A68
PCIE_TX0+ for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
D52 PEG_TX0+.

Module has integrated

AC Coupling Capacitor.
PCIe x1/x4/x8 - Connect
to COME pin A69
PCIE_TX0- for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
D53 PEG_TX0-

Connect to GND
PCIe - PU 10KΩ to
+3,3V and connect to
Hot Plug Control Logic
for x1 connector
PEG - N/C
Connect to GND

Module has integrated

AC Coupling Capacitor.
PCIe x1/x4/x8 - Connect
to COME pin A64
PCIE_TX1+ for x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
D55 PEG_TX1+.
Module has integrated
AC Coupling Capacitor.
PCIe x1/x4/x8 - Connect
to COME pin A65
PCIE_TX1- for x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
D56 PEG_TX1-

Connect to GND
Connect to GND

Module has integrated

AC Coupling Capacitor.
PCIe x1/x4/x8 - Connect
to COME pin A61
PCIE_TX2+ for x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
D58 PEG_TX2+.

Module has integrated

AC Coupling Capacitor.
PCIe x1/x4/x8 - Connect
to COME pin A62
PCIE_TX2- for x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
D59 PEG_TX2-

Connect to GND
Connect to GND
Module has integrated
AC Coupling Capacitor.
PCIe x1/x4/x8 - Connect
to COME pin A58
PCIE_TX3+ for x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
D61 PEG_TX3+.

Module has integrated

AC Coupling Capacitor.
PCIe x1/x4/x8 - Connect
to COME pin A59
PCIE_TX3- for x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
D62 PEG_TX3-

Connect to GND
N/C

PCIe - Connect to pin

B17 and PU 10KΩ to
+3.3V and then connect
to Hot Plug Control
Logic for x4 connector
PEG - N/C

Connect to GND
Module has integrated
AC Coupling Capacitor.
PCIe x1/x4/x8 - Connect
to COME pin A55
PCIE_TX4+ for x8
connector.
PCIe x16/PEG -
Connect to COME pin
D65 PEG_TX4+.

Module has integrated

AC Coupling Capacitor.
PCIe x1/x4/x8 - Connect
to COME pin A56
PCIE_TX4- for x8
connector.
PCIe x16/PEG -
Connect to COME pin
D66 PEG_TX4-

Connect to GND
Connect to GND

Module has integrated

AC Coupling Capacitor.
PCIe x1/x4/x8 - Connect
to COME pin A52
PCIE_TX5+ for x8
connector.
PCIe x16/PEG -
Connect to COME pin
D68 PEG_TX5+.
Module has integrated
AC Coupling Capacitor.
PCIe x1/x4/x8 - Connect
to COME pin A53
PCIE_TX5- for x8
connector.
PCIe x16/PEG -
Connect to COME pin
D69 PEG_TX5-

Connect to GND
Connect to GND

Module has integrated

AC Coupling Capacitor.
PCIe x1/x4/x8 - Connect
to COME pin D19
PCIE_TX6+ for x8
connector.
PCIe x16/PEG -
Connect to COME pin
D71 PEG_TX6+.

Module has integrated

AC Coupling Capacitor.
PCIe x1/x4/x8 - Connect
to COME pin D20
PCIE_TX6- for x8
connector.
PCIe x16/PEG -
Connect to COME pin
D72 PEG_TX6-
Connect to GND
Connect to GND
Module has integrated
AC Coupling Capacitor.
PCIe x1/x4/x8 - Connect
to COME pin D22
PCIE_TX7+ for x8
connector.
PCIe x16/PEG -
Connect to COME pin
D74 PEG_TX7+.

Module has integrated

AC Coupling Capacitor.
PCIe x1/x4/x8 - Connect
to COME pin D23
PCIE_TX7- for x8
connector.
PCIe x16/PEG -
Connect to COME pin
D75 PEG_TX7-

Connect to GND

PCIe - Connect to pin

B17, B31 and PU 10K to
+3.3V and then connect
to Hot Plug Control
Logic for x8 connector
PEG - N/C

Connect to GND

Module has integrated

AC Coupling Capacitor.
PCIe x16/PEG -
Connect to COME pin
D78 PEG_TX8+.
Module has integrated
AC Coupling Capacitor.
PCIe x16/PEG -
Connect to COME pin
D79 PEG_TX8-

Connect to GND
Connect to GND

Module has integrated

AC Coupling Capacitor.
PCIe x16/PEG -
Connect to COME pin
D81 PEG_TX9+.

Module has integrated

AC Coupling Capacitor.
PCIe x16/PEG -
Connect to COME pin
D82 PEG_TX9-

Connect to GND
Connect to GND

Module has integrated

AC Coupling Capacitor.
PCIe x16/PEG -
Connect to COME pin
D85 PEG_TX10+.

Module has integrated

AC Coupling Capacitor.
PCIe x16/PEG -
Connect to COME pin
D86 PEG_TX10-

Connect to GND
Connect to GND
Module has integrated
AC Coupling Capacitor.
PCIe x16/PEG -
Connect to COME pin
D88 PEG_TX11+.

Module has integrated

AC Coupling Capacitor.
PCIe x16/PEG -
Connect to COME pin
D89 PEG_TX11-

Connect to GND
Connect to GND

Module has integrated

AC Coupling Capacitor.
PCIe x16/PEG -
Connect to COME pin
D91 PEG_TX12+.

Module has integrated

AC Coupling Capacitor.
PCIe x16/PEG -
Connect to COME pin
D92 PEG_TX12-

Connect to GND
Connect to GND

Module has integrated

AC Coupling Capacitor.
PCIe x16/PEG -
Connect to COME pin
D94 PEG_TX13+.

Module has integrated

AC Coupling Capacitor.
PCIe x16/PEG -
Connect to COME pin
D95 PEG_TX13-
Connect to GND
Connect to GND

Module has integrated

AC Coupling Capacitor.
PCIe x16/PEG -
Connect to COME pin
D98 PEG_TX14+.

Module has integrated

AC Coupling Capacitor.
PCIe x16/PEG -
Connect to COME pin
D99 PEG_TX14-

Connect to GND
Connect to GND

Module has integrated

AC Coupling Capacitor.
PCIe x16/PEG -
Connect to COME pin
D101 PEG_TX15+.

Module has integrated

AC Coupling Capacitor.
PCIe x16/PEG -
Connect to COME pin
D102 PEG_TX15-

Connect to GND

PCIe - Connect to pin

B17, B31, B48 and PU
10KΩ to +3.3V and then
connect to Hot Plug
Control Logic for x16
connector
PEG - Connect to
COME pin D97
PEG_ENABLE#

N/C
Connect 0Ω in series to
GND

Connect to 12V power

Connect to 12V power
Connect to GND

Connect to JTAG TCK

of TAP(Test Access
Port) Controller
PD 4.7K to GND if not
used.

Connect to JTAG TDO

of TAP(Test Access
Port) Controller
PU 4.7K to +3.3V if not
used.

Connect to JTAG TDI of

TAP(Test Access Port)
Controller.
N/C if not used.

Connect to JTAG TMS

of TAP(Test Access
Port) Controller
PU 4.7K to +3.3V if not
used.

Connect to 3.3V power

Connect to 3.3V power
Module has integrated
3.3VDUAL buffer and
series resistor
Connect to COME pin
B50 CB_RESET#

Connect to GND

Module has integrated

series resistor
Connect to COME pin
A88 PCIE_CLK_REF+
for single PCIe device or
PCIe Clock Buffer
DB400/800 differential
clock positive output pin
for more than one.

Module has integrated

series resistor
Connect to COME pin
A89 PCIE_CLK_REF-
for single PCIe device or
PCIe Clock Buffer
DB400/800 differential
clock negative output pin
for more than one.

Connect to GND
PCIe x1/x4/x8 - Connect
to COME pin B68
PCIE_RX0+ for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
C52 PEG_RX0+.
PCIe x1/x4/x8 - Connect
to COME pin B69
PCIE_RX0- for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
C53 PEG_RX0-
Connect to GND

N/C
Connect to GND
PCIe x1/x4/x8 - Connect
to COME pin B64
PCIE_RX1+ for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
C55 PEG_RX1+.

PCIe x1/x4/x8 - Connect

to COME pin B65
PCIE_RX1- for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
C56 PEG_RX1-
Connect to GND
Connect to GND
PCIe x1/x4/x8 - Connect
to COME pin B61
PCIE_RX2+ for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
C58 PEG_RX2+.
PCIe x1/x4/x8 - Connect
to COME pin B62
PCIE_RX2- for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
C59 PEG_RX2-
Connect to GND
Connect to GND
PCIe x1/x4/x8 - Connect
to COME pin B58
PCIE_RX3+ for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
C61 PEG_RX3+.

PCIe x1/x4/x8 - Connect

to COME pin B59
PCIE_RX3- for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
C62 PEG_RX3-
Connect to GND
N/C

N/C
Connect to GND
PCIe x1/x4/x8 - Connect
to COME pin B55
PCIE_RX4+ for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
C65 PEG_RX4+.
PCIe x1/x4/x8 - Connect
to COME pin B56
PCIE_RX4- for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
C66 PEG_RX4-
Connect to GND
Connect to GND
PCIe x1/x4/x8 - Connect
to COME pin B52
PCIE_RX5+ for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
C68 PEG_RX5+.

PCIe x1/x4/x8 - Connect

to COME pin B53
PCIE_RX5- for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
C69 PEG_RX5-
Connect to GND
Connect to GND
PCIe x1/x4/x8 - Connect
to COME pin C19
PCIE_RX6+ for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
C71 PEG_RX6+.

PCIe x1/x4/x8 - Connect

to COME pin C20
PCIE_RX6- for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
C72 PEG_RX6-
Connect to GND
Connect to GND
PCIe x1/x4/x8 - Connect
to COME pin C22
PCIE_RX7+ for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
C74 PEG_RX7+.

PCIe x1/x4/x8 - Connect

to COME pin C23
PCIE_RX7- for x1/x4/x8
connector.
PCIe x16/PEG -
Connect to COME pin
C75 PEG_RX7-
Connect to GND

N/C
Connect to GND
PCIe x16/PEG -
Connect to COME pin
C78 PEG_RX8+.
PCIe x16/PEG -
Connect to COME pin
C79 PEG_RX8-
Connect to GND
Connect to GND
PCIe x16/PEG -
Connect to COME pin
C81 PEG_RX9+.
PCIe x16/PEG -
Connect to COME pin
C82 PEG_RX9-
Connect to GND
Connect to GND
PCIe x16/PEG -
Connect to COME pin
C85 PEG_RX10+.
PCIe x16/PEG -
Connect to COME pin
C86 PEG_RX10-
Connect to GND
Connect to GND
PCIe x16/PEG -
Connect to COME pin
C88 PEG_RX11+.
PCIe x16/PEG -
Connect to COME pin
C89 PEG_RX11-
Connect to GND
Connect to GND
PCIe x16/PEG -
Connect to COME pin
C91 PEG_RX12+.
PCIe x16/PEG -
Connect to COME pin
C92 PEG_RX12-
Connect to GND
Connect to GND
PCIe x16/PEG -
Connect to COME pin
C94 PEG_RX13+.
PCIe x16/PEG -
Connect to COME pin
C95 PEG_RX13-
Connect to GND
Connect to GND
PCIe x16/PEG -
Connect to COME pin
C98 PEG_RX14+.
PCIe x16/PEG -
Connect to COME pin
C99 PEG_RX14-
Connect to GND
Connect to GND
PCIe x16/PEG -
Connect to COME pin
C101 PEG_RX15+.
PCIe x16/PEG -
Connect to COME pin
C102 PEG_RX15-
Connect to GND

Baseboard

Connect to 3.3V standby

power or 3.3V power
Connect to GND
Connect to 1.5V
Connect LED and
current limiting resistors
300 to 330 Ω to
+3.3Vaux
N/C if notLED
Connect used.
and
current limiting resistors
300 to 330 Ω to
+3.3Vaux
N/C if notLED
Connect used.
and
current limiting resistors
300 to 330 Ω to
+3.3Vaux
N/C if not used.
Connect to GND
Connect to COME
USBx+

Connect to COME
USBx-
Connect to GND

Module has integrated

PU resistor to
3.3VDUAL
Connect to COME pin
B14 SMB_DAT.
Module has integrated
PU resistor to
3.3VDUAL
Connect to COME pin
B13 SMB_CLK.

Connect to 1.5V
Connect to GND
Connect to 3.3V standby
power or 3.3V power

Module has integrated

3.3VDUAL buffer and
series resistor
Connect to COME pin
B50 CB_RESET#

Connect to disable radio

operation Control Logic

Connect to GND
Connet to pin C6 of UIM
socket
N/C if not used.

Connet to pin C2 of UIM

socket
N/C if not used.
Connet to pin C3 of UIM
socket
N/C if not used.
Connet to pin C7 of UIM
socket
N/C if not used.

Connet to pin C1 of UIM

socket
N/C if not used.

Connect to 1.5V
Connect to GND
Connect to 3.3V standby
power or 3.3V power

N/C
N/C
N/C
N/C
PCIe Mini Card only -
Connect to GND
mSATA/PCIe Mini Card
Switch - PU 10KΩ to
3.3V and connect to
Differential Channel
Mux/Demux pin SEL for
PCIe Mini Card

Connect to 3.3V standby

power or 3.3V power

Connect to 3.3V standby

power or 3.3V power
Connect to GND
Connect to GND

PCIe Mini Card only -

Connect to COME
PCIE_TXx+
mSATA/PCIe Mini Card
Switch - Connect to
Differential Channel
Mux/Demux pin TX+ for
PCIe Mini Card

PCIe Mini Card only -

Connect to COME
PCIE_TXx-
mSATA/PCIe Mini Card
Switch - Connect to
Differential Channel
Mux/Demux pin TX- for
PCIe Mini Card

Connect to GND
Connect to GND
PCIe Mini Card only -
Connect to COME
PCIE_RXx+
mSATA/PCIe Mini Card
Switch - Connect to
Differential Channel
Mux/Demux pin RX+ for
PCIe Mini Card

PCIe Mini Card only -

Connect to COME
PCIE_RXx-
mSATA/PCIe Mini Card
Switch - Connect to
Differential Channel
Mux/Demux pin RX- for
PCIe Mini Card

Connect to GND
Connet to pin C4 of UIM
socket
N/C if not used.
Connet to pin C8 of UIM
socket
N/C if not used.

Connect to GND

Module has integrated

series resistor
Connect to COME pin
A88 PCIE_CLK_REF+
for single PCIe device or
PCIe Clock Buffer
DB400/800 differential
clock positive output pin
for more than one.
Module has integrated
series resistor
Connect to COME pin
A89 PCIE_CLK_REF-
for single PCIe device or
PCIe Clock Buffer
DB400/800 differential
clock negative output pin
for more than one.

Connect to GND

PU 10KΩ to +3.3Vaux
Connect to PCIe Clock
Buffer DB400/800
CLKREQ# or OE# active
low pin for REFCLK+/-
output enable

Definition of this pin is

for OEM Specification
N/C if not used.

Definition of this pin is

for OEM Specification
N/C if not used.

Module has integrated

PU resistor to
3.3VDUAL
Connect to COME pin
B66 WAKE0#.
 Pwr Rail /
Pin No. ExpressCard Support Pin Type
Tolerance

A49 EXCD0_CPPE#

I CMOS 3.3V / 3.3V

B48 EXCD1_CPPE#

A48 EXCD0_PERST#

O CMOS 3.3V / 3.3V

B47 EXCD1_PRST#

4.3.7 ExpressCard
ExpressCard is a small form factor expansion card for mobile systems that uses PCI Express or USB as the
interface. It is similar in concept and scope to CardBus. COM Express™ Modules shall provide support functions
for at least one ExpressCard. This does not mean that a Module PCI Express lane or USB link are specifically
allocated to ExpressCard use, but it does mean that the Module pins for ExpressCard detection and support are
present.
The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V
with a 10kΩ resistor
• EXCD[0:1]_CPPE#

ExpressCard Pwr Rail /

Pin No. Pin Type
Connector Tolerance
1 GND Power

2 USBD-

3.3V /
I/O
3.3V
USB
Suspend

3 USBD+

O 3.3V /
4 CPUSB#
CMOS 3.3V

I/O OD 3.3V /
5 USB3#
CMOS 3.3V

6 RESERVED RSVD
 3.3V
I/O OD
7 SMBCLK Suspend /
CMOS
3.3V

3.3V
I/O OD
8 SMBDATA Suspend /
CMOS
3.3V

9 +1.5 V Power 1.5V

10 +1.5 V Power 1.5V

3.3V
O OD
11 WAKE# Suspend /
CMOS
3.3V
 3.3V
12 +3.3 VAUX Power
Suspend

I 3.3V /
13 PERST#
CMOS 3.3V

14 +3.3 V Power 3.3V

15 +3.3 V Power 3.3V

3.3V
O OD
16 CLKREQ# Suspend /
CMOS
3.3V

O 3.3V /
17 CPPE#
CMOS 3.3V

18 REFCLK-

I 3.3V /
PCIe 3.3V
 I 3.3V /
PCIe 3.3V

19 REFCLK+

20 GND Power

21 PERn0/SSRX-

O
AC coupled
PCIE/USB off module
3.0

22 PERp0/SSRX+

23 GND Power

24 PETn0/SSTX-
I
AC coupled
PCIE/USB on module
3.0
25 PETp0/SSTX+

26 GND Power
ExpressCard Pwr Rail /
Pin No. Pin Type
Power Switch Tolerance
3.3 VIN Power 3.3V

1.5VIN Power 1.5V

3.3V
3.3VAUX Power
Suspend

3.3VOUT Power 3.3V

1.5VOUT Power 1.5V

 3.3V
3.3VAUXOUT Power
Suspend

3.3V
I
SYSRST# Suspend /
CMOS
3.3V

3.3V
I
SHDN# Suspend /
CMOS
3.3V

3.3V
I
STBY# Suspend /
CMOS
3.3V

3.3V
I
CPPE# Suspend /
CMOS
3.3V

3.3V
I
CPUSB# Suspend /
CMOS
3.3V

O 3.3V /
PERST#
CMOS 3.3V

3.3V
I/O OD
CLKEN Suspend /
CMOS
3.3V

3.3V
OD
OC# Suspend /
CMOS
3.3V
PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 SOM-5894 A101-4
Description Baseboard
Baseboard

Module has integrated Module has integrated

PU resistor to 3.3V PU resistor to 3.3V
Connect 0Ω(NL) in Connect 0Ω(NL) in
series to ExpressCard's series to ExpressCard's
CPPE# and CPPE# and
ExpressCard's CPPE# ExpressCard's CPPE#
connects to Power connects to Power
Switch CPPE# input pin Switch CPPE# input pin
N/C if not used. N/C if not used.

PCI ExpressCard: PCI Express capable card

request, active low, one per card

Module has integrated Module has integrated

PU resistor to 3.3V PU resistor to 3.3V
Connect 0Ω(NL) in Connect 0Ω(NL) in
series to ExpressCard's series to ExpressCard's
CPPE# and CPPE# and
ExpressCard's CPPE# ExpressCard's CPPE#
connects to Power connects to Power
Switch CPPE# input pin Switch CPPE# input pin
N/C if not used. N/C if not used.

Module has integrated

PU resistor to 3.3V Connect 0Ω(NL) in
Connect 0Ω(NL) in series to ExpressCard's
series to ExpressCard's PERST# and
PERST# and ExpressCard's PERST#
ExpressCard's PERST# connects to Power
connects to Power Switch PERST# output
Switch PERST# output pin
pin N/C if not used.
N/C if not used.
PCI ExpressCard: reset, active low, one per card

Module has integrated

PU resistor to 3.3V Connect 0Ω(NL) in
Connect 0Ω(NL) in series to ExpressCard's
series to ExpressCard's PERST# and
PERST# and ExpressCard's PERST#
ExpressCard's PERST# connects to Power
connects to Power Switch PERST# output
Switch PERST# output pin
pin N/C if not used.
N/C if not used.
 for mobile systems that uses PCI Express or USB as the
Bus. COM Express™ Modules shall provide support functions
that a Module PCI Express lane or USB link are specifically
at the Module pins for ExpressCard detection and support are

gnals below. The following signals should be pulled-up to 3.3V

Description ExpressCard Module Baseboard

Return current path, Ground Connect to GND Connect to GND
Connect ESD
suppressors to GND and
Connect to USBD- of
90Ω @100MHz
USB device
Common Choke in
series to COME USBx-
USB serial data interface
Connect ESD
suppressors to GND and
Connect to USBD+ of
90Ω @100MHz
USB device
Common Choke in
series to COME USBx+

PU 100KΩ~200KΩ to
3.3VDUAL
USB interface presence detect Connect 0Ω to GND Connect to Power
Switch CPUSB# input
pin
PU 100KΩ~200KΩ to
This signal is used for USB 3.0-based interface 3.3 V
Connect 0Ω to GND
detection Connect to USB 3.0
detection circuit
Reserved N/A N/C
 3.3VSB SMBus device
- Connect to SMBCLK of
SMBus device.
3.3V SMBus device -
Connect 3.3V isolation
circuit controlled by 3.3V
to SMBCLK of SMBus
Module has integrated
device.
PU resistor to
SMBus clock signal compliant to the SMBus 2.0 5VSB SMBus device -
3.3VDUAL
specification Connect 5V Level
Connect to COME pin
Shifter to SMBCLK of
B13 SMB_CLK.
SMBus device.
5V SMBus device -
Connect 5V isolation
circuit controlled by 3.3V
to SMBCLK of SMBus
device
N/C if not used.

3.3VSB SMBus device

- Connect to SMBDAT of
SMBus device.
3.3V SMBus device -
Connect 3.3V isolation
circuit controlled 3.3V to
SMBDAT of SMBus
Module has integrated
device.
PU resistor to
SMBus data signal compliant to the SMBus 2.0 5VSB SMBus device -
3.3VDUAL
specification Connect 5V Level
Connect to COME pin
Shifter to SMBDAT of
B14 SMB_DAT.
SMBus device.
5V SMBus device -
Connect 5V isolation
circuit controlled by 3.3V
to SMBDAT of SMBus
device
N/C if not used.

Connect to Power
Secondary voltage source, 1.5V N/A Switch 1.5VOUT power
pin
Connect to Power
Secondary voltage source, 1.5V N/A Switch 1.5VOUT power
pin
Module has integrated
PU resistor to
Request that the host interface return to full Connect to WAKE# of
3.3VDUAL
operation and respond to PCI Express PCIe device
Connect to COME pin
B66 WAKE0#
 Connect to Power
Auxiliary voltage source, 3.3VAUX N/A Switch 3.3VAUXOUT
power pin

Connect to Power
Switch PERST# output
pin and COME pin A48
Connect to PERST# of EXCD0_PERST# for
PCIe Reset input
PCIe device ExpressCard0 or B47
EXCD1_PERST# for
ExpressCard1 with
0Ω(NL) in series

Connect to Power
Primary voltage source, 3.3V N/A Switch 3.3VOUT power
pin
Connect to Power
Primary voltage source, 3.3V N/A Switch 3.3VOUT power
pin

PU 10KΩ to 3.3VDUAL
Connect to PCIe Clock
Connect to CLKREQ# of Buffer DB400/800
Request that REFCLK be enabled
PCIe device CLKREQ# or OE# active
low pin for REFCLK+/-
output enable

Module has integrated

PU resistor to 3.3V
Connect to Power
Switch CPPE# input pin
and COME A49
PCI Express interface presence detect Connect 0Ω to GND
EXCD0_CPPE# for
ExpressCard0 or B48
EXCD1_CPPE# for
ExpressCard1 with with
0Ω(NL) in series

Module has integrated

series resistor
Connect to COME pin
A89 PCIE_CLK_REF-
Connect to REFCLK- of
for single PCIe device or
PCIe device
PCIe Clock Buffer
DB400/800 differential
clock negative output pin
for more than one.

PCI Express reference clock input

PCI Express reference clock input

Module has integrated

series resistor
Connect to COME pin
A88 PCIE_CLK_REF+
Connect to REFCLK+ of
for single PCIe device or
PCIe device
PCIe Clock Buffer
DB400/800 differential
clock positive output pin
for more than one.

Return current path, Ground Connect to GND Connect to GND

Connect AC Coupling
cap 0.1uF to PETn0 of
Connect to COME
PCIe device
PCIE_RXx-
Connect AC Coupling
Connect to COME
cap 0.1uF to
USB_SSRXx-
StdA_SSTX- of USB3.0
PCI Express x1 Differential Receive Pairs
device
interface
USB 3.0 SuperSpeed series data interface.
Connect AC Coupling
Differential Receive Pairs
cap 0.1uF to PETp0 of
Connect to COME
PCIe device
PCIE_RXx+
Connect AC Coupling
Connect to COME
cap 0.1uF to
USB_SSRXx+
StdA_SSTX+ of USB3.0
device
Return current path, Ground Connect to GND Connect to GND

Connect to PERn0 of Connect to COME

PCIe device PCIE_TXx-
Connect to StdA_SSRX- Connect to COME
PCI Express x1 Differential Transmit Pairs of USB3.0 device USB_SSTXx-
interface
USB 3.0 SuperSpeed series data interface. Connect to PERp0 of
Differential Transmit Pairs Connect to COME
PCIe device
PCIE_TXx+
Connect to
Connect to COME
StdA_SSRX+ of USB3.0
USB_SSTXx+
device
Return current path, Ground Connect to GND Connect to GND
ExpressCard
Description Baseboard
Power Switch
Connect to 3.3V power
3.3-V input for 3.3VOUT
input
Connect to 1.5V power
1.5-V input for 1.5VOUT
input
Connect to 3.3VSB or
AUX input for AUXOUT and chip power
3.3V power input
Connect to ExpressCard
Switched output that delivers 0 V, 3.3 V or high
Conn. pin14,pin15 +3.3
impedance to card
V

Switched output that delivers 0 V, 1.5 V or high Connect to ExpressCard

impedance to card Conn. pin9,pin10 +1.5 V
 Switched output that delivers 0 V, AUX or high Connect to ExpressCard
impedance to card Conn. pin12 +3.3 VAUX

System Reset input – active low, logic level Connect to COME pin
Pulled up to AUXIN.
signal. Internally pulled up to AUXIN. B50 CB_RESET#

Low - All voltage

Shutdown input – active low, logic level signal. outputs turn off
Pulled up to AUXIN.
Internally pulled up to AUXIN. High or floating -
Former status

Low - 3.3VAUXOUT
turns on and 3.3VOUT
and 1.5VOUT turn off if
Standby input – active low, logic level signal.
Pulled up to AUXIN. ExpressCard is inserted.
Internally pulled up to AUXIN.
High or floating - All
voltage outputs turn on if
ExpressCard is inserted.

Connect to ExpressCard
Conn. pin17 CPPE#
Low - ExpressCard is
Card Present input for PCI Express cards.
Pulled up to AUXIN. inserted.
Internally pulled up to AUXIN
High or floating -
ExpressCard isn't
inserted.

Connect to ExpressCard
Conn. Pin4 CPUSB#
Card Present input for USB cards. Internally Low - USB card is
Pulled up to AUXIN.
pulled up to AUXIN. inserted.
High or floating - USB
card isn't inserted.

Connect to ExpressCard
A logic level power good to slot 0 (with delay)
Conn. Pin13 PERST#

Reference Clock Enable signal.

Connect to PCIe Clock
As an output, a logic level power good to host for
Buffer DB400/800 OE
slot 0 (no delay – open drain).
Pulled up to AUXIN. active high pin for
As an input, if kept inactive (low) by the host,
REFCLK+/- output
prevents PERST from being de-asserted.
enable
Internally pulled up to AUXIN.

Connect to COME
Overcurrent status output for slot 0 (open drain) USB_OC# for USB
overcurrent detective.
d from x.xVSB in S3,S4,S5
 Pwr Rail /
Pin No. DDI Pin Type
Tolerance

I 3.3V / 3.3V
D34 DDI1_DDC_AUX_SEL
CMOS

I 3.3V / 3.3V
C34 DDI2_DDC_AUX_SEL
CMOS

I 3.3V / 3.3V
C38 DDI3_DDC_AUX_SEL
CMOS

I 3.3V / 3.3V
B95 DDI0_DDC_AUX_SEL
CMOS
4.4.6 Digital Display Interfaces (DDI)
The cCarrier based termination requirements are dependent on the video interfaces supported by the Module’s DDI implemen
the display type connected to the cCarrier. A DDI can be used to support one or more of the following interfaces: SDVO, DP, T
or Dual-Mode (DisplayPort and TMDS). Refer to the VESA DisplayPort Interoperability Guideline Version 1.1a dated February
at the VESA website after registration http://www.vesa.org/vesa-standards/ http://www.vesa.org/Standards/free.htm for more in
supporting TMDS (DVI/HDMI) from a Dual-Mode Module.

Carriers that support DisplayPort (DisplayPort only or dual mode):

• Carrier DDI[n]_DDC_AUX_SEL should be connected to pin 13 of the DisplayPort connector to enable Modules that can sup
DisplayPort interface.
Figure 4-1: Dual-Mode COM Express® Module Implementation
 Description Pin Availability Baseboard

Module has integrated

PD resistor to GND
DP1 AUX+/- - N/C
DDI1 CRTLCLK and
CTRLDATA - PU 100K
T6
to 3.3V
or connects to DP Conn.
pin 13 of Dual-Mode
DisplayPort interface
N/C if not used.

Module has integrated

PD resistor to GND
Selects the function of DDI[1:3]_CTRLCLK_AUX+
DP2 AUX+/- - N/C
and DDI[1:3]_CTRLDATA_AUX-. This pin shall
DDI2 CRTLCLK and
have a 1M pull-down to logic ground on the
CTRLDATA - PU 100K
Module. If this input is floating the AUX pair is T6
to 3.3V
used for the DP AUX+/- signals. If pulled-high the
or connects to DP Conn.
AUX pair contains the CRTLCLK and CTRLDATA
pin 13 of Dual-Mode
signals.
DisplayPort interface
N/C if not used.

Module has integrated

PD resistor to GND
DP3 AUX+/- - N/C
DDI3 CRTLCLK and
CTRLDATA - PU 100K
T6
to 3.3V
or connects to DP Conn.
pin 13 of Dual-Mode
DisplayPort interface
N/C if not used.

Module has integrated

PD resistor to GND
Selects the function of DDI[0]_CTRLCLK_AUX+
DP0 AUX+/- - N/C
and DDI[0]_CTRLDATA_AUX-. This pin shall
DDI0 CRTLCLK and
have a 1M pull-down to logic ground on the
CTRLDATA - PU 100K
Module. If this input is floating the AUX pair is T10
to 3.3V
used for the DP AUX+/- signals. If pulled-high the
or connects to DP Conn.
AUX pair contains the CRTLCLK and CTRLDATA
pin 13 of Dual-Mode
signals.
DisplayPort interface
N/C if not used.
dent on the video interfaces supported by the Module’s DDI implementation as well as
e used to support one or more of the following interfaces: SDVO, DP, TMDS(DVI/HDMI),
SA DisplayPort Interoperability Guideline Version 1.1a dated February 5, 2009 available
rg/vesa-standards/ http://www.vesa.org/Standards/free.htm for more information on
e.

al mode):
o pin 13 of the DisplayPort connector to enable Modules that can support a Dual-Mode

mentation
 SOM-5894 A101-4
Baseboard

Module has integrated

PD resistor to GND
DP1 AUX+/- - N/C
DDI1 CRTLCLK and
CTRLDATA - PU 100K
to 3.3V
or connects to DP Conn.
pin 13 of Dual-Mode
DisplayPort interface
N/C if not used.

Module has integrated

PD resistor to GND
DP2 AUX+/- - N/C
DDI2 CRTLCLK and
CTRLDATA - PU 100K
to 3.3V
or connects to DP Conn.
pin 13 of Dual-Mode
DisplayPort interface
N/C if not used.

Module has integrated

PD resistor to GND
DP3 AUX+/- - N/C
DDI3 CRTLCLK and
CTRLDATA - PU 100K
to 3.3V
or connects to DP Conn.
pin 13 of Dual-Mode
DisplayPort interface
N/C if not used.

N/C
 Pwr Rail /
Pin No. DDI-SDVO Pin Type
Tolerance

D26 SDVO1_RED+

O AC coupled off
PCIE Module

D27 SDVO1_RED-

D29 SDVO1_GRN+

O AC coupled off
PCIE Module

D30 SDVO1_GRN-

D32 SDVO1_BLU+

O AC coupled off
PCIE Module
 O AC coupled off
PCIE Module

D33 SDVO1_BLU-

D36 SDVO1_CK+

O AC coupled off
PCIE Module

D37 SDVO1_CK-

C25 SDVO1_INT+

I AC coupled off
PCIE Module

C26 SDVO1_INT-
C29 SDVO1_TVCLKIN+

I AC coupled off
PCIE Module

C30 SDVO1_TVCLKIN-

C15 SDVO1_FLDSTALL+

I AC coupled off
PCIE Module

C16 SDVO1_FLDSTALL-
 I/O OD 3.3V / 3.3V
D15 SDVO1_CTRLCLK
CMOS

I/O OD 3.3V / 3.3V

D16 SDVO1_CTRLDATA
CMOS

B71 SDVO0_RED+

O AC coupled off
PCIE Module

B72 SDVO0_RED-
B73 SDVO0_GRN+

O AC coupled off
PCIE Module

B74 SDVO0_GRN-

B75 SDVO0_BLU+

O AC coupled off
PCIE Module

B76 SDVO_BLU-

B81 SDVO0_CK+

O AC coupled off
PCIE Module
 O AC coupled off
PCIE Module

B82 SDVO0_CK-

B77 SDVO0_INT+

I AC coupled off
PCIE Module

B78 SDVO0_INT-

B91 SDVO0_TVCLKIN+

I AC coupled off
PCIE Module
 I AC coupled off
PCIE Module

B92 SDVO0_TVCLKIN-

B93 SDVO0_FLDSTALL+

I AC coupled off
PCIE Module

B94 SDVO0_FLDSTALL-

I/O OD 3.3V / 3.3V

B98 SDVO0_CTRLCLK
CMOS
 I/O OD 3.3V / 3.3V
B99 SDVO0_CTRLDATA
CMOS

4.3.17 DDI Signals: SDVO

Carriers that support SDVO:
• DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm resistor to configure the DDI[n]_AUX pa
channel.
• DC blocking capacitors shall be placed on the Carrier for the SDVO RED, GRN, BLU, CK, INT, TVCLKIN, and FLDSTAL
The DDI signals can be used to support a variety of video interfaces. The circuits required to realize the different video inte
determined by a future PICMG Carrier Design Guide subcommittee. At this time, thew only requirement placed on Modules
signals is the maximum trace length specified below. SDVO Loss Budget

SDVO Insertion Loss Budget

max. Length
Segment Notes
[mm/inches]
LA 127/5.0 Allowance for module trace. Coupling cap effects included within simulation.
LB COM Express™ connector simulated at 2.5 GHz.
LC TBD Allowance for Carrier Board trace.
Total TBD
The TBD values will be determined by a future PICMG Carrier Design Guide.
 Pwr Rail /
Pin No. SDVO Slot Pin Type
Tolerance
Side B
B1 12 V Power
B2 12 V Power
B3 12 V Power
B4 GND Power
B5 NC
B6 NC
B7 GND Power
B8 3.3 V Power
B9 NC
B10 NC
B11 NC
Mechanical key
B12 Reserved
B13 GND Power

B14 SDVOB_Red+

I AC coupled
PCIe on module

B15 SDVOB_Red-

B16 GND Power

I/O OD
B17 SDVO_CtrlClk 2.5V / 2.5V
CMOS

B18 GND Power

End of the x1 connector

B19 SDVOB_Green+

I AC coupled
PCIe on module
 I AC coupled
PCIe on module

B20 SDVOB_Green-

B21 GND Power

B22 GND Power

B23 SDVOB_Blue+

I AC coupled
PCIe on module

B24 SDVOB_Blue-

B25 GND Power

B26 GND Power

B27 SDVOB_Clk+

I AC coupled
PCIe on module

B28 SDVOB_Clk-

B29 GND Power

B30 Reserved

I/O OD
B31 SDVO_CtrlData 2.5V / 2.5V
CMOS

B32 GND Power

End of the x4 connector
B33 SDVOC_Red+ I AC coupled
B34 SDVOC_Red- PCIe on module
B35 GND Power
B36 GND Power
B37 SDVOC_Green+ I AC coupled
B38 SDVOC_Green- PCIe on module
B39 GND Power
B40 GND Power
B41 SDVOC_Blue+ I AC coupled
PCIe on module
 I AC coupled
B42 SDVOC_Blue- PCIe on module
B43 GND Power
B44 GND Power
B45 SDVOC_Clk+ I AC coupled
B46 SDVOC_Clk- PCIe on module
B47 GND Power
B48 NC
B49 GND Power
End of the x8 connector
B50 NC
B51 NC
B52 GND Power
B53 GND Power
B54 NC
B55 NC
B56 GND Power
B57 GND Power
B58 NC
B59 NC
B60 GND Power
B61 GND Power
B62 NC
B63 NC
B64 GND Power
B65 GND Power
B66 NC
B67 NC
B68 GND Power
B69 GND Power
B70 NC
B71 NC
B72 GND Power
B73 GND Power
B74 NC
B75 NC
B76 GND Power
B77 GND Power
B78 NC
B79 NC
B80 GND Power
B81 NC
B82 Reserved
End of the x16 connector
Side A
A1 NC
A2 12 V Power
A3 12 V Power
A4 GND Power
A5 NC
O
A6 TDI 3.3V / 3.3V
CMOS
I
A7 TDO 3.3V / 3.3V
CMOS
A8 NC
A9 3.3 V Power
A10 3.3 V Power

I 3.3V Suspend
A11 Fundamental Reset
CMOS / 3.3V

Mechanical key
A12 GND Power
A13 NC
A14 NC
A15 GND Power

A16 SDVO_TVClkIn+

O AC coupled
PCIe off module

A17 SDVO_TVClkIn-

A18 GND Power

End of the x1 connector
A19 Reserved
A20 GND Power

A21 SDVOB_Int+
O AC coupled
PCIe off module
A22 SDVOB_Int-

A23 GND Power

A24 GND Power

A25 SDVO_Stall+

O AC coupled
PCIe off module

A26 SDVO_Stall-

A27 GND Power

A28 GND Power
A29 NC
A30 NC
A31 GND Power
A32 Reserved
 End of the x4 connector
A33 Reserved
A34 GND Power
A35 NC
A36 NC
A37 GND Power
A38 GND Power
A39 SDVOC_Int+ O AC coupled
A40 SDVOC_Int- PCIe off module
A41 GND Power
A42 GND Power
A43 NC
A44 NC
A45 GND Power
A46 GND Power
A47 NC
A48 NC
A49 GND Power
End of the x8 connector
A50 Reserved
A51 GND Power
A52 NC
A53 NC
A54 GND Power
A55 GND Power
A56 NC
A57 NC
A58 GND Power
A59 GND Power
A60 NC
A61 NC
A62 GND Power
A63 GND Power
A64 NC
A65 NC
A66 GND Power
A67 GND Power
A68 NC
A69 NC
A70 GND Power
A71 GND Power
A72 NC
A73 NC
A74 GND Power
A75 GND Power
A76 NC
A77 NC
A78 GND Power
A79 GND Power
A80 NC
A81 NC
A82 GND Power
End of the x16 connector
PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 Description Pin Availability Baseboard

Connect AC Coupling
Capacitors 75~200nF
near COME to
Device - Connect to
SDVO device
SDVO_RED+.
Slot - Connect to SDVO
Conn pin B14
SDVO_RED+.
N/C if not used.
Serial Digital Video red output differential pair

Connect AC Coupling
Capacitors 75~200nF
near COME to
Device - Connect to
SDVO device
SDVO_RED-
Slot - Connect to SDVO
Conn pin B15
SDVO_RED-
N/C if not used.

Connect AC Coupling
Capacitors 75~200nF
near COME to
Device - Connect to
SDVO device
SDVO_GRN+
Slot - Connect to SDVO
Conn pin B19
SDVO_GRN+
N/C if not used.
Serial Digital Video green output differential pair

Connect AC Coupling
Capacitors 75~200nF
near COME to
Device - Connect to
SDVO device
SDVO_GRN-
Slot - Connect to SDVO
Conn pin B20
SDVO_GRN-
N/C if not used.

Connect AC Coupling
Capacitors 75~200nF
near COME to
Device - Connect to
SDVO device
SDVO_BLU+
Slot - Connect to SDVO
Conn pin B23
SDVO_BLU+
N/C if not used.
Serial Digital Video blue output differential pair
Serial Digital Video blue output differential pair

Connect AC Coupling
Capacitors 75~200nF
near COME to
Device - Connect to
SDVO device
SDVO_BLU-
Slot - Connect to SDVO
Conn pin B24
SDVO_BLU-
N/C if not used.

Connect AC Coupling
Capacitors 75~200nF
near COME to
Device - Connect to
SDVO device
SDVO_CK+
Slot - Connect to SDVO
Conn pin B27
SDVO_CK+
N/C if not used.
Serial Digital Video clock output differential pair.

Connect AC Coupling
Capacitors 75~200nF
near COME to
Device - Connect to
SDVO device
SDVO_CK-
Slot - Connect to SDVO
Conn pin B28
SDVO_CK-
N/C if not used.

Device - Connect AC
Coupling cap 75~200nF
near COME to SDVO
device SDVO_INT+
Slot - Connect to SDVO
Conn pin A21
SDVO_INT+
T6 PCH recommendation
if not used.

Serial Digital Video interrupt input differential

pair.

Device - Connect AC
Coupling cap 75~200nF
near COME to SDVO
device SDVO_INT-
Slot - Connect to SDVO
Conn pin A22
SDVO_INT-
PCH recommendation
if not used.
 Device - Connect AC
Coupling cap 75~200nF
near COME to SDVO
device
SDVO_TVCLKIN+
Slot - Connect to SDVO
Conn pin A16
SDVO_TVCLKIN+
PCH recommendation
if not used.

Serial Digital Video TVOUT synchronization

clock input

Device - Connect AC
Coupling cap 75~200nF
near COME to SDVO
device
SDVO_TVCLKIN-
Slot -Connect to SDVO
Conn pin A17
SDVO_TVCLKIN-
PCH recommendation
if not used.

Device - Connect AC
Coupling cap 75~200nF
near COME to SDVO
device
SDVO_FLDSTALL+
Slot - Connect to SDVO
Conn pin A25
SDVO_FLDSTALL+
PCH recommendation
if not used.

Serial Digital Video Field Stall input differential

pair.

Device - Connect AC
Coupling cap 75~200nF
near COME to SDVO
device
SDVO_FLDSTALL-
Slot - Connect to SDVO
Conn pin A26
SDVO_FLDSTALL-
PCH recommendation
if not used.
 PU 2.2KΩ to 3.3V and
connect 2.5V to 3.3V
Level Shifter to
Device - SDVO device
SDVO_CTRLCLK with
SDVO I2C clock line -to set up SDVO
PU 4K~9KΩ to 2.5V
peripherals.
Slot - SDVO Conn pin
B17 SDVO_CTRLCLK
N/C if not used
Set the I²C address of
SDVO to be 70h

PU 2.2KΩ to 3.3V and

connect 2.5V to 3.3V
Level Shifter to
Device - SDVO device
SDVO_CTRLDATA with
SDVO I2C data line -to set up SDVO peripherals.
PU 4K~9KΩ to 2.5V.
Slot - SDVO Conn pin
B31 SDVO_CTRLDATA
N/C if not used
Set the I²C address of
SDVO to be 70h

Connect AC Coupling
Capacitors 75~200nF
near COME to
Device - Connect to
SDVO device
SDVO_RED+.
Slot - Connect to SDVO
Conn pin B14
SDVO_RED+.
N/C if not used.
Serial Digital Video red output differential pair

Connect AC Coupling
Capacitors 75~200nF
near COME to
Device - Connect to
SDVO device
SDVO_RED-
Slot - Connect to SDVO
Conn pin B15
SDVO_RED-
N/C if not used.
 Connect AC Coupling
Capacitors 75~200nF
near COME to
Device - Connect to
SDVO device
SDVO_GRN+
Slot - Connect to SDVO
Conn pin B19
SDVO_GRN+
N/C if not used.
Serial Digital Video green output differential pair

Connect AC Coupling
Capacitors 75~200nF
near COME to
Device - Connect to
SDVO device
SDVO_GRN-
Slot - Connect to SDVO
Conn pin B20
SDVO_GRN-
N/C if not used.

Connect AC Coupling
Capacitors 75~200nF
near COME to
Device - Connect to
SDVO device
SDVO_BLU+
Slot - Connect to SDVO
Conn pin B23
SDVO_BLU+
N/C if not used.
Serial Digital Video blue output differential pair

Connect AC Coupling
Capacitors 75~200nF
near COME to
Device - Connect to
SDVO device
SDVO_BLU-
Slot - Connect to SDVO
Conn pin B24
SDVO_BLU-
N/C if not used.

Connect AC Coupling
Capacitors 75~200nF
near COME to
Device - Connect to
SDVO device
SDVO_CK+
Slot - Connect to SDVO
Conn pin B27
SDVO_CK+
N/C if not used.
Serial Digital Video clock output differential pair.
Serial Digital Video clock output differential pair.

Connect AC Coupling
Capacitors 75~200nF
near COME to
Device - Connect to
SDVO device
SDVO_CK-
Slot - Connect to SDVO
Conn pin B28
SDVO_CK-
N/C if not used.

Device - Connect AC
Coupling cap 75~200nF
near COME to SDVO
device SDVO_INT+
Slot - Connect to SDVO
Conn pin A21
T10 SDVO_INT+
PCH recommendation
if not used.

Serial Digital Video interrupt input differential

pair.

Device - Connect AC
Coupling cap 75~200nF
near COME to SDVO
device SDVO_INT-
Slot - Connect to SDVO
Conn pin A22
SDVO_INT-
PCH recommendation
if not used.

Device - Connect AC
Coupling cap 75~200nF
near COME to SDVO
device
SDVO_TVCLKIN+
Slot - Connect to SDVO
Conn pin A16
SDVO_TVCLKIN+
PCH recommendation
if not used.

Serial Digital Video TVOUT synchronization

clock input
 Serial Digital Video TVOUT synchronization
clock input

Device - Connect AC
Coupling cap 75~200nF
near COME to SDVO
device
SDVO_TVCLKIN-
Slot -Connect to SDVO
Conn pin A17
SDVO_TVCLKIN-
PCH recommendation
if not used.

Device - Connect AC
Coupling cap 75~200nF
near COME to SDVO
device
SDVO_FLDSTALL+
Slot - Connect to SDVO
Conn pin A25
SDVO_FLDSTALL+
PCH recommendation
if not used.

Serial Digital Video Field Stall input differential

pair.

Device - Connect AC
Coupling cap 75~200nF
near COME to SDVO
device
SDVO_FLDSTALL-
Slot - Connect to SDVO
Conn pin A26
SDVO_FLDSTALL-
PCH recommendation
if not used.

PU 2.2KΩ to 3.3V and

connect 2.5V to 3.3V
Level Shifter to
Device - SDVO device
SDVO_CTRLCLK with
SDVO I2C clock line -to set up SDVO
PU 4K~9KΩ to 2.5V
peripherals.
Slot - SDVO Conn pin
B17 SDVO_CTRLCLK
N/C if not used
Set the I²C address of
SDVO to be 70h
 PU 2.2KΩ to 3.3V and
connect 2.5V to 3.3V
Level Shifter to
Device - SDVO device
SDVO_CTRLDATA with
SDVO I2C data line -to set up SDVO peripherals.
PU 4K~9KΩ to 2.5V.
Slot - SDVO Conn pin
B31 SDVO_CTRLDATA
N/C if not used
Set the I²C address of
SDVO to be 70h

n the Carrier with a 100K Ohm resistor to configure the DDI[n]_AUX pair as the DDC

rrier for the SDVO RED, GRN, BLU, CK, INT, TVCLKIN, and FLDSTALL signals.
video interfaces. The circuits required to realize the different video interfaces will be
e subcommittee. At this time, thew only requirement placed on Modules for the DDI
. SDVO Loss Budget

Loss Budget
Notes

module trace. Coupling cap effects included within simulation.

™ connector simulated at 2.5 GHz.
Carrier Board trace.

MG Carrier Design Guide.

 Description ADD2-N card
Side B
12 V power Connect to 12V power
12 V power Connect to 12V power
12 V power Connect to 12V power
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
3.3 V power Connect to 3.3V power
NC N/C
NC N/C
NC N/C
Mechanical key
Reserved N/C
Ground Connect to GND

Connect to SDVO
device SDVO_RED+.

Serial Digital Video B red output differential pair

Connect to SDVO
device SDVO_RED-

Ground Connect to GND

Connect to to SDVO
device
SDVO I C clock line
2
SDVO_CTRLCLK with
PU 2.2K~5.6 KΩ to 2.5V

Ground Connect to GND

End of the x1 connector

Connect to SDVO
device SDVO_GRN+

Serial Digital Video B green output differential pair

 Serial Digital Video B green output differential pair

Connect to SDVO
device SDVO_GRN-

Ground Connect to GND

Ground Connect to GND

Connect to SDVO
device SDVO_BLU+

Serial Digital Video B blue output differential pair

Connect to SDVO
device SDVO_BLU-

Ground Connect to GND

Ground Connect to GND

Connect to SDVO
device SDVOB_CK+

Serial Digital Video B clock output differential pair.

Connect to SDVO
device SDVOB_CK-

Ground Connect to GND

Reserved N/C

Connect to to SDVO
device
SDVO I2C data line
SDVO_CTRLDATA with
PU 2.2K~5.6 KΩ to 2.5V

Ground Connect to GND

End of the x4 connector
Serial Digital Video C red output differential pair.
Ground Connect to GND
Ground Connect to GND
Serial Digital Video C green output differential pair.
Ground Connect to GND
Ground Connect to GND
Serial Digital Video C blue output differential pair
 Serial Digital Video C blue output differential pair
Ground Connect to GND
Ground Connect to GND
Serial Digital Video C clock output differential pair.
Ground Connect to GND
NC N/C
Ground Connect to GND
End of the x8 connector
NC N/C
NC N/C
Ground Connect to GND
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
NC N/C
Reserved N/C
End of the x16 connector
Side A
NC N/C
12 V power Connect to 12V power
12 V power Connect to 12V power
Ground Connect to GND
NC N/C
Connect to JTAG TDI of
TDI (Test Data Input)
Device
Connect to JTAG TDO
TDO (Test Data Output)
of Device
NC N/C
 3.3 V power Connect to 3.3V power
3.3 V power Connect to 3.3V power

Connect to PERST# of
Fundamental Reset
device.

Mechanical key
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND

Connect AC Coupling
cap 0.1uF near COME
to SDVO device
SDVO_TVCLKIN+
Serial Digital Video TVOUT synchronization clock input differential pair.
Connect AC Coupling
cap 0.1uF near COME
to SDVO device
SDVO_TVCLKIN-

Ground Connect to GND

End of the x1 connector
Reserved N/C
Ground Connect to GND
Connect AC Coupling
cap 0.1uF near COME
to SDVO device
SDVO_INT+
Serial Digital Video B interrupt input differential pair.
Connect AC Coupling
cap 0.1uF near COME
to SDVO device
SDVO_INT-
Ground Connect to GND
Ground Connect to GND

Connect AC Coupling
cap 0.1uF near COME
to SDVO device
SDVO_FLDSTALL+
Serial Digital Video Field Stall input differential pair.
Connect AC Coupling
cap 0.1uF near COME
to SDVO device
SDVO_FLDSTALL-

Ground Connect to GND

Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
Reserved N/C
End of the x4 connector
Reserved N/C
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
Ground Connect to GND
Serial Digital Video C interrupt input differential pair.
Ground Connect to GND
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
End of the x8 connector
Reserved N/C
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
Ground Connect to GND
NC N/C
NC N/C
Ground Connect to GND
End of the x16 connector
from x.xVSB in S3,S4,S5
SOM-5894 A101-4
Baseboard
N/C
 Baseboard

Connect to 12V power

Connect to 12V power
Connect to 12V power
Connect to GND
N/C
N/C
Connect to GND
Connect to 3.3V power
N/C
N/C
N/C

N/C
Connect to GND

Connect AC Coupling
Capacitors 75~200 nF
near COME to COME
pin D26 SDVO1_RED+
or B71 SDVO0_RED+

Connect AC Coupling
Capacitors 75~200 nF
near COME to COME
pin D27 SDVO1_RED-
or B72 SDVO0_RED-

Connect to GND
Connect to to COME pin
D15 SDVO1_CTRLCLK
or B98
SDVO0_CTRLCLK
Set the I²C address of
SDVOB to be 70h and
SDVOC to be 72h
Connect to GND

Connect AC Coupling
Capacitors 75~200 nF
near COME to COME
pin D29 SDVO1_GRN+
or B73 SDVO0_GRN+
Connect AC Coupling
Capacitors 75~200 nF
near COME to COME
pin D30 SDVO1_GRN-
or B74 SDVO0_GRN-

Connect to GND
Connect to GND

Connect AC Coupling
Capacitors 75~200 nF
near COME to COME
pin D32 SDVO1_BLU+
or B75 SDVO0_BLU+

Connect AC Coupling
Capacitors 75~200 nF
near COME to COME
pin D33 SDVO1_BLU-
or B76 SDVO_BLU-

Connect to GND
Connect to GND
Connect AC Coupling
Capacitors 75~200 nF
near COME to COME
pin D36 SDVO1_CK+ or
B81 SDVO0_CK+

Connect AC Coupling
Capacitors 75~200 nF
near COME to COME
pin D37 SDVO1_CK- or
B82 SDVO0_CK-
Connect to GND
N/C
Connect to COME
pinD16
SDVO1_CTRLDATA or
B99
SDVO0_CTRLDATA
Set the I²C address of
SDVOB to be 70h and
SDVOC to be 72h
Connect to GND

N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
 N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
N/C
Connect to GND

N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
N/C
N/C

N/C
Connect to 12V power
Connect to 12V power
Connect to GND
N/C
Connect 0Ω in series to
TDO
Connect 0Ω in series to
TDI
N/C
Connect to 3.3V power
Connect to 3.3V power

Module has integrated

3.3VDUAL buffer and
series resistor
Connect to COME pin
B50 CB_RESET#

Connect to GND
N/C
N/C
Connect to GND

Connect to COME pin

C29 SDVO1_TVCLKIN+
or B91
SDVO0_TVCLKIN+

Connect to COME pin

C30 SDVO1_TVCLKIN-
or B92
SDVO0_TVCLKIN-

Connect to GND

N/C
Connect to GND

Connect to COME pin

C25 SDVO1_INT+ or
B77 SDVO0_INT+

Connect to COME pin

C26 SDVO1_INT- or
B78 SDVO0_INT-

Connect to GND
Connect to GND
Connect to COME pin
C15
SDVO1_FLDSTALL+ or
B93
SDVO0_FLDSTALL+
Connect to COME pin
C16
SDVO1_FLDSTALL- or
B94
SDVO0_FLDSTALL-
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
N/C
 N/C
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND

N/C
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
Connect to GND
N/C
N/C
Connect to GND
 Pwr Rail /
Pin No. DDI-DisplayPort Pin Type
Tolerance

D26 DP1_LANE0+

D27 DP1_LANE0-

D29 DP1_LANE1+

D30 DP1_LANE1-

O AC coupled off
PCIE Module
 O AC coupled off
PCIE Module

D32 DP1_LANE2+

D33 DP1_LANE2-

D36 DP1_LANE3+

D37 DP1_LANE3-
D15 DP1_AUX+

I/O AC coupled on
PCIE Module

D16 DP1_AUX-

I
C24 DP1_HPD 3.3V / 3.3V
CMOS

D39 DP2_LANE0+
D40 DP2_LANE0-

D42 DP2_LANE1+

D43 DP2_LANE1-

O AC coupled off
PCIE Module

D46 DP2_LANE2+
D47 DP2_LANE2-

D49 DP2_LANE3+

D50 DP2_LANE3-

C32 DP2_AUX+

I/O AC coupled on
PCIE Module
 I/O AC coupled on
PCIE Module

C33 DP2_AUX-

I
D44 DP2_HPD 3.3V / 3.3V
CMOS

C39 DP3_LANE0+

C40 DP3_LANE0-
C42 DP3_LANE1+

C43 DP3_LANE1-

O AC coupled off
PCIE Module

C46 DP3_LANE2+

C47 DP3_LANE2-
C49 DP3_LANE3+

C50 DP3_LANE3-

C36 DP3_AUX+

I/O AC coupled on
PCIE Module

C37 DP3_AUX-
 I
C44 DP3_HPD 3.3V / 3.3V
CMOS

B71 DP0_LANE0+

B72 DP0_LANE0-

B73 DP0_LANE1+
B74 DP0_LANE1-

O AC coupled off
PCIE Module

B75 DP0_LANE2+

B76 DP0_LANE2-

B81 DP0_LANE3+
B82 DP0_LANE3-

B98 DP0_AUX+

I/O AC coupled on
PCIE Module

B99 DP0_AUX-

I
B89 DP0_HPD 3.3V / 3.3V
CMOS
4.3.16 DDI Signals: DisplayPort
Carriers that support DisplayPort (DisplayPort only or dual mode):
• DC blocking capacitors shall be placed on the Carrier for the DDI[n]_PAIR[0:3] signals.
• The Carrier shall include a blocking FET on DDI[n]_HPD to prevent back-drive current from damaging the Module.

When implementing DisplayPort on the Carrier Board, the DP_AUX+ line shall have a pulldown resistor to GND. The resistor
be 100kΩ. The DP_AUX- line shall have a pull-up resistor to 2.5V. The resistor value should be 100kΩ. The resistors shall b
the DisplayPort connector side of the AC coupling capacitors. The DP_HP signal shall include a blocking FET to prevent back
damage. The DP_HP signal shall be pulled-down to GND with a 110kΩ resistor.
The DDI signals can be used to support a variety of video interfaces. The circuits required to realize the different video interfac
determined by a future PICMG Carrier Design Guide subcommittee. At this time, thew only requirement placed on Modules for
signals is the maximum trace length specified below.
DisplayPort Loss Budget

DisplayPort Insertion Loss Budget

max. Length
Segment Notes
[mm/inches]
LA 127/5.0 Allowance for module trace. Coupling cap effects included within simulation.
LB COM Express™ connector simulated at 2.5 GHz.
LC TBD Allowance for Carrier Board trace.
Total TBD
The TBD values will be determined by a future PICMG Carrier Design Guide.
 Source-side DisplayPort Pwr Rail /
Pin Pin Type
Connector Tolerance

I AC Coupled
1 ML_Lane 0 (p) DP on Module

2 GND Power

I AC Coupled
3 ML_Lane 0 (n) DP on Module

I AC Coupled
4 ML_Lane 1 (p) DP on Module

5 GND Power

I AC Coupled
6 ML_Lane 1 (n) DP on Module
 I AC Coupled
7 ML_Lane 2 (p) DP on Module

8 GND Power

I AC Coupled
9 ML_Lane 2 (n) DP on Module

I AC Coupled
10 ML_Lane 3 (p) DP on Module

11 GND Power

I AC Coupled
12 ML_Lane 3 (n) DP on Module
 GND or CAD
13 Power
(CONFIG1)

GND or CEC
14 Power
(CONFIG2)

O AC Coupled
15 AUX CH (p) DP off Module

16 GND Power

O AC Coupled
17 AUX CH (n) DP off Module
 O
18 Hot Plug Detect DP
3.3V / 3.3V

19 Return Power
20 DP_PWR Power 3.3V

Source-side Mini Pwr Rail /

Pin Pin Type
DisplayPort Connector Tolerance
1 GND Power

O
2 Hot Plug Detect DP
3.3V / 3.3V

I AC Coupled
3 ML_Lane 0 (p) DP on Module

GND or CAD
4 Power
(CONFIG1)
 I AC Coupled
5 ML_Lane 0 (n) DP on Module

GND or CEC
6 Power
(CONFIG2)

7 GND Power
8 GND Power

I AC Coupled
9 ML_Lane 1 (p) DP on Module

I AC Coupled
10 ML_Lane 3 (p) DP on Module

I AC Coupled
11 ML_Lane 1 (n) DP on Module

I AC Coupled
12 ML_Lane 3 (n) DP on Module

13 GND Power
14 GND Power
 I AC Coupled
15 ML_Lane 2 (p) DP on Module

O AC Coupled
16 AUX CH (p) DP off Module

I AC Coupled
17 ML_Lane 2 (n) DP on Module

O AC Coupled
18 AUX CH (n) DP off Module

19 Return Power
20 DP_PWR Power 3.3V

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 Description Pin Availability Baseboard

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort1
receiver ML_Lane 0(p).
DisplayPort -
DisplayPort1 Conn pin 1
ML_Lane 0(p) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort1
receiver ML_Lane 0(n).
DisplayPort -
DisplayPort1 Conn pin 3
ML_Lane 0(n) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort1
receiver ML_Lane 1(p).
DisplayPort -
DisplayPort1 Conn pin 4
ML_Lane 1(p) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort1
receiver ML_Lane 1(n).
DisplayPort -
DisplayPort1 Conn pin 6
ML_Lane 1(n) and ESD
protection
N/C if not used.
Uni-directional main link for the transport of
isochronous streams and secondary-data packets
 Uni-directional main link for the transport of
isochronous streams and secondary-data packets

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort1
receiver ML_Lane 2(p).
DisplayPort -
DisplayPort1 Conn pin 7
ML_Lane 2(p) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort1
receiver ML_Lane 2(n).
DisplayPort -
DisplayPort1 Conn pin 9
ML_Lane 2(n) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort1
receiver ML_Lane 3(p).
DisplayPort -
DisplayPort1 Conn pin
10 ML_Lane 3(p) and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort1
receiver ML_Lane 3(n).
DisplayPort -
DisplayPort1 Conn pin
12 ML_Lane 3(n) and
ESD protection
N/C if not used.
 Module has integrated
AC Coupling Capacitor
and PD resistor to GND
Connect to
Device - DisplayPort1
receiver AUX CH(p).
DisplayPort -
DisplayPort1 Conn pin
15 AUX CH(p) and ESD
protection
N/C if not used.
Half-duplex bi-directional AUX channel for
services such as link configuration or
maintenance and EDID access
Module has integrated
AC Coupling Capacitor
and PU resistor to 3.3V
Connect to
Device - DisplayPort1
receiver AUX CH(n).
DisplayPort -
DisplayPort1 Conn pin
17 AUX CH(n) and ESD
protection
N/C if not used.

Module has integrated

current blocking circuit
and PD resistor to GND
Connect to
Detection of Hot Plug / Unplug and notification Device - DisplayPort1
of the link layer device Hot Plug Detect
DisplayPort -
DisplayPort1 Conn pin
18 Hot Plug Detect
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device -DisplayPort2
receiver ML_Lane 0(p).
DisplayPort -
DisplayPort2 Conn pin 1
ML_Lane 0(p) and ESD
protection
N/C if not used.
 Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort2
receiver ML_Lane 0(n).
DisplayPort -
DisplayPort2 Conn pin 3
ML_Lane 0(n) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort2
receiver ML_Lane 1(p).
DisplayPort -
DisplayPort2 Conn pin 4
ML_Lane 1(p) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort2
receiver ML_Lane 1(n).
DisplayPort -
DisplayPort2 Conn pin 6
ML_Lane 1(n) and ESD
protection
N/C if not used.
Uni-directional main link for the transport of
isochronous streams and secondary-data packets

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort2
receiver ML_Lane 2(p).
DisplayPort -
DisplayPort2 Conn pin 7
ML_Lane 2(p) and ESD
protection
N/C if not used.

T6
 T6 Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort2
receiver ML_Lane 2(n).
DisplayPort -
DisplayPort2 Conn pin 9
ML_Lane 2(n) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort2
receiver ML_Lane 3(p).
DisplayPort -
DisplayPort2 Conn pin
10 ML_Lane 3(p) and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort2
receiver ML_Lane 3(n).
DisplayPort -
DisplayPort2 Conn pin
12 ML_Lane 3(n) and
ESD protection
N/C if not used.

Module has integrated

AC Coupling Capacitor
and PD resistor to GND
Connect to
Device - DisplayPort2
receiver AUX CH(p).
DisplayPort -
DisplayPort2 Conn pin
15 AUX CH(p) and ESD
protection
N/C if not used.
Half-duplex bi-directional AUX channel for
services such as link configuration or
maintenance and EDID access
 Half-duplex bi-directional AUX channel for
services such as link configuration or
maintenance and EDID access
Module has integrated
AC Coupling Capacitor
and PU resistor to 3.3V
Connect to
Device - DisplayPort2
receiver AUX CH(n).
DisplayPort -
DisplayPort2 Conn pin
17 AUX CH(n) and ESD
protection
N/C if not used.

Module has integrated

current blocking circuit
and PD resistor to GND
Connect to
Detection of Hot Plug / Unplug and notification Device - DisplayPort2
of the link layer device Hot Plug Detect
DisplayPort -
DisplayPort2 Conn pin
18 Hot Plug Detect
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort3
receiver ML_Lane 0(p).
DisplayPort -
DisplayPort3 Conn pin 1
ML_Lane 0(p) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort3
receiver ML_Lane 0(n).
DisplayPort -
DisplayPort3 Conn pin 3
ML_Lane 0(n) and ESD
protection
N/C if not used.
 Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort3
receiver ML_Lane 1(p).
DisplayPort -
DisplayPort3 Conn pin 4
ML_Lane 1(p) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort3
receiver ML_Lane 1(n).
DisplayPort -
DisplayPort3 Conn pin 6
ML_Lane 1(n) and ESD
protection
N/C if not used.
Uni-directional main link for the transport of
isochronous streams and secondary-data packets

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort3
receiver ML_Lane 2(p).
DisplayPort -
DisplayPort3 Conn pin 7
ML_Lane 2(p) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort3
receiver ML_Lane 2(n).
DisplayPort -
DisplayPort3 Conn pin 9
ML_Lane 2(n) and ESD
protection
N/C if not used.
 Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort3
receiver ML_Lane 3(p).
DisplayPort -
DisplayPort3 Conn pin
10 ML_Lane 3(p) and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort3
receiver ML_Lane 3(n).
DisplayPort -
DisplayPort3 Conn pin
12 ML_Lane 3(n) and
ESD protection
N/C if not used.

Module has integrated

AC Coupling Capacitor
and PD resistor to GND
Connect to
Device - DisplayPort3
receiver AUX CH(p).
DisplayPort -
DisplayPort3 Conn pin
15 AUX CH(p) and ESD
protection
N/C if not used.
Half-duplex bi-directional AUX channel for
services such as link configuration or
maintenance and EDID access
Module has integrated
AC Coupling Capacitor
and PU resistor to 3.3V
Connect to
Device - DisplayPort3
receiver AUX CH(n).
DisplayPort -
DisplayPort3 Conn pin
17 AUX CH(n) and ESD
protection
N/C if not used.
 Module has integrated
current blocking circuit
and PD resistor to GND
Connect to
Detection of Hot Plug / Unplug and notification Device - DisplayPort3
of the link layer device Hot Plug Detect
DisplayPort -
DisplayPort3 Conn pin
18 Hot Plug Detect
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort0
receiver ML_Lane 0(p).
DisplayPort -
DisplayPort0 Conn pin 1
ML_Lane 0(p) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort0
receiver ML_Lane 0(n).
DisplayPort -
DisplayPort0 Conn pin 3
ML_Lane 0(n) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort0
receiver ML_Lane 1(p).
DisplayPort -
DisplayPort0 Conn pin 4
ML_Lane 1(p) and ESD
protection
N/C if not used.
 Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort0
receiver ML_Lane 1(n).
DisplayPort -
DisplayPort0 Conn pin 6
ML_Lane 1(n) and ESD
protection
N/C if not used.
Uni-directional main link for the transport of
isochronous streams and secondary-data packets

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort0
receiver ML_Lane 2(p).
DisplayPort -
DisplayPort0 Conn pin 7
ML_Lane 2(p) and ESD
protection
N/C if not used.

T10 Connect AC Coupling

Capacitors 75~200 nF
near COME to
Device - DisplayPort0
receiver ML_Lane 2(n).
DisplayPort -
DisplayPort0 Conn pin 9
ML_Lane 2(n) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort0
receiver ML_Lane 3(p).
DisplayPort -
DisplayPort0 Conn pin
10 ML_Lane 3(p) and
ESD protection
N/C if not used.
 Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort0
receiver ML_Lane 3(n).
DisplayPort -
DisplayPort0 Conn pin
12 ML_Lane 3(n) and
ESD protection
N/C if not used.

Module has integrated

AC Coupling Capacitor
and PD resistor to GND
Connect to
Device - DisplayPort0
receiver AUX CH(p).
DisplayPort -
DisplayPort0 Conn pin
15 AUX CH(p) and ESD
protection
N/C if not used.
Half-duplex bi-directional AUX channel for
services such as link configuration or
maintenance and EDID access
Module has integrated
AC Coupling Capacitor
and PU resistor to 3.3V
Connect to
Device - DisplayPort0
receiver AUX CH(n).
DisplayPort -
DisplayPort0 Conn pin
17 AUX CH(n) and ESD
protection
N/C if not used.

Module has integrated

current blocking circuit
and PD resistor to GND
Connect to
Detection of Hot Plug / Unplug and notification Device - DisplayPort0
of the link layer device Hot Plug Detect
DisplayPort -
DisplayPort0 Conn pin
18 Hot Plug Detect
N/C if not used.
nly or dual mode):
rrier for the DDI[n]_PAIR[0:3] signals.
n]_HPD to prevent back-drive current from damaging the Module.

d, the DP_AUX+ line shall have a pulldown resistor to GND. The resistor value should
esistor to 2.5V. The resistor value should be 100kΩ. The resistors shall be placed on
apacitors. The DP_HP signal shall include a blocking FET to prevent back-drive current
o GND with a 110kΩ resistor.
video interfaces. The circuits required to realize the different video interfaces will be
e subcommittee. At this time, thew only requirement placed on Modules for the DDI
.
DisplayPort Loss Budget

rtion Loss Budget

Notes

module trace. Coupling cap effects included within simulation.

™ connector simulated at 2.5 GHz.
Carrier Board trace.

MG Carrier Design Guide.

 Description Pin Availability DisplayPort

Connect to DisplayPort
‘True’ Signal – Main Link Lane 0 Muxed with x16 PEG
receiver ML_Lane 0(p).

High Speed Main Link Lane 0 Ground Connect to GND

Connect to DisplayPort
‘Complement’ Signal – Main Link Lane 0 Muxed with x16 PEG
receiver ML_Lane 0(n).

Connect to DisplayPort
‘True’ Signal – Main Link Lane 1 Muxed with x16 PEG
receiver ML_Lane 1(p).

High Speed Main Link Lane 1 Ground Connect to GND

Connect to DisplayPort
‘Complement’ Signal – Main Link Lane 1 Muxed with x16 PEG
receiver ML_Lane 1(n).
 Connect to DisplayPort
‘True’ Signal – Main Link Lane 2 Muxed with x16 PEG
receiver ML_Lane 2(p).

High Speed Main Link Lane 2 Ground Connect to GND

Connect to DisplayPort
‘Complement’ Signal – Main Link Lane 2 Muxed with x16 PEG
receiver ML_Lane 2(n).

Connect to DisplayPort
‘True’ Signal – Main Link Lane 3 Muxed with x16 PEG
receiver ML_Lane 3(p).

High Speed Main Link Lane 3 Ground Connect to GND

Connect to DisplayPort
‘Complement’ Signal – Main Link Lane 3 Muxed with x16 PEG
receiver ML_Lane 3(n).
CONFIG1, connected to Ground directly in DP
mode or through a pull-down device for Cable
Adaptor Detect (CAD) in DP++, DVI, and HDMI
Modes.

CONFIG2, connected to Ground directly in DP

and DVI modes or through a pull-down device for
Consumer Electronics Control (CEC) in HDMI
mode.

Connect AC Coupling
cap 0.1uF in series and
‘True’ Signal – Auxiliary channel Muxed with x16 PEG PU 1MΩ to DP_PWR to
DisplayPort receiver
AUX CH(p)

High Speed Main Link Lane AUX Ground Connect to GND

Connect AC Coupling
cap 0.1uF in series and
‘Complement’ Signal – Auxiliary channel Muxed with x16 PEG PD 1MΩ to GND to
DisplayPort0 receiver
AUX CH(n)
 Connect to DisplayPort
Hot Plug Detect Muxed with x16 PEG
device Hot Plug Detect

Power Return (Ground) Connect to GND

Connect to 3.3V power
Display Power output
of device

Description Pin Availability Mini DisplayPort

High Speed Main Link Lane 0 Ground Connect to GND

Connect to DisplayPort
Hot Plug Detect Muxed with x16 PEG
device Hot Plug Detect

Connect to DisplayPort
‘True’ Signal – Main Link Lane 0 Muxed with x16 PEG
receiver ML_Lane 0(p).

CONFIG1, connected to Ground directly in DP

mode or through a pull-down device for Cable
Adaptor Detect (CAD) in DP++, DVI, and HDMI
Modes.
 Connect to DisplayPort
‘Complement’ Signal – Main Link Lane 0 Muxed with x16 PEG
receiver ML_Lane 0(n).

CONFIG2, connected to Ground directly in DP

and DVI modes or through a pull-down device for
Consumer Electronics Control (CEC) in HDMI
mode.

High Speed Main Link Lane 1 Ground Connect to GND

High Speed Main Link Lane 3 Ground Connect to GND

Connect to DisplayPort
‘True’ Signal – Main Link Lane 1 Muxed with x16 PEG
receiver ML_Lane 1(p).

Connect to DisplayPort
‘True’ Signal – Main Link Lane 3 Muxed with x16 PEG
receiver ML_Lane 3(p).

Connect to DisplayPort
‘Complement’ Signal – Main Link Lane 1 Muxed with x16 PEG
receiver ML_Lane 1(n).

Connect to DisplayPort
‘Complement’ Signal – Main Link Lane 3 Muxed with x16 PEG
receiver ML_Lane 3(n).

High Speed Main Link Lane 2 Ground Connect to GND

High Speed Main Link Lane AUX Ground Connect to GND
 Connect to DisplayPort
‘True’ Signal – Main Link Lane 2 Muxed with x16 PEG
receiver ML_Lane 2(p).

Connect AC Coupling
cap 0.1uF in series and
‘True’ Signal – Auxiliary channel Muxed with x16 PEG PU 1MΩ to DP_PWR to
DisplayPort receiver
AUX CH(p)

Connect to DisplayPort
‘Complement’ Signal – Main Link Lane 2 Muxed with x16 PEG
receiver ML_Lane 2(n).

Connect AC Coupling
cap 0.1uF in series and
‘Complement’ Signal – Auxiliary channel Muxed with x16 PEG PD 1MΩ to GND to
DisplayPort0 receiver
AUX CH(n)

Power Return (Ground) Connect to GND

Connect to 3.3V power
Display Power output
of device

from x.xVSB in S3,S4,S5

 SOM-5894 A101-4
Baseboard

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort1
receiver ML_Lane 0(p).
DisplayPort -
DisplayPort1 Conn pin 1
ML_Lane 0(p) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort1
receiver ML_Lane 0(n).
DisplayPort -
DisplayPort1 Conn pin 3
ML_Lane 0(n) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort1
receiver ML_Lane 1(p).
DisplayPort -
DisplayPort1 Conn pin 4
ML_Lane 1(p) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort1
receiver ML_Lane 1(n).
DisplayPort -
DisplayPort1 Conn pin 6
ML_Lane 1(n) and ESD
protection
N/C if not used.
Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort1
receiver ML_Lane 2(p).
DisplayPort -
DisplayPort1 Conn pin 7
ML_Lane 2(p) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort1
receiver ML_Lane 2(n).
DisplayPort -
DisplayPort1 Conn pin 9
ML_Lane 2(n) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort1
receiver ML_Lane 3(p).
DisplayPort -
DisplayPort1 Conn pin
10 ML_Lane 3(p) and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort1
receiver ML_Lane 3(n).
DisplayPort -
DisplayPort1 Conn pin
12 ML_Lane 3(n) and
ESD protection
N/C if not used.
Module has integrated
AC Coupling Capacitor
and PD resistor to GND
Connect to
Device - DisplayPort1
receiver AUX CH(p).
DisplayPort -
DisplayPort1 Conn pin
15 AUX CH(p) and ESD
protection
N/C if not used.

Module has integrated

AC Coupling Capacitor
and PU resistor to 3.3V
Connect to
Device - DisplayPort1
receiver AUX CH(n).
DisplayPort -
DisplayPort1 Conn pin
17 AUX CH(n) and ESD
protection
N/C if not used.

Module has integrated

current blocking circuit
and PD resistor to GND
Connect to
Device - DisplayPort1
device Hot Plug Detect
DisplayPort -
DisplayPort1 Conn pin
18 Hot Plug Detect
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device -DisplayPort2
receiver ML_Lane 0(p).
DisplayPort -
DisplayPort2 Conn pin 1
ML_Lane 0(p) and ESD
protection
N/C if not used.
Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort2
receiver ML_Lane 0(n).
DisplayPort -
DisplayPort2 Conn pin 3
ML_Lane 0(n) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort2
receiver ML_Lane 1(p).
DisplayPort -
DisplayPort2 Conn pin 4
ML_Lane 1(p) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort2
receiver ML_Lane 1(n).
DisplayPort -
DisplayPort2 Conn pin 6
ML_Lane 1(n) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort2
receiver ML_Lane 2(p).
DisplayPort -
DisplayPort2 Conn pin 7
ML_Lane 2(p) and ESD
protection
N/C if not used.
Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort2
receiver ML_Lane 2(n).
DisplayPort -
DisplayPort2 Conn pin 9
ML_Lane 2(n) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort2
receiver ML_Lane 3(p).
DisplayPort -
DisplayPort2 Conn pin
10 ML_Lane 3(p) and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort2
receiver ML_Lane 3(n).
DisplayPort -
DisplayPort2 Conn pin
12 ML_Lane 3(n) and
ESD protection
N/C if not used.

Module has integrated

AC Coupling Capacitor
and PD resistor to GND
Connect to
Device - DisplayPort2
receiver AUX CH(p).
DisplayPort -
DisplayPort2 Conn pin
15 AUX CH(p) and ESD
protection
N/C if not used.
Module has integrated
AC Coupling Capacitor
and PU resistor to 3.3V
Connect to
Device - DisplayPort2
receiver AUX CH(n).
DisplayPort -
DisplayPort2 Conn pin
17 AUX CH(n) and ESD
protection
N/C if not used.

Module has integrated

current blocking circuit
and PD resistor to GND
Connect to
Device - DisplayPort2
device Hot Plug Detect
DisplayPort -
DisplayPort2 Conn pin
18 Hot Plug Detect
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort3
receiver ML_Lane 0(p).
DisplayPort -
DisplayPort3 Conn pin 1
ML_Lane 0(p) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort3
receiver ML_Lane 0(n).
DisplayPort -
DisplayPort3 Conn pin 3
ML_Lane 0(n) and ESD
protection
N/C if not used.
Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort3
receiver ML_Lane 1(p).
DisplayPort -
DisplayPort3 Conn pin 4
ML_Lane 1(p) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort3
receiver ML_Lane 1(n).
DisplayPort -
DisplayPort3 Conn pin 6
ML_Lane 1(n) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort3
receiver ML_Lane 2(p).
DisplayPort -
DisplayPort3 Conn pin 7
ML_Lane 2(p) and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort3
receiver ML_Lane 2(n).
DisplayPort -
DisplayPort3 Conn pin 9
ML_Lane 2(n) and ESD
protection
N/C if not used.
Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort3
receiver ML_Lane 3(p).
DisplayPort -
DisplayPort3 Conn pin
10 ML_Lane 3(p) and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to
Device - DisplayPort3
receiver ML_Lane 3(n).
DisplayPort -
DisplayPort3 Conn pin
12 ML_Lane 3(n) and
ESD protection
N/C if not used.

Module has integrated

AC Coupling Capacitor
and PD resistor to GND
Connect to
Device - DisplayPort3
receiver AUX CH(p).
DisplayPort -
DisplayPort3 Conn pin
15 AUX CH(p) and ESD
protection
N/C if not used.

Module has integrated

AC Coupling Capacitor
and PU resistor to 3.3V
Connect to
Device - DisplayPort3
receiver AUX CH(n).
DisplayPort -
DisplayPort3 Conn pin
17 AUX CH(n) and ESD
protection
N/C if not used.
Module has integrated
current blocking circuit
and PD resistor to GND
Connect to
Device - DisplayPort3
device Hot Plug Detect
DisplayPort -
DisplayPort3 Conn pin
18 Hot Plug Detect
N/C if not used.
N/C
 Baseboard

Module has integrated

AC Coupling Capacitor.
Connect to COME D26
DP1_LANE0+ or D39
DP2_LANE0+ or C39
DP3_LANE0+ or B71
DP0_LANE0+ with ESD
protection

Connect to GND

Module has integrated

AC Coupling Capacitor.
Connect to COME D27
DP1_LANE0- or D40
DP2_LANE0- or C40
DP3_LANE0- or B72
DP0_LANE0- with ESD
protection

Module has integrated

AC Coupling Capacitor.
Connect to COME D29
DP1_LANE1+ or D42
DP2_LANE1+ or C42
DP3_LANE1+ or B73
DP0_LANE1+ with ESD
protection

Connect to GND

Module has integrated

AC Coupling Capacitor.
Connect to COME D30
DP1_LANE1- or D43
DP2_LANE1- or C43
DP3_LANE1- or B74
DP0_LANE1- with ESD
protection
Module has integrated
AC Coupling Capacitor.
Connect to COME D32
DP1_LANE2+ or D46
DP2_LANE2+ or C46
DP3_LANE2+ or B75
DP0_LANE2+ with ESD
protection

Connect to GND

Module has integrated

AC Coupling Capacitor.
Connect to COME D33
DP1_LANE2- or D47
DP2_LANE2- or C47
DP3_LANE2- or B76
DP0_LANE2- with ESD
protection

Module has integrated

AC Coupling Capacitor.
Connect to COME D36
DP1_LANE3+ or D49
DP2_LANE3+ or C49
DP3_LANE3+ or B81
DP0_LANE3+ with ESD
protection

Connect to GND

Module has integrated

AC Coupling Capacitor.
Connect to COME D37
DP1_LANE3- or D50
DP2_LANE3- or C50
DP3_LANE3- or B82
DP0_LANE3- with ESD
protection
DP mode - Connect to
GND
DP++, DVI, and HDMI
Modes - Connect to
COME D34
DDI1_DDC_AUX_SEL
or C34
DDI2_DDC_AUX_SEL
or C38
DDI3_DDC_AUX_SEL
or B95
DDI0_DDC_AUX_SEL

DP and DVI modes -

Connect to GND
HDMI mode - through a
pull-down device for
Consumer Electronics
Control (CEC)

Module has integrated

AC Coupling Capacitor
and PD resistor to GND
Connect to COME D15
DP1_AUX+ or C32
DP2_AUX+ or C36
DP3_AUX+ or B98
DP0_AUX+ with ESD
protection

Connect to GND

Module has integrated

AC Coupling Capacitor
and PU resistor to 3.3V
Connect to COME D16
DP1_AUX- or C33
DP2_AUX- or C37
DP3_AUX- or B99
DP0_AUX- with ESD
protection
Module has integrated
current blocking circuit
and PD resistor to GND
Connect to COME C24
DP1_HPD or D44
DP2_HPD or C44
DP3_HPD or B89
DP0_HPD

Connect to GND
Connect fuse and EMI
solution to 3.3V

Baseboard
Connect to GND
PD 110KΩ to GND and
connect a current
blocking circuit to COME
C61 DPB_HPD or C74
DPC_HPD or C88
DPD_HPD

Module has integrated

AC Coupling Capacitor.
Connect to COME D52
DPB_LANE0+ or D65
DPC_LANE0+ or D78
DPD_LANE0+ with ESD
protection

DP mode - Connect to
GND
DP++, DVI, and HDMI
Modes - Connect to
COME D34
DDI1_DDC_AUX_SEL
or C34
DDI2_DDC_AUX_SEL
or C38
DDI3_DDC_AUX_SEL
or B95
DDI0_DDC_AUX_SEL
Module has integrated
AC Coupling Capacitor.
Connect to COME D53
DPB_LANE0- or D66
DPC_LANE0- or D79
DPD_LANE0- with ESD
protection

DP and DVI modes -

Connect to GND
HDMI mode - through a
pull-down device for
Consumer Electronics
Control (CEC)
Connect to GND
Connect to GND

Module has integrated

AC Coupling Capacitor.
Connect COME to D55
DPB_LANE1+ or D68
DPC_LANE1+ or D81
DPD_LANE1+ with ESD
protection

Module has integrated

AC Coupling Capacitor.
Connect to COME D61
DPB_LANE3+ or D74
DPC_LANE3+ or D88
DPD_LANE3+ with ESD
protection

Module has integrated

AC Coupling Capacitor.
Connect to COME D56
DPB_LANE1- or D69
DPC_LANE1- or D82
DPD_LANE1- with ESD
protection

Module has integrated

AC Coupling Capacitor.
Connect to COME D62
DPB_LANE3- or D75
DPC_LANE3- or D89
DPD_LANE3- with ESD
protection

Connect to GND
Connect to GND
Module has integrated
AC Coupling Capacitor.
Connect to COME D58
DPB_LANE2+ or D71
DPC_LANE2+ or D85
DPD_LANE2+ with ESD
protection

Connect ESD protection,

PD 100KΩ to GND and
AC Coupling cap 0.1uF
in series to COME C58
DPB_AUX+ or C71
DPC_AUX+ or C85
DPD_AUX+

Module has integrated

AC Coupling Capacitor.
Connect to COME D59
DPB_LANE2- or D72
DPC_LANE2- or D86
DPD_LANE2- with ESD
protection

Connect ESD protection,

PU 100KΩ to 2.5V~3.3V
and AC Coupling cap
0.1uF in series to COME
C59 DPB_AUX- or C72
DPC_AUX- or C86
DPD_AUX-

Connect to GND
Connect fuse and EMI
solution to 3.3V
 Pwr Rail /
Pin No. DDI-TMDS Pin Type
Tolerance

D26 TMDS1_DATA2+

O AC coupled off
PCIE Module

D27 TMDS1_DATA2-

D29 TMDS1_DATA1+

O AC coupled off
PCIE Module
 O AC coupled off
PCIE Module

D30 TMDS1_DATA1-

D32 TMDS1_DATA0+

O AC coupled off
PCIE Module

D33 TMDS1_DATA0-
D36 TMDS1_CLK+

O AC coupled off
PCIE Module

D37 TMDS1_CLK-

3.3V / 3.3V
C24 HDMI1_HPD I

I/O OD 3.3V / 3.3V

D15 HMDI1_CTRLCLK
CMOS
 I/O OD 3.3V / 3.3V
D16 HMDI1_CTRLDATA
CMOS

D39 TMDS2_DATA2+

O AC coupled
PCIE off Module

D40 TMDS2_DATA2-
D42 TMDS2_DATA1+

O AC coupled off
PCIE Module

D43 TMDS2_DATA1-

D46 TMDS2_DATA0+

O AC coupled off
PCIE Module
 O AC coupled off
PCIE Module

D47 TMDS2_DATA0-

D49 TMDS2_CLK+

O AC coupled off
PCIE Module

D50 TMDS2_CLK-

3.3V / 3.3V
D44 HDMI2_HPD I
 I/O OD 3.3V / 3.3V
C32 HDMI2_CTRLCLK
CMOS

I/O OD 3.3V / 3.3V

C33 HDMI2_CTRLDATA
CMOS

C39 TMDS3_DATA2+

O AC coupled off
PCIE Module
 O AC coupled off
PCIE Module

C40 TMDS3_DATA2-

C42 TMDS3_DATA1+

O AC coupled off
PCIE Module

C43 TMDS3_DATA1-
C46 TMDS3_DATA0+

O AC coupled off
PCIE Module

C47 TMDS3_DATA0-

C49 TMDS3_CLK+

O AC coupled off
PCIE Module
 O AC coupled off
PCIE Module

C50 TMDS3_CLK-

3.3V / 3.3V
C44 HDMI3_HPD I

I/O OD 3.3V / 3.3V

C36 HDMI3_CTRLCLK
CMOS
 I/O OD 3.3V / 3.3V
C37 HDMI3_CTRLDATA
CMOS

B71 TMDS0_DATA2+

O AC coupled off
PCIE Module

B72 TMDS0_DATA2-
B73 TMDS0_DATA1+

O AC coupled off
PCIE Module

B74 TMDS0_DATA1-

B75 TMDS0_DATA0+

O AC coupled off
PCIE Module
 O AC coupled off
PCIE Module

B76 TMDS0_DATA0-

B81 TMDS0_CLK+

O AC coupled off
PCIE Module

B82 TMDS0_CLK-

3.3V / 3.3V
B89 HDMI0_HPD I
 I/O OD 3.3V / 3.3V
B98 HMDI0_CTRLCLK
CMOS

I/O OD 3.3V / 3.3V

B99 HMDI0_CTRLDATA
CMOS

4.3.18 DDI Signals: HDMI / DVI

Carriers that support TMDS (DVI/HDMI):
• DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm resistor to configure the DDI[n]_AUX pa
channel.
• Bi-directional level translators shall be placed on the Carrier DDI[n]_CTRLDATA_AUX- and DDI[n]_CTRLCLK_AUX+ to
DDC channel on the Module to the 5V DDC channel for the TMDS display.
• Pull-up resistors shall be placed on the Carrier from 3.3V (Module side of level translator) and 5V (display side of level tr
[n]_CTRLDATA_AUX- and DDI[n]_CTRLCLK_AUX+ signals. The pull-up resistor should be 2k.
• Level translators Shall be placed on the Carrier DDI[n]_PAIR[0:3] signals.
• DC blocking capacitors shall be placed on the Carrier for the DDI[n]_PAIR[0:3] signals. Some Modules may require DC
capacitors on DDI[n]_PAIR[0:3]. If DC blocking capacitors are required by the DDI generating silicon, the DC blocking capa
placed on the Carrier.
• The Carrier shall include a blocking FET on DDI[n]_HPD to prevent back-drive current from damaging the mModule.

When implementing HDMI level shifters shall be used on the TMDS signals. Bi-directional level shifters shall be used betw
5V CTRLCLK and CTRLDATA signals with 2.2kΩ pull-ups to 3.3V and 5V.
The DDI signals can be used to support a variety of video interfaces. The circuits required to realize the different video inte
determined by a future PICMG Carrier Design Guide subcommittee. At this time, thew only requirement placed on Modules
signals is the maximum trace length specified below.
TMDS Loss Budget
 TMDS Insertion Loss Budget
max. Length
Segment Notes
[mm/inches]
LA 127/5.0 Allowance for module trace. Coupling cap effects included within simulation.
LB COM Express™ connector simulated at 2.5 GHz.
LC TBD Allowance for Carrier Board trace.
Total TBD
The TBD values will be determined by a future PICMG Carrier Design Guide.

Pwr Rail /
Pin No. DVI-I Pin Type
Tolerance

AC Coupled
T2-T5 on the
I
1 TMDS Data 2- Module
TMDS
T6/10 off the
Module
 AC Coupled
T2-T5 on the
I
2 TMDS Data 2+ Module
TMDS
T6/10 off the
Module

3 TMDS Data 2/4 shield Power

AC Coupled
T2-5 on the
I
4 TMDS Data 4- Module
TMDS
T6/10 off the
Module
AC Coupled
T2-5 on the
I
5 TMDS Data 4+ Module
TMDS
T6/10 off the
Module

I
6 DDC clock 5V / 5V
CMOS
 I/O OD
7 DDC data 5V / 5V
CMOS

I
8 Analog vertical sync 3.3V / 3.3V
CMOS

AC Coupled
T2-5 on the
I
9 TMDS Data 1- Module
TMDS
T6/10 off the
Module

AC Coupled
T2-5 on the
I
10 TMDS Data 1+ Module
TMDS
T6/10 off the
Module
11 TMDS Data 1/3 shield Power

AC Coupled
T2-5 on the
I
12 TMDS Data 3- Module
TMDS
T6/10 off the
Module
AC Coupled
T2-5 on the
I
13 TMDS Data 3+ Module
TMDS
T6/10 off the
Module

14 +5V Power

15 DDC/CEC Ground Power

O
16 Hot plug detect 5V / 5V
CMOS

AC Coupled
T2-5 on the
I
17 TMDS data 0- Module
TMDS
T6/10 off the
Module
 AC Coupled
T2-5 on the
I
18 TMDS data 0+ Module
TMDS
T6/10 off the
Module

19 TMDS data 0/5 shield Power

AC Coupled
T2-5 on the
I
20 TMDS data 5- Module
TMDS
T6/10 off the
Module
AC Coupled
T2-5 on the
I
21 TMDS data 5+ Module
TMDS
T6/10 off the
Module
22 TMDS clock shield Power

AC Coupled
T2-5 on the
I
23 TMDS clock+ Module
TMDS
T6/10 off the
Module

AC Coupled
T2-5 on the
I
24 TMDS clock- Module
TMDS
T6/10 off the
Module
 I
C1 Analog red 0.7 V p-p
Analog

I
C2 Analog green 0.7 V p-p
Analog

I
C3 Analog blue 0.7 V p-p
Analog

I
C4 Analog horizontal sync 3.3V / 3.3V
CMOS

C5 Analog ground Power

 Pwr Rail /
Pin No. HDMI Type A Pin Type
Tolerance

AC Coupled
T2-T5 on the
I
1 TMDS Data 2+ Module
TMDS
T6/10 off the
Module

2 TMDS Data 2 Shield Power

AC Coupled
T2-T5 on the
I
3 TMDS Data 2– Module
TMDS
T6/10 off the
Module

AC Coupled
T2-5 on the
I
4 TMDS Data 1+ Module
TMDS
T6/10 off the
Module

5 TMDS Data 1 Shield Power

 AC Coupled
T2-5 on the
I
6 TMDS Data 1– Module
TMDS
T6/10 off the
Module

AC Coupled
T2-5 on the
I
7 TMDS Data 0+ Module
TMDS
T6/10 off the
Module

8 TMDS Data 0 Shield Power

AC Coupled
T2-5 on the
I
9 TMDS Data 0– Module
TMDS
T6/10 off the
Module

AC Coupled
T2-5 on the
I
10 TMDS Clock+ Module
TMDS
T6/10 off the
Module

11 TMDS Clock Shield Power

 AC Coupled
T2-5 on the
I
12 TMDS Clock– Module
TMDS
T6/10 off the
Module

I/O
13 CEC 3.3V / 3.3V
CMOS

Reserved (N.C. on
14 device)

I
15 SCL 5V / 5V
CMOS
 I/O OD
16 SDA 5V / 5V
CMOS

17 DDC/CEC Ground Power

+5 V Power (max 50
18 mA)
Power

O
19 Hot Plug Detect 5V / 5V
CMOS

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 Description Pin Availability Baseboard

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA2+.
DVI - DVI Conn pin 2
TMDS_DATA2+ and
ESD protection
HDMI - HDMI Conn pin
1 TMDS Data2+ and
ESD protection
N/C if not used.

HDMI/DVI TMDS lanes 2 differential pairs

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA2-
DVI - DVI Conn pin 1
TMDS_DATA2- and
ESD protection
HDMI - HDMI Conn pin
3 TMDS Data2- and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA1+
DVI - DVI Conn pin 10
TMDS_DATA1+ and
ESD protection
HDMI - HDMI Conn pin
4 TMDS Data1+ and
ESD protection
N/C if not used.

HDMI/DVI TMDS lanes 1 differential pairs

HDMI/DVI TMDS lanes 1 differential pairs

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA1-
DVI - DVI Conn pin 9
TMDS_DATA1- and
ESD protection
HDMI - HDMI Conn pin
6 TMDS Data1- and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA0+
DVI - DVI Conn pin 18
TMDS_DATA0+ and
ESD protection
HDMI - HDMI Conn pin
7 TMDS Data0+ and
ESD protection
N/C if not used.

HDMI/DVI TMDS lanes 0 differential pairs

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA0-
DVI - DVI Conn pin 17
TMDS_DATA0- and
ESD protection
HDMI - HDMI Conn pin
9 TMDS Data0- and
ESD protection
N/C if not used.
 Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_CLK+
DVI - DVI Conn pin 23
TMDS_CLK+ and ESD
protection
HDMI - HDMI Conn pin
10 TMDS Clock+ and
ESD protection
N/C if not used.
HDMI/DVI TMDS Clock differential pair
Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_CLK-
DVI - DVI Conn pin 24
TMDS_CLK- and ESD
protection
HDMI - HDMI Conn pin
12 TMDS Clock- and
ESD protection
N/C if not used.

Module has integrated

current blocking circuit
and PD resistor to GND
Connect to
Device - TMDS device
HDMI/DVI Hot-Plug Detect TMDS_HPD
DVI - DVI Conn pin 16
Hot Plug Detect
HDMI - HDMI Conn pin
19 Hot Plug Detect
N/C if not used.

PU 2.2KΩ to 3.3V and

connect 3.3V to 5V
Level Shifter with PU
2.2K to 5V to
Device - TMDS receiver
TMDS_DDC_CLK
HDMI/DVI I2C control clock
DVI - DVI Conn pin 6
DDC Clock
HDMI - HDMI Conn pin
15 SCL
PCH recommendation
if not used.
 PU 2.2KΩ to 3.3V and
connect 3.3V to 5V
Level Shifter with PU
2.2K to 5V to
Device - TMDS receiver
TMDS_DDC_DAT
HDMI/DVI I2C control data
DVI - DVI Conn pin 7
DDC Data
HDMI - HDMI Conn pin
16 SDA
PCH recommendation
if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA2+.
DVI - DVI Conn pin 2
TMDS_DATA2+ and
ESD protection
HDMI - HDMI Conn pin
1 TMDS Data2+ and
ESD protection
N/C if not used.

HDMI/DVI TMDS lanes 2 differential pairs

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA2-
DVI - DVI Conn pin 1
TMDS_DATA2- and
ESD protection
HDMI - HDMI Conn pin
3 TMDS Data2- and
ESD protection
N/C if not used.
 Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA1+
DVI - DVI Conn pin 10
TMDS_DATA1+ and
ESD protection
HDMI - HDMI Conn pin
4 TMDS Data1+ and
ESD protection
N/C if not used.

HDMI/DVI TMDS lanes 1 differential pairs

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA1-
DVI - DVI Conn pin 9
TMDS_DATA1- and
ESD protection
HDMI - HDMI Conn pin
6 TMDS Data1- and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA0+
DVI - DVI Conn pin 18
TMDS_DATA0+ and
ESD protection
HDMI - HDMI Conn pin
7 TMDS Data0+ and
ESD protection
N/C if not used.

HDMI/DVI TMDS lanes 0 differential pairs

T6
HDMI/DVI TMDS lanes 0 differential pairs

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
T6 TMDS_DATA0-
DVI - DVI Conn pin 17
TMDS_DATA0- and
ESD protection
HDMI - HDMI Conn pin
9 TMDS Data0- and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_CLK+
DVI - DVI Conn pin 23
TMDS_CLK+ and ESD
protection
HDMI - HDMI Conn pin
10 TMDS Clock+ and
ESD protection
N/C if not used.
HDMI/DVI TMDS Clock differential pair
Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_CLK-
DVI - DVI Conn pin 24
TMDS_CLK- and ESD
protection
HDMI - HDMI Conn pin
12 TMDS Clock- and
ESD protection
N/C if not used.

Module has integrated

current blocking circuit
and PD resistor to GND
Connect to
Device - TMDS device
HDMI/DVI Hot-Plug Detect TMDS_HPD
DVI - DVI Conn pin 16
Hot Plug Detect
HDMI - HDMI Conn pin
19 Hot Plug Detect
N/C if not used.
 PU 2.2KΩ to 3.3V and
connect 3.3V to 5V
Level Shifter with PU
2.2K to 5V to
Device - TMDS receiver
TMDS_DDC_CLK
HDMI/DVI I2C control clock
DVI - DVI Conn pin 6
DDC Clock
HDMI - HDMI Conn pin
15 SCL
PCH recommendation
if not used.

PU 2.2KΩ to 3.3V and

connect 3.3V to 5V
Level Shifter with PU
2.2K to 5V to
Device - TMDS receiver
TMDS_DDC_DAT
HDMI/DVI I2C control data
DVI - DVI Conn pin 7
DDC Data
HDMI - HDMI Conn pin
16 SDA
PCH recommendation
if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA2+.
DVI - DVI Conn pin 2
TMDS_DATA2+ and
ESD protection
HDMI - HDMI Conn pin
1 TMDS Data2+ and
ESD protection
N/C if not used.

HDMI/DVI TMDS lanes 2 differential pairs

HDMI/DVI TMDS lanes 2 differential pairs

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA2-
DVI - DVI Conn pin 1
TMDS_DATA2- and
ESD protection
HDMI - HDMI Conn pin
3 TMDS Data2- and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA1+
DVI - DVI Conn pin 10
TMDS_DATA1+ and
ESD protection
HDMI - HDMI Conn pin
4 TMDS Data1+ and
ESD protection
N/C if not used.

HDMI/DVI TMDS lanes 1 differential pairs

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA1-
DVI - DVI Conn pin 9
TMDS_DATA1- and
ESD protection
HDMI - HDMI Conn pin
6 TMDS Data1- and
ESD protection
N/C if not used.
 Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA0+
DVI - DVI Conn pin 18
TMDS_DATA0+ and
ESD protection
HDMI - HDMI Conn pin
7 TMDS Data0+ and
ESD protection
N/C if not used.

HDMI/DVI TMDS lanes 0 differential pairs

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA0-
DVI - DVI Conn pin 17
TMDS_DATA0- and
ESD protection
HDMI - HDMI Conn pin
9 TMDS Data0- and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_CLK+
DVI - DVI Conn pin 23
TMDS_CLK+ and ESD
protection
HDMI - HDMI Conn pin
10 TMDS Clock+ and
ESD protection
N/C if not used.
HDMI/DVI TMDS Clock differential pair
HDMI/DVI TMDS Clock differential pair
Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_CLK-
DVI - DVI Conn pin 24
TMDS_CLK- and ESD
protection
HDMI - HDMI Conn pin
12 TMDS Clock- and
ESD protection
N/C if not used.

Module has integrated

current blocking circuit
and PD resistor to GND
Connect to
Device - TMDS device
HDMI/DVI Hot-Plug Detect TMDS_HPD
DVI - DVI Conn pin 16
Hot Plug Detect
HDMI - HDMI Conn pin
19 Hot Plug Detect
N/C if not used.

PU 2.2KΩ to 3.3V and

connect 3.3V to 5V
Level Shifter with PU
2.2K to 5V to
Device - TMDS receiver
TMDS_DDC_CLK
HDMI/DVI I2C control clock
DVI - DVI Conn pin 6
DDC Clock
HDMI - HDMI Conn pin
15 SCL
PCH recommendation
if not used.
 PU 2.2KΩ to 3.3V and
connect 3.3V to 5V
Level Shifter with PU
2.2K to 5V to
Device - TMDS receiver
TMDS_DDC_DAT
HDMI/DVI I2C control data
DVI - DVI Conn pin 7
DDC Data
HDMI - HDMI Conn pin
16 SDA
PCH recommendation
if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA2+.
DVI - DVI Conn pin 2
TMDS_DATA2+ and
ESD protection
HDMI - HDMI Conn pin
1 TMDS Data2+ and
ESD protection
N/C if not used.

HDMI/DVI TMDS lanes 2 differential pairs

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA2-
DVI - DVI Conn pin 1
TMDS_DATA2- and
ESD protection
HDMI - HDMI Conn pin
3 TMDS Data2- and
ESD protection
N/C if not used.
 Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA1+
DVI - DVI Conn pin 10
TMDS_DATA1+ and
ESD protection
HDMI - HDMI Conn pin
4 TMDS Data1+ and
ESD protection
N/C if not used.

HDMI/DVI TMDS lanes 1 differential pairs

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA1-
DVI - DVI Conn pin 9
TMDS_DATA1- and
ESD protection
HDMI - HDMI Conn pin
6 TMDS Data1- and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA0+
DVI - DVI Conn pin 18
TMDS_DATA0+ and
ESD protection
HDMI - HDMI Conn pin
7 TMDS Data0+ and
ESD protection
N/C if not used.

HDMI/DVI TMDS lanes 0 differential pairs

T10
HDMI/DVI TMDS lanes 0 differential pairs

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
T10 Device - TMDS receiver
TMDS_DATA0-
DVI - DVI Conn pin 17
TMDS_DATA0- and
ESD protection
HDMI - HDMI Conn pin
9 TMDS Data0- and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_CLK+
DVI - DVI Conn pin 23
TMDS_CLK+ and ESD
protection
HDMI - HDMI Conn pin
10 TMDS Clock+ and
ESD protection
N/C if not used.
HDMI/DVI TMDS Clock differential pair
Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_CLK-
DVI - DVI Conn pin 24
TMDS_CLK- and ESD
protection
HDMI - HDMI Conn pin
12 TMDS Clock- and
ESD protection
N/C if not used.

Module has integrated

current blocking circuit
and PD resistor to GND
Connect to
Device - TMDS device
HDMI/DVI Hot-Plug Detect TMDS_HPD
DVI - DVI Conn pin 16
Hot Plug Detect
HDMI - HDMI Conn pin
19 Hot Plug Detect
N/C if not used.
 PU 2.2KΩ to 3.3V and
connect 3.3V to 5V
Level Shifter with PU
2.2K to 5V to
Device - TMDS receiver
TMDS_DDC_CLK
HDMI/DVI I2C control clock
DVI - DVI Conn pin 6
DDC Clock
HDMI - HDMI Conn pin
15 SCL
PCH recommendation
if not used.

PU 2.2KΩ to 3.3V and

connect 3.3V to 5V
Level Shifter with PU
2.2KΩ to 5V to
Device - TMDS receiver
TMDS_DDC_DAT
HDMI/DVI I2C control data
DVI - DVI Conn pin 7
DDC Data
HDMI - HDMI Conn pin
16 SDA
PCH recommendation
if not used.

n the Carrier with a 100K Ohm resistor to configure the DDI[n]_AUX pair as the DDC

he Carrier DDI[n]_CTRLDATA_AUX- and DDI[n]_CTRLCLK_AUX+ to convert the 3.3V

for the TMDS display.
m 3.3V (Module side of level translator) and 5V (display side of level translator) and the
+ signals. The pull-up resistor should be 2k.
DI[n]_PAIR[0:3] signals.
rrier for the DDI[n]_PAIR[0:3] signals. Some Modules may require DC blocking
acitors are required by the DDI generating silicon, the DC blocking capacitors shall be

n]_HPD to prevent back-drive current from damaging the mModule.

ed on the TMDS signals. Bi-directional level shifters shall be used between the 3.3V and
ull-ups to 3.3V and 5V.
video interfaces. The circuits required to realize the different video interfaces will be
e subcommittee. At this time, thew only requirement placed on Modules for the DDI
.
TMDS Loss Budget
Loss Budget
Notes

module trace. Coupling cap effects included within simulation.

™ connector simulated at 2.5 GHz.
Carrier Board trace.

MG Carrier Design Guide.

Description Pin Availability DVI-I

T2-T5 - Muxed with x16

TMDS link 0 channel 2 differential pair PEG
T6/T10 - From DDI
 T2-T5 - Muxed with x16
TMDS link 0 channel 2 differential pair PEG
T6/T10 - From DDI

Shared shield for TMDS link 0 channel 2 and link

Connect to GND
1 channel 1

TMDS link 1 channel 1 differential pair

TMDS link 1 channel 1 differential pair

The clock line for the DDC interface

The data line for the DDC interface

Vertical synchronization signal for the analog

interface.

T2-T5 - Muxed with x16

TMDS link 0 channel 1 differential pair PEG
T6/T10 - From DDI

T2-T5 - Muxed with x16

TMDS link 0 channel 1 differential pair PEG
T6/T10 - From DDI
Shared shield for TMDS link 0 channel 1 and link
Connect to GND
1 channel 0

TMDS link 1 channel 0 differential pair

TMDS link 1 channel 0 differential pair

+5 volt signal provided by the system to enable

Connect to DDC power
the monitor to provide EDID data when the
input
monitor circuitry is not powered.
Ground reference for +5 volt power pin. Connect to GND

Signal is driven by monitor to enable the system

to identify the presence of a monitor.

T2-T5 - Muxed with x16

TMDS link 0 channel 0 differential pair PEG
T6/T10 - From DDI
 T2-T5 - Muxed with x16
TMDS link 0 channel 0 differential pair PEG
T6/T10 - From DDI

Shared shield for TMDS link 0 channel 0 and link

Connect to GND
1 channel 2

TMDS link 1 channel 2 differential pair

TMDS link 1 channel 2 differential pair

Shield for TMDS clock differential pair Connect to GND

T2-T5 - Muxed with x16

TMDS clock differential pair PEG
T6/T10 - From DDI

T2-T5 - Muxed with x16

TMDS clock differential pair PEG
T6/T10 - From DDI
Analog Red signal.

Analog Green signal.

Analog Blue signal.

Horizontal synchronization signal for the analog

interface.

Return for R, G and B signals Connect to GND

 Description Pin Availability HDMI Type A

T2-T5 - Muxed with x16

TMDS channel 2 differential pair PEG
T6/T10 - From DDI

Shield for TMDS channel 2 Connect to GND

T2-T5 - Muxed with x16

TMDS channel 2 differential pair PEG
T6/T10 - From DDI

T2-T5 - Muxed with x16

TMDS channel 1 differential pair PEG
T6/T10 - From DDI

Shield for TMDS channel 1 Connect to GND

 T2-T5 - Muxed with x16
TMDS channel 1 differential pair PEG
T6/T10 - From DDI

T2-T5 - Muxed with x16

TMDS channel 0 differential pair PEG
T6/T10 - From DDI

Shield for TMDS channel 0 Connect to GND

T2-T5 - Muxed with x16

TMDS channel 0 differential pair PEG
T6/T10 - From DDI

T2-T5 - Muxed with x16

TMDS clock differential pair PEG
T6/T10 - From DDI

Shield for TMDS clock differential pair Connect to GND

 T2-T5 - Muxed with x16
TMDS clock differential pair PEG
T6/T10 - From DDI

PU to 3.3V and connect

Consumer Electronics Control
to isolating diode

Not Connected N.C

The clock line for the DDC interface

 The data line for the DDC interface

Ground reference for DDC/CEC pin. Connect to GND

+5 volt signal provided by the system to enable
Connect to DDC power
the monitor to provide EDID data when the
input
monitor circuitry is not powered.

Signal is driven by monitor to enable the system

to identify the presence of a monitor.

from x.xVSB in S3,S4,S5

 SOM-5894 A101-4
Baseboard

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA2+.
DVI - DVI Conn pin 2
TMDS_DATA2+ and
ESD protection
HDMI - HDMI Conn pin
1 TMDS Data2+ and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA2-
DVI - DVI Conn pin 1
TMDS_DATA2- and
ESD protection
HDMI - HDMI Conn pin
3 TMDS Data2- and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA1+
DVI - DVI Conn pin 10
TMDS_DATA1+ and
ESD protection
HDMI - HDMI Conn pin
4 TMDS Data1+ and
ESD protection
N/C if not used.
Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA1-
DVI - DVI Conn pin 9
TMDS_DATA1- and
ESD protection
HDMI - HDMI Conn pin
6 TMDS Data1- and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA0+
DVI - DVI Conn pin 18
TMDS_DATA0+ and
ESD protection
HDMI - HDMI Conn pin
7 TMDS Data0+ and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA0-
DVI - DVI Conn pin 17
TMDS_DATA0- and
ESD protection
HDMI - HDMI Conn pin
9 TMDS Data0- and
ESD protection
N/C if not used.
Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_CLK+
DVI - DVI Conn pin 23
TMDS_CLK+ and ESD
protection
HDMI - HDMI Conn pin
10 TMDS Clock+ and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_CLK-
DVI - DVI Conn pin 24
TMDS_CLK- and ESD
protection
HDMI - HDMI Conn pin
12 TMDS Clock- and
ESD protection
N/C if not used.

Module has integrated

current blocking circuit
and PD resistor to GND
Connect to
Device - TMDS device
TMDS_HPD
DVI - DVI Conn pin 16
Hot Plug Detect
HDMI - HDMI Conn pin
19 Hot Plug Detect
N/C if not used.

PU 2.2KΩ to 3.3V and

connect 3.3V to 5V
Level Shifter with PU
2.2K to 5V to
Device - TMDS receiver
TMDS_DDC_CLK
DVI - DVI Conn pin 6
DDC Clock
HDMI - HDMI Conn pin
15 SCL
N/C if not used.
PU 2.2KΩ to 3.3V and
connect 3.3V to 5V
Level Shifter with PU
2.2K to 5V to
Device - TMDS receiver
TMDS_DDC_DAT
DVI - DVI Conn pin 7
DDC Data
HDMI - HDMI Conn pin
16 SDA
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA2+.
DVI - DVI Conn pin 2
TMDS_DATA2+ and
ESD protection
HDMI - HDMI Conn pin
1 TMDS Data2+ and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA2-
DVI - DVI Conn pin 1
TMDS_DATA2- and
ESD protection
HDMI - HDMI Conn pin
3 TMDS Data2- and
ESD protection
N/C if not used.
Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA1+
DVI - DVI Conn pin 10
TMDS_DATA1+ and
ESD protection
HDMI - HDMI Conn pin
4 TMDS Data1+ and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA1-
DVI - DVI Conn pin 9
TMDS_DATA1- and
ESD protection
HDMI - HDMI Conn pin
6 TMDS Data1- and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA0+
DVI - DVI Conn pin 18
TMDS_DATA0+ and
ESD protection
HDMI - HDMI Conn pin
7 TMDS Data0+ and
ESD protection
N/C if not used.
Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA0-
DVI - DVI Conn pin 17
TMDS_DATA0- and
ESD protection
HDMI - HDMI Conn pin
9 TMDS Data0- and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_CLK+
DVI - DVI Conn pin 23
TMDS_CLK+ and ESD
protection
HDMI - HDMI Conn pin
10 TMDS Clock+ and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_CLK-
DVI - DVI Conn pin 24
TMDS_CLK- and ESD
protection
HDMI - HDMI Conn pin
12 TMDS Clock- and
ESD protection
N/C if not used.

Module has integrated

current blocking circuit
and PD resistor to GND
Connect to
Device - TMDS device
TMDS_HPD
DVI - DVI Conn pin 16
Hot Plug Detect
HDMI - HDMI Conn pin
19 Hot Plug Detect
N/C if not used.
PU 2.2KΩ to 3.3V and
connect 3.3V to 5V
Level Shifter with PU
2.2K to 5V to
Device - TMDS receiver
TMDS_DDC_CLK
DVI - DVI Conn pin 6
DDC Clock
HDMI - HDMI Conn pin
15 SCL
N/C if not used.

PU 2.2KΩ to 3.3V and

connect 3.3V to 5V
Level Shifter with PU
2.2K to 5V to
Device - TMDS receiver
TMDS_DDC_DAT
DVI - DVI Conn pin 7
DDC Data
HDMI - HDMI Conn pin
16 SDA
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA2+.
DVI - DVI Conn pin 2
TMDS_DATA2+ and
ESD protection
HDMI - HDMI Conn pin
1 TMDS Data2+ and
ESD protection
N/C if not used.
Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA2-
DVI - DVI Conn pin 1
TMDS_DATA2- and
ESD protection
HDMI - HDMI Conn pin
3 TMDS Data2- and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA1+
DVI - DVI Conn pin 10
TMDS_DATA1+ and
ESD protection
HDMI - HDMI Conn pin
4 TMDS Data1+ and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA1-
DVI - DVI Conn pin 9
TMDS_DATA1- and
ESD protection
HDMI - HDMI Conn pin
6 TMDS Data1- and
ESD protection
N/C if not used.
Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA0+
DVI - DVI Conn pin 18
TMDS_DATA0+ and
ESD protection
HDMI - HDMI Conn pin
7 TMDS Data0+ and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_DATA0-
DVI - DVI Conn pin 17
TMDS_DATA0- and
ESD protection
HDMI - HDMI Conn pin
9 TMDS Data0- and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_CLK+
DVI - DVI Conn pin 23
TMDS_CLK+ and ESD
protection
HDMI - HDMI Conn pin
10 TMDS Clock+ and
ESD protection
N/C if not used.
Connect AC Coupling
Capacitors 75~200 nF
near COME and Level
Shifter to
Device - TMDS receiver
TMDS_CLK-
DVI - DVI Conn pin 24
TMDS_CLK- and ESD
protection
HDMI - HDMI Conn pin
12 TMDS Clock- and
ESD protection
N/C if not used.

Module has integrated

current blocking circuit
and PD resistor to GND
Connect to
Device - TMDS device
TMDS_HPD
DVI - DVI Conn pin 16
Hot Plug Detect
HDMI - HDMI Conn pin
19 Hot Plug Detect
N/C if not used.

PU 2.2KΩ to 3.3V and

connect 3.3V to 5V
Level Shifter with PU
2.2K to 5V to
Device - TMDS receiver
TMDS_DDC_CLK
DVI - DVI Conn pin 6
DDC Clock
HDMI - HDMI Conn pin
15 SCL
N/C if not used.
PU 2.2KΩ to 3.3V and
connect 3.3V to 5V
Level Shifter with PU
2.2K to 5V to
Device - TMDS receiver
TMDS_DDC_DAT
DVI - DVI Conn pin 7
DDC Data
HDMI - HDMI Conn pin
16 SDA
N/C if not used.
N/C
N/C
 Baseboard

T2-5 - Connect to D53

TMDS_DATA2- or D66
TMDS_DATA5- and
ESD protection
T6 - Connect to D27
TMDS1_DATA2- or D40
TMDS2_DATA2- or C40
TMDS3_DATA2- and
ESD protection
T10 - Connect to B72
TMDS0_DATA2- and
ESD protection
T2-5 - Connect to D52
TMDS_DATA2+ or D65
TMDS_DATA5+ and
ESD protection
T6 - Connect to D26
TMDS1_DATA2+ or D39
TMDS2_DATA2+ or C39
TMDS3_DATA2+ and
ESD protection
T10 - Connect to B71
TMDS0_DATA2+ and
ESD protection

Connect to GND

N/C

N/C

ESD protection, PU 4.7K

to 5V and connect 5V to
3.3V Level Shifter to
T2-5 - D73
TMDSA_DDC_CLK or
D83 HDMIB_CTRLCLK
for DVI-D or B95
VGA_I2C_CK for DVI-I
T6 - D15
HMDI1_CTRLCLK or
C32
HDMI2_CTRLCLK(DVI-
D Only) or C36
HDMI3_CTRLCLK(DVI-
D Only)
T10 - Connect to B98
HMDI0_CTRLCLK
ESD protection, PU 4.7K
to 5V and connect 5V to
3.3V Level Shifter to
T2-5 - C73
TMDSA_DDC_DAT or
C83 TMDSB_DDC_DAT
for DVI-D or B96
VGA_I2C_DAT for DVI-I
T6 - D16
HMDI1_CTRLDATA or
C33
HDMI2_CTRLDATA(DVI
-D Only) or C37
HDMI3_CTRLDATA(DVI
-D Only)
T10 - Connect to B99
HMDI0_CTRLDATA

Connect
1. Bypass
33p~50pF(NL) to GND.
2. 27~39Ω in series
to COME Pin B94
VGA_VSYNC

T2-5 - Connect to D56

TMDS_DATA1- or D69
TMDS_DATA4- and
ESD protection
T6 - Connect to D30
TMDS1_DATA1- or D43
TMDS2_DATA1- or C43
TMDS3_DATA1- and
ESD protection
T10 - Connect to B74
TMDS0_DATA1- and
ESD protection

T2-5 - Connect to D55

TMDS_DATA1+ or D68
TMDS_DATA4+ and
ESD protection
T6 - Connect to D29
TMDS1_DATA1+ or D42
TMDS2_DATA1+ or C42
TMDS3_DATA1+ and
ESD protection
T10 - Connect to B73
TMDS0_DATA1+ and
ESD protection
Connect to GND

N/C

N/C

Connect fuse and EMI

solution to 5V
Connect to GND

T2-5 - Connect to C61

HDMIA_HPD or C74
HDMIB_HPD and ESD
protection
T6 - Connect to C24
HDMI1_HPD or D44
HDMI2_HPD or C44
HDMI3_HPD and ESD
protection
T10 - Connect to B89
HDMI0_HPD and ESD
protection

T2-5 - Connect D59

TMDS_DATA0- or D72
TMDS_DATA3- and
ESD protection
T6 - Connect to D33
TMDS1_DATA0- or D47
TMDS2_DATA0- or C47
TMDS3_DATA0- and
ESD protection
T10 - Connect to B76
TMDS0_DATA0- and
ESD protection
T2-5 - Connect to D58
TMDS_DATA0+ or D71
TMDS_DATA3+ and
ESD protection
T6 - Connect to D32
TMDS1_DATA0+ or D46
TMDS2_DATA0+ or C46
TMDS3_DATA0+ and
ESD protection
T10 - Connect to B75
TMDS0_DATA0+ and
ESD protection

Connect to GND

N/C

N/C

Connect to GND

T2-5 - Connect to D61

TMDS_CLK+ or D74
TMDSB_CLK+ and ESD
protection
T6 - Connect to D36
TMDS1_CLK+ or D49
TMDS2_CLK+ or C49
TMDS3_CLK+ and ESD
protection
T10 - Connect to B81
TMDS0_CLK+ and ESD
protection

T2-5 Connect to D62

TMDS_CLK- or D75
TMDSB_CLK- and ESD
protection
T6 - Connect to D37
TMDS1_CLK- or D50
TMDS2_CLK- or C50
TMDS3_CLK- and ESD
protection
T10 - Connect to B82
TMDS0_CLK- and ESD
protection
Connect to
1. VGA detection circuit
(Option for Intel).
2. ESD diode protection
connected to 3.3V.
3. 2-pole filter(10
pF,bead 47 Ω
@100MHz and 22 pF)
4. 150-Ω±1% resistor
to GND
to COME Pin B89
VGA_RED

Connect to
1. VGA detection circuit
(Option for Intel).
2. ESD diode protection
connected to 3.3V.
3. 2-pole filter(10
pF,bead 47 Ω
@100MHz and 22 pF)
4. 150-Ω±1% resistor
to GND
to COME Pin B91
VGA_GRN

Connect to
1. VGA detection circuit
(Option for Intel).
2. ESD diode protection
connected to 3.3V.
3. 2-pole filter(10
pF,bead 47 Ω
@100MHz and 22 pF)
4. 150-Ω±1% resistor
to GND
to COME Pin B92
VGA_BLU

Connect
1. Bypass
33p~50pF(NL) to GND.
2. 27~39Ω in series
to COME Pin B93
VGA_HSYNC

Connect to GND
 Baseboard

T2-5 - Connect to D52

TMDS_DATA2+ or D65
TMDS_DATA5+ and
ESD protection
T6 - Connect to D26
TMDS1_DATA2+ or D39
TMDS2_DATA2+ or C39
TMDS3_DATA2+ and
ESD protection
T10 - Connect to B71
TMDS0_DATA2+ and
ESD protection

Connect to GND

T2-5 - Connect to D53

TMDS_DATA2- or D66
TMDS_DATA5- and
ESD protection
T6 - Connect to D27
TMDS1_DATA2- or D40
TMDS2_DATA2- or C40
TMDS3_DATA2- and
ESD protection
T10 - Connect to B72
TMDS0_DATA2- and
ESD protection

T2-5 - Connect to D55

TMDS_DATA1+ or D68
TMDS_DATA4+ and
ESD protection
T6 - Connect to D29
TMDS1_DATA1+ or D42
TMDS2_DATA1+ or C42
TMDS3_DATA1+ and
ESD protection
T10 - Connect to B73
TMDS0_DATA1+ and
ESD protection

Connect to GND
T2-5 - Connect to D56
TMDS_DATA1- or D69
TMDS_DATA4- and
ESD protection
T6 - Connect to D30
TMDS1_DATA1- or D43
TMDS2_DATA1- or C43
TMDS3_DATA1- and
ESD protection
T10 - Connect to B74
TMDS0_DATA1- and
ESD protection

T2-5 - Connect to D58

TMDS_DATA0+ or D71
TMDS_DATA3+ and
ESD protection
T6 - Connect to D32
TMDS1_DATA0+ or D46
TMDS2_DATA0+ or C46
TMDS3_DATA0+ and
ESD protection
T10 - Connect to B75
TMDS0_DATA0+ and
ESD protection

Connect to GND

T2-5 - Connect D59

TMDS_DATA0- or D72
TMDS_DATA3- and
ESD protection
T6 - Connect to D33
TMDS1_DATA0- or D47
TMDS2_DATA0- or C47
TMDS3_DATA0- and
ESD protection
T10 - Connect to B76
TMDS0_DATA0- and
ESD protection

T2-5 - Connect to D61

TMDS_CLK+ or D74
TMDSB_CLK+ and ESD
protection
T6 - Connect to D36
TMDS1_CLK+ or D49
TMDS2_CLK+ or C49
TMDS3_CLK+ and ESD
protection
T10 - Connect to B81
TMDS0_CLK+ and ESD
protection

Connect to GND
T2-5 Connect to D62
TMDS_CLK- or D75
TMDSB_CLK- and ESD
protection
T6 - Connect to D37
TMDS1_CLK- or D50
TMDS2_CLK- or C50
TMDS3_CLK- and ESD
protection
T10 - Connect to B82
TMDS0_CLK- and ESD
protection

Connect to CEC bus

N/C

PU 4.7K to 5V and
connect 5V to 3.3V
Level Shifter to
T2-5 - D73
TMDSA_DDC_CLK or
D83 HDMIB_CTRLCLK
for DVI-D or B95
VGA_I2C_CK for DVI-I
and ESD protection
T6 - D15
HMDI1_CTRLCLK or
C32 HDMI2_CTRLCLK
or C36
HDMI3_CTRLCLK and
ESD protection
T10 - Connect to B98
HMDI0_CTRLCLK and
ESD protection
PU 4.7K to 5V and
connect 5V to 3.3V
Level Shifter to
T2-5 - C73
TMDSA_DDC_DAT or
C83 TMDSB_DDC_DAT
for DVI-D or B96
VGA_I2C_DAT for DVI-I
and ESD protection
T6 - D16
HMDI1_CTRLDATA or
C33
HDMI2_CTRLDATA or
C37 HDMI3_CTRLDATA
and ESD protection
T10 - Connect to B99
HMDI0_CTRLDATA and
ESD protection

Connect to GND
Connect fuse and EMI
solution to 5V

T2-5 - Connect to C61

HDMIA_HPD or C74
HDMIB_HPD and ESD
protection
T6 - Connect to C24
HDMI1_HPD or D44
HDMI2_HPD or C44
HDMI3_HPD and ESD
protection
T10 - Connect to B89
HDMI0_HPD and ESD
protection
 Pwr Rail / Tolerance
Pin No. PCI Bus Pin Type Description Baseboard

Connect to
Device - AD[00]
PCI Slot - Pin A58
C24 PCI_AD0
AD[00]
MiniPCI - Pin 96 AD[00]
N/C if not used

Connect to
Device - AD[01]
PCI Slot - Pin B58
D22 PCI_AD1
AD[01]
MiniPCI - Pin 99 AD[01]
N/C if not used

Connect to
Device - AD[02]
PCI Slot - Pin A57
C25 PCI_AD2
AD[02]
MiniPCI - Pin 94 AD[02]
N/C if not used

Connect to
Device - AD[03]
PCI Slot - Pin B56
D23 PCI_AD3
AD[03]
MiniPCI - Pin 95 AD[03]
N/C if not used

Connect to
Device - AD[04]
PCI Slot - Pin A55
C26 PCI_AD4
AD[04]
MiniPCI - Pin 92 AD[04]
N/C if not used
 Connect to
Device - AD[05]
PCI Slot - Pin B55
D24 PCI_AD5
AD[05]
MiniPCI - Pin 91 AD[05]
N/C if not used

Connect to
Device - AD[06]
PCI Slot - Pin A54
C27 PCI_AD6
AD[06]
MiniPCI - Pin 90 AD[06]
N/C if not used

Connect to
Device - AD[07]
PCI Slot - Pin B53
D25 PCI_AD7
AD[07]
MiniPCI - Pin 87 AD[07]
N/C if not used

Connect to
Device - AD[08]
PCI Slot - Pin B52
C28 PCI_AD8
AD[08]
MiniPCI - Pin 85 AD[08]
N/C if not used

Connect to
Device - AD[09]
PCI Slot - Pin A49
D27 PCI_AD9
AD[09]
MiniPCI - Pin 84 AD[09]
N/C if not used
 Connect to
Device - AD[10]
PCI Slot - Pin B48
C29 PCI_AD10
AD[10]
MiniPCI - Pin 81 AD[10]
N/C if not used

Connect to
Device - AD[11]
PCI Slot - Pin A47
D28 PCI_AD11
AD[11]
MiniPCI - Pin 80 AD[11]
N/C if not used

Connect to
Device - AD[12]
PCI Slot - Pin B47
C30 PCI_AD12
AD[12]
MiniPCI - Pin 79 AD[12]
N/C if not used

Connect to
Device - AD[13]
PCI Slot - Pin A46
D29 PCI_AD13
AD[13]
MiniPCI - Pin 78 AD[13]
N/C if not used

Connect to
Device - AD[14]
PCI Slot - Pin B45
C32 PCI_AD14
AD[14]
MiniPCI - Pin 75 AD[14]
N/C if not used

I/O
3.3V / 5V PCI bus multiplexed address and data lines
CMOS
 Connect to
Device - AD[15]
PCI Slot - Pin A44
D30 PCI_AD15
AD[15]
MiniPCI - Pin 76 AD[15]
N/C if not used
I/O
3.3V / 5V PCI bus multiplexed address and data lines
CMOS
Connect to
Device - AD[16]
PCI Slot - Pin A32
D37 PCI_AD16
AD[16]
MiniPCI - Pin 60 AD[16]
N/C if not used

Connect to
Device - AD[17]
PCI Slot - Pin B32
C39 PCI_AD17
AD[17]
MiniPCI - Pin 57 AD[17]
N/C if not used

Connect to
Device - AD[18]
PCI Slot - Pin A31
D38 PCI_AD18
AD[18]
MiniPCI - Pin 58 AD[18]
N/C if not used

Connect to
Device - AD[19]
PCI Slot - Pin B30
C40 PCI_AD19
AD[19]
MiniPCI - Pin 53 AD[19]
N/C if not used
 Connect to
Device - AD[20]
PCI Slot - Pin A29
D39 PCI_AD20
AD[20]
MiniPCI - Pin 54 AD[20]
N/C if not used

Connect to
Device - AD[21]
PCI Slot - Pin B29
C42 PCI_AD21
AD[21]
MiniPCI - Pin 51 AD[21]
N/C if not used

Connect to
Device - AD[22]
PCI Slot - Pin A28
D40 PCI_AD22
AD[22]
MiniPCI - Pin 52 AD[22]
N/C if not used

Connect to
Device - AD[23]
PCI Slot - Pin B27
C43 PCI_AD23
AD[23]
MiniPCI - Pin 47 AD[23]
N/C if not used

Connect to
Device - AD[24]
PCI Slot - Pin A25
D42 PCI_AD24
AD[24]
MiniPCI - Pin 46 AD[24]
N/C if not used
 Connect to
Device - AD[25]
PCI Slot - Pin B24
C45 PCI_AD25
AD[25]
MiniPCI - Pin 41 AD[25]
N/C if not used

Connect to
Device - AD[26]
PCI Slot - Pin A23
D43 PCI_AD26
AD[26]
MiniPCI - Pin 44 AD[26]
N/C if not used

Connect to
Device - AD[27]
PCI Slot - Pin B23
C46 PCI_AD27
AD[27]
MiniPCI - Pin 39 AD[27]
N/C if not used

Connect to
Device - AD[28]
PCI Slot - Pin A22
D44 PCI_AD28
AD[28]
MiniPCI - Pin 42 AD[28]
N/C if not used

Connect to
Device - AD[29]
PCI Slot - Pin B21
C47 PCI_AD29
AD[29]
MiniPCI - Pin 35 AD[29]
N/C if not used
 Connect to
Device - AD[30]
PCI Slot - Pin A20
D45 PCI_AD30
AD[30]
MiniPCI - Pin 38 AD[30]
N/C if not used

Connect to
Device - AD[31]
PCI Slot - Pin B20
C48 PCI_AD31
AD[31]
MiniPCI - Pin 33 AD[31]
N/C if not used

Connect to
Device - C/BE[0]#
PCI Slot - Pin A52
D26 PCI_C/BE0# C/BE[0]#
MiniPCI - Pin 86
C/BE[0]#
N/C if not used

Connect to
Device - C/BE[1]#
PCI Slot - Pin B44
C33 PCI_C/BE1# C/BE[1]#
MiniPCI - Pin 73
C/BE[1]#
N/C if not used
I/O
3.3V / 5V PCI bus byte enable lines, active low
CMOS
Connect to
Device - C/BE[2]#
PCI Slot - Pin B33
C38 PCI_C/BE2# C/BE[2]#
MiniPCI - Pin 59
C/BE[2]#
N/C if not used
 Connect to
Device - C/BE[3]#
PCI Slot - Pin B26
C44 PCI_C/BE3# C/BE[3]#
MiniPCI - Pin 45
C/BE[3]#
N/C if not used

Module has integrated

PU resistor to 3.3V or
5V
Connect to
I/O Device - DEVSEL#
C36 PCI_DEVSEL# 3.3V / 5V PCI bus Device Select, active low.
CMOS PCI Slot - Pin B37
DEVSEL#
MiniPCI - Pin 72
DEVSEL#
N/C if not used

Module has integrated

PU resistor to 3.3V or
5V
Connect to
I/O Device - FRAME#
D36 PCI_FRAME# 3.3V / 5V PCI bus Frame control line, active low.
CMOS PCI Slot - Pin A34
FRAME#
MiniPCI - Pin 64
FRAME#
N/C if not used

Module has integrated

PU resistor to 3.3V or
5V
Connect to
I/O
C37 PCI_IRDY# 3.3V / 5V PCI bus Initiator Ready control line, active low. Device - IRDY#
CMOS
PCI Slot - Pin B35
IRDY#
MiniPCI - Pin 61 IRDY#
N/C if not used
 Module has integrated
PU resistor to 3.3V or
5V
Connect to
I/O
D35 PCI_TRDY# 3.3V / 5V PCI bus Target Ready control line, active low. Device - TRDY#
CMOS
PCI Slot - Pin A36
TRDY#
MiniPCI - Pin 66 TRDY#
N/C if not used

Module has integrated

PU resistor to 3.3V or
5V
Connect to
I/O PCI bus STOP control line, active low, driven by
D34 PCI_STOP# 3.3V / 5V Device - STOP#
CMOS cycle initiator.
PCI Slot - Pin A38
STOP#
MiniPCI - Pin 68 STOP#
N/C if not used

Connect to
Device - PAR
I/O
D32 PCI_PAR 3.3V / 5V PCI bus parity PCI Slot - Pin A43 PAR
CMOS
MiniPCI - Pin 56 PAR
N/C if not used

Module has integrated

PU resistor to 3.3V or
5V
Connect to
I/O Parity Error: An external PCI device drives PERR#
C34 PCI_PERR# 3.3V / 5V Device - PERR#
CMOS when it receives data that has a parity error.
PCI Slot - Pin B40
PERR#
MiniPCI - Pin 71 PERR#
N/C if not used
 Module has integrated
PU resistor to 3.3V or
5V
Connect to
C22 PCI_REQ0# Device - REQ#
PCI Slot - Pin B18
REQ#
MiniPCI - Pin 29 REQ#
N/C if not used

Module has integrated

PU resistor to 3.3V or
5V
Connect to
C19 PCI_REQ1# Device - REQ#
PCI Slot - Pin B18
REQ#
MiniPCI - Pin 29 REQ#
N/C if not used
I
3.3V / 5V PCI bus master request input lines, active low.
CMOS
Module has integrated
PU resistor to 3.3V or
5V
Connect to
C17 PCI_REQ2# Device - REQ#
PCI Slot - Pin B18
REQ#
MiniPCI - Pin 29 REQ#
N/C if not used
 Module has integrated
PU resistor to 3.3V or
5V
Connect to
D20 PCI_REQ3# Device - REQ#
PCI Slot - Pin B18
REQ#
MiniPCI - Pin 29 REQ#
N/C if not used

Connect to
Device - GNT#
PCI Slot - Pin A17
C20 PCI_GNT0#
GNT#
MiniPCI - Pin 30 GNT#
N/C if not used

Connect to
Device - GNT#
PCI Slot - Pin A17
C18 PCI_GNT1#
GNT#
MiniPCI - Pin 30 GNT#
N/C if not used
O
3.3V / 5V PCI bus master grant output lines, active low.
CMOS
Connect to
Device - GNT#
PCI Slot - Pin A17
C16 PCI_GNT2#
GNT#
MiniPCI - Pin 30 GNT#
N/C if not used

Connect to
Device - GNT#
PCI Slot - Pin A17
D19 PCI_GNT3#
GNT#
MiniPCI - Pin 30 GNT#
N/C if not used
 Connect to
Device - RST#
O 3.3V / 5V Suspend PCI Slot - Pin A15
C23 PCI_RESET# PCI Reset output, active low.
CMOS 3.3V Suspend / 5V RST#
MiniPCI - Pin 26 RST#
N/C if not used

Module has integrated

PU resistor to 3.3V or
5V
I/O Connect to
C35 PCI_LOCK# 3.3V / 5V PCI Lock control line, active low.
CMOS Device - LOCK#
PCI Slot - Pin B39
LOCK#
N/C if not used

Module has integrated

PU resistor to 3.3V or
5V
System Error: SERR# may be pulsed active by Connect to
I/O OD
D33 PCI_SERR# 3.3V / 5V any PCI device that detects a system error Device - SERR#
CMOS
condition. PCI Slot - Pin B42
SERR#
MiniPCI - Pin 67 SERR#
N/C if not used

Module has integrated

PU resistor to
3.3VDUAL
PCI Power Management Event: PCI peripherals Connect to
I 3.3V / 5V Suspend
C15 PCI_PME# drive PME# to wake system from low-power states Device - PME#
CMOS 3.3V Suspend / 5V
S1–S5. PCI Slot - Pin A19
PME#
MiniPCI - Pin 34 PME#
N/C if not used
 Module has integrated
PU resistor to 3.3V
Connect to
I/O Bidirectional pin used to support PCI clock run
D48 PCI_CLKRUN# 3.3V / 5V Device - CLKRUN#
CMOS protocol for mobile systems.
MiniPCI - Pin 65
CLKRUN#
N/C if not used

Module has integrated

PU resistor to 3.3V or
5V
Connect to
Device - INTA# for
AD20
PCI Slot - Pin A6 INTA#
C49 PCI_IRQA# for AD20, B8 INTD# for
AD21, A7 INTC# for
AD22, B7 INTB# for
AD23
MiniPCI - Pin 20 INTA#
for AD20, 17 INTB# for
AD23
N/C if not used

Module has integrated

PU resistor to 3.3V or
5V
Connect to
Device - INTA# for
AD21
PCI Slot - Pin B7 INTB#
C50 PCI_IRQB# for AD20, A6 INTA# for
AD21, B8 INTD# for
AD22, A7 INTC# for
AD23;
MiniPCI - Pin 20 INTA#
for AD21, 17 INTB# for
AD20
N/C if not used
I
3.3V / 5V PCI interrupt request lines.
CMOS
 I
3.3V / 5V PCI interrupt request lines.
CMOS
Module has integrated
PU resistor to 3.3V or
5V
Connect to
Device - INTA# for
AD22
PCI Slot - Pin A7 INTC#
D46 PCI_IRQC# for AD20, B7 INTB# for
AD21, A6 INTA# for
AD22, B8 INTD# for
AD23;
MiniPCI - Pin 20 INTA#
for AD22, 17 INTB# for
AD21
N/C if not used

Module has integrated

PU resistor to 3.3V or
5V
Connect to
Device - INTA# for
AD23
PCI Slot - Pin B8 INTD#
D47 PCI_IRQD# for AD20, A7 INTC# for
AD21, B7 INTB# for
AD22, A6 INTA# for
AD23;
MiniPCI - Pin 20 INTA#
for AD23, 17 INTB# for
AD22
N/C if not used

Module has integrated

series resistor.
Connect to
O
D50 PCI_CLK 3.3V / 3.3V PCI 33MHz clock output. Device - CLK
CMOS
PCI Slot - Pin B16 CLK
MiniPCI - Pin 25
N/C if not used
 Module has integrated
PU resistor to 3.3V
Module input signal indicates whether an off-
Bypass 0.01uF to GND
module PCI device is capable of 66MHz operation.
and connect to
Pulled to GND by Carrier Board device or by Slot
PCI - M66EN
Card if the devices are NOT capable of 66 MHz
PCI Slot - Pin B49
operation.
M66EN on 3.3V System
I If the module is not capable of supporting 66 MHz
D49 PCI_M66EN 3.3V / 5V Environment pinout
CMOS PCI operation, this input maybe a no-connect on
MiniPCI - Pin 104
the module.
M66EN
If the module is capable of supporting 66 MHz PCI
and configure
operation, and if this input is held low by the Carrier
66MHz - N/C
Board, the module PCI interface shall operate at
33MHz - PD 100Ω to
33 MHz.
GND
N/C if not used

This pin is not present on the COM Express

module connector, but it is present on each PCI
Connect 300Ω to 900Ω
slot connector or device. IDSEL is an input to the
in series to ADxx
device and is used to set a device’s configuration
PCI Routing Table -
address for PCI configuration cycles. The IDSEL
I AD20 - INTA#
IDSEL 3.3V / 5V pin of each device is typically connected to one of
COMS AD21 - INTB#
the AD lines to set a unique configuration address.
AD22 - INTC#
In COM Express systems, the four external bus
AD23 - INTD#
slots or devices are assumed to use AD[20..23] for
IDSEL connections. See the COM Express Design
Guide for details.

4.3.8 PCI Bus

The PCI bus interface is specified to be a 32-bit PCI 2.3 compliant bus with speed options of 33MHz or 66MHz.
The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a
8.2kΩ resistor
• PCI_IRQ[A:D]#
• PCI_IRDY#
• PCI_LOCK#
• PCI_PERR#
• PCI_REQ[0:3]#
• PCI_SERR#
• PCI_STOP#
• PCI_TRDY#
• PCI_FRAME#
• PCI_CLKRUN#

The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V Standby
with a 10kΩ resistor
• PCI_PME#

5.5 PCI Bus Implementation

5.5.1 Carrier Board PCI Resource Allocation
On COM Express® modules with Type 2 and 3 pin-outs, four off-module PCI devicesCarrier Board PCI targets shall be
supported. The off-module devices are referred to referenced as Slot 0,1,2 and 3 devices. They may be PCI slots
(connectors) on the Carrier Board, or they may be actual PCI devices on the Carrier Board itself. The PCI implementation
shall support four REQ / GNT pairs for off-module use.
The interrupts in Table 5.165.18 are PCI interrupts defined by the PCI SIG specification and not meant to imply direct
connection to the legacy ISA IRQ lines.
The following table summarizes how resources are allocated on a Carrier Board implementation.
Table 5.215.165.18: Carrier Board PCI Resource Allocation
Slot / Device
Slot / Device 0 Slot / Device 1 Slot / Device 2 Slot / Device 3
Signal
IDSEL PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23]
PCI Clock PCI_CLK replica PCI_CLK replica PCI_CLK replica PCI_CLK replica

INTA# PCI_IRQ[A]# PCI_IRQ[B]# PCI_IRQ[C]# PCI_IRQ[D]#

INTB# (if used) PCI_IRQ[B]# PCI_IRQ[C]# PCI_IRQ[D]# PCI_IRQ[A]#
INTC# (if used) PCI_IRQ[C]# PCI_IRQ[D]# PCI_IRQ[A]# PCI_IRQ[B]#
INTD# (if used) PCI_IRQ[D]# PCI_IRQ[A]# PCI_IRQ[B]# PCI_IRQ[C]#

REQ# PCI_REQ[0]# PCI_REQ[1]# PCI_REQ[2]# PCI_REQ[3]#

GNT# PCI_GNT[0]# PCI_GNT[1]# PCI_GNT[2]# PCI_GNT[3]#

5.5.2 PCI Clocks

COM Express® specifies only a single copy of the PCI clock for off-moduleCarrier Board target device use. If only one Carrier
Board PCI device is implemented, then that single clock may be routed to the device. If more than one Carrier Board PCI
device is implemented, then the Carrier Board should replicate the PCI clock using a zero delay buffer. The zero delay buffer
if used should support spread spectrum clocking. See the Carrier Design Guide for specific commendations of buffers that
support spread spectrum clocking. The Module EEPROM spread spectrum clocking bit should be set appropriately so that
the Module can determine the capabilities of the Carrier Board.
The PCI Local Bus Specification requires that PCI clocks be synchronous within a 2 ns window at the destination devices;
that the maximum propagation delay for the clock be 10 ns, and that PCI slot based add-on cards implement a PCI clock
trace length of 2.5 inches.
COM Express® Carrier Board implementations should allow 1.6 ns +/- 0.1 ns for the PCI clock propagation delay from the
COM Express® module connector pin to the destination device pin.
Propagation delay varies with construction details such as trace geometry, PCB stack up, and PCB material dielectric
constant. Propagation delay values of 140 ps / inch to 180 ps / inch are
common for outer layer traces. A propagation delay value of 180 ps / inch is common for inner layer traces. Using 180 ps
/inch as the propagation delay value for an inner layer Carrier Board PCI clock,
then the COM Express® Carrier Board delay of 1.6 ns works out to 8.88 inches of trace.
If the destination device is on an add on card, then the propagation delay associated with the 2.5 inches of add on card trace
are deducted from the 1.6 ns. Using 160 ps / inch as a typical value for an
outer layer slot card clock trace, the 2.5 inches of slot card clock trace length work out to a propagation delay of 0.4 ns. The
Carrier Board PCI clock delay in this example would be 1.6 ns – 0.4 ns or
1.2 ns.
The following definitions and equations apply:
TMD Propagation delay: module PCI clock source to on-module PCI device
TMC Propagation delay: module PCI clock source to module connector PCI clock pin
TCD Propagation delay: module connector to Carrier Board device.
Fixed by COM ExpressTM Specification at 1.6 ns
TCS Propagation delay: module connector to slot connector pin
LSD Length: slot card connector pin to slot card device.
Fixed by PCI Local Bus Specification at 2.5 inches
PSD Inverse propagation speed: slot card connector pin to slot card device (units of time / length)
Determined by slot card PCB design; typical value 160 ps / inch
TMD = TMC + TCD
TMD = TMC + TCS + LSD * PSD
TCS = TCD – LSD * PSD
The parameters TMD and TMC apply to module designs. Module designers should minimize TMC, and then arrange that TMD
satisfies the relation
TMD = TMC + TCD.

PCI Clocks — Carrier Board PCI Device PCI Clocks — Slot Card PCI Device
 TMD = TMC + TCS + LSD * PSD
TMD = TMC + TCD
TCS = TCD – LSD*PSD

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
SOM-5894 A101-4
Baseboard
 N/C, PCIe to PCI
Bridge like PLX
PEX8112 or Pericom
PI7C9X110 is
suggested.
Pin No. USB Pin Type Pwr Rail / Tolerance Description Baseboard

Device - Connect to
A46 USB0+ D+/-
Conn. - Connect 90Ω
@100MHz Common
Choke in series and
ESD suppressors to
GND to Pin 3 D+ / Pin 2
A45 USB0- D-
N/C if not used

Device - Connect to
B46 USB1+ D+/-
Conn. - Connect 90Ω
@100MHz Common
Choke in series and
ESD suppressors to
GND to Pin 3 D+ / Pin 2
B45 USB1- D-
N/C if not used

Device - Connect to
A43 USB2+ D+/-
Conn. - Connect 90Ω
@100MHz Common
Choke in series and
ESD suppressors to
GND to Pin 3 D+ / Pin 2
A42 USB2- D-
N/C if not used
 Device - Connect to
B43 USB3+ D+/-
Conn. - Connect 90Ω
@100MHz Common
Choke in series and
ESD suppressors to
GND to Pin 3 D+ / Pin 2
B42 USB3- D-
USB differential pairs, channels 0 through 7 N/C if not used
USB7 may be configured as a USB client or as a
I/O 3.3V / 3.3V Suspend
host, or both, at the Module designer's discretion.
USB 3.3V Suspend / 3.3V
All other USB ports, if implemented, shall be host
ports. Device - Connect to
A40 USB4+ D+/-
Conn. - Connect 90Ω
@100MHz Common
Choke in series and
ESD suppressors to
GND to Pin 3 D+ / Pin 2
A39 USB4- D-
N/C if not used

Device - Connect to
B40 USB5+ D+/-
Conn. - Connect 90Ω
@100MHz Common
Choke in series and
ESD suppressors to
GND to Pin 3 D+ / Pin 2
B39 USB5- D-
N/C if not used
 Device - Connect to
A37 USB6+ D+/-
Conn. - Connect 90Ω
@100MHz Common
Choke in series and
ESD suppressors to
GND to Pin 3 D+ / Pin 2
A36 USB6- D-
N/C if not used

Device - Connect to
B37 USB7+ D+/-
Conn. - Connect 90Ω
@100MHz Common
Choke in series and
ESD suppressors to
GND to Pin 3 D+ / Pin 2
B36 USB7- D-
N/C if not used

Module has integrated

AC Coupling Capacitors
D4 USB_SSTX0+ Device - Connect to
StdA_SSRX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Additional transmit signal differential pairs for the Choke(NL) combined in
O PCIE AC coupled on Module
SuperSpeed USB data path. series and USB3.0 ESD
suppressors to GND to
Pin 9 StdA_SSTX+ / Pin
8 StdA_SSTX-, the
value of CMC depends
on EMI and signal
integrity performance.
N/C if not used
 AC Coupling Capacitors
Device - Connect to
StdA_SSRX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Additional transmit signal differential pairs for the Choke(NL) combined in
O PCIE AC coupled on Module
SuperSpeed USB data path. series and USB3.0 ESD
suppressors to GND to
Pin 9 StdA_SSTX+ / Pin
8 StdA_SSTX-, the
value of CMC depends
D3 USB_SSTX0- on EMI and signal
integrity performance.
N/C if not used

Module has integrated

AC Coupling Capacitors
D7 USB_SSTX1+ Device - Connect to
StdA_SSRX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Additional transmit signal differential pairs for the Choke(NL) combined in
O PCIE AC coupled on Module
SuperSpeed USB data path. series and USB3.0 ESD
suppressors to GND to
Pin 9 StdA_SSTX+ / Pin
8 StdA_SSTX-, the
value of CMC depends
D6 USB_SSTX1- on EMI and signal
integrity performance.
N/C if not used
 Module has integrated
AC Coupling Capacitors
D10 USB_SSTX2+ Device - Connect to
StdA_SSRX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Additional transmit signal differential pairs for the Choke(NL) combined in
O PCIE AC coupled on Module
SuperSpeed USB data path. series and USB3.0 ESD
suppressors to GND to
Pin 9 StdA_SSTX+ / Pin
8 StdA_SSTX-, the
value of CMC depends
D9 USB_SSTX2- on EMI and signal
integrity performance.
N/C if not used

Module has integrated

AC Coupling Capacitors
D13 USB_SSTX3+ Device - Connect to
StdA_SSRX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Additional transmit signal differential pairs for the Choke(NL) combined in
O PCIE AC coupled on Module
SuperSpeed USB data path. series and USB3.0 ESD
suppressors to GND to
Pin 9 StdA_SSTX+ / Pin
8 StdA_SSTX-, the
value of CMC depends
on EMI and signal
integrity performance.
N/C if not used
 AC Coupling Capacitors
Device - Connect to
StdA_SSRX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Additional transmit signal differential pairs for the Choke(NL) combined in
O PCIE AC coupled on Module
SuperSpeed USB data path. series and USB3.0 ESD
suppressors to GND to
Pin 9 StdA_SSTX+ / Pin
8 StdA_SSTX-, the
value of CMC depends
D12 USB_SSTX3- on EMI and signal
integrity performance.
N/C if not used

Device - Connect AC
Coupling Capacitors
C4 USB_SSRX0+ 100nF near COME to
StdA_SSTX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Additional receive signal differential pairs for the Choke(NL) combined in
I PCIE AC coupled off Module
SuperSpeed USB data path. series and USB3.0 ESD
suppressors to GND to
Pin 6 StdA_SSRX+ / Pin
5 StdA_SSRX-, the
value of CMC depends
C3 USB_SSRX0- on EMI and signal
integrity performance.
N/C if not used
 Device - Connect AC
Coupling Capacitors
C7 USB_SSRX1+ 100nF near COME to
StdA_SSTX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Additional receive signal differential pairs for the Choke(NL) combined in
I PCIE AC coupled off Module
SuperSpeed USB data path. series and USB3.0 ESD
suppressors to GND to
Pin 6 StdA_SSRX+ / Pin
5 StdA_SSRX-, the
value of CMC depends
C6 USB_SSRX1- on EMI and signal
integrity performance.
N/C if not used

Device - Connect AC
Coupling Capacitors
C10 USB_SSRX2+ 100nF near COME to
StdA_SSTX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Additional receive signal differential pairs for the Choke(NL) combined in
I PCIE AC coupled off Module
SuperSpeed USB data path. series and USB3.0 ESD
suppressors to GND to
Pin 6 StdA_SSRX+ / Pin
5 StdA_SSRX-, the
value of CMC depends
on EMI and signal
integrity performance.
N/C if not used
 Coupling Capacitors
100nF near COME to
StdA_SSTX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Additional receive signal differential pairs for the Choke(NL) combined in
I PCIE AC coupled off Module
SuperSpeed USB data path. series and USB3.0 ESD
suppressors to GND to
Pin 6 StdA_SSRX+ / Pin
5 StdA_SSRX-, the
value of CMC depends
C9 USB_SSRX2- on EMI and signal
integrity performance.
N/C if not used

Device - Connect AC
Coupling Capacitors
C13 USB_SSRX3+ 100nF near COME to
StdA_SSTX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Additional receive signal differential pairs for the Choke(NL) combined in
I PCIE AC coupled off Module
SuperSpeed USB data path. series and USB3.0 ESD
suppressors to GND to
Pin 6 StdA_SSRX+ / Pin
5 StdA_SSRX-, the
value of CMC depends
C12 USB_SSRX3- on EMI and signal
integrity performance.
N/C if not used
 Module has integrated
AC Coupling Capacitors
B23 USB_SSTX0+ Device - Connect to
StdA_SSRX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Additional transmit signal differential pairs for the Choke(NL) combined in
O PCIE AC coupled on Module
SuperSpeed USB data path. series and USB3.0 ESD
suppressors to GND to
Pin 9 StdA_SSTX+ / Pin
8 StdA_SSTX-, the
value of CMC depends
B22 USB_SSTX0- on EMI and signal
integrity performance.
N/C if not used

Module has integrated

AC Coupling Capacitors
B26 USB_SSTX1+ Device - Connect to
StdA_SSRX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Additional transmit signal differential pairs for the Choke(NL) combined in
O PCIE AC coupled on Module
SuperSpeed USB data path. series and USB3.0 ESD
suppressors to GND to
Pin 9 StdA_SSTX+ / Pin
8 StdA_SSTX-, the
value of CMC depends
on EMI and signal
integrity performance.
N/C if not used
 AC Coupling Capacitors
Device - Connect to
StdA_SSRX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Additional transmit signal differential pairs for the Choke(NL) combined in
O PCIE AC coupled on Module
SuperSpeed USB data path. series and USB3.0 ESD
suppressors to GND to
Pin 9 StdA_SSTX+ / Pin
8 StdA_SSTX-, the
value of CMC depends
B25 USB_SSTX1- on EMI and signal
integrity performance.
N/C if not used

Device - Connect AC
Coupling Capacitors
A23 USB_SSRX0+ 100nF near COME to
StdA_SSTX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Additional receive signal differential pairs for the Choke(NL) combined in
I PCIE AC coupled off Module
SuperSpeed USB data path. series and USB3.0 ESD
suppressors to GND to
Pin 6 StdA_SSRX+ / Pin
5 StdA_SSRX-, the
value of CMC depends
A22 USB_SSRX0- on EMI and signal
integrity performance.
N/C if not used
 Device - Connect AC
Coupling Capacitors
A26 USB_SSRX1+ 100nF near COME to
StdA_SSTX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Additional receive signal differential pairs for the Choke(NL) combined in
I PCIE AC coupled off Module
SuperSpeed USB data path. series and USB3.0 ESD
suppressors to GND to
Pin 6 StdA_SSRX+ / Pin
5 StdA_SSRX-, the
value of CMC depends
A25 USB_SSRX1- on EMI and signal
integrity performance.
N/C if not used

Module has integrated

USB over-current sense, USB channels 0 and 1. PU 10KΩ resistor to
A pull-up for this line shall be present on the 3.3VDUAL
I 3.3V / 3.3V Suspend module. An open drain driver from a USB current Connect to Overcurrent
B44 USB_0_1_OC#
CMOS 3.3V Suspend / 3.3V monitor on the Carrier Board may drive this line of Power Distribution
low. Do not pull this line high on the Carrier Switch and Bypass
Board. 0.1uF to GND
N/C if not used
 Module has integrated
USB over-current sense, USB channels 2 and 3. PU 10KΩ resistor to
A pull-up for this line shall be present on the 3.3VDUAL
I 3.3V / 3.3V Suspend module. An open drain driver from a USB current Connect to Overcurrent
A44 USB_2_3_OC#
CMOS 3.3V Suspend / 3.3V monitor on the Carrier Board may drive this line of Power Distribution
low. Do not pull this line high on the Carrier Switch and Bypass
Board. 0.1uF to GND
N/C if not used

Module has integrated

USB over-current sense, USB channels 4 and 5. PU 10KΩ resistor to
A pull-up for this line shall be present on the 3.3VDUAL
I 3.3V / 3.3V Suspend module. An open drain driver from a USB current Connect to Overcurrent
B38 USB_4_5_OC#
CMOS 3.3V Suspend / 3.3V monitor on the Carrier Board may drive this line of Power Distribution
low. Do not pull this line high on the Carrier Switch and Bypass
Board. 0.1uF to GND
N/C if not used

Module has integrated

USB over-current sense, USB channels 6 and 7. PU 10KΩ resistor to
A pull-up for this line shall be present on the 3.3VDUAL
I 3.3V / 3.3V Suspend module. An open drain driver from a USB current Connect to Overcurrent
A38 USB_6_7_OC#
CMOS 3.3V Suspend / 3.3V monitor on the Carrier Board may drive this line of Power Distribution
low. Do not pull this line high on the Carrier Switch and Bypass
Board. 0.1uF to GND
N/C if not used
 USB Conn. Pin 1
connects to
1. Clampling diode, 1uF
Module USB client may detect the presence of a and 100KΩ to GND
I
B96 USB_HOST_PRSNT 3.3V Suspend/ 3.3V USB host. A high value indicates that a host is 2. 5V to 3.3V level
CMOS
present. shifter circuit
to COME
USB_HOST_PRSNT
N/C if not used

1. Intel recommends one 220 µF and two 470 pF

capacitors for every two power lines.
5V / 5V
USB_VCC Power 2. Either a thermister or a power distribution
Suspend
switch (with short circuit and thermal protection) is
required
4.3.9 USB
All USB interfaces shall be USB 2.0 compliant. The minimum of 4 USB channels provides support for keyboard, mouse, CD/DVD drive,
and one additional device. Up to four of the eight USB 2.0 ports can may support the extended signaling for SuperSpeed USB 3.0. Note
that this usage is not required and the actual Carrier Board usage of the USB port is not defined by this specification. USB7 may
optionally be configured as a USB client.

4.4.4 USB
No termination is required on USB pairs. A common mode choke is advisable if USB pairs on the Carrier Board are routed to a
connector for use with an external cable.
Signals USB_0_1_OC#, USB_2_3_OC#, USB_4_5_OC# and USB_6_7_OC# are used to flag a USB over-current situation. Carrier
Board USB current monitors may pull these lines to GND with open drain drivers to indicate that the monitor’s current limit has been
exceeded. Do not pull up these lines to 3.3V on the Carrier Board – this shall be done on the module.
If a USB 2.0 Debug port is present it should be routed to port 0.
The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V Standby with a 10kΩ
resistor
• USB_[0,2,4,6]_[1,3,5,7]_OC#

5.4.4 USB 2.0 Insertion Loss Budget

Figure 5-4: USB 2.0 Insertion Loss Budget

Table 5.195.14: USB Insertion Loss Budget, 400 MHz

Segment Loss (dB) Notes
LA 0.67 Up to 6 inches of module trace @ 0.28 dB / GHz / inch
LB 0.05 COM Express® connector at 400 MHz measured value
LC 1.68 Up to 14 inches of Carrier Board trace @ 0.28 dB / GHz / inch
LD 1.00 USB connector and ferrite loss
LE 5.80 USB cable and far end connector loss, per source specification
Total 9.20
COM Express® USB implementations should conform to insertion loss values less than or equal to those shown in the table above.
The insertion loss values shown account for frequency dependent material losses only. Cross talk losses are separate from material
losses in the USB specification.
"Device Down” implementations, in which the USB target device is implemented on the Carrier Board, may add the ferrite and USB
connector insertion loss values to the Carrier Board budget. The Carrier Board insertion loss budget then becomes LC + LD, or 2.68 dB.

5.4.5 SuperSpeed USB Insertion Loss Budget

Figure 5-5: SuperSpeed USB Insertion Loss Budget

Table 5.15: SuperSpeed USB Insertion Loss Budget

Segment Loss (dB) Notes
LA 1.94 Up to 3 inches of Module trace @ 2.5 GHz
LB 1.20 COM Express connector at 2.5 GHz
LC 3.64 Up to 5 inches of Carrier Board trace @ 2.5 GHz with Common-Mode Component
Total 6.78
USB 2.0 Type A Connector

USB 2.0 Type B Connector

USB 2.0 Standard Connector Signal Description

Pin No. USB Pin Type Pwr Rail / Tolerance Description USB 2.0

1 VBUS Power 5V Suspend / 5V +5V Power Supply

Universal Serial Bus Data, negative differential

2 D- I/O USB 3.3V Suspend / 3.3V
signal.

Universal Serial Bus Data, positive differential

3 D+ I/O USB 3.3V Suspend / 3.3V
signal.
4 GND Power Ground
USB 2.0 Mini-B Connector

USB 2.0 Micro-AB Connector

USB 2.0 Micro-B Connector

USB 2.0 Mini/Micro Connector Signal Description

Pin No. USB Pin Type Pwr Rail / Tolerance Description USB 2.0 Mini/Micro

1 VBUS Power 5V Suspend / 5V +5V Power Supply

 Universal Serial Bus Data, negative differential
2 D- I/O USB 3.3V Suspend / 3.3V
signal.

Universal Serial Bus Data, positive differential

3 D+ I/O USB 3.3V Suspend / 3.3V
signal.

Identification. This is used to differentiate A plug

from B plug.
4 ID I
A plug - connected to Signal ground
B plug - not connected

5 GND Power Ground

USB 3.0 Type A Connector

USB 3.0 Type A Connector Signal Description

Pin No. USB Pin Type Pwr Rail / Tolerance Description USB 3.0 Type A

1 VBUS Power 5V Suspend / 5V +5V Power Supply

2 D- I/O USB 3.3V Suspend / 3.3V USB 2.0, negative differential pair signal.

3 D+ I/O USB 3.3V Suspend / 3.3V USB 2.0, positive differential pair signal.

4 GND Power Ground for power return

SuperSpeed, receiver negative differential pair

5 StdA_SSRX-
signal.

O USB AC coupled off Module

SuperSpeed, receiver positive differential pair

6 StdA_SSRX+
signal.

7 GND_DRAIN Power Ground for signal return

SuperSpeed, transmitter negative differential pair

8 StdA_SSTX-
signal.

I USB AC coupled on Module

SuperSpeed, transmitter positive differential pair

9 StdA_SSTX+
signal.

USB 3.0 Type B Connector

USB 3.0 Type B Connector Signal Description
Pin No. USB Pin Type Pwr Rail / Tolerance Description USB 3.0 Type B

1 VBUS Power 5V Suspend / 5V +5V Power Supply

2 D- I/O USB 3.3V Suspend / 3.3V USB 2.0, negative differential pair signal.

3 D+ I/O USB 3.3V Suspend / 3.3V USB 2.0, positive differential pair signal.

4 GND Power Ground for power return

SuperSpeed, transmitter negative differential pair

5 StdB_SSTX-
signal.

I USB AC coupled on Module

 I USB AC coupled on Module

SuperSpeed, transmitter positive differential pair

6 StdB_SSTX+
signal.

7 GND_DRAIN Power Ground for signal return

SuperSpeed, receiver negative differential pair

8 StdB_SSRX-
signal.

O USB AC coupled off Module

SuperSpeed, receiver positive differential pair

9 StdB_SSRX+
signal.

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 SOM-5894 A101-4
Baseboard

Device - Connect to
D+/-
Conn. - Connect 90Ω
@100MHz Common
Choke in series and
ESD suppressors to
GND to Pin 3 D+ / Pin 2
D-
N/C if not used

Device - Connect to
D+/-
Conn. - Connect 90Ω
@100MHz Common
Choke in series and
ESD suppressors to
GND to Pin 3 D+ / Pin 2
D-
N/C if not used

Device - Connect to
D+/-
Conn. - Connect 90Ω
@100MHz Common
Choke in series and
ESD suppressors to
GND to Pin 3 D+ / Pin 2
D-
N/C if not used
Device - Connect to
D+/-
Conn. - Connect 90Ω
@100MHz Common
Choke in series and
ESD suppressors to
GND to Pin 3 D+ / Pin 2
D-
N/C if not used

Device - Connect to
D+/-
Conn. - Connect 90Ω
@100MHz Common
Choke in series and
ESD suppressors to
GND to Pin 3 D+ / Pin 2
D-
N/C if not used

Device - Connect to
D+/-
Conn. - Connect 90Ω
@100MHz Common
Choke in series and
ESD suppressors to
GND to Pin 3 D+ / Pin 2
D-
N/C if not used
Device - Connect to
D+/-
Conn. - Connect 90Ω
@100MHz Common
Choke in series and
ESD suppressors to
GND to Pin 3 D+ / Pin 2
D-
N/C if not used

Device - Connect to
D+/-
Conn. - Connect 90Ω
@100MHz Common
Choke in series and
ESD suppressors to
GND to Pin 3 D+ / Pin 2
D-
N/C if not used

Module has integrated

AC Coupling Capacitors
Device - Connect to
StdA_SSRX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Choke(NL) combined in
series and USB3.0 ESD
suppressors to GND to
Pin 9 StdA_SSTX+ / Pin
8 StdA_SSTX-, the
value of CMC depends
on EMI and signal
integrity performance.
N/C if not used
AC Coupling Capacitors
Device - Connect to
StdA_SSRX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Choke(NL) combined in
series and USB3.0 ESD
suppressors to GND to
Pin 9 StdA_SSTX+ / Pin
8 StdA_SSTX-, the
value of CMC depends
on EMI and signal
integrity performance.
N/C if not used

Module has integrated

AC Coupling Capacitors
Device - Connect to
StdA_SSRX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Choke(NL) combined in
series and USB3.0 ESD
suppressors to GND to
Pin 9 StdA_SSTX+ / Pin
8 StdA_SSTX-, the
value of CMC depends
on EMI and signal
integrity performance.
N/C if not used
Module has integrated
AC Coupling Capacitors
Device - Connect to
StdA_SSRX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Choke(NL) combined in
series and USB3.0 ESD
suppressors to GND to
Pin 9 StdA_SSTX+ / Pin
8 StdA_SSTX-, the
value of CMC depends
on EMI and signal
integrity performance.
N/C if not used

Module has integrated

AC Coupling Capacitors
Device - Connect to
StdA_SSRX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Choke(NL) combined in
series and USB3.0 ESD
suppressors to GND to
Pin 9 StdA_SSTX+ / Pin
8 StdA_SSTX-, the
value of CMC depends
on EMI and signal
integrity performance.
N/C if not used
AC Coupling Capacitors
Device - Connect to
StdA_SSRX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Choke(NL) combined in
series and USB3.0 ESD
suppressors to GND to
Pin 9 StdA_SSTX+ / Pin
8 StdA_SSTX-, the
value of CMC depends
on EMI and signal
integrity performance.
N/C if not used

Device - Connect AC
Coupling Capacitors
100nF near COME to
StdA_SSTX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Choke(NL) combined in
series and USB3.0 ESD
suppressors to GND to
Pin 6 StdA_SSRX+ / Pin
5 StdA_SSRX-, the
value of CMC depends
on EMI and signal
integrity performance.
N/C if not used
Device - Connect AC
Coupling Capacitors
100nF near COME to
StdA_SSTX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Choke(NL) combined in
series and USB3.0 ESD
suppressors to GND to
Pin 6 StdA_SSRX+ / Pin
5 StdA_SSRX-, the
value of CMC depends
on EMI and signal
integrity performance.
N/C if not used

Device - Connect AC
Coupling Capacitors
100nF near COME to
StdA_SSTX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Choke(NL) combined in
series and USB3.0 ESD
suppressors to GND to
Pin 6 StdA_SSRX+ / Pin
5 StdA_SSRX-, the
value of CMC depends
on EMI and signal
integrity performance.
N/C if not used
Coupling Capacitors
100nF near COME to
StdA_SSTX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Choke(NL) combined in
series and USB3.0 ESD
suppressors to GND to
Pin 6 StdA_SSRX+ / Pin
5 StdA_SSRX-, the
value of CMC depends
on EMI and signal
integrity performance.
N/C if not used

Device - Connect AC
Coupling Capacitors
100nF near COME to
StdA_SSTX+/-
Conn. - Connect 0Ω and
90Ω @100MHz USB3.0
Common Mode
Choke(NL) combined in
series and USB3.0 ESD
suppressors to GND to
Pin 6 StdA_SSRX+ / Pin
5 StdA_SSRX-, the
value of CMC depends
on EMI and signal
integrity performance.
N/C if not used
N/C
N/C
Module has integrated
PU resistor to
3.3VDUAL
Connect to Overcurrent
of Power Distribution
Switch and Bypass
0.1uF to GND
N/C if not used
Module has integrated
PU resistor to
3.3VDUAL
Connect to Overcurrent
of Power Distribution
Switch and Bypass
0.1uF to GND
N/C if not used

Module has integrated

PU resistor to
3.3VDUAL
Connect to Overcurrent
of Power Distribution
Switch and Bypass
0.1uF to GND
N/C if not used

Module has integrated

PU resistor to
3.3VDUAL
Connect to Overcurrent
of Power Distribution
Switch and Bypass
0.1uF to GND
N/C if not used
N/C
 Baseboard
Connect bypass 470pF
near connector and
100uF~150uF to power
distribution switch
Connect ESD
suppressors and 90Ω
@100MHz Common
Choke in series to
COME USBx-
Connect ESD
suppressors and 90Ω
@100MHz Common
Choke in series to
COME USBx+
Connect to GND

Baseboard
Connect bypass 470pF
near connector and
100uF~150uF to power
distribution switch
Connect ESD
suppressors and 90Ω
@100MHz Common
Choke in series to
COME USBx-
Connect ESD
suppressors and 90Ω
@100MHz Common
Choke in series to
COME USBx+

PU 4.7KΩ(NL) to 3.3V
and connect to ID of
USB OTG controller for
A plug from B plug
Identification
Host - Connect to GND
Client - Floating
Connect to GND

Baseboard
Connect bypass 470pF
near connector and
100uF~150uF to power
distribution switch
Connect ESD
suppressors and 90Ω
@100MHz Common
Choke in series to
COME USBx-
Connect ESD
suppressors and 90Ω
@100MHz Common
Choke in series to
COME USBx+
Connect to GND
Connect ESD
suppressors and 90Ω
@100MHz Common
Choke in series to
COME USB_SSRXx-
Connect ESD
suppressors and 90Ω
@100MHz Common
Choke in series to
COME USB_SSRXx+
Connect to GND
Connect ESD
suppressors and 90Ω
@100MHz Common
Choke in series to
COME USB_SSTXx-
Connect ESD
suppressors and 90Ω
@100MHz Common
Choke in series to
COME USB_SSTXx+
 Baseboard
Connect bypass 470pF
near connector and
100uF~150uF to power
distribution switch
Connect ESD
suppressors and 90Ω
@100MHz Common
Choke in series to
COME USBx-
Connect ESD
suppressors and 90Ω
@100MHz Common
Choke in series to
COME USBx+
Connect to GND
Connect ESD
suppressors and 90Ω
@100MHz Common
Choke in series to
COME USB_SSTXx-
Connect ESD
suppressors and 90Ω
@100MHz Common
Choke in series to
COME USB_SSTXx+
Connect to GND
Connect ESD
suppressors and 90Ω
@100MHz Common
Choke in series to
COME USB_SSRXx-
Connect ESD
suppressors and 90Ω
@100MHz Common
Choke in series to
COME USB_SSRXx+
 Pwr Rail /
Pin No. LVDS Flat Panel Pin Type Description Baseboard
Tolerance

Connect 100Ω
A71 LVDS_A0+ @100MHz Common
Choke in series to
Reciever - RXinO0+/-
with 100Ω termination
A72 LVDS_A0- Conn. - RXinO0+/-
N/C if not used

Connect 100Ω
A73 LVDS_A1+ @100MHz Common
Choke in series to
Reciever - RXinO1+/-
with 100Ω termination
A74 LVDS_A1- Conn. - RXinO1+/-
N/C if not used
O
LVDS LVDS Channel A differential pairs
LVDS
Connect 100Ω
A75 LVDS_A2+ @100MHz Common
Choke in series to
Reciever - RXinO2+/-
with 100Ω termination
A76 LVDS_A2- Conn. - RXinO2+/-
N/C if not used

Connect 100Ω
A78 LVDS_A3+ @100MHz Common
Choke in series to
Reciever - RXinO3+/-
with 100Ω termination
A79 LVDS_A3- Conn. - RXinO3+/-
N/C if not used
 Connect 100Ω
A81 LVDS_A_CK+ @100MHz Common
Choke in series to
O
LVDS LVDS Channel A differential clock Reciever - RXOC+/-
LVDS
with 100Ω termination
A82 LVDS_A_CK- Conn. - RXOC+/-
N/C if not used

Connect 100Ω
B71 LVDS_B0+ @100MHz Common
Choke in series to
Reciever - RXinE0+/-
with 100Ω termination
B72 LVDS_B0- Conn. - RXinE0+/-
N/C if not used

Connect 100Ω
B73 LVDS_B1+ @100MHz Common
Choke in series to
Reciever - RXinE1+/-
with 100Ω termination
B74 LVDS_B1- Conn. - RXinE1+/-
N/C if not used
O
LVDS LVDS Channel B differential pairs
LVDS
Connect 100Ω
B75 LVDS_B2+ @100MHz Common
Choke in series to
Reciever - RXinE2+/-
with 100Ω termination
B76 LVDS_B2- Conn. - RXinE2+/-
N/C if not used
 Connect 100Ω
B77 LVDS_B3+ @100MHz Common
Choke in series to
Reciever - RXinE3+/-
with 100Ω termination
B78 LVDS_B3- Conn. - RXinE3+/-
N/C if not used

Connect 100Ω
B81 LVDS_B_CK+ @100MHz Common
Choke in series to
O
LVDS LVDS Channel B differential clock Reciever - RXEC+/-
LVDS
with 100Ω termination
B82 LVDS_B_CK- Conn. - RXEC+/-
N/C if not used

Module has integrated

PD resistor to GND
O Connect to enable
A77 LVDS_VDD_EN 3.3V / 3.3V LVDS panel power enable
CMOS control of LVDS panel
power circuit.
N/C if not used

Module has integrated

PD resistor to GND
O Connect to enable
B79 LVDS_BKLT_EN 3.3V / 3.3V LVDS panel backlight enable
CMOS control of LVDS panel
backlight power circuit.
N/C if not used

Connect to brightness
O control of LVDS panel
B83 LVDS_BKLT_CTRL 3.3V / 3.3V LVDS panel backlight brightness control
CMOS backlight power circuit.
N/C if not used
 Module has integrated
PU resistor to 3.3V
I/O OD
A83 LVDS_I2C_CK 3.3V / 3.3V I2C clock output for LVDS display use Connect to DDC clock of
CMOS
LVDS panel
N/C if not used

Module has integrated

PU resistor to 3.3V
I/O OD
A84 LVDS_I2C_DAT 3.3V / 3.3V I2C data line for LVDS display use Connect to DDC data of
CMOS
LVDS panel
N/C if not used

4.3.10 LVDS Flat Panel

Low voltage differential signaling flat-panel interface. The Module pin-out allows one single channel display interfaces (1
pixel per clock) with up to 24 bits per color. Alternatively, one dual channel display (2 pixels per clock) with up to 24 bits per
color, 48 bits per clock is allowed. Includes panel backlight control and EDID support.
The LVDS A channel and the control signals are pin shared with eDP signals. Refer to Section 4.3.29 'eDP - Embedded
DisplayPort

4.4.3 LVDS
The LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-. LVDS_A_CK+/-, LVDS_B_CK+/-) shall have
100-ohm terminations across the pairs at the destination. This These terminations may be on the Carrier Board, if the
Carrier Board implements a LVDS de-serializer on-board.
Unused LVDS lines may be left open.

The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a
2.2kΩ resistor
• LVDS_I2C_CK
• LVDS_I2C_DAT

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 SOM-5894 A101-4
Baseboard

Connect 100Ω
@100MHz Common
Choke in series to
Reciever - RXinO0+/-
with 100Ω termination
Conn. - RXinO0+/-
N/C if not used

Connect 100Ω
@100MHz Common
Choke in series to
Reciever - RXinO1+/-
with 100Ω termination
Conn. - RXinO1+/-
N/C if not used

Connect 100Ω
@100MHz Common
Choke in series to
Reciever - RXinO2+/-
with 100Ω termination
Conn. - RXinO2+/-
N/C if not used

Connect 100Ω
@100MHz Common
Choke in series to
Reciever - RXinO3+/-
with 100Ω termination
Conn. - RXinO3+/-
N/C if not used
Connect 100Ω
@100MHz Common
Choke in series to
Reciever - RXOC+/-
with 100Ω termination
Conn. - RXOC+/-
N/C if not used

Connect 100Ω
@100MHz Common
Choke in series to
Reciever - RXinE0+/-
with 100Ω termination
Conn. - RXinE0+/-
N/C if not used

Connect 100Ω
@100MHz Common
Choke in series to
Reciever - RXinE1+/-
with 100Ω termination
Conn. - RXinE1+/-
N/C if not used

Connect 100Ω
@100MHz Common
Choke in series to
Reciever - RXinE2+/-
with 100Ω termination
Conn. - RXinE2+/-
N/C if not used
Connect 100Ω
@100MHz Common
Choke in series to
Reciever - RXinE3+/-
with 100Ω termination
Conn. - RXinE3+/-
N/C if not used

Connect 100Ω
@100MHz Common
Choke in series to
Reciever - RXEC+/-
with 100Ω termination
Conn. - RXEC+/-
N/C if not used

Connect to enable
control of LVDS panel
power circuit.
N/C if not used

Module has integrated

PD resistor to GND
Connect to enable
control of LVDS panel
backlight power circuit.
N/C if not used

Connect to brightness
control of LVDS panel
backlight power circuit.
N/C if not used
Module has integrated
PU resistor to 3.3V
Connect to DDC clock of
LVDS panel
N/C if not used

Module has integrated

PU resistor to 3.3V
Connect to DDC data of
LVDS panel
N/C if not used
 Pwr Rail /
Pin No. eDP Panel Pin Type
Tolerance

A71 eDP_TX2+

A72 eDP_TX2-

A73 eDP_TX1+

A74 eDP_TX1-

O AC coupled
PCIE off Module

A75 eDP_TX0+

A76 eDP_TX0-

A81 eDP_TX3+

A82 eDP_TX3-
 O
A77 eDP_VDD_EN 3.3V / 3.3V
CMOS

O
B79 eDP_BKLT_EN 3.3V / 3.3V
CMOS

O
B83 eDP_BKLT_CTRL 3.3V / 3.3V
CMOS

I/O AC coupled
A83 eDP_AUX+
PCIE off Module

I/O AC coupled
A84 eDP_AUX-
PCIE off Module

I
A87 eDP_HPD 3.3V / 3.3V
CMOS

The off Module AC coupling of the eDP signals makes dual LVDS/eDP Module implementations easier.

4.3.29 eDP - Embedded DisplayPort

Type 6 and Type 10 Modules allow the LVDS channel A signals (refer to Section 4.3.10 'LVDS Flat Panel') to be
alternatively used for embedded DisplayPort (eDP). The manner in which LVDS or eDP operation is chosen is vendor
dependent.
Table 4.35: Module and Carrier Combinations Type 6 and Type 10 Modules
Module Carrier / Panel Adapter Requirements
None -Straight through to eDP Header
eDP only
eDP only
N/A – not a valid combination
LVDS N/A – not a valid combination
only None -Straight through to LVDS receptacle
Dual None -Straight through to eDP receptacle
Mode None – Straight through to LVDS receptacle
Requirements
Module LVDS Channel A/eDP may support any combination of LVDS and eDP.
Module LVDS Channel A/eDP may support Dual Mode.
Module that support Dual-Mode shall implement the necessary muxing circuitry and control logic to ensure that the Module
works properly with Carriers expecting either eDP or LVDS.
Table 4.37: LVDS / eDP Pin Assignment

Type 6/10
Pin eDP Pin Name
Number

A71 eDP_TX2+ LVDS_A0+

A72 eDP_TX2- LVDS_A0-
A73 eDP_TX1+ LVDS_A1+
A74 eDP_TX1- LVDS_A1-
A75 eDP_TX0+ LVDS_A2+
A76 eDP_TX0- LVDS_A2-
A81 eDP_TX3+ LVDS_A_CK+
A82 eDP_TX3- LVDS_A_CK-
A77 eDP_VDD_EN LVDS_VDD_EN
B79 eDP_BKLT_EN LVDS_BKLT_EN
A83 eDP_AUX+ LVDS_I2C_CK
A84 eDP_AUX- LVDS_I2C_DAT
B83 eDP_BKLT_CTRL LVDS_BKLT_CTRL
A87 eDP_HPD RSVD

20-Pin 1 or 2 Lane eDP

Pwr Rail /
Pin Connector for CCFL Pin Type
Tolerance
Backlight

1 NC - Reserved
2 H_GND Power

I AC coupled
3 Lane1_N
DP off Module

I AC coupled
4 Lane1_P
DP off Module

5 H_GND Power
 I AC coupled
6 Lane0_N
DP off Module

I AC coupled
7 Lane0_P
DP off Module

8 H_GND Power

I AC coupled
9 AUX_CH_P
DP off Module

I AC coupled
10 AUX_CH_N
DP off Module

11 H_GND Power

12 LCD_VCC Power

13 LCD_VCC Power

14 LCD_Self_Test or NC
15 LCD_GND Power
16 LCD_GND Power

O
17 HPD 3.3V / 3.3V
CMOS

18 NC - Reserved

19 NC - Reserved

20 NC - Reserved
 30-Pin 1 or 2 Lane eDP
Pwr Rail /
Pin Connector for LED Pin Type
Tolerance
Backlight w/o Driver

1 NC - Reserved
2 H_GND Power

I AC coupled
3 Lane1_N
DP off Module

I AC coupled
4 Lane1_P
DP off Module

5 H_GND Power

I AC coupled
6 Lane0_N
DP off Module

I AC coupled
7 Lane0_P
DP off Module

8 H_GND Power

I AC coupled
9 AUX_CH_P
DP off Module

I AC coupled
10 AUX_CH_N
DP off Module

11 H_GND Power

12 LCD_VCC Power
13 LCD_VCC Power

14 LCD_Self_Test or NC
15 LCD_GND Power
16 LCD_GND Power

O
17 HPD 3.3V / 3.3V
CMOS

18 NC - Reserved

19 NC - Reserved

20 Vdc1

21 Vdc2

22 Vdc3

23 Vdc4

24 Vdc5

25 Vdc6
26 NC
27 Vdc

28 Vdc

29 Vdc

30 NC - Reserved

30-Pin 1 or 2 Lane eDP

Pwr Rail /
Pin Connector for LED Pin Type
Tolerance
Backlight with Driver

1 NC - Reserved
2 H_GND Power

I AC coupled
3 Lane1_N
DP off Module
 I AC coupled
4 Lane1_P
DP off Module

5 H_GND Power

I AC coupled
6 Lane0_N
DP off Module

I AC coupled
7 Lane0_P
DP off Module

8 H_GND Power

I AC coupled
9 AUX_CH_P
DP off Module

I AC coupled
10 AUX_CH_N
DP off Module

11 H_GND Power

12 LCD_VCC Power

13 LCD_VCC Power

14 LCD_Self_Test or NC
15 LCD_GND Power
16 LCD_GND Power
 O
17 HPD 3.3V / 3.3V
CMOS

18 BL_GND Power
19 BL_GND Power
20 BL_GND Power
21 BL_GND Power

I
22 BL_ENABLE 3.3V / 3.3V
CMOS

I
23 BL_PWM_DIM 3.3V / 3.3V
CMOS
24 NC - Reserved

25 NC - Reserved

26 BL_PWR Power

27 BL_PWR Power

28 BL_PWR Power

29 BL_PWR Power

30 NC - Reserved

40-Pin upto 4 Lane eDP

Pwr Rail /
Pin Connector for LED Pin Type
Tolerance
Backlight with Driver

1 NC - Reserved
2 H_GND Power

I AC coupled
3 Lane3_N
DP off Module
 I AC coupled
4 Lane3_P
DP off Module

5 H_GND Power

I AC coupled
6 Lane2_N
DP off Module

I AC coupled
7 Lane2_P
DP off Module

8 H_GND Power

I AC coupled
9 Lane1_N
DP off Module

I AC coupled
10 Lane1_P
DP off Module

11 H_GND Power

I AC coupled
12 Lane0_N
DP off Module

I AC coupled
13 Lane0_P
DP off Module

14 H_GND Power
 I AC coupled
15 AUX_CH_P
DP off Module

I AC coupled
16 AUX_CH_N
DP off Module

17 H_GND Power

18 LCD_VCC Power

19 LCD_VCC Power

20 LCD_VCC Power

21 LCD_VCC Power

22 LCD_Self_Test or NC
23 LCD_GND Power
24 LCD_GND Power
25 LCD_GND Power
26 LCD_GND Power

O
27 HPD 3.3V / 3.3V
CMOS

28 BL_GND Power
29 BL_GND Power
30 BL_GND Power
31 BL_GND Power

I
32 BL_ENABLE 3.3V / 3.3V
CMOS

I
33 BL_PWM_DIM 3.3V / 3.3V
CMOS
34 NC - Reserved
35 NC - Reserved

36 BL_PWR Power

37 BL_PWR Power

38 BL_PWR Power

39 BL_PWR Power

40 NC - Reserved

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 SOM-5894 A101-4
Description Baseboard
Baseboard
Connect AC Coupling
Capacitors 75~200 nF
near COME to eDP
Conn Lane2_P and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to eDP
Conn Lane2_N and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to eDP
Conn Lane1_P and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to eDP
Conn Lane1_N and ESD
protection
N/C if not used.
eDP differential pairs
Connect AC Coupling
Capacitors 75~200 nF
near COME to eDP
Conn Lane0_P and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to eDP
Conn Lane0_N and ESD
protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to eDP
Conn Lane3_P and ESD
protection N/C
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to eDP
Conn Lane3_N and ESD
protection
N/C if not used.
 Module has integrated
PD resistor to GND
Connect to enable
eDP power enable
control of eDP panel
power circuit.
N/C if not used

Module has integrated

PD resistor to GND
Connect to enable
eDP backlight enable
control of eDP panel
backlight power circuit.
N/C if not used

Connect to brightness
control of eDP panel
eDP backlight brightness control
backlight power circuit.
N/C if not used

Connect AC Coupling
Capacitors 75~200 nF
near COME to eDP
eDP AUX+
Conn AUX_CH_P and
ESD protection
N/C if not used.

Connect AC Coupling
Capacitors 75~200 nF
near COME to eDP
eDP AUX-
Conn AUX_CH_N and
ESD protection
N/C if not used.

Module has integrated

inverting level shifter
Detection of Hot Plug / Unplug and notification of and PD resistor to GND
N/C
the link layer Connect to eDP Conn
HPD
N/C if not used.

VDS/eDP Module implementations easier.

als (refer to Section 4.3.10 'LVDS Flat Panel') to be

ner in which LVDS or eDP operation is chosen is vendor

binations Type 6 and Type 10 Modules

Destination
eDP
 LVDS
eDP
LVDS
eDP
LVDS

of LVDS and eDP.

ry muxing circuitry and control logic to ensure that the Module

n Assignment

Pin Name

VDS_A0+
VDS_A0-
VDS_A1+
VDS_A1-
VDS_A2+
VDS_A2-
VDS_A_CK+
VDS_A_CK-
VDS_VDD_EN
VDS_BKLT_EN
VDS_I2C_CK
VDS_I2C_DAT
VDS_BKLT_CTRL
SVD

Description DisplayPort Baseboard

Designed by LCD
Reserved for LCD manufacturer’s use
requirement
High Speed Ground Connect to GND

Connect ESD protection

and AC Coupling
Complement Signal Link Lane 1 Capacitors 75~200 nF
near COME to COME
eDP_TX1-

Connect ESD protection

and AC Coupling
True Signal Link Lane 1 Capacitors 75~200 nF
near COME to COME
eDP_TX1+

High Speed Ground Connect to GND

 Connect ESD protection
and AC Coupling
Complement Signal Link Lane 0 Capacitors 75~200 nF
near COME to COME
eDP_TX0-

Connect ESD protection

and AC Coupling
True Signal Link Lane 0 Capacitors 75~200 nF
near COME to COME
eDP_TX0+

High Speed Ground Connect to GND

Connect ESD protection

and AC Coupling
True Signal Auxiliary Ch. Capacitors 75~200 nF
near COME to COME
eDP_AUX+

Connect ESD protection

and AC Coupling
Complement Signal Auxiliary Ch. Capacitors 75~200 nF
near COME to COME
eDP_AUX-

High Speed Ground Connect to GND

Connect to LCD logic
LCD logic and driver power and driver power by
LCD requirement
Connect to LCD logic
LCD logic and driver power and driver power by
LCD requirement
LCD Panel Self Test Enable (Optional) N/C
LCD logic and driver ground Connect to GND
LCD logic and driver ground Connect to GND

Module has integrated

inverting level shifter
HPD signal pin and PD resistor to GND
Connect to COME
eDP_HPD

Designed by LCD
Reserved for LCD manufacturer’s use
requirement
Designed by LCD
Reserved for LCD manufacturer’s use
requirement
Designed by LCD
Reserved for LCD manufacturer’s use
requirement
 Description DisplayPort Baseboard

Designed by LCD
Reserved for LCD manufacturer’s use
requirement
High Speed Ground Connect to GND

Connect ESD protection

and AC Coupling
Complement Signal Link Lane 1 Capacitors 75~200 nF
near COME to COME
eDP_TX1-

Connect ESD protection

and AC Coupling
True Signal Link Lane 1 Capacitors 75~200 nF
near COME to COME
eDP_TX1+

High Speed Ground Connect to GND

Connect ESD protection

and AC Coupling
Complement Signal Link Lane 0 Capacitors 75~200 nF
near COME to COME
eDP_TX0-

Connect ESD protection

and AC Coupling
True Signal Link Lane 0 Capacitors 75~200 nF
near COME to COME
eDP_TX0+

High Speed Ground Connect to GND

Connect ESD protection

and AC Coupling
True Signal Auxiliary Ch. Capacitors 75~200 nF
near COME to COME
eDP_AUX+

Connect ESD protection

and AC Coupling
Complement Signal Auxiliary Ch. Capacitors 75~200 nF
near COME to COME
eDP_AUX-

High Speed Ground Connect to GND

Connect to LCD logic
LCD logic and driver power and driver power by
LCD requirement
 Connect to LCD logic
LCD logic and driver power and driver power by
LCD requirement
LCD Panel Self Test Enable (Optional) N/C
LCD logic and driver ground Connect to GND
LCD logic and driver ground Connect to GND

Module has integrated

inverting level shifter
HPD signal pin and PD resistor to GND
Connect to COME
eDP_HPD

Designed by LCD
Reserved for LCD manufacturer’s use
requirement
Designed by LCD
Reserved for LCD manufacturer’s use
requirement
Designed by LCD
LED Cathode
requirement
Designed by LCD
LED Cathode
requirement
Designed by LCD
LED Cathode
requirement
Designed by LCD
LED Cathode
requirement
Designed by LCD
LED Cathode
requirement
Designed by LCD
LED Cathode
requirement
N/C
Designed by LCD
LED Anode
requirement
Designed by LCD
LED Anode
requirement
Designed by LCD
LED Anode
requirement
Designed by LCD
Reserved for LCD manufacturer’s use
requirement

Description DisplayPort Baseboard

Designed by LCD
Reserved for LCD manufacturer’s use
requirement
High Speed Ground Connect to GND

Connect ESD protection

and AC Coupling
Complement Signal Link Lane 1 Capacitors 75~200 nF
near COME to COME
eDP_TX1-
 Connect ESD protection
and AC Coupling
True Signal Link Lane 1 Capacitors 75~200 nF
near COME to COME
eDP_TX1+

High Speed Ground Connect to GND

Connect ESD protection

and AC Coupling
Complement Signal Link Lane 0 Capacitors 75~200 nF
near COME to COME
eDP_TX0-

Connect ESD protection

and AC Coupling
True Signal Link Lane 0 Capacitors 75~200 nF
near COME to COME
eDP_TX0+

High Speed Ground Connect to GND

Connect ESD protection

and AC Coupling
True Signal Auxiliary Ch. Capacitors 75~200 nF
near COME to COME
eDP_AUX+

Connect ESD protection

and AC Coupling
Complement Signal Auxiliary Ch. Capacitors 75~200 nF
near COME to COME
eDP_AUX-

High Speed Ground Connect to GND

Connect to LCD logic

LCD logic and driver power and driver power by
LCD requirement

Connect to LCD logic

LCD logic and driver power and driver power by
LCD requirement

LCD Panel Self Test Enable (Optional) N/C

LCD logic and driver ground Connect to GND
LCD logic and driver ground Connect to GND
 Module has integrated
inverting level shifter
HPD signal pin and PD resistor to GND
Connect to COME
eDP_HPD

Backlight ground Connect to GND

Backlight ground Connect to GND
Backlight ground Connect to GND
Backlight ground Connect to GND

Module has integrated

PD resistor to GND
Backlight On/Off
Connect to COME
eDP_BKLT_EN

Connect to COME
System PWM signal input for dimming
eDP_BKLT_CTRL
Designed by LCD
Reserved for LCD manufacturer’s use
requirement
Designed by LCD
Reserved for LCD manufacturer’s use
requirement
Connect to LCD
Backlight power backlight power by LCD
requirement
Connect to LCD
Backlight power backlight power by LCD
requirement
Connect to LCD
Backlight power backlight power by LCD
requirement
Connect to LCD
Backlight power backlight power by LCD
requirement
Designed by LCD
Reserved for LCD manufacturer’s use
requirement

Description DisplayPort Baseboard

Designed by LCD
Reserved for LCD manufacturer’s use
requirement
High Speed Ground Connect to GND

Connect ESD protection

and AC Coupling
Complement Signal Link Lane 3 Capacitors 75~200 nF
near COME to COME
eDP_TX3-
 Connect ESD protection
and AC Coupling
True Signal Link Lane 3 Capacitors 75~200 nF
near COME to COME
eDP_TX3+

High Speed Ground Connect to GND

Connect ESD protection

and AC Coupling
Complement Signal Link Lane 2 Capacitors 75~200 nF
near COME to COME
eDP_TX2-

Connect ESD protection

and AC Coupling
True Signal Link Lane 2 Capacitors 75~200 nF
near COME to COME
eDP_TX2+

High Speed Ground Connect to GND

Connect ESD protection

and AC Coupling
Complement Signal Link Lane 1 Capacitors 75~200 nF
near COME to COME
eDP_TX1-

Connect ESD protection

and AC Coupling
True Signal Link Lane 1 Capacitors 75~200 nF
near COME to COME
eDP_TX1+

High Speed Ground Connect to GND

Connect ESD protection

and AC Coupling
Complement Signal Link Lane 0 Capacitors 75~200 nF
near COME to COME
eDP_TX0-

Connect ESD protection

and AC Coupling
True Signal Link Lane 0 Capacitors 75~200 nF
near COME to COME
eDP_TX0+

High Speed Ground Connect to GND

 Connect ESD protection
and AC Coupling
True Signal Auxiliary Ch. Capacitors 75~200 nF
near COME to COME
eDP_AUX+

Connect ESD protection

and AC Coupling
Complement Signal Auxiliary Ch. Capacitors 75~200 nF
near COME to COME
eDP_AUX-

High Speed Ground Connect to GND

Connect to LCD logic
LCD logic and driver power and driver power by
LCD requirement
Connect to LCD logic
LCD logic and driver power and driver power by
LCD requirement
Connect to LCD logic
LCD logic and driver power and driver power by
LCD requirement
Connect to LCD logic
LCD logic and driver power and driver power by
LCD requirement
LCD Panel Self Test Enable (Optional) N/C
LCD logic and driver ground Connect to GND
LCD logic and driver ground Connect to GND
LCD logic and driver ground Connect to GND
LCD logic and driver ground Connect to GND

Module has integrated

inverting level shifter
HPD signal pin and PD resistor to GND
Connect to COME
eDP_HPD

Backlight ground Connect to GND

Backlight ground Connect to GND
Backlight ground Connect to GND
Backlight ground Connect to GND

Module has integrated

PD resistor to GND
Backlight On/0ff
Connect to COME
eDP_BKLT_EN

Connect to COME
System PWM signal input for dimming
eDP_BKLT_CTRL
Designed by LCD
Reserved for LCD manufacturer’s use
requirement
 Designed by LCD
Reserved for LCD manufacturer’s use
requirement
Connect to LCD
Backlight power backlight power by LCD
requirement
Connect to LCD
Backlight power backlight power by LCD
requirement
Connect to LCD
Backlight power backlight power by LCD
requirement
Connect to LCD
Backlight power backlight power by LCD
requirement
Designed by LCD
Reserved for LCD manufacturer’s use
requirement

VSB in S3,S4,S5
 Pwr Rail /
Pin No. Analog VGA Pin Type Description Baseboard
Tolerance

Module has integrated

PD 150Ω to GND
Connect to
1. 150Ω±1% resistor to
GND
2. 2-pole filter(10
O Red for monitor. Analog DAC output, designed to pF,bead 47 Ω
B89 VGA_RED Analog
Analog drive a 37.5Ω equivalent load. @100MHz and 22 pF)
3. ESD diode protection
connected to 3.3V or 5V.
4. VGA detection circuit
(Option for Intel).
to VGA Conn Pin 1 RED
N/C if not used
 Module has integrated
PD 150Ω to GND
Connect to
1. 150Ω±1% resistor to
GND
2. 2-pole filter(10
pF,bead 47 Ω
O Green for monitor. Analog DAC output, designed
B91 VGA_GRN Analog @100MHz and 22 pF)
Analog to drive a 37.5Ω equivalent load.
3. ESD diode protection
connected to 3.3V or 5V.
4. VGA detection circuit
(Option for Intel).
to VGA Conn Pin 2
GREEN
N/C if not used
 Module has integrated
PD 150Ω to GND
Connect to
1. 150Ω±1% resistor to
GND
2. 2-pole filter(10
pF,bead 47 Ω
O Blue for monitor. Analog DAC output, designed
B92 VGA_BLU Analog @100MHz and 22 pF)
Analog to drive a 37.5Ω equivalent load.
3. ESD diode protection
connected to 3.3V or 5V.
4. VGA detection circuit
(Option for Intel).
to VGA Conn Pin 3
BLUE
N/C if not used

Module has integrated

series resistor and
3.3V(5V alternative)
buffer
Connect
1. 27~39Ω in series
O
B93 VGA_HSYNC 3.3V / 3.3V Horizontal sync output to VGA monitor 2. Bypass
CMOS
33p~50pF(NL) to GND.
3. ESD diode protection
connected to 3.3V or 5V
to VGA Conn Pin 13
Hsync
N/C if not used
 Module has integrated
series resistor and
3.3V(5V alternative)
buffer
Connect
1. 27~39Ω in series
O
B94 VGA_VSYNC 3.3V / 3.3V Vertical sync output to VGA monitor 2. Bypass
CMOS
33p~50pF(NL) to GND.
3. ESD diode protection
connected to 3.3V or 5V
to VGA Conn Pin 14
Vsync
N/C if not used

Module has integrated

3.3V(5V alternative)
Voltage translation
I/O OD DDC clock line (I2C port dedicated to identify Connect to VGA Conn
B95 VGA_I2C_CK 3.3V / 3.3V
CMOS VGA monitor capabilities) Pin 15 SCL with ESD
diode to 3.3V or 5V near
connector
N/C if not used

Module has integrated

3.3V(5V alternative)
Voltage translation
I/O OD Connect to VGA Conn
B96 VGA_I2C_DAT 3.3V / 3.3V DDC data line.
CMOS Pin 12 SDA with ESD
diode to 3.3V or 5V near
connector.
N/C if not used
4.3.13 Analog VGA
Analog RGB interface for CRT monitor and DDC support.
4.4.2 Analog VGA
If analog VGA is used, the VGA_RED, VGA_GRN, and VGA_BLU signals shall each be terminated on the Carrier Board
through a 150 Ω resistor to ground. These resistors should be placed close to the VGA connector on the Carrier Board.
These lines may be left unterminated if the analog VGA function is not used.
The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a
2.2kΩ resistor
• VGA_I2C_CK
• VGA_I2C_DAT

Analog VGA Pwr Rail /

Pin No. Pin Type Description Analog VGA monitor
Connector Tolerance
 I 75Ω ±1% resistor to
1 RED 0.7 V p-p Red video
Analog GND

I 75Ω ±1% resistor to

2 GREEN 0.7 V p-p Green video
Analog GND
 I 75Ω ±1% resistor to
3 BLUE 0.7 V p-p Blue video
Analog GND

4 N/C Not connected N/C

5 GND Power Ground (HSync) Connect to GND
6 RED_RTN Power Red return Connect to GND
7 GREEN_RTN Power Green return Connect to GND
8 BLUE_RTN Power Blue return Connect to GND
Connect to power of
9 SENSE Power 5V +5 V DC from Baseboard
DDC circuit
10 GND Power Ground (VSync, DDC) Connect to GND
11 ID0 Monitor ID Bit 0 (optional)

I/O OD Connect to SDA of DDC

12 SDA 3.3V / 3.3V DDC data
CMOS circuit
 I Connect to Hsync of
13 Hsync 3.3V / 3.3V Horizontal sync
CMOS CRT circuit

I Connect to Vsync of
14 Vsync 3.3V / 3.3V Vertical sync
CMOS CRT circuit

I Connect to SCL of DDC

15 SCL 3.3V / 3.3V DDC clock
CMOS circuit

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 SOM-5894 A101-4
Baseboard

Module has integrated

PD 150Ω to GND
Connect to
1. 150Ω±1% resistor to
GND
2. 2-pole filter(10
pF,bead 47 Ω
@100MHz and 22 pF)
3. ESD diode protection
connected to 3.3V.
4. VGA detection circuit
(Option for Intel).
to VGA Conn Pin 1 RED
N/C if not used
Module has integrated
PD 150Ω to GND
Connect to
1. 150Ω±1% resistor to
GND
2. 2-pole filter(10
pF,bead 47 Ω
@100MHz and 22 pF)
3. ESD diode protection
connected to 3.3V.
4. VGA detection circuit
(Option for Intel).
to VGA Conn Pin 2
GREEN
N/C if not used
Module has integrated
PD 150Ω to GND
Connect to
1. 150Ω±1% resistor to
GND
2. 2-pole filter(10
pF,bead 47 Ω
@100MHz and 22 pF)
3. ESD diode protection
connected to 3.3V.
4. VGA detection circuit
(Option for Intel).
to VGA Conn Pin 3
BLUE
N/C if not used

Module has integrated

series resistor and 3.3V
buffer
Connect
1. 20Ω in series
2. Bypass
33p~50pF(NL) to GND.
3. ESD diode protection
connected to 3.3V with
bypass 0.1uF
to VGA Conn Pin 13
Hsync
N/C if not used
Module has integrated
series resistor and 3.3V
buffer
Connect
1. 20Ω in series
2. Bypass
33p~50pF(NL) to GND.
3. ESD diode protection
connected to 3.3V with
bypass 0.1uF
to VGA Conn Pin 14
Vsync
N/C if not used

Module has integrated

3.3V Voltage translation
Connect to VGA Conn
Pin 15 SCL with ESD
diode to 3.3V near
connector
N/C if not used

Module has integrated

3.3V Voltage translation
Connect to VGA Conn
Pin 12 SDA with ESD
diode to 3.3V near
connector.
N/C if not used
Baseboard
Connect to
1. VGA detection circuit
(Option for Intel).
2. ESD diode protection
connected to 3.3V.
3. 2-pole filter(10
pF,bead 47 Ω
@100MHz and 22 pF)
4. 150-Ω ±1% resistor to
GND
to COM1 Pin B89
VGA_RED

Connect to
1. VGA detection circuit
(Option for Intel).
2. ESD diode protection
connected to 3.3V.
3. 2-pole filter(10
pF,bead 47 Ω
@100MHz and 22 pF)
4. 150-Ω±1% resistor
to GND
to COM1 Pin B91
VGA_GRN
Connect to
1. VGA detection circuit
(Option for Intel).
2. ESD diode protection
connected to 3.3V.
3. 2-pole filter(10
pF,bead 47 Ω
@100MHz and 22 pF)
4. 150-Ω±1% resistor
to GND
to COM1 Pin B92
VGA_BLU

N/C
Connect to GND
Connect to GND
Connect to GND
Connect to GND
Connect 1A Polyswitch
in series to 5V
Connect to GND
N/C
Connect to COME Pin
B96 VGA_I2C_DAT and
ESD diode to 3.3V near
connector
Connect
1. Bypass
33p~50pF(NL) to GND.
2. 27~39Ω in series
to COME Pin B93
VGA_HSYNC

Connect
1. Bypass
33p~50pF(NL) to GND.
2. 27~39Ω in series
to COME Pin B94
VGA_VSYNC

Connect to COME Pin

B95 VGA_I2C_CK and
ESD diode to 3.3V near
connector
 Pwr Rail /
Pin No. TV Out Pin Type Description Baseboard
Tolerance

Module has integrated

PD 150Ω to GND
Connect
1. 150-Ω±1% resistor
to GND
2. 1-pole filter(6pF,bead
TVDAC Channel A Output supports the 150Ω @100MHz and
following: 6pF)
O Composite video: CVBS 3. ESD diode protection
B97 TV_DAC_A
Analog Component video: Chrominance (Pb) analog connected to 3.3V or 5V.
signal to
S-Video: not used Composite Video -
CVBS
Component Video -
Chrominance (Pb)
PD 150-Ω±1%
resistor to GND if not
used
 Module has integrated
PD 150Ω to GND
Connect
1. 150-Ω±1% resistor
to GND
2. 1-pole filter(6pF,bead
TVDAC Channel B Output supports the 150Ω @100MHz and
following: 6pF)
O
B98 TV_DAC_B Composite video: not used 3. ESD diode protection
Analog
Component video: Luminance (Y) analog signal. connected to 3.3V or 5V.
S-Video: Luminance analog signal. to
Component Video -
Luminance (Y)
S-Video - Luminance
PD 150-Ω±1%
resistor to GND if not
used
 Module has integrated
PD 150Ω to GND
Connect
1. 150-Ω±1% resistor
to GND
2. 1-pole filter(6pF,bead
TVDAC Channel C Output supports the 150Ω @100MHz and
following: 6pF)
O
B99 TV_DAC_C Composite video: not used 3. ESD diode protection
Analog
Component: Chrominance (Pr) analog signal. connected to 3.3V or 5V.
S-Video: Chrominance analog signal. to
Component Video -
Chrominance (Pr)
S-Video - Chrominance
PD 150-Ω±1%
resistor to GND if not
used

If TV Out is used, the TV_DAC_A, TV_DAC_B, and TV_DAC_C lines shall be terminated on the Carrier Board through a
150Ω resistor to ground. The termination resistors should be placed close to the external TV-Out connector(s). These
lines may be left un-terminated if the TV Out function is not used.
 Pwr Rail / Mini-DIN 4 TV
Pin No. S-Video Pin Type Description
Tolerance Connector
1 Y_RTN Power Y Return
2 C_RTN Power C Return

I
3 Y 1.1 V p-p Luminance analog signal.
Analog

I
4 C 1.1 V p-p Chrominance analog signal.
Analog
 S-Video+Composite Pwr Rail / Mini-DIN 7 TV
Pin No. Pin Type Description
video Tolerance Connector
1 Y_RTN Power Y Return
2 C_RTN Power C Return

I
3 Y 1.1 V p-p Luminance analog signal.
Analog
 I
4 C 1.1 V p-p Chrominance analog signal.
Analog

I
5 CVBS 1.3 V p-p CVBS
Analog

6 CVBS_RTN Power CVBS Return

7 No Connect Not connected
 Pwr Rail / Mini-DIN 7 TV
Pin No. Component video Pin Type Description
Tolerance Connector
1 Y_RTN Power Y Return
2 Pr_RTN Power Pr Return

I
3 Y 0.7 V p-p Luminance (Y) analog signal.
Analog

I
4 Pr 0.7 V p-p Chrominance (Pr) analog signal.
Analog
 I
5 Pb 0.7 V p-p Chrominance (Pb) analog signal
Analog

6 Pb_RTN Power Pb Return

7 No Connect Not connected

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 SOM-5894 A101-4
Baseboard

N/C, HDMI/DVI to TV
encoder like Chrotel
CH7105/7106 is
suggested.
N/C, HDMI/DVI to TV
encoder like Chrotel
CH7105/7106 is
suggested.
 Baseboard
Connect to GND
Connect to GND

Connect
1. ESD diode protection
connected to 3.3V
2. 1-pole filter(6pF,bead
150Ω @100MHz and
6pF)
3. 150-Ω±1% resistor
to GND
to COME pin B98
TV_DAC_B

Connect
1. ESD diode protection
connected to 3.3V
2. 1-pole filter(6pF,bead
150Ω @100MHz and
6pF)
3. 150-Ω±1% resistor
to GND
to COME pin B99
TV_DAC_C
 Baseboard
Connect to GND
Connect to GND

Connect
1. ESD diode protection
connected to 3.3V
2. 1-pole filter(6pF,bead
150Ω @100MHz and
6pF)
3. 150-Ω±1% resistor
to GND
to COME pin B98
TV_DAC_B
Connect
1. ESD diode protection
connected to 3.3V
2. 1-pole filter(6pF,bead
150Ω @100MHz and
6pF)
3. 150-Ω±1% resistor
to GND
to COME pin B99
TV_DAC_C

Connect
1. ESD diode protection
connected to 3.3V
2. 1-pole filter(6pF,bead
150Ω @100MHz and
6pF)
3. 150-Ω±1% resistor
to GND
to COME pin B99
TV_DAC_A

Connect to GND
N/C
 Baseboard
Connect to GND
Connect to GND

Connect
1. ESD diode protection
connected to 3.3V
2. 1-pole filter(6pF,bead
150Ω @100MHz and
6pF)
3. 150-Ω±1% resistor
to GND
to COME pin B98
TV_DAC_B

Connect
1. ESD diode protection
connected to 3.3V
2. 1-pole filter(6pF,bead
150Ω @100MHz and
6pF)
3. 150-Ω±1% resistor
to GND
to COME pin B99
TV_DAC_C
Connect
1. ESD diode protection
connected to 3.3V
2. 1-pole filter(6pF,bead
150Ω @100MHz and
6pF)
3. 150-Ω±1% resistor
to GND
to COME pin B99
TV_DAC_A

Connect to GND
N/C
 Pwr Rail /
Pin No. LPC Interface Pin Type Description Baseboard
Tolerance

Module has integrated

PU resistor to 3.3V
Connect to
B4 LPC_AD0
LPC - LAD0
FWH - Pin 13 LAD0
N/C if not used

Module has integrated

PU resistor to 3.3V
Connect to
B5 LPC_AD1
LPC - LAD1
FWH - Pin 14 LAD1
N/C if not used
I/O LPC multiplexed address, command and data
3.3V / 3.3V
CMOS bus
Module has integrated
PU resistor to 3.3V
Connect to
B6 LPC_AD2
LPC - LAD2
FWH - Pin 15 LAD2
N/C if not used

Module has integrated

PU resistor to 3.3V
Connect to
B7 LPC_AD3
LPC - LAD3
FWH - Pin 17 LAD3
N/C if not used
 Connect to
O LPC - LFRAME#
B3 LPC_FRAME# 3.3V / 3.3V LPC frame indicates the start of an LPC cycle
CMOS FWH - Pin 23 LFRAME#
N/C if not used

Module has integrated

PU resistor to 3.3V
B8 LPC_DRQ0# Connect to
LPC - LDRQ0#
N/C if not used
I
3.3V / 3.3V LPC serial DMA request
CMOS
Module has integrated
PU resistor to 3.3V
B9 LPC_DRQ1# Connect to
LPC - LDRQ1#
N/C if not used

Module has integrated

PU resistor to 3.3V
I/O
A50 LPC_SERIRQ 3.3V / 3.3V LPC serial interrupt Connect to
CMOS
LPC - SERIRQ
N/C if not used

Module has integrated

LPC clock output - 33MHz nominal
resistor in series.
Carrier Board LPC devices should be clocked
O Connect to
B10 LPC_CLK 3.3V / 3.3V with the LPC clock provided by the module
CMOS LPC - LCLK
interface. LPC clock length guidelines are the
FWH - Pin 31 LCLK
same as those for the PCI clock.
N/C if not used

4.3.11 LPC Interface

The LPC bus provides legacy I/O support on a Carrier Board via a Super I/O and system management devices.
 The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a
8.2kΩ resistor
• LPC_SERIRQ

5.6 Carrier Board LPC Devices

Carrier Board LPC devices should be clocked with the LPC clock provided by the module interface. LPC clock length
guidelines are the same as those for the PCI clock. If the Carrier Board has two loads on the LPC clock these loads
should be connected to the common clock without a buffer. The Carrier Board should not have more than two loads on
the LPC clock.
Carrier Board LPC devices should be reset with signal CB_RESET#.
A typical routing topology for a Module LPC device and two Carrier Board LPC devices clock is shown below. This
topology is used by Modules that start and stop the LPC clock on the fly. In this case, a buffer cannot be used and all LPC
devices must share a common clock.

Figure 5-95-11: Typical routing topology for a Module LPC device

LA 500 mils max
LB1 = LB2 = 150 mils max
LC1 = 8.88”+LC2
LC2 = .25” max
LE2 = 1” max
LD2 + LE2 (note 2 instances of LE2) = 8.88”
R1 = R2 = 22Ω

Pwr Rail /
Pin No. PLCC32 Socke Pin Type Description FWH
Tolerance

Block Erase/Program Power Supply. For

erasing array blocks or programming data. VPP =
3.3 V or 12 V VPP. With VPP ≤ VPPLK, memory
3.3V / contents cannot be altered. Attempting a block
1 VPP Power
3.3V erase or program with an invalid VPP will produce
spurious results and should not be attempted.
VPP may only be held at 12 V for 80 hours over
the lifetime of the device.

Interface Reset. Valid for Intel FWH interface

operation. When driven low, RST# inhibits write
operations to provide data protection during
I 3.3V / power transitions, resets internal
2 RST#
CMOS 3.3V automation, and tri-states pins FWH[3:0] (in Intel
FWH interface mode). RST#-high enables normal
operation. When exiting from reset, the device
defaults to read array mode.

3 FGPI3 Intel FWH General Purpose Inputs. These

individual inputs can be used for additional board
flexibility. The state of these pins can be read
4 FGPI2 immediately at boot, through Intel FWH registers.
I 3.3V / These inputs should be at their desired state
CMOS 3.3V before the start of the PCI clock cycle during
which the read is attempted, and they should
remain at the same level until the end of the read
cycle. They may only be used for 3.3-V signals.
Unused FGPI pins must not be floated.
 Intel FWH General Purpose Inputs. These
individual inputs can be used for additional board
flexibility. The state of these pins can be read
immediately at boot, through Intel FWH registers.
I 3.3V / These inputs should be at their desired state
CMOS 3.3V before the start of the PCI clock cycle during
5 FGPI1 which the read is attempted, and they should
remain at the same level until the end of the read
cycle. They may only be used for 3.3-V signals.
6 FGPI0 Unused FGPI pins must not be floated.

Write Protect. When low, prevents programming

or block erase to all but the highest addressable
block (0-6 in a 4-Mbit, 0-14 in an 8- Mbit
component), regardless of the state of the
I 3.3V /
7 WP# orresponding lock registers. WP#-high disables
CMOS 3.3V
hardware write protection for these blocks,
though register-based protection still applies. The
status of TBL# does not affect the status of block-
locking registers.

Top Block Lock. When low, it prevents

programming or block erase to the highest
addressable block (7 in a 4-Mbit, 15 in an 8-Mbit
I 3.3V / component), regardless of the state of the lock
8 TBL#
CMOS 3.3V register. TBL#-high hardware write protection for
the top block, though registerbased protection still
applies. The status of TBL# does not affect the
status of block-locking registers.

I 3.3V /
9 ID3 Identification Inputs. These four pins are part of
CMOS 3.3V
the mechanism that allows multiple parts to be
attached to the same bus. The strapping of these
pins is used to identify the component. The boot
I 3.3V / device must have ID[3:0] = 0000, and it is
10 ID2
CMOS 3.3V recommended that all subsequent devices use
sequential up-count strapping (0001,
0010,0011,...). These pins are pulled down with
internal resistors, with values between 20 and
100 kΩ, when in the Intel FWH mode. Any ID pins
pulled high will exhibit a leakage current of
approximately 200 µA. Any pins intended to be
low may be left to float. In a single Intel FWH
system, all may be left floating.
 Identification Inputs. These four pins are part of
the mechanism that allows multiple parts to be
attached to the same bus. The strapping of these
pins is used to identify the component. The boot
device must have ID[3:0] = 0000, and it is
recommended that all subsequent devices use
sequential up-count strapping (0001,
0010,0011,...). These pins are pulled down with
I 3.3V / internal resistors, with values between 20 and
11 ID1 100 kΩ, when in the Intel FWH mode. Any ID pins
CMOS 3.3V
pulled high will exhibit a leakage current of
approximately 200 µA. Any pins intended to be
low may be left to float. In a single Intel FWH
I 3.3V / system, all may be left floating.
12 ID0
CMOS 3.3V

I/O 3.3V /
13 FWH0 Intel FWH I/Os. I/O communication
CMOS 3.3V
I/O 3.3V /
14 FWH1 Intel FWH I/Os. I/O communication
CMOS 3.3V
I/O 3.3V /
15 FWH2 Intel FWH I/Os. I/O communication
CMOS 3.3V
16 GND Power Ground. Do not float any ground pins.
I/O 3.3V /
17 FWH3 Intel FWH I/Os. I/O communication
CMOS 3.3V
18 RFU
Reserved For Future Use. These pins are
19 RFU reserved for future generations of this product.
20 RFU They may be left disconnected or driven.
21 RFU If they are driven, the voltage levels should satisfy
VIH and VIL requirements.
22 RFU
I 3.3V /
23 FWH4 Intel FWH Input. Input communication
CMOS 3.3V

Processor Reset. This is a second reset pin for

in-system use. This pin is internally combined
with the RST# pin. If this pin or RST# is driven
I 3.3V /
24 INIT# low, identical operation is exhibited. This signal is
CMOS 3.3V
designed to be connected to the chipset INIT
signal (Max. voltage depends on the processor.
Do not use 3.3 V).
 Device Power Supply. Internal detection
automatically configures the device for optimized
read performance. Do not float any power pins.
3.3V / With VCC ≤ VLKO, all attempts to write to flash
25 VCC Power
3.3V memory are inhibited. Device operations at
invalid VCC voltages (see DC Characteristics)
produce spurious results and should not be
attempted.

26 GND Power Ground. Do not float any ground pins.

3.3V / Analog Power Supply. This supply should
27 VCCa Power
3.3V share the same systemsupply as VCC.

Analog Ground. Should be tied to same plane

28 GNDa Power
as GND.

Interface Configuration Pin. This pin

determines which interface is used to
communicate with the device. When it is held low,
the Intel FWH interface is enabled. When it is
held High, the A/A Mux interface is enabled. This
pin must be set at power-up or before return from
I 3.3V /
29 IC reset, and must not be changed during device
CMOS 3.3V
operation.
This pin is pulled down with an internal resistor of
between 20 and 100 kΩ. When the IC is High
(A/A Mux mode), this pin will exhibit a leakage
current of approximately 200 µA. This pin may be
floated, which will select the Intel FWH mode.

I 3.3V /
30 FGPI4 Intel FWH General Purpose Inputs.
CMOS 3.3V
 33-MHz Clock for Intel FWH Interface. This
I 3.3V /
31 CLK input is the same as that for the PCI clock and
CMOS 3.3V
adheres to the PCI specification.

Device Power Supply. Internal detection

automatically configures the device for optimized
read performance. Do not float any power pins.
3.3V / With VCC ≤ VLKO, all attempts to write to flash
32 VCC Power
3.3V memory are inhibited. Device operations at
invalid VCC voltages (see DC Characteristics)
produce spurious results and should not be
attempted.

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 SOM-5894 A101-4
Baseboard

Module has integrated

PU resistor to 3.3V
Connect to
LPC - LAD0
FWH - Pin 13 LAD0
N/C if not used

Module has integrated

PU resistor to 3.3V
Connect to
LPC - LAD1
FWH - Pin 14 LAD1
N/C if not used

Module has integrated

PU resistor to 3.3V
Connect to
LPC - LAD2
FWH - Pin 15 LAD2
N/C if not used

Module has integrated

PU resistor to 3.3V
Connect to
LPC - LAD3
FWH - Pin 17 LAD3
N/C if not used
Connect to
LPC - LFRAME#
FWH - Pin 23 LFRAME#
N/C if not used

Module has integrated

PU resistor to 3.3V
Connect to
LPC - LDRQ0#
N/C if not used

Module has integrated

PU resistor to 3.3V
Connect to
LPC - LDRQ1#
N/C if not used

Module has integrated

PU resistor to 3.3V
Connect to
LPC - SERIRQ
N/C if not used

Module has integrated

resistor in series.
Connect to
LPC - LCLK
FWH - Pin 31 LCLK
N/C if not used
 Baseboard

Connect to 3.3V

Connect to COME B50

CB_RESET#

PU 10KΩ to 3.3V

PU 10KΩ to 3.3V
PU 10KΩ to 3.3V

PU 10KΩ to 3.3V

PU 10KΩ to 3.3V

PU 10KΩ to 3.3V

PD 20~100KΩ to GND

PD 20~100KΩ to GND
PD 20~100KΩ to GND

PD 20~100KΩ to GND

Connect to COME B4
LPC_AD0
Connect to COME B5
LPC_AD1
Connect to COME B6
LPC_AD2
Connect to GND
Connect to COME B7
LPC_AD3
N/C
N/C
N/C
N/C
N/C
Connect to COME B3
LPC_FRAME#

Connect to COME B50

CB_RESET#
Connect to 3.3V

Connect to GND
Connect to 3.3V

PD 0Ω to GND or
connect 0Ω in series to
COME pin A34
BIOS_DIS0# for Module
BIOS disable.

PD 20~100KΩ to GND

PU 10KΩ to 3.3V
Connect to COME B10
LPC_CLK

Connect to 3.3V
 Pwr Rail /
Pin No. SPI Pin Type Description
Tolerance

O 3.3V Suspend / Chip select for Carrier Board SPI - may be

B97 SPI_CS#
CMOS 3.3V sourced from chipset SPI0 or SPI1

I 3.3V Suspend /
A92 SPI_MISO Data in to Module from Carrier SPI
CMOS 3.3V

O 3.3V Suspend /
A95 SPI_MOSI Data out from Module to Carrier SPI
CMOS 3.3V

O 3.3V Suspend /
A94 SPI_CLK Clock from Module to Carrier SPI
CMOS 3.3V

from Module – nominally 3.3V. The Module

3.3V Suspend / provide a minimum of 100mA on SPI_POW
A91 SPI_POWER O
3.3V Carriers shall use less than 100mA of
SPI_POWER. SPI_POWER

I Selection straps to determine the BIOS boo

A34 BIOS_DIS0# 3.3V / 3.3V
CMOS device

Selection straps to determine the BIOS boo

device.
I NA3.3V
B88 BIOS_DIS1# The Carrier should only float these or pull
CMOS Suspend / 3.3V
low, please refer to Table 4.13 for strapping
options of BIOS disable signals.

4.3.12 SPI Interface

SPI. The SPI bus is used to support a SPI-compatible flash devices. The SPI flash device can be up to 16 MB (128 Mb). T
bus is clocked at either 20 MHz, 25 MHz, 33 MHz or 50 MHz. SPI devices selected should support one of these frequenci
SPI support is introduced in COM.0 R2.0 for all Types.

The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 10
resistor
• BIOS_DISABLE#
When supporting Carrier Board based SPI devices, the SPI_MISO line shall have a series resistor of 33Ω.
 On COM.0 R1.0, there is a single pin dedicated to the BIOS Disable function. The pin is A34, named BIOS_DISABLE#. If
Carrier Board leaves BIOS_DISABLE# floating, then the Module boots from the BIOS on the Module. That Module BIOS c
on any bus the Module designer chooses (LPC, SPI, etc.). If the Carrier Board pulls BIOS_DISABLE# to GND, then the on
Module BIOS is disabled and the Module boots from a Carrier Board firmware hub on the LPC bus.
FromIn COM.0 R2.0, the Carrier based BIOS options have been expanded to support SPI devices. A second BIOS DISAB
pin (BIOS_DIS1#) has been added to allow for multiple Carrier implementations for external BIOS devices. The BIOS_DIS
pin has been renamed to BIOS_DIS0#. Additional pins have been added to bring the SPI signals to the Carrier. These pins
defined in Table 4.12 above.

The Table below allows for Carrier Board LPC FWH operation that is backward compatible with COM.0 Rev.1 Carriers. It
allows two Carrier SPI options: SPI0 on Carrier and SPI1 on the Module, or SPI0 on the Module and SP1 on the Carrier.
Table 4.13: Effect of the BIOS disable signals
Chipset SPI CS1# Chipset SPI CS0# Carrier SPI
BIOS_DIS1# BIOS_DIS0#
Destination Destination SPI_CS# Descriptor
1 1 Module Module High Module

1 0 Module Module High Module

0 1 Module Carrier SPI0 Carrier

0 0 Carrier Module SPI1 Module

The BIOS Entry point may be in SPI0 or SPI1 as determined by the descriptor table in the SPI0 device. The Module may
one or two SPI devices, or a FWH. Carrier Boards may have zero or one SPI device, and may have zero or one LPC FWH
With special circuitry on the Module it's possible to have a single SPI device, but allow the Module GBE, ME and Platform
to stay with the Module even in the case of a Carrier Board SPI BIOS entry per Ref Line 2 above. The Module SPI would in
a descriptor table, BIOS code, GBE parameters, ME parameters, and platform data. For table line entries 0 and 1 above, t
Module SPI device would be selected by SPI CS0# from the chipset. For table line entry 2 above, the Module SPI device w
be selected by chipset SPI CS1# instead of CS0#. This would be achieved by low cost circuitry on the Module. The Modul
device descriptor table and the Module BIOS code would be used in table line entries 0, 1 and 3.

An alternative arrangement would be to have two SPI devices on the Module. The descriptor table and the actual BIOS ar
SPI0, and that the GBE LAN data, ME data and platform data reside in SPI1. Then a Carrier Board SPI option is allowed (
line ref 2) in which the actual BIOS is on the Carrier, and the Module specific data stays with the Module in SPI1. The Mod
SPI1 device has to be write-enabled. The Carrier SPI0 device could be write protected if desired (as is the case in some
regulated industries such as casino gaming).
Note that in the case of the BIOS boot from Carrier FWH (table line ref 1), the module SPI devices are still enabled and ac
They are used by the GBE LAN hardware and the management engine.
They can keep the BIOS code as well, but it is not used. The ICH pin straps cause an LPC FWH BIOS boot.
SPI Power
Introducing a SPI_POWER pin is desirable because some Module implementations will have the SPI power domain in pow
state S0 and others in S5. It is easier for Carrier board designers to take the Carrier SPI power from a pin on the Module.
Module Vs Carrier Board Pull-ups
There shall not be any Carrier Board pull-ups or pull-downs on the seven SPI related signals. All such terminations shall
the Module. The Module designer shall determine the correct power domain that these signals are terminated to.

5.7 SPI Devices

All Module types may implement a SPI bus. The SPI bus is replacing the LPC bus for BIOS EEPROM devices. If a Module
supports an external BIOS is shall support an external SPI BIOS and may support an external LPC BIOS. The diagram be
depicts a typical SPI topology. Note that other SPI configurations are possible including Module or Carrier based CS1# SP
device. SeeRefer to Section 4.3.12 'SPI Interface' for other implementation options.
Figure 5-105-12: Typical SPI topology
(LA1 + LB1), (LA2 + LB2), (LA3 + LC3 + LB3), (LA4 + LB4) max length 2” match all within .1”
LD2, LD3, LD4, LD5 max length .25” (maximum stub length to COM.0 connector)
LE2, LE3, LE4, LE5 max length 4.5” match within .1”
(LA4 + LB4), (LA2 + LB2) match within .5” (match CLK & MOSI within .5” Module)
(LA4 + LD4), (LA2 + LD2) match within .4” (match CLK & MOSI within .5” Carrier Board)
(LA4 + LB4), (LA1 + LB1) match within .5” (match CLK & CS within .5” Module)
(LA4 + LD4), (LA1 + LA5) match within .4” (match CLK & CS within .5” Carrier Board)
R1 = 33Ω

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 SOM-5894 A101-4
Description Baseboard
Baseboard

Module has integrated Module has integrated

series resistor series resistor
or Carrier Board SPI - may be
Connect to SPI flash pin Connect to SPI flash pin
chipset SPI0 or SPI1
1 Chip Select 1 Chip Select
N/C if not used N/C if not used

Connect 15~33Ω in Connect 33Ω in series to

series to SPI flash pin 2 SPI flash pin 2 Serial
dule from Carrier SPI
Serial Output Output
N/C if not used N/C if not used
Connect 33~47 Ω in Connect 33Ω in series
series to SPI flash pin 5 to SPI flash pin 5 Serial
m Module to Carrier SPI
Serial Input Input
N/C if not used N/C if not used
Connect 33~47Ω in
Connect 33Ω in series to
series to SPI flash pin 6
odule to Carrier SPI SPI flash pin 6 Clock
Clock
N/C if not used
N/C if not used
– nominally 3.3V. The Module shall
Connect to SPI flash pin Connect to SPI flash pin
mum of 100mA on SPI_POWER.
8 VDD 8 VDD
l use less than 100mA of
N/C if not used N/C if not used
SPI_POWER shall only be used to

Module has integrated

Module has integrated
PU resistor to
PU resistor to 3.3V
3.3VDUAL
1 - N/C
aps to determine the BIOS boot 1 - N/C
0 - PD 1K to GND
0 - PD 1K to GND
BIOS options are shown
BIOS options are shown
in Table "Effect of the
in Table "Effect of the
BIOS disable signals"
BIOS disable signals"

Module has integrated

Module has integrated
PU resistor to
aps to determine the BIOS boot PU resistor to 3.3V
3.3VDUAL
1 - N/C
1 - N/C
hould only float these or pull them 0 - PD 1K to GND
0 - PD 1K to GND
fer to Table 4.13 for strapping BIOS options are shown
BIOS options are shown
OS disable signals. in Table "Effect of the
in Table "Effect of the
BIOS disable signals"
BIOS disable signals"

n be up to 16 MB (128 Mb). The SPI

upport one of these frequencies.

be pulled-up to 3.3V with a 10kΩ

esistor of 33Ω.
 , named BIOS_DISABLE#. If the
Module. That Module BIOS can be
ISABLE# to GND, then the on-
C bus.
evices. A second BIOS DISABLE
BIOS devices. The BIOS_DISABLE#
nals to the Carrier. These pins are

with COM.0 Rev.1 Carriers. It also

ule and SP1 on the Carrier.

Bios Entry Ref Line

SPI0/SPI1 0
Carrier FWH
1

SPI0/SPI1 2
SPI0/SPI1 3

PI0 device. The Module may have

ay have zero or one LPC FWH.
odule GBE, ME and Platform data
ove. The Module SPI would include
e line entries 0 and 1 above, the
bove, the Module SPI device would
try on the Module. The Module SPI
d 3.

r table and the actual BIOS are in

Board SPI option is allowed (table
the Module in SPI1. The Module
red (as is the case in some

evices are still enabled and active.

WH BIOS boot.

e the SPI power domain in power

er from a pin on the Module.

s. All such terminations shall be on

als are terminated to.

EEPROM devices. If a Module

nal LPC BIOS. The diagram below
ule or Carrier based CS1# SPI
 Pwr Rail /
Pin No. GPSI Pin Type
Tolerance

O
A98 SER0_TX 5V / 12V
CMOS

O
A101 SER1_TX 5V / 12V
CMOS
 I
A99 SER0_RX 5V / 12V
CMOS

I
A102 SER1_RX 5V / 12V
CMOS

These signals use reclaimed VCC_12V pins. SeeRefer to sectionSection 5.10 'Protecting COM.0 Pins Reclaimed From
the VCC_12V Pool' for additional design considerations
Different to Type 1-6 in Pin-out location and voltage levels

4.3.19 General Purpose Serial Interface

Two TTL level compatible two wire ports are available on Module Types 6 and 10. This feature is introduced in COM.0
Revision 2 and uses pins on the A-B connector that have been re-claimed from the A-B VCC_12V pool. As such, it is
possible that if a Type 6 or 10 Module is deployed in an Carrier Board for Module Types 1,2,3,4,5 then the Module TTL
level serial pins may be exposed to the 12V supply, and Module designers should plan for this.
Similarly, an R1.0 Module deployed on an R2.0 Carrier may bridge 12V to the serial pins and Carrier designers must
plan for this. These pins are designated SER0_TX, SER0_RX, SER1_TX and SER1_RX. Data out of the Module is on
the _TX pins. Hardware handshaking and hardware flow control are not supported.
Any of the Module asynchronous serial ports, if implemented on an Intel X86 architecture Module platform, shall be I/O
mapped serial ports that are register compatible with the National Semiconductor 16550 UARTs that were used in the
PC AT architecture.
The Module asynchronous serial ports are intended for general purpose use and for use with debugging software that
make use of the “console redirect” features available in many operating systems. The Module
asynchronous serial ports should not be implemented as USB peripherals, as such implementations are
generally not useful for low level debug purposes.
The serial ports, if implemented, shall support standard asynchronous serial port bit rates up to and
including 115.2 kbits/second.

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 SOM-5894 A101-4
Description Baseboard
Baseboard

Module has integrated Module has integrated

forward Schottky Diode forward Schottky Diode
Vf max = 0.6V in series. Vf max = 0.6V in series.
R1.0/R2.x Module both R1.0/R2.0 Module both
- Connect protection - Connect protection
scheme referred to scheme referred to
Figure 5-11 of COM.0 Figure 5-11 of COM.0
R2.0 or Figure 5-13 of R2.0 or Figure 5-13 of
COM.0 R2.1 Spec to COM.0 R2.1 Spec to
General purpose serial port transmitter
R2.x Module only - PD R2.0 Module only -
4.7K to GND and Connect with PD 47K to
connect to GND to
Device - TXD Device - TXD
COM DB-9 port - TxIN COM DB-9 port - TxIN
of Serial Transceiver of Serial Transceiver
and TxOUT to DB-9 pin and TxOUT to DB-9 pin
3 TXD 3 TXD
N/C if not used. N/C if not used.

Module has integrated Module has integrated

forward Schottky Diode forward Schottky Diode
Vf max = 0.6V in series. Vf max = 0.6V in series.
R1.0/R2.x Module both R1.0/R2.0 Module both
- Connect protection - Connect protection
scheme referred to scheme referred to
Figure 5-11 of COM.0 Figure 5-11 of COM.0
R2.0 or Figure 5-13 of R2.0 or Figure 5-13 of
COM.0 R2.1 Spec to COM.0 R2.1 Spec to
General purpose serial port transmitter
R2.x Module only - PD R2.0 Module only -
4.7K to GND and Connect with PD 47K to
connect to GND to
Device - TXD Device - TXD
COM DB-9 port - TxIN COM DB-9 port - TxIN
of Serial Transceiver of Serial Transceiver
and TxOUT to DB-9 pin and TxOUT to DB-9 pin
3 TXD 3 TXD
N/C if not used. N/C if not used.
 Module has integrated Module has integrated
PU 47KΩ to 5V and PU 47KΩ to 3.3V and
forward Schottky Diode forward Schottky Diode
Vf max = 0.6V in series. Vf max = 0.6V in series.
R1.0/R2.x Module both R1.0/R2.0 Module both
- Connect protection - Connect protection
scheme referred to scheme referred to
Figure 5-11 of COM.0 Figure 5-11 of COM.0
R2.0 or Figure 5-13 of R2.0 or Figure 5-13 of
General purpose serial port receiver
COM.0 R2.1 Spec to COM.0 R2.1 Spec to
R2.x Module only - R2.0 Module only -
Connect to Connect to
Device - RXD Device - RXD
COM DB-9 port - COM DB-9 port -
TxOUT of Serial TxOUT of Serial
Transceiver and TxIN to Transceiver and TxIN to
DB-9 pin 2 RXD DB-9 pin 2 RXD
N/C if not used. N/C if not used.

Module has integrated Module has integrated

PU 47KΩ to 5V and PU 47KΩ to 3.3V and
forward Schottky Diode forward Schottky Diode
Vf max = 0.6V in series. Vf max = 0.6V in series.
R1.0/R2.x Module both R1.0/R2.0 Module both
- Connect protection - Connect protection
scheme referred to scheme referred to
Figure 5-11 of COM.0 Figure 5-11 of COM.0
R2.0 or Figure 5-13 of R2.0 or Figure 5-13 of
General purpose serial port receiver
COM.0 R2.1 Spec to COM.0 R2.1 Spec to
R2.x Module only - R2.0 Module only -
Connect to Connect to
Device - RXD Device - RXD
COM DB-9 port - COM DB-9 port -
TxOUT of Serial TxOUT of Serial
Transceiver and TxIN to Transceiver and TxIN to
DB-9 pin 2 RXD DB-9 pin 2 RXD
N/C if not used. N/C if not used.

sectionSection 5.10 'Protecting COM.0 Pins Reclaimed From

e
 Module Types 6 and 10. This feature is introduced in COM.0
been re-claimed from the A-B VCC_12V pool. As such, it is
arrier Board for Module Types 1,2,3,4,5 then the Module TTL
Module designers should plan for this.
ay bridge 12V to the serial pins and Carrier designers must
_RX, SER1_TX and SER1_RX. Data out of the Module is on
control are not supported.
ted on an Intel X86 architecture Module platform, shall be I/O
National Semiconductor 16550 UARTs that were used in the

eneral purpose use and for use with debugging software that
any operating systems. The Module
USB peripherals, as such implementations are

synchronous serial port bit rates up to and

x.xVSB in S3,S4,S5
 Pwr Rail /
Pin No. CAN Bus Pin Type
Tolerance

O 3.3V / 3.3V
A101 CAN_TX
CMOS

I 3.3V / 3.3V
A102 CAN_RX
CMOS

4.3.30 CAN Bus

CAN Bus Operation Over SER1 Lines

The SER1_TX and SER1_RX asynchronous serial port lines defined for COM.0 Types 6 and 10 may be used
alternatively to carry CMOS 3.3V logic level CAN (Controller Area Network) bus signals from a COM Express Module
based CAN protocol controller. The CAN bus is an asynchronous, message based protocol widely used in the
automotive and industrial control sectors. It is defined by ISO 11519, ISO 11898, and SAEJ2411. Data rates on a CAN
bus may be as high as 1 MBit/s, although lower rates in the range from 10 kBit/s to 125 kBit/s are more common.
Use of the CAN bus in a COM Express system requires a CAN bus transceiver on the Carrier board to interface to the
CAN physical layer. CAN bus transceivers are available from NXP, Texas Instruments, Linear Technology, and others.

Data from the COM Express Module based CAN controller to the Carrier Board CAN transceiver is carried on Module
line SER1_TX. Data from the Carrier Board CAN transceiver to the COM Express Module based CAN controller is
carried on Module line SER1_RX. The Carrier Board CAN transceiver converts the logic level CAN protocol TX and RX
signals from the Module into a differential half duplex line per the CAN specification.
How the SER1 asynchronous lines are shared with CAN bus operation is Module vendor specific. A vendor may choose
to use the SER1 TX and RX lines to support asynchronous serial port operation, or CAN bus operation, or both, or
neither. Module build option(s) or software controlled muxing implementations may be used.

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 Description Baseboard

CAN (Controller Area Network) TX output for Connect to CAN Bus

CAN Bus channel 0. This pin is shared with transceiver transmit data
SER1_TX (refer to Section 4.3.19 'General input TXD pin
Purpose Serial Interface') N/C if not used
Connect to CAN Bus
RX input for CAN Bus channel 0. This pin is
transceiver receive data
shared with SER1_RX (refer to Section 4.3.19
output RXD pin
'General Purpose Serial Interface')
N/C if not used

nes defined for COM.0 Types 6 and 10 may be used

ler Area Network) bus signals from a COM Express Module
hronous, message based protocol widely used in the
SO 11519, ISO 11898, and SAEJ2411. Data rates on a CAN
he range from 10 kBit/s to 125 kBit/s are more common.
CAN bus transceiver on the Carrier board to interface to the
om NXP, Texas Instruments, Linear Technology, and others.

er to the Carrier Board CAN transceiver is carried on Module

ver to the COM Express Module based CAN controller is
N transceiver converts the logic level CAN protocol TX and RX
per the CAN specification.
bus operation is Module vendor specific. A vendor may choose
us serial port operation, or CAN bus operation, or both, or
ing implementations may be used.

x.xVSB in S3,S4,S5
Pin No. Miscellaneous Pin Type Pwr Rail / Tolerance Description Baseboard

Module has integrated

PU resistor to
3.3VDUAL
3.3VSB I2C device -
Connect to SCL of I2C
device
3.3V I2C device -
Connect 3.3V isolation
circuit controlled by
COME pin B24
PWR_OK to SCL of I2C
I/O OD 3.3V / 3.3V
B33 I2C_CK General purpose I2C port clock output device.
CMOS 3.3V Suspend/ 3.3V
5VSB I2C device -
Connect 5VSB Level
Shifter to SCL of I2C
device
5V I2C device -
Connect an 5V isolation
circuit controlled by
COME pin B24
PWR_OK to SCL of I2C
device.
N/C if not used
 Module has integrated
PU resistor to
3.3VDUAL
3.3VSB I2C device -
Connect to SDA of I2C
device
3.3V I2C device -
Connect 3.3V isolation
circuit controlled by
COME pin B24
PWR_OK to SDA of I2C
I/O OD 3.3V / 3.3V
B34 I2C_DAT General purpose I2C port data I/O line device
CMOS 3.3V Suspend/ 3.3V
5VSB I2C device -
Connect 5VSB Level
Shifter to SDA of I2C
device
5V I2C device -
Connect an 5V isolation
circuit controlled by
COME pin B24
PWR_OK to SDA of I2C
device
N/C if not used

Module has integrated

Output for audio enunciator - the "speaker" in
PD resistor to GND
O PC-AT systems
B32 SPKR 3.3V / 3.3V Connect to Speaker
CMOS This port provides the PC beep signal and is
circuit.
mostly intended for debugging purposes.
N/C if not used
 PD 0Ω to GND or
Module BIOS disable input. Pull low to disable connect 0Ω in series to
I
A34 BIOS_DISABLE# 3.3V / 3.3V module BIOS. Used to allow off-module BIOS pin 28 of FWH to disable
CMOS
implementations. Module BIOS
N/C if not used

Module has integrated

Input to module from (optional) external
PU resistor to 3.3V
I keyboard controller that can force a reset. Pulled
A86 KBD_RST# 3.3V / 3.3V Connect to SIO or KBC
CMOS high on the module. This is a legacy artifact of the
KBRST#
PC-AT.
N/C if not used

Input to module from (optional) external

Module has integrated
keyboard controller that can be used to control
PU resistor to 3.3V
I the CPU A20 gate line. The A20GATE restricts
A87 KBD_A20GATE 3.3V / 3.3V Connect to SIO or KBC
CMOS the memory access to the bottom megabyte and
A20_GATE#
is a legacy artifact of the PC-AT. Pulled low high
N/C if not used
on the module.
Output indicating that a watchdog time-out event Connect to Watchdog
O
B27 WDT 3.3V / 3.3V has occurred. Refer to Section 5.9 'Watchdog trigger input.
CMOS
Timer' on page 96124 for details. N/C if not used
 Module has integrated
PU 10KΩ to 3.3V and
forward Schottky Diode
Vf max = 0.6V in series.
R1.0/R2.x Module both
- Connect protection
scheme referred to
Figure 5-11 of COM.0
R2.0 or Figure 5-13 of
Fan speed control. Uses the Pulse Width
O OD COM.0 R2.1 Spec to
B101 FAN_PWMOUT* 3.3V / 12V Modulation (PWM) technique to control the fan’s
CMOS FAN connector pin 2
RPM.
PWMOUT via Smart
FAN circuit
R2.x Module only - PD
4.7K to GND and
connect to FAN
connector pin 2
PWMOUT via Smart
FAN circuit
N/C if not used
 Module has integrated
PU 47KΩ to 3.3V and
forward Schottky Diode
Vf max = 0.6V in series.
R1.0/R2.x Module both
- Connect protection
scheme referred to
Figure 5-11 of COM.0
I OD Fan tachometer input for a fan with a two pulse R2.0 or Figure 5-13 of
B102 FAN_TACHIN* 3.3V / 12V
CMOS output. COM.0 R2.1 Spec to
FAN connector pin 3
TACHIN via Smart FAN
circuit
R2.x Module only -
Connect to FAN
connector pin 3 TACHIN
via Smart FAN circuit
N/C if not used

Physical Absence -
Trusted Platform Module (TPM) Physical
N/C
I Presence pin. Active high. TPM chip has an
A96 TPM_PP* 3.3V / 12V Physical Presence -
CMOS internal pull down. This signal is used to indicate
PU 1KΩ to 3.3V
Physical Presence to the TPM.
N/C if not used

Module has integrated

System Management Interrupt: This signal is PU resistor to 3.3V.
I
A52 SMI# 3.3V / 3.3V generated by the external system management Connect to SMI output
CMOS
controller of device.
N/C if not used
 Module has integrated
PU resistor to
Active Low Interrupt Pin. Signals Host that there
3.3VDUAL
I has been a change of status in battery or AC
B96 BATT_ALERT# 3.3V Suspend / 3.3V Connect to
CMOS presence. Also used to indicate charging status of
SMBALERT# of battery
Battery
charger.
N/C if not used.
*These signals use reclaimed VCC_12V pins. See 'Protecting COM.0 Pins Reclaimed From the VCC_12V Pool' for additional design
considerations

O This clock is an output of the RTC generator

SUSCLK 3.3V / 3.3V Suspend N/A
CMOS circuit to use by other chips for refresh clock.

4.3.20 I2C Bus

The I2C port shall be available in addition to the SMBus. The I2C clock shall support 100kHz and should support 400kHz
operation. The maximum capacitance on the Carrier Board shall benot exceed 100pF. The I2C interface should support multi-
master operation.10 This capability will allow a cCarrier to read an option Module EEPROM before powering up the mModule.
Revision 1.0 of the specification placed the I2C interface on the non-standby power domain. With this connection, the I2C interface
can only be used when the mModule is powered on.

Since the I2C interface is used to connect to an optional Carrier EEPROM and since it is desirable to allow a mModule based board
controller access to the optional Carrier EEPROM before the mModule is powered on, revision 2.0 of this specification changes the
power domain of the I2C interface to standby-power allowing access during power down and suspend states. There is a possible
leakage issue that can arise when using a R2.0 mModule with a R1.0 cCarrier that supports I2C devices. The R1.0 cCarrier will
power any I2C devices from the non-standby power rail. A R2.0 mModule will pull-up the I2C clock and data lines to the standby-rail
through a 2.2K resistor. The difference in the power domains on the mModule and cCarrier can provide a leakage path from the
standby power rail to the non-standby power rail. This leakage can be minimized if the mModule drives the I2C lines low when the
mModule is in a suspend state and the I2C interface is not in use.
I2C multi-master support starts with COM Express® Rev. 2.0
The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 2.2kΩ
resistor
• I2C_CK
• I2C_DAT
4.3.21 Miscellaneous
These signals FAN_PWMOUT, FAN_TACHIN use reclaimed VCC_12V pins. SeeRefer to sSection 5.10 'Protecting COM.0 Pins
Reclaimed From the VCC_12V Pool' for additional design considerations
The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 10kΩ
resistor
• KBD_A20GATE
• KBD_RST#
• FAN_TACHIN

Modules implementing a TPM shall pull down TPM_PP. The value of the pull down resistor will be module specific. Carries that
support TPM should tie this signal to 3.3V when TPM features that require physical presence should be activated.
5.85.9 Watchdog Timer
COM Express® modules may implement a watchdog timer output to the Carrier Board. If the watchdog timer (WDT) is implemented,
it should have the characteristics described below.
5.8.15.9.1 Output Options and Characteristics

The watchdog should implement the following output options:

• Reset: the module shall reset. Module pins PCI_RST# , IDE_RST# and CB_RESET# shall be pulsed low. The module WDT pin
goes high until the unit resets.
• NMI (non-maskable interrupt) is generated. The module WDT pin goes high and stays high until cleared by software.
• Output to module WDT pin only. The WDT pin stays high until cleared by software.
• Disabled: the module WDT pin is driven low.

The above output options may be realized by software configurable hardware or by module build options. The watchdog output
shall come up as a logic low and shall be disabled upon power-on-reset (VCC_12V power cycle) or external system reset (when
SYS_RST# pin is toggled low by external hardware). The watchdog may be enabled by BIOS or system software. If the watchdog is
enabled and times out, the module WDT pin shall be driven to a logic high level and shall remain high for at least one microsecond.

The support of a watch dog timer on the Module is optional. If a Module supports a watchdog timer it shall minimally support output
mode 1 and may also support output modes 2 or 3 as defined below. The selection of the output modes may be realized by
software configurable hardware or by Module build options.
Table 5.185.20: Watchdog Timer Output Modes
Output Mode Description
The Module generates an internal reset. Module pins PCI_RST#, IDE_RST, and
1 CB_RESET# that are supported are pulsed low. WDT pin is driven high until the unit resets.

2 The Module only drives WDT pin high until cleared by Module software.
3 The Module generates an NMI. WDT pin is driven high until cleared by Module software.

The watchdog output shall come up as a logic low and shall be disabled upon power-onreset (VCC_12V power cycle) or external
system reset (when SYS_RST# pin is toggled low by external hardware). The watchdog may be enabled by BIOS or system
software.
5.8.25.9.2 Watchdog Enable and Strobe
Typically, the watchdog parameters (output options, enabling, enable delay, timeout delay) are managed by the module BIOS, often
via a BIOS setup screen. The regular watchdog strobes to prevent a watchdog timeout are typically handled by the module’s
application software. There may be BIOS abstractions to isolate the application software from the watchdog hardware.
The software programmable Watchdog Enable Delay is the time between when the watchdog is enabled by firmware and when the
first watchdog strobe is needed to prevent a watchdog time out. The enable delay allows time for the operating system to boot and
the application to load and initialize.
After the initial Enable Delay, the enabled watchdog must be periodically strobed by software to prevent a watchdog timeout. The
Strobe Interval shall be software programmable.
Recommended ranges in enable delay and max strobe periods are given in the following table.

Table 5-235.195.21: Watchdog Enable and Strobe Parameter Range

Min Value Max Value
Enable Delay 1 second 10 minutes
Strobe Interval 0.1 second 10 minutes

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 SOM-5894 A101-4
Baseboard

Module has integrated

PU resistor to
3.3VDUAL
3.3VSB I2C device -
Connect to SCL of I2C
device
3.3V I2C device -
Connect 3.3V isolation
circuit controlled by
COME pin B24
PWR_OK to SCL of I2C
device.
5VSB I2C device -
Connect 5VSB Level
Shifter to SCL of I2C
device
5V I2C device -
Connect an 5V isolation
circuit controlled by
COME pin B24
PWR_OK to SCL of I2C
device.
N/C if not used
Module has integrated
PU resistor to
3.3VDUAL
3.3VSB I2C device -
Connect to SDA of I2C
device
3.3V I2C device -
Connect 3.3V isolation
circuit controlled by
COME pin B24
PWR_OK to SDA of I2C
device
5VSB I2C device -
Connect 5VSB Level
Shifter to SDA of I2C
device
5V I2C device -
Connect an 5V isolation
circuit controlled by
COME pin B24
PWR_OK to SDA of I2C
device
N/C if not used

Module has integrated

PD resistor to GND after
CB_RESET# asserts.
Connect to Speaker
circuit.
N/C if not used
Module has integrated
PU resistor to
3.3VDUAL
1 - N/C
0 - PD 1K to GND
BIOS options are shown
in Table "Effect of the
BIOS disable signals"

N/C, KBD_RST# if R240

is stuffed on the Module

N/C

Connect to Watchdog
trigger input.
N/C if not used
Module has integrated
PU 10KΩ to 3.3V and
forward Schottky Diode
Vf max = 0.6V in series.
R1.0/R2.0 Module both
- Connect protection
scheme referred to
Figure 5-11 of COM.0
R2.0 or Figure 5-13 of
COM.0 R2.1 Spec to
FAN connector pin 2
PWMOUT via Smart
FAN circuit
R2.0 Module only - PD
4.7K to GND. Connect
to FAN connector pin 2
PWMOUT via Smart
FAN circuit
N/C if not used
Module has integrated
PU 47KΩ to 3.3V and
forward Schottky Diode
Vf max = 0.6V in series.
R1.0/R2.0 Module both
- Connect protection
scheme referred to
Figure 5-11 of COM.0
R2.0 or Figure 5-13 of
COM.0 R2.1 Spec to
FAN connector pin 3
TACHIN via Smart FAN
circuit
R2.0 Module only -
Connect to FAN
connector pin 3 TACHIN
via Smart FAN circuit
N/C if not used

Physical Absence -
N/C
Physical Presence -
PU 1KΩ to 3.3V
N/C if not used

N/C
N/C
 Module Type Pwr Rail /
Pin No. Pin Type Description
Definition Tolerance

C54 TYPE0#

The TYPE pins indicate to the Carrier Board the Pin-out Type that is
implemented on the module. The pins are tied on the module to either ground
(GND) or are no-connects (NC). For Pin-out Type 1 and Type 10, these pins are
don’t care (X).
TYPE2# TYPE1# TYPE0#
X X X Pin-out Type 1 and Type 10
NC NC NC Pin-out Type 2
NC NC GND Pin-out Type 3 (no IDE)
PDS
C57 TYPE1# NC GND NC Pin-out Type 4 (no PCI)
NC GND GND Pin-out Type 5 (no IDE, no PCI)
GND NC NC Pin-out Type 6 (no IDE, no PCI)

The Carrier Board should implement combinatorial logic that monitors the
module TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for
an ATX power supply) if an incompatible Module pin-out type is detected. The
Carrier Board logic may also implement a fault indicator such as an LED.

D57 TYPE2#
 Dual use pin. Indicates to the Carrier Board that a Type 10 Module is installed.
Indicates to the Carrier that a Rev 1.0/2.0 Module is installed

TYPE10#
NC Pin-out R2.0
PD Pin-out Type 10 pull down to ground with 4.747KΩ resistor
A97 TYPE10# PDS 12V Pin-out R1.0

This pin is reclaimed from the VCC_12V pool. In R1.0 Modules this pin will
connect to other VCC_12V pins. In R2.0 this pin is defined as a no connect for
types 1-6. A Carrier can detect a R1.0 Module by the presence of 12V on this
pin. R2.0 Module types 1-6 will no connect this pin. Type 10 Modules shall pull
this pin to ground through a 4.747K resistor.

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 SOM-5894 A101-4
Baseboard
Baseboard

PU 47KΩ to 3.3VSB or
5VSB and connects to PU 47KΩ to 3.3VSB or
Module type detective 5VSB and connects to
circuit Module type detective
High - Pin-out Type 1 or circuit
Type 2 or Type 6 or High - Pin-out Type 6
Type 10 Low - Keep power off
Low - Keep power off N/C if Module type you
N/C if Module type you selects is fixed.
selects is fixed.

PU 47KΩ to 3.3VSB or
5VSB and connects to PU 47KΩ to 3.3VSB or
Module type detective 5VSB and connects to
circuit Module type detective
High - Pin-out Type 1 or circuit
Type 2 or Type 6 or High - Pin-out Type 6
Type 10 Low - Keep power off
Low - Keep power off N/C if Module type you
N/C if Module type you selects is fixed.
selects is fixed.

PU 47KΩ to 3.3VSB or
PU 47KΩ to 3.3VSB or
5VSB and connects to
5VSB and connects to
Module type detective
Module type detective
circuit
circuit
High - Pin-out Type 1 or
High - Keep power off
Type 2 or Type 10
Low - Pin-out Type 6
Low - Pin-out Type 6
N/C if Module type you
N/C if Module type you
selects is fixed.
selects is fixed.
Pin-out R1.0 - Connect
to 12V
Pin-out R2.0 - PU 47 PU 47KΩ to 3.3VSB or
470KΩ to 3.3VSB or 5VSB and connects to
5VSB and connects to Module type detective
Module type detective circuit
circuit High - Pin-out Type 6
High - Pin-out Type 1 Low - Keep power off
or Type 2 or Type 6 N/C if Module type you
Low - Pin-out Type 10 selects is fixed.
N/C if Module type you
selects is fixed.
 Pwr Rail /
Pin No. General Purpose I/O Pin Type Description Baseboard
Tolerance

Module has integrated

PU resistor to 3.3V
Connect to GPO0
F75111 - F75111R pin
General purpose output pins. Upon a hardware
23 or F75111N pin 20
reset, these outputs should be low.
GPIO24
A93 GPO0 From COM-Express Extension Spec V0.7, this
EC IT8516E - pin 25
pin is also recommended to be used as LID
GPA1
function and announce PME to system.
EC IT8518E - pin 119
GPC0
in Module
N/C if not used.

Module has integrated

PU resistor to 3.3V
Connect to GPO1
F75111 - F75111R pin
22 or F75111N pin 19
GPIO25
B54 GPO1
EC IT8516E - pin 95
GPH2
EC IT8518E - pin 87
GPF2
in Module
N/C if not used.
3.3V /
O CMOS
3.3V

General purpose output pins. Upon a hardware

reset, these outputs should be low.
 3.3V /
O CMOS
3.3V
Module has integrated
PU resistor to 3.3V
Connect to GPO2
F75111 - F75111R pin
21 or F75111N pin 18
General purpose output pins. Upon a hardware GPIO26
B57 GPO2
reset, these outputs should be low. EC IT8516E - pin 94
GPH1
EC IT8518E - pin 88
GPF3
in Module
N/C if not used.

Module has integrated

PU resistor to 3.3V
Connect to GPO3
F75111 - F75111R pin
20 or F75111N pin 17
GPIO27
B63 GPO3
EC IT8516E - pin 93
GPH0
EC IT8518E - pin 56
GPC3
in Module
N/C if not used.
 Module has integrated
PU resistor to 3.3V
Connect to GPI0
F75111 - F75111R pin 6
General purpose input pins. Pulled high internally
or F75111N pin 6
on the module.
GPIO20
A54 GPI0 From COM-Express Extension Spec V0.7, this
EC IT8516E - pin 48
pin is also recommended to be used as external
GPD7
fan control.
EC IT8518E - pin 120
GPC4
in Module
N/C if not used.

Module has integrated

PU resistor to 3.3V
Connect to GPI1
F75111 - (F75111R pin
7 or F75111N pin 7
GPIO21
A63 GPI1
EC IT8516E - pin 29
GPA3
EC IT8518E - pin 57
GPC5
in Module
N/C if not used.
3.3V /
I CMOS
3.3V

General purpose input pins. Pulled high internally

on the module.
 3.3V /
I CMOS
3.3V
Module has integrated
PU resistor to 3.3V
Connect to GPI2
F75111 - F75111R pin 8
or F75111N pin 8
General purpose input pins. Pulled high internally GPIO22
A67 GPI2
on the module. EC IT8516E - pin 28
GPA2
EC IT8518E - pin 124
GPC6
in Module
N/C if not used.

Module has integrated

PU resistor to 3.3V
Connect to GPI3
F75111 - F75111R pin
24 or F75111N pin 21
GPIO23
A85 GPI3
EC IT8516E - pin 107
GPG1
EC IT8518E - pin 16
GPC7
in Module
N/C if not used.

4.3.25 General Purpose Input Output

GPI and GPO pins may be implemented as GPIO (Module specific). GPI and GPO pins may be implemented as
SDIO.(refer to Section 4.3.26 'SDIO'). If SDIO is supported the BIOS may be used to set the default state (SDIO or
GPIO) of the GPIO.

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 SOM-5894 A101-4
Baseboard

Module has integrated

PU resistor to
3.3VDUAL
Connect to GPO0
EC IT8518E - pin 119
GPC0
in Module
N/C if not used.

Module has integrated

PU resistor to
3.3VDUAL
Connect to GPO1
EC IT8518E - pin 87
GPF2
in Module
N/C if not used.
Module has integrated
PU resistor to
3.3VDUAL
Connect to GPO2
EC IT8518E - pin 88
GPF3
in Module
N/C if not used.

Module has integrated

PU resistor to
3.3VDUAL
Connect to GPO3
EC IT8518E - pin 56
GPC3
in Module
N/C if not used.
Module has integrated
PU resistor to
3.3VDUAL
Connect to GPI0
EC IT8518E - pin 120
GPC4
in Module
N/C if not used.

Module has integrated

PU resistor to
3.3VDUAL
Connect to GPI1
EC IT8518E - pin 57
GPC5
in Module
N/C if not used.
Module has integrated
PU resistor to
3.3VDUAL
Connect to GPI2
EC IT8518E - pin 124
GPC6
in Module
N/C if not used.

Module has integrated

PU resistor to
3.3VDUAL
Connect to GPI3
EC IT8518E - pin 16
GPC7
in Module
N/C if not used.
 Pwr Rail /
Pin No. SDIO Pin Type
Tolerance

I 3.3V / 3.3V
B63 SDIO_CD#
CMOS

O 3.3V / 3.3V
A93 SDIO_CLK
CMOS

O 3.3V / 3.3V
B54 SDIO_CMD
CMOS

IO 3.3V / 3.3V
B57 SDIO_WP
CMOS

A54 SDIO_DAT0

A63 SDIO_DAT1

IO 3.3V / 3.3V
CMOS
 IO 3.3V / 3.3V
CMOS

A67 SDIO_DAT2

A85 SDIO_DAT3

4.3.26 SDIO
Support for an SDIO interface is optional and added in R2.0. The SDIO signals are piggybacked on the existing COM.0
General Purpose IO (GPIO) signals. (refer to Section 4.3.25 'General Purpose Input Output'). The signal mapping is such that
SDIO card inputs connect to GPI and SDIO card outputs connect to GPO. With this mapping, any combination of Module and
Carrier Board SDIO interface support will not result in damage. An EEPROM bit is added so that the Carrier Board can define
if the GPIO are used as GPIO or SDIO. The Module may use this information to allow boot from SDIO. Modules that support
SDIO over GPIO shall implement the pin mapping based on the table below.

Table 4.31: SD card interface signals

COM Express
SD card interface signals Comments
Signal
GPI0 SD_DATA0 Bidirectional signal
GPI1 SD_DATA1 Bidirectional signal
GPI2 SD_DATA2 Bidirectional signal
GPI3 SD_DATA3 Bidirectional signal
GPO0 SD_CLK Output from COM Ex, input to SD
GPO1 SD_CMD Output from COM Ex, input to SD
Input to COM Ex when used as SD_WP.Output from COM Ex,
GPO2 SD_WP
input to SD
Input to COM Ex when used as SD_CD#. Output from COM
GPO3 SD_CD#
Ex, input to SD

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 SOM-5894 A101-4
Description Baseboard
Baseboard

Module has integrated

SDIO Card Detect. This signal indicates when a PU resistor to 3.3V
SDIO/MMC card is present. Maps to GPO3 used Connect to SDIO Device N/C
as an input when used for SD card support. or Card pin CD#
N/C if not used.

Module has integrated

SDIO Clock. With each cycle of this signal a one-
series resistor
bit transfer on the command and each data line
Connect to SDIO Device N/C
occurs. This signal has maximum frequency of 48
or Card pin CLK
MHz. Maps to GPO0.
N/C if not used.

Module has integrated

SDIO Command/Response. This signal is used
PU resistor to 3.3V and
for card initialization and for command transfers.
series resistor
During initialization mode this signal is open N/C
Connect to SDIO Device
drain. During command transfer this signal is in
or Card pin CMD
push-pull mode. Maps to GPO1
N/C if not used.

Module has integrated

SDIO Write Protect. This signal denotes the
PU resistor to 3.3V
state of the write-protect tab on SD cards. Maps
Connect to SDIO Device N/C
to GPO2 used as an input when used for SD card
or Card pin WP
support.
N/C if not used.

Module has integrated

series resistor
Connect to SDIO Device N/C
or Card pin DATA0
N/C if not used.

Module has integrated

series resistor
Connect to SDIO Device N/C
or Card pin DATA1
N/C if not used.
SDIO Data lines. These signals operate in push-
pull mode. Maps to GPI[0:3]
 SDIO Data lines. These signals operate in push-
pull mode. Maps to GPI[0:3]
Module has integrated
series resistor
Connect to SDIO Device N/C
or Card pin DATA2
N/C if not used.

Module has integrated

series resistor
Connect to SDIO Device N/C
or Card pin DATA3
N/C if not used.

he SDIO signals are piggybacked on the existing COM.0

eneral Purpose Input Output'). The signal mapping is such that
ect to GPO. With this mapping, any combination of Module and
An EEPROM bit is added so that the Carrier Board can define
his information to allow boot from SDIO. Modules that support
e table below.

ce signals
Comments
Bidirectional signal
Bidirectional signal
Bidirectional signal
Bidirectional signal
Output from COM Ex, input to SD
Output from COM Ex, input to SD
Input to COM Ex when used as SD_WP.Output from COM Ex,
input to SD
Input to COM Ex when used as SD_CD#. Output from COM
Ex, input to SD

SB in S3,S4,S5
 Power and System
Pin No. Pin Type Pwr Rail / Tolerance Description Baseboard
Management

Module has integrated

PU resistor to
A falling edge creates a power button event.
3.3VDUAL
Power button events can be used to bring a
ATX - Connect to Power
I 3.3V / 3.3V Suspend system out of S5 soft off and other suspend
B12 PWRBTN# Button or SIO Power
CMOS 3.3V Suspend / 3.3V states, as well as powering the system down.
Button output pin (Active
Power button to bring system out of S5 (soft off),
low)
active on rising falling edge.
AT - N/C
N/C if not used

Reset button input. Active low input. System is

held in hardware reset while this input is low, and
Module has integrated
comes out of reset upon release. Reset button
PU resistor to
I 3.3V / 3.3V Suspend input. Active low request for Module to reset and
B49 SYS_RESET# 3.3VDUAL
CMOS 3.3V Suspend / 3.3V reboot. May be falling edge sensitive. For
Connect to Reset button
situations when SYS_RESET# is not able to
N/C if not used
reestablish control of the system, PWR_OK or a
power cycle may be used.

Reset output from module to Carrier Board.

Active low. Issued by module chipset and may Module has integrated
result from a low SYS_RESET# input, a low 3.3VDUAL buffer and
PWR_OK input, a VCC_12V power input that falls series resistor
O 3.3V / 3.3V Suspend
B50 CB_RESET# below the minimum specification, a watchdog Connect to reset pin of
CMOS 3.3V Suspend / 3.3V
timeout, or may be initiated by the module devices except PCI slots
software. or devices.
Carrier Board LPC devices should be reset with N/C if not used.
signal CB_RESET#.
 Module has integrated
PD resistor to GND.
Connect to power good
pin of main power
supply
ATX - PW-OK pin 8 of
ATX power connector
connects 3.3V level
shifter to COME
Power OK from main power supply. A high value
PWR_OK
indicates that the power is good. This signal can
I AT - PG pin P8.1 of AT
B24 PWR_OK 3.3V / 3.3V be used to hold off Module startup to allow
CMOS power connector
Carrier based FPGAs or other configurable
connects 3.3V level
devices time to be programmed.
shifter to COME
PWR_OK
Other - PWROK of 12V
power generator circuit
connects 3.3V level
shifter to COME
PWR_OK
N/C is not allowed
N/C if not used.

Connect to LPCPD# of
O 3.3V / 3.3V Suspend Indicates imminent suspend operation; used to
B18 SUS_STAT# LPC device.
CMOS 3.3V Suspend / 3.3V notify LPC devices.
N/C if not used.

Indicates system is in Suspend to RAM state. Connect to SLP_S3#

O 3.3V / 3.3V Suspend Active low output. An inverted copy of SUS_S3# (Suspend To RAM) of
A15 SUS_S3#
CMOS 3.3V Suspend / 3.3V on the Carrier Board may may be used to enable LPC device or SIO.
the non-standby power on a typical ATX supply. N/C if not used.

Connect to SLP_S4#
O 3.3V / 3.3V Suspend Indicates system is in Suspend to Disk state. (Suspend To Disk) of
A18 SUS_S4#
CMOS 3.3V Suspend / 3.3V Active low output. LPC device or SIO.
N/C if not used.
Connect to SLP_S5#
Indicates system is in Soft Off state. Also known
O 3.3V / 3.3V Suspend (Soft Off) of LPC device
A24 SUS_S5# as "PS_ON" and can be used to control an ATX
CMOS 3.3V Suspend / 3.3V or SIO.
power supply.
N/C if not used.
 Module has integrated
PU resistor to
3.3VDUAL
Device - Connect to
WAKE# pin of PCIE
device.
I 3.3V / 3.3V Suspend
B66 WAKE0# PCI Express wake up signal. Slot - Connect to
CMOS 3.3V Suspend / 3.3V
WAKE# pin B11 of PCIE
slot.
ExpressCard - Connect
to WAKE# pin 11 of
ExpressCard socket.
N/C if not used.

Module has integrated

General purpose wake up signal. May be used to PU resistor to
I 3.3V / 3.3V Suspend
B67 WAKE1# implement wake-up on PS2 keyboard or mouse 3.3VDUAL
CMOS 3.3V Suspend / 3.3V
activity. Connect to PME# of SIO
N/C if not used.

Module has integrated

Indicates that external battery is low. PU resistor to
I 3.3V / 3.3V Suspend This port provides a battery-low signal to the 3.3VDUAL
A27 BATLOW#
CMOS 3.3V Suspend / 3.3V Module for orderly transitioning to power saving Connect to BATLOW# of
or power cut-off ACPI modes. Smart Battery
N/C if not used.

Module has integrated

PU resistor to 3.3V
I Input from off-module temp sensor indicating an Connect to THRM#
B35 THRM# 3.3V / 3.3V
CMOS over-temp situation. output of Hardware
Monitor.
N/C if not used.
 Module has integrated
PU resistor to 3.3V
O Active low output indicating that the CPU has Connect to
A35 THERMTRIP# 3.3V / 3.3V
CMOS entered thermal shutdown. THERMTRIP# input of
devices.
N/C if not used.

Module has integrated

PU resistor to
3.3VDUAL
3.3VSB SMBus device
- Connect to SMBCLK of
SMBus device.
3.3V SMBus device -
Connect 3.3V isolation
circuit controlled by
COME pin B24
PWR_OK to SMBCLK of
I/O OD 3.3V / 3.3V Suspend
B13 SMB_CLK System Management Bus bidirectional clock line. SMBus device.
CMOS 3.3V Suspend / 3.3V
5VSB SMBus device -
Connect 5V Level
Shifter to SMBCLK of
SMBus device.
5V SMBus device -
Connect 5V isolation
circuit controlled by
COME pin B24
PWR_OK to SMBCLK of
SMBus device
N/C if not used.
 Module has integrated
PU resistor to
3.3VDUAL
3.3VSB SMBus device
- Connect to SMBDAT of
SMBus device.
3.3V SMBus device -
Connect 3.3V isolation
circuit controlled by
COME pin B24
PWR_OK to SMBDAT of
I/O OD 3.3V / 3.3V Suspend
B14 SMB_DAT System Management Bus bidirectional data line. SMBus device.
CMOS 3.3V Suspend / 3.3V
5VSB SMBus device -
Connect 5V Level
Shifter to SMBDAT of
SMBus device.
5V SMBus device -
Connect 5V isolation
circuit controlled by
COME pin B24
PWR_OK to SMBDAT of
SMBus device
N/C if not used.

Module has integrated

System Management Bus Alert – active low input PU resistor to
can be used to generate an SMI# (System 3.3VDUAL
I 3.3V / 3.3V Suspend
B15 SMB_ALERT# Management Interrupt) or to wake the system. Connect to
CMOS 3.3V Suspend / 3.3V
Power sourced through 5V standby rail and main SMBALERT# of SMBus
power rails device.
N/C if not used.

Module has integrated

PU resistor to
I 3.3V / This may be driven low by external circuitry to 3.3VDUAL
B88 RI#
CMOS 3.3V Suspend signal an external power-management event. Connect to Inverted RI
of Series port.
N/C if not used.
 Module has integrated
PU 10KΩ to 3.3VDUAL
and connects forward
Schottky Diode Vf max =
0.6V in series.
R1.0/R2.x Module both
LID buttonswitch. - Connect protection
I OD
A103 LID#* 3.3V Suspend / 12V Low active signal used by the ACPI operating scheme referred to
CMOS
system for a LID switch. Figure 5-11 of COM.0
R2.0 or Figure 5-13 of
COM.0 R2.1 Spec to
LID button.
R2.x Module only -
Connect to LID button.
N/C if not used.

Module has integrated

PU 10KΩ to 3.3VDUAL
and connects forward
Schottky Diode Vf max =
0.6V in series.
R1.0/R2.x Module both
Sleep button.
- Connect protection
I OD Low active signal used by the ACPI operating
B103 SLEEP#* 3.3V Suspend / 12V scheme referred to
CMOS system to bring the system to sleep state or to
Figure 5-11 of COM.0
wake it up again.
R2.0 or Figure 5-13 of
COM.0 R2.1 Spec to
Sleep button.
R2.x Module only -
Connect to Sleep button.
N/C if not used.

* These signals use reclaimed VCC_12V pins. SeeRefer to sectionSection 5.10 'Protecting COM.0 Pins Reclaimed From the
VCC_12V Pool' for additional design considerations
4.3.22 Power and System Management
Signals PWR_OK, SYS_RESET#, and CB_RESET# shall be supported for all Module pin-out types. Signal PCI_RESET# shall be
supported for pin-out types 2 and 3. Signal IDE_RESET# shall be supported for pin-out types 2 and 4. Additionally, signal PWR_OK
indicates that all the power supplies to the Module are stable within specified ranges and can be used to enable Module internal
power supplies.

PWR_OK has been traditionally used to hold off a Module startup to allow devices on the Carrier such as FPGAs to initialize. The
Module will typically not power up until the PWR_OK signal goes active. There is the potential for the Carrier to back drive voltages
from the Carrier to the Module when the Carrier is powered but the Module is not. Designers of Modules and Carrier are encourage
to follow the terminations as specified in Section 4.4 'Signals Requiring Carrier Board Termination'. The use of SYS_RESET# to hold
off a Module startup may not produce the desired results since the behavior of SYS_RESET# is Module chipset dependent. In
typical designs, the reset initiation happens on the falling edge of SYS_RESET# therefore holding the SYS_RESET# low will not
result in preventing the Module for starting. PWR_OK should not be deactivated after the module enters S0 unless there is a power
fail condition.

Signals SUS_S3#, SUS_S4# and SUS_S5# defines the signaling to indicate that the Module has entered the ACPI power-saving
mode S3 (Suspend-To-RAM or STR), S4 (Suspend-To- Disk or STD), or S5 (Soft-Off).
Wake. This port defines the signaling to wake up the Module from a power saving mode. Most prevalent choices for these signals
are RING# and LID#, although other choices can be implemented.
Power Button. This port defines the signaling for powering the Module up and down.
Power Good. This port defines the signaling for the correct power conditions to proceed with normal startup of the Module.

The Module shall provide the termination for the signals below. The following signal should be pulled-up to 3.3V Standby with a
1.2kΩ resistor
• WAKE0#

The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V Standby with a
10kΩ resistor
• SYS_RESET#
• BATLOW#
• WAKE1#
• PWRBTN#
• SLEEP#
• LID#

4.3.23 Thermal Protection

This port provides thermal signaling to protect critical components on the Module and the Carrier Board.
4.3.24 SM Bus
The SMBus port is specified for system management functions. It is used on the Module to manage system functions such as
reading the DRAM SPD EEPROM and setting clock synthesizer parameters. Off Module, the SMBus should be used carefully. If the
SMBus is used on the baseboard, then great care must be taken that no conflicts with the on-Module SMBus devices occur. It may
be useful for implementation on the Carrier Board of standards such as Smart Battery. The maximum capacitance on the Carrier
Board shall benot exceed 100pF.
The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V Standby with a
2.2kΩ resistor
• SMB_CK

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5

SMBus Capacitance and Pull-Up Resistor

 SOM-5894 A101-4
Baseboard

Module has integrated

PU resistor to
3.3VDUAL
ATX - Connect to Power
Button or SIO Power
Button output pin (Active
low)
AT - N/C
N/C if not used

Module has integrated

PU resistor to
3.3VDUAL
Connect to Reset button
N/C if not used

Module has integrated

3.3V buffer and series
resistor
Connect to reset pin of
devices.
N/C if not used.
Connect to power good
pin of main power
supply
ATX - PW-OK pin 8 of
ATX power connector
connects 3.3V level
shifter to COME
PWR_OK
AT - PG pin P8.1 of AT
power connector
connects 3.3V level
shifter to COME
PWR_OK
Other - PWROK of 12V
power generator circuit
connects 3.3V level
shifter to COME
PWR_OK
N/C is not allowed

Connect to LPCPD# of
LPC device.
N/C if not used.

Connect to SLP_S3#
(Suspend To RAM) of
LPC device or SIO.
N/C if not used.

Connect to SLP_S4#
(Suspend To Disk) of
LPC device or SIO.
N/C if not used.
Connect to SLP_S5#
(Soft Off) of LPC device
or SIO.
N/C if not used.
Module has integrated
PU resistor to
3.3VDUAL
Device - Connect to
WAKE# pin of PCIE
device.
Slot - Connect to
WAKE# pin B11 of PCIE
slot.
ExpressCard - Connect
to WAKE# pin 11 of
ExpressCard socket.
N/C if not used.

Module has integrated

PU resistor to
3.3VDUAL
Connect to PME# of SIO
N/C if not used.

Module has integrated

PU resistor to
3.3VDUAL
Connect to BATLOW# of
Smart Battery
N/C if not used.

Module has integrated

PU resistor to 3.3V
Connect to THRM#
output of Hardware
Monitor.
N/C if not used.
Module has integrated
PU resistor to 3.3V
Connect to
THERMTRIP# input of
devices.
N/C if not used.

Module has integrated

PU resistor to
3.3VDUAL
3.3VSB SMBus device
- Connect to SMBCLK of
SMBus device.
3.3V SMBus device -
Connect 3.3V isolation
circuit controlled by
COME pin B24
PWR_OK to SMBCLK of
SMBus device.
5VSB SMBus device -
Connect 5V Level
Shifter to SMBCLK of
SMBus device.
5V SMBus device -
Connect 5V isolation
circuit controlled by
COME pin B24
PWR_OK to SMBCLK of
SMBus device
N/C if not used.
Module has integrated
PU resistor to
3.3VDUAL
3.3VSB SMBus device
- Connect to SMBDAT of
SMBus device.
3.3V SMBus device -
Connect 3.3V isolation
circuit controlled by
COME pin B24
PWR_OK to SMBDAT of
SMBus device.
5VSB SMBus device -
Connect 5V Level
Shifter to SMBDAT of
SMBus device.
5V SMBus device -
Connect 5V isolation
circuit controlled by
COME pin B24
PWR_OK to SMBDAT of
SMBus device
N/C if not used.

Module has integrated

PU resistor to
3.3VDUAL
Connect to
SMBALERT# of SMBus
device.
N/C if not used.

N/C
Module has integrated
PU 10KΩ to 3.3VDUAL
and connects forward
Schottky Diode Vf max =
0.6V in series.
R1.0/R2.x Module both
- Connect protection
scheme referred to
Figure 5-11 of COM.0
R2.0 or Figure 5-13 of
COM.0 R2.1 Spec to
LID button.
R2.x Module only -
Connect to LID button.
N/C if not used.

Module has integrated

PU 10KΩ to 3.3VDUAL
and connects forward
Schottky Diode Vf max =
0.6V in series.
R1.0/R2.x Module both
- Connect protection
scheme referred to
Figure 5-11 of COM.0
R2.0 or Figure 5-13 of
COM.0 R2.1 Spec to
Sleep button.
R2.x Module only -
Connect to Sleep button.
N/C if not used.
 Pwr Rail /
Pin No. Power and GND Pin Type Description Baseboard
Tolerance
A97~A99,A101~
A103, Primary power input: +12V nominal. SeeRefer to Connect to 12V
A104~A109 sectionSection 7 "Electrical Specifications" Add rapid discharge
B101~B103, VCC_12V Power section for allowable input range. All available circuit if system needs to
B104~B109 VCC_12V pins on the connector(s) shall be implement quick power
C104~C109 used. cycle.
D104~D109

Standby power input: +5.0V nominal. SeeRefer

to sectionSection 7 "Electrical Specifications" ATX - Connect to 5VSB
section for allowable input range. If VCC5_SBY is AT - N/C
used, all available VCC_5V_SBY pins on the Add rapid discharge
B84~B87 VCC_5V_SBY Power
connector(s) shall be used. Only used for circuit if system needs to
standby and suspend functions. May be left implement quick power
unconnected if these functions are not used in cycle.
the system design.

Module has integrated

common source
Real-time clock circuit-power input. Nominally
3.3VDUAL to diode for
A47 VCC_RTC Power +3.0V. SeeRefer to sectionSection 7 "Electrical
RTC power.
Specifications" section for details.
Connect 1KΩ in series
to 3V Battery
A1,A11,A21,A31
,A41,A51,A57,A
60,A66,A70,A80
,A90,A96,A100,
A110
B1,B11,B21,B31
,B41,B51,B60,B
70,B80,B90,B10
0,B110
C1,C11,C21,C31
,C41,C51,C60,C
Ground - DC power and signal and AC signal
70,C76,C80,C84
return path.
,C87,C90,C93,C GND Power Connect to GND
All available GND connector pins shall be used
96,C100,C103,C
and tied to Carrier Board GND plane.
110,Type 6 - C2,
C5, C8, C14,
C73
D1,D11,D21,D31
,D41,D51,D60,D
67,D70,D76,D80
,D84,D87,D90,D
93,D96,D100,D1
03,D110, Type 6
- D2, D5, D8,
D14, D73

4.4.7 VCC_RTC
To implement the RTC Battery according to the Underwriters Laboratories Inc® (UL) guidelines, battery cells must be protected
against a reverse current going to the cell. This can be done by either a series Schottky diode or a series resistor. Revision 1.0
of this specification did not specify the location of this diode and the location was vendor implementation specific. For revision
2.0 Carrier Boards, a protection diode or a series resistor shall be placed on the Carrier Board. For backwards compatibility, a
revision 2.0 Module may also implement the protection diode.

PU - Pull Up
PD - Pull Down
JS - Jumper Selection
NL - No Loaded
x.xV - Power active in S0
x.xVSB - Power active in S0~S5
x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5
 SOM-5894 A101-4
Baseboard

Connect to 12V
Add rapid discharge
circuit if system needs to
implement quick power
cycle.

ATX - Connect to 5VSB

AT - N/C
Add rapid discharge
circuit if system needs to
implement quick power
cycle.

Module has integrated

common source
3.3VDUAL to diode for
RTC power.
Connect 1KΩ in series
to 3V Battery
Connect to GND
5.10 Protecting COM.0 Pins Reclaimed From the VCC_12V Pool
The COM.0 Rev. 2 Type 6 and Type 10 pin-out types introduce eight signals that are mapped to pins that are re-claimed from
These signals include
• SER0_TX, SER1_TX TTL level outputs from the Module
• SER0_RX, SER1_RX TTL level inputs to the Module
• LID#, SLEEP# 3.3V logic level inputs to the Module, in the suspend domain
• FAN_TACHIN 3.3V logic level input to the Module
• FAN_PWMOUT 3.3V logic level output from the Module
A new Type strap pin is also introduced in COM.0 Rev 2, for all Module Types. It also falls on a pin that was used exclusively
• TYPE10#
VCC_12V on COM.0 Rev. 1 Module Types 1,2,3,4,5
No connect on COM.0 Rev. 2 Module Types 1,2,3,4,5,6
4.7K Module pull-down to GND on Module Type 10
All nine of the signals referenced above on COM.0 Rev. 2 compliant Module and Carrier designs shall be able to withstand c
a 12V power supply).

One line of defense against such unintended connections is for Carrier designs to decode the Module TYPE pins (3 pins on th
to not power the system up if an improper Module Type is detected.
Examples of this may be found in the PICMG Carrier Design Guide. However, there are some situations in which this can not
into a Rev. 1 Type 1 Carrier. Since the TYPE10# strap was not anticipated in the Rev. 1 Carrier, the Carrier will apply power to
Modules be able to withstand 12V exposure to the pins reclaimed from the VCC_12V pool.

5.10.1 Logic Level Signals on Pins Reclaimed from VCC_12V

Module logic level inputs and outputs that are implemented on pins reclaimed from the VCC_12V pool shall implement the se
The Schottky diode should be a BAT54 device. For inputs in this group, a 47K pull-up to the local 3.3V S0 or S5 rail (as appro
Carrier Board logic level inputs and outputs that are implemented on pins reclaimed from the VCC_12V pool shall be protecte
shown in the left side of the figure below may be used. Any scheme that is used shall be able to pull the reclaimed Module inp
voltage of 0.5V for a logic low, as indicated in the figure.
Figure 5-115-13: Protecting Logic Level Signals on Pins Reclaime
5.10.2 TYPE10# Strap - Reclaimed from VCC_12V
No additional protection is needed for the TYPE10# strap on the Module side:
• On Type 10# Modules, this pin is tied through a 4.7K resistor to GND. Exposure of this Module pin to 12V is harmless.
• On Rev. 1 Type 1,2,3,4,5 Modules, this pin is tied to VCC_12V already.
• On Rev. 2 Type 1,2,3,4,5 Modules, this pin is a no connect.
• On Type 6 Modules, this pin is a no connect.
On the Carrier side, protection against accidental 12V exposure is required. Carrier board designs shall be tolerant of protrac
example, would expose the TYPE10# pin on a Rev. 2 Type 1,2,3,4,5 Carrier to 12V (unless the Carrier design does not allow
The TYPE10# Module pin is, in effect, a tri-level pin: it is tied, depending on Module Type and COM.0 Revision level, to either
be created that distinguish between the 3 levels. If implemented, this would allow the Carrier board to determine whether a Ty
may be illustrated in a future edition of the PCIMG Carrier Design Guide.
1 Introduction
A Computer-On-Module, or COM, is a module with all components necessary for a bootable host computer, packaged as a
power up. COMs are used to build single board computer solutions and offer OEMs fast time-to-market with reduced deve
freedom in meeting form-fit-function requirements. For all these reasons the COM methodology has gained much popularit

COM Express® is an open industry standard for Computer-On-Modules. It is designed to be future proof and to provide a s
Differential Signaling) interfaces. These include the PCI bus and parallel ATA on the one hand and PCI Express and Seria

Key features include:

• Rich complement of contemporary high bandwidth serial interfaces, including PCI Express, Serial ATA, USB 2.0, and Gig
• 32-bit PCI, LPC and Parallel ATA options preserved for easy interface to a range of peripherals
• Extended power-management capabilities
• Robust thermal and mechanical concept
• Cost-effective design
• Legacy-free design (no Super I/O, PS2 keyboard or mouse)
• Compact module size with two footprint options to satisfy a range of performance requirements
• Small Module size with multiple footprint options to satisfy a range of performance requirements
• High-performance mezzanine connector with several pin-out types to satisfy a range of applications
• Extensive video port support, including VGA, LVDS, SDVO, DP, eDP, DVI and HDMI terminal drivers plus x16 PEG port

The COM Express® specification has been created to appeal to a range of vertical embedded markets. It has also been fo
to bench-top to handheld. Markets and applications include but are not limited to:

• Healthcare - clinical diagnostic imaging systems, patient bedside monitors, etc.

• Retail & advertising - electronic shopping carts, billboards, kiosks, POS systems, etc.
• Test & measurement - scientific and industrial test and measurement instruments
• Gaming & entertainment - simulators, slot machines, etc.
• Industrial automation - industrial robots, vision systems, etc.
• Security - digital CCTV, luggage scanners, intrusion detectors, etc.
• Defense & government - unmanned vehicles, rugged laptops, wearable computers, etc.

Systems based on the COM Express® Specification require the implementation of an application-specific Carrier Board th
specific features such as external connector choices and locations and peripheral circuits can be tailored to suit the applica
board design. The OEM also benefits from a wide choice of modules providing a scalable range of price and performance

1.1 Objective
This specification defines COM Express
1.2 COM.0R2.0 Changes from R1.0
Type 6
Added definition of a Type 6 pin-out. This pin-out is based on Type 2 with the following changes:

• The PCI interface has been removed and the pins are now used to support the Digital Display Interfaces and additional P
• The IDE interface has been removed and the pins are now used to support the additional SuperSpeed differential pairs fo
• Three dedicated Digital Display Interfaces have been add ed (Port 1, Port 2, Port 3). Ports 1, 2, and 3 can be individually
SDVO.
• Added two optional 2 wire serial ports
• SDVO is no longer multiplexed on the PEG port. The SDVO interface is now multiplexed on Digital Display Interface 1
• The PEG interface optionally support multiplexed display interfaces. Definition of this multiplexing is outside the scope of
• Added two additional PCI Express lanes (Lane 6 and Lane 7)
• Added support for the physical presence signal for a TPM option, and a lid switch
• Added support for fan tach input and PWM output.
• Removed support for carrier board Carrier Board keyboard/mouse controller
Type 10
Added definition of a Type 10 pin-out. This pin-out is based on Type 1 but it is not fully backwards compatible with existing

• Reduction to single channel LVDS only

• Added Digital Display Interface, realized as SDVO, DP, or TMDS
• Added two optional 2 wire serial ports
• Added support for the physical presence signal for a TPM option, and a lid switch
• Added support for fan tach input and PWM output
• Reduction to 4 PCIe x1 links
• Reduction to 2 SATA interfaces
• No analog VGA
• Removed support for carrier board Carrier Board keyboard/mouse controller

All Types
Additional changes to all Module Types

• Added SPI using previously reserved pins on the A-B connector. SPI is the primary interface for Carrier mounted BIOS fla
Types. In R1.0 the LPC interface was used for external BIOS support. R2.0 Modules must support SPI and might also sup
• Added PCI Express Gen2 signaling for all PCI Express lanes.
• AC97 pins are now used to support AC97 and HD audio.
• TV out pins have been redefined. The TV out function is not supported
• Added the definition for a 95 x 95 mm Module called a Compact Module
• Added optional support for SDIO using the existing GPIO signals.
• Added multi-master support for the I2C bus
• Added TYPE10# pin in reclaimed VCC_12V pool to allow detection of Rev 2.0 compliant Modules types
• Added a section Section “Signals Requiring Module Termination” to further clarify signal terminations
• Incorporated COM.0R1.0 Errata-002
• Incorporated change requests from the Carrier Design Guide subcommittee as well as those submitted during the develo
• Moved I2C to standby power rail to allow interrogation of a Carrier based EEPROM for Module configuration strappings
• Reduced maximum input power for Types 2-5 to 137W and to 68W for Type 1
• Allow optional USB client support on COM.0 USB7

1.3 COM.0 Revision 1.0 vs. 2.0 Compatibility Considerations

For designers wishing to build either modules Module compatible with both Revision 1.0 and 2.0 carriers Carriers, or carrie
attention is called to the following COM Express Revision 2.0 compatibility considerations. Even if new Revision 2.0 design
reclamation consideration is important to protect against pairing with an incompatible Revision 1.0 counterpart.
AC97 / HDA
The original Revision 1.0 AC97 interface on all types has been updated to support High Definition Audio. See Refer to sec
Carrier based BIOS devices
In COM Express Revision 1.0, carrier boards Carrier Boards wishing to support an on-carrier on-Carrier BIOS enabled via
module Module LPC interface. With the progression in technology, the Firmware Hub is less commonly available and COM
SPI interface. See Refer to section Section 4.3.12 'SPI Interface' for further details.
SDVO
To support advances in technology, the SDVO interface, which was formerly multiplexed on the PEG port in Types 2-5, is
the new Revision 2.0 Types 6 and 10. See Refer to sections Section 4.3.6 'PEG PCI Express Lanes',4.3.14 'PEG Multiplex
4.3.17 'DDI Signals: SDVO' for further details.
TV Out
The TV Out interface has been removed and reused on Types 1-5 within COM Express Revision 2.0
12V Pin Reclamation
COM Express R2.0 Types 6 and 10 reclaimed several 12V pins for new functions while Revision 2.0 reserved these forme
to be tolerant of 12V on these pins if it is installed on a Revision 1.0 carrier Carrier. Similarly, a Revision 2.0 carrier Carrier
installed on the carrier Carrier. See Refer to section Section 5.10 'Protecting COM.0 Pins Reclaimed From the VCC_12V P

1.4 COM.0 R2.1 Changes from R2.0

Mini form factor
Added definitions for Mini 84x55mm form factor
Section 6.1 'Module Size – Mini Module'
Section 6.10 'Heat-Spreader'
Section Figure 6-11: Mini Module Heat-Spreader'
Section 9.1 'Mounting positions and connector location for Carrier Boards'
I/Os
Added CAN Bus for Type 6 and Type 10 in Section 4.3.30 'CAN Bus'
Added USB 3.0 for Type 10
Added a pin for USB Client Host detection for Type 10
Added option for eDP overlayed on LVDS Channel A for Type 6 and Type 10 Modules
Power
Allowed for wide input voltage range for Mini size Module
Updates
Updated Section 4.5 'Signals Requiring Module Termination'
Corrected SDIO Section 4.3.26 'SDIO', Table 4.31 'SD card interface signals' and Table 4.32 'SDIO Signals, Pin Types, an
Clarify SYS_RESET# and PWR_OK usage

Contributors
The following companies were members of the COM Express® subcommittee and participated in developing this specifica

• ADLink
• Congatec
• Diversified Technology
• Foxconn
• GNP
• Intel
• Kontron
• Maxim Integrated Products
• MEN Mikro Elektronik GmbH
• Microbus
• PFU Systems
• RadiSys
• SBS Technologies
• Tyco

1.4 1.5 Name and Logo Usage

The PCI Industrial Computer Manufacturers Group policies regarding the use of its logos and trademarks are as follows:

Permission to use the PICMG® organization logo is automatically granted to designated members only as stipulated on th
during the period of time for which their membership dues are paid. Nonmembers may not use the PICMG® organization l

The PICMG® organization logo must be printed in black or color as shown in the files available for download from the mem
“PICMG® ”is set horizontally and the aspect ratio of the entire logo must be maintained, but the size may be varied. Nothin

Manufacturers’ distributors and sales representatives may use the COM Express® logo (but not the PICMG® organization
use of the COM Express® logo is a privilege granted by the PICMG® organization to companies who have purchased the
believe their products comply with these specifications. Use of the logos by either members or non-members implies such
are misused.

The use of the COM Express logo is a privilege granted by the PICMG® organization to companies who have purchased t
that believe their products comply with these specifications. Manufacturers' distributors and sales representatives may use
the manufacturer. Use of the logos by either members or nonmembers implies such compliance. Only PICMG Executive a
revoke permission to use logos if they are misused.

The COM Express logo can be found on the PICMG web site, www.picmg.org.

The COM Express® logo must be used exactly as shown in the files available for download from the PICMG® Web site. T
varied. Nothing may be added to or deleted from the COM Express® logo.

The PICMG® name and logo are registered trademarks of PICMG® . Registered trademarks must be followed by the ® sy
and advertising material in which the logo appears:

PICMG, the COM Express name and logo and the PICMG logo are registered trademarks of the PCI Industrial Computers

The COM Express® name and logo are trademarks of PICMG® in process of registration. These trademarks must be follo
published literature and advertising material in which the logo appears:

COM Express and the COM Express logo are trademarks of the PCI Industrial Computers Manufacturers Group.

The Consortium draws attention to the fact that it is claimed that compliance with this specification may involve the use of a
evidence, validity or scope of this IPR.
1.5 1.6 Intellectual Property
The holder of this IPR has assured the Consortium that it is willing to license or sublicense all such IPR to those licensees
The statement of the holder of this IPR to such effect has been filed with the Consortium.

Attention is also drawn to the possibility that some of the elements of this specification may be the subject of IPR other tha
identifying any or all such IPR.

No representation is made as to the availability of any license rights for use of any IPR inherent in this specification for any

This specification conforms to the current PICMG® Intellectual Property Rights Policy and the Policies and Procedures for
property that is not
1.5.1 1.6.1 available for licensing
Necessary Claimsunder Reasonable
(referring toand Non-discriminatory
mandatory terms. In the course offeatures)
or recommended Membership R
Tyco has the following patents, which may cover some aspects of the PICMG® COM Express® Module and Carrier Board
information.

• USA patent 6,095,832 “Cap housing for electrical connectors”

• USA patent 6,159,021 “Electrical connector for printed circuit boards”
• USA patent 6,558,195 “Electrical connector for printed circuit boards”
• Japan patent 11-040243 “ELECTRICAL CONNECTOR CAP AND ELECTRICAL CONNECTOR ASSEMBLY”
• Japan patent 11-074027 “BOARD-MOUNTING TYPE CONNECTOR”
• Japan patent 11-260464 “CAP ON ELECTRIC CONNECTOR”
• Japan patent 11-354227 “BASE BOARD INSTALLING TYPE CONNECTOR ASSEMBLY”
• Japan patent 2000-003751 “SUBSTRATE MOUNTING TYPE CONNECTOR ASSEMBLY”
• Japan patent 2000-048876 “ELECTRICAL CONNECTOR FOR CONNECTING MUTUAL BOARDS”

1.5.2 1.6.2 Unnecessary Claims(referring to optional features or non-normative ele

No disclosures in this category were made during subcommittee review.
1.5.3 1.6.3 Third Party Disclosures
(Note that third party IPR submissions do not contain any claim of willingness to license the IPR.)

No disclosures in this category were made during subcommittee review.

Refer to PICMG® IPR Policies and Procedures and the company owner of the patent for terms and conditions of usage.

PICMG® makes no judgment as to the validity of these claims or the licensing terms offered by the claimants.

THIS SPECIFICATION IS BEING OFFERED WITHOUT ANY WARRANTY WHATSOEVER, AND IN PARTICULAR, ANY
USE OF THIS SPECIFICATION SHALL BE MADE ENTIRELY AT THE IMPLEMENTER'S OWN RISK, AND NEITHER TH
HAVE ANY LIABILITY WHATSOEVER TO ANY IMPLEMENTER OR THIRD PARTY FOR ANY DAMAGES OF ANY NATU
USE OF THIS SPECIFICATION.

Compliance with this specification does not absolve manufacturers of COM Express® equipment from the requirements of

PICMG® and the COM Express® logos are trademarks of the PCI Industrial Computer Manufacturers Group.

All other brand or product names may be trademarks or registered trademarks of their respective holder.

1.6 1.7 Copyright Notice

© 2005, 2010, 2011, 2012 PICMG. All rights reserved. All text, pictures and graphics are protected by copyrights. No copy

PICMG has made every attempt to ensure that the information in this document is accurate yet the information contained w

Trademarks

Intel and Pentium are registered trademarks of Intel Corporation. ExpressCard is a (PCMCIA). PCI Express is a registered
SIG). COM Express is a registered trademark of PCI Industrial Computer Manufacturers Group (PICMG). I2C is a registere
of CompactFlash Association.

Winbond is a registered trademark of Winbond Electronics Corp. AVR is a registered trademark of Atmel Corporation. Micr
registered trademarks of Microsoft Corporation. VxWorks is a registered trademark of WindRiver. All product names and lo

1.7 1.8 Special Word Usage

Mandatory features are indicated by the use of the word “shall.”

Recommended features are indicated by the use of the word “should.”

Optional features are indicated by the use of the word “may.”

1.8 1.9 Acronyms / Definitions
Table 1.1: Terms and Definitions
Term
AC ‘97
ACPI
Basic Module
BIOS

CAN
Carrier Board
CCTV
CVBS
Compact Module
DDC
DDI
DIMM

DisplayPort
DRAM

DVI

EAPI

EEPROM
Embedded DisplayPort
Extended Module
FR4
Gb
GBE
GPI
GPIO
GPO

HAD
HDMI
I2C
IDE

Legacy Device

LAN
LPC
LS

LVDS

ME
Mini Module
MS
NA
NC
NTSC
OEM
PAL
PATA
PC-AT
PCB
PCI
PCI Express PCIE
PEG
PHY
Pin-out Type
PS2 PS2 Keyboard PS2
Mouse
Ra

ROM

RTC
SAS
SCSI
SPD
SPI
SO-DIMM

S0, S1, S2, S3, S4, S5

SATA

SDVO

SM Bus

Super I/O

TFT
TMDS
TPM
USB
VGA
WDT
XAUI

1.9 1.10 Applicable Documents and Standards

The following publications are used in conjunction with this standard. When any of the referenced specifications are supers
obtained from their respective organizations.

• Advanced Configuration and Power Interface Specification Revision 2.0c, August 25, 2003 Copyright © 1996-2003 Comp
Technologies Ltd., Toshiba Corporation. All rights reserved.
http://www .info/
• Advanced Configuration and Power Interface Specification Revision 4.0, June 16, 2009 Copyright © 1996-2003 Compaq
Technologies Ltd., Toshiba Corporation. All rights reserved.
http://www.acpi.info/
• ANSI/TIA/EIA-644-A-2001: Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, Janu
http://www.ansi.org/
• ANSI INCITS 361-2002: AT Attachment with Packet Interface - 6 (ATA/ATAPI-6), November 1, 2002.
http://www.ansi.org/
• ANSI INCITS 376-2003: American National Standard for Information Technology – Serial Attached SCSI (SAS), October
http://www.ansi.org/
• Audio Codec ’97 Revision 2.3 Revision 1.0, April 2002 Copyright © 2002 Intel Corporation. All rights reserved.
http://www.intel.com/labs/media/audio/
• Display Data Channel Command Interface (DDC/CI) Standard (formerly DDC2Bi) Version 1, August 14, 1998 Copyright ©
http://www.vesa.org/summary/sumddcci.htm
• ExpressCard Standard Release 1.0, December 2003 Copyright © 2003 PCMCIA. All rights reserved.
http://www.expresscard.org/
• ExpressCard® Standard 2.0, June 2009 Copyright © 2009 PCMCIA. All rights reserved.
http://www.expresscard.org/
• HDA - High Definition Audio Specification, Revision 1.0, April 15, 2004 Copyright © 2002 Intel Corporation. All rights rese
http://www.intel.com/standards/hdaudio/
• IEEE 802.3-2002, IEEE Standard for Information technology, Telecommunications and information exchange between sy
Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specificatio
http://www.ieee.org
• IEEE 802.3-2005, IEEE Standard for Information technology, Telecommunications and information exchange between sy
Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specificatio
http://www.ieee.org
• IEEE 802.3ae (Amendment to IEEE 802.3-2002), Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/C
Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation.
http://www.ieee.org
• IEEE 802.3ae (Amendment to IEEE 802.3-2005), Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/C
Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation.
http://www.ieee.org
• Intel Low Pin Count (LPC) Interface Specification Revision 1.1, August 2002 Copyright © 2002 Intel Corporation. All right
http://developer.intel.com/design/chipsets/industry/lpc.htm
• PCI Express Base Specification Revision 1.1, March 28, 2005, Copyright © 2002-2005 PCI Special Interest Group. All rig
http://www.pcisig.com/
• PCI Express Base Specification Revision 2.0, December 20, 2006, Copyright © 2002- 2006 PCI Special Interest Group. A
http://www.pcisig.com/
• PCI Express Card Electromechanical Specification Revision 1.1, March 28, 2005, Copyright © 2002-2005 PCI Special In
http://www.pcisig.com/
• PCI Express Card Electromechanical Specification Revision 2.0, April 11, 2007, Copyright © 2002-2007 PCI Special Inte
http://www.pcisig.com/
• PCI Local Bus Specification Revision 2.3, March 29, 2002 Copyright © 1992, 1993, 1995, 1998, 2002 PCI Special Interes
http://www.pcisig.com/
• PCI Local Bus Specification Revision 3.0, February 3, 2004 Copyright © 1992, 1993, 1995, 1998, and 2004 PCI Special
http://www.pcisig.com/
• PICMG® Policies and Procedures for Specification Development, Revision 2.0, September 14, 2004, PCI Industrial Com
Wakefield, MA 01880 USA, Tel: 781.224.1100, Fax: 781.224.1239.
http://www.picmg.org/
• PICMG® EAPI - Embedded Application Software Interface Specification, Revision 1.0, 2009, PCI Industrial Computer Ma
MA 01880 USA, Tel: 781.224.1100, Fax: 781.224.1239.
http://www.picmg.org/
• SDIO, Secure Digital Input/Output SD Specifications Part E1 SDIO Specification Version 2.00, February 8, 2007 Copyrig
http://www.sdcard.org
• Serial ATA: High Speed Serialized AT Attachment Revision 1.0a January 7, 2003 Copyright © 2000-2003, APT Technolo
Corporation, Seagate Technology LLC. All rights reserved.
http://www.sata-io.org/
• Smart Battery Data Specification Revision 1.1, December 11, 1998.
http://www.sbs-forum.org
• System Management Bus (SMBus) Specification Version 2.0, August 3, 2000 Copyright © 1994, 1995, 1998, 2000 Durac
Linear Technology Inc., Maxim Integrated Products, Mitsubishi Electric Semiconductor Company, PowerSmart, Inc., Toshi
reserved.
http://www.smbus.org/
• Universal Serial Bus Specification Revision 2.0, April 27, 2000 Copyright © 2000 Compaq Computer Corporation, Hewlet
Corporation, NEC Corporation, Koninklijke Philips Electronics N.V. All rights reserved.
http://www.usb.org/
• USB 3.0 Specification, Revision 1.0, November 12, 2008, 2000 Copyright © 2007-2008 Hewlett-Packard Company, Intel
and Texas Instruments. All rights reserved.
http://www.usb.org/
• SPI, Serial Peripheral Interface Bus
http://elm-chan.org/docs/spi_e.html
• Trusted Platform Module (TPM), Trusted Computing Group Specification 1.2 Revision 103, July 9, 2007,
http://www.trustedcomputinggroup.org
• DisplayPort Standard Version 1.1
http://www.vesa.org
• DisplayPort Interoperability Guideline Version 1.1a dated February 5, 2009
http://www.vesa.org/Standards/free.htm
• High-Definition Multimedia Interface specification version 1.3
http://www.hdmi.org

1.10 1.11 Statement of Compliance

Statements of compliance with this specification take the form specified in the PICMG® Policies and Procedures for Speci

“This product complies with PICMG® COM.0 Revision 1.0.”

“This product complies with PICMG® COM.0 Revision 2.0 2.1.”

Products making this simple claim of compliance must provide, at a minimum, all features defined in this specification as b
specification. Such products may also provide recommended features associated with the keyword “should” and permitted
Because the specification provides for a number of recommended and permitted features beyond the mandatory minimum
of product compliance are encouraged.
duction
On-Module, or COM, is a module with all components necessary for a bootable host computer, packaged as a super component. A CO
OMs are used to build single board computer solutions and offer OEMs fast time-to-market with reduced development cost. Like integrat
eeting form-fit-function requirements. For all these reasons the COM methodology has gained much popularity with OEMs in the embed

s® is an open industry standard for Computer-On-Modules. It is designed to be future proof and to provide a smooth transition path from
ignaling) interfaces. These include the PCI bus and parallel ATA on the one hand and PCI Express and Serial ATA on the other hand.

include:

ement of contemporary high bandwidth serial interfaces, including PCI Express, Serial ATA, USB 2.0, and Gigabit Ethernet
LPC and Parallel ATA options preserved for easy interface to a range of peripherals
ower-management capabilities
mal and mechanical concept
ve design
e design (no Super I/O, PS2 keyboard or mouse)
odule size with two footprint options to satisfy a range of performance requirements
ule size with multiple footprint options to satisfy a range of performance requirements
mance mezzanine connector with several pin-out types to satisfy a range of applications
ideo port support, including VGA, LVDS, SDVO, DP, eDP, DVI and HDMI terminal drivers plus x16 PEG port to Carrier Board graphics

press® specification has been created to appeal to a range of vertical embedded markets. It has also been formulated to be applicable
to handheld. Markets and applications include but are not limited to:

- clinical diagnostic imaging systems, patient bedside monitors, etc.

vertising - electronic shopping carts, billboards, kiosks, POS systems, etc.
surement - scientific and industrial test and measurement instruments
entertainment - simulators, slot machines, etc.
utomation - industrial robots, vision systems, etc.
igital CCTV, luggage scanners, intrusion detectors, etc.
government - unmanned vehicles, rugged laptops, wearable computers, etc.

ed on the COM Express® Specification require the implementation of an application-specific Carrier Board that accepts the module. Th
res such as external connector choices and locations and peripheral circuits can be tailored to suit the application. The OEM can focus
. The OEM also benefits from a wide choice of modules providing a scalable range of price and performance upgrade options.

ective
ation defines COM Express® modules at a level of detail sufficient to allow interoperability between independent vendors’ modules and
M.0R2.0 Changes from R1.0

ion of a Type 6 pin-out. This pin-out is based on Type 2 with the following changes:

terface has been removed and the pins are now used to support the Digital Display Interfaces and additional PCI Express lanes
erface has been removed and the pins are now used to support the additional SuperSpeed differential pairs for four USB 3.0 ports
cated Digital Display Interfaces have been add ed (Port 1, Port 2, Port 3). Ports 1, 2, and 3 can be individually configured for DisplayPo

optional 2 wire serial ports

o longer multiplexed on the PEG port. The SDVO interface is now multiplexed on Digital Display Interface 1
nterface optionally support multiplexed display interfaces. Definition of this multiplexing is outside the scope of this specification.
additional PCI Express lanes (Lane 6 and Lane 7)
port for the physical presence signal for a TPM option, and a lid switch
port for fan tach input and PWM output.
support for carrier board Carrier Board keyboard/mouse controller
 ion of a Type 10 pin-out. This pin-out is based on Type 1 but it is not fully backwards compatible with existing Types. Changes:

to single channel LVDS only

tal Display Interface, realized as SDVO, DP, or TMDS
optional 2 wire serial ports
port for the physical presence signal for a TPM option, and a lid switch
port for fan tach input and PWM output
to 4 PCIe x1 links
to 2 SATA interfaces
VGA
support for carrier board Carrier Board keyboard/mouse controller

anges to all Module Types

using previously reserved pins on the A-B connector. SPI is the primary interface for Carrier mounted BIOS flash. External BIOS suppo
.0 the LPC interface was used for external BIOS support. R2.0 Modules must support SPI and might also support LPC external BIOS.
Express Gen2 signaling for all PCI Express lanes.
are now used to support AC97 and HD audio.
have been redefined. The TV out function is not supported
definition for a 95 x 95 mm Module called a Compact Module
onal support for SDIO using the existing GPIO signals.
i-master support for the I2C bus
E10# pin in reclaimed VCC_12V pool to allow detection of Rev 2.0 compliant Modules types
ction Section “Signals Requiring Module Termination” to further clarify signal terminations
d COM.0R1.0 Errata-002
d change requests from the Carrier Design Guide subcommittee as well as those submitted during the development of this document.
to standby power rail to allow interrogation of a Carrier based EEPROM for Module configuration strappings
aximum input power for Types 2-5 to 137W and to 68W for Type 1
nal USB client support on COM.0 USB7

M.0 Revision 1.0 vs. 2.0 Compatibility Considerations

s wishing to build either modules Module compatible with both Revision 1.0 and 2.0 carriers Carriers, or carriers Carriers compatible wit
alled to the following COM Express Revision 2.0 compatibility considerations. Even if new Revision 2.0 designs are not intended to supp
consideration is important to protect against pairing with an incompatible Revision 1.0 counterpart.

Revision 1.0 AC97 interface on all types has been updated to support High Definition Audio. See Refer to section Section 4.3.1 'AC97 A
d BIOS devices
ess Revision 1.0, carrier boards Carrier Boards wishing to support an on-carrier on-Carrier BIOS enabled via the BIOS_DISABLE# pin
ule LPC interface. With the progression in technology, the Firmware Hub is less commonly available and COM Express Revision 2.0 ad
. See Refer to section Section 4.3.12 'SPI Interface' for further details.

dvances in technology, the SDVO interface, which was formerly multiplexed on the PEG port in Types 2-5, is now de-multiplexed from P
sion 2.0 Types 6 and 10. See Refer to sections Section 4.3.6 'PEG PCI Express Lanes',4.3.14 'PEG Multiplexed SDVO',4.3.15 'Digital D
Signals: SDVO' for further details.

nterface has been removed and reused on Types 1-5 within COM Express Revision 2.0
lamation
s R2.0 Types 6 and 10 reclaimed several 12V pins for new functions while Revision 2.0 reserved these former 12V pins for Types 1-5. A
of 12V on these pins if it is installed on a Revision 1.0 carrier Carrier. Similarly, a Revision 2.0 carrier Carrier needs to be tolerant of 12
he carrier Carrier. See Refer to section Section 5.10 'Protecting COM.0 Pins Reclaimed From the VCC_12V Pool' for further details.

M.0 R2.1 Changes from R2.0

ctor
ions for Mini 84x55mm form factor
Module Size – Mini Module'
'Heat-Spreader'
re 6-11: Mini Module Heat-Spreader'
Mounting positions and connector location for Carrier Boards'

Bus for Type 6 and Type 10 in Section 4.3.30 'CAN Bus'

3.0 for Type 10
for USB Client Host detection for Type 10
n for eDP overlayed on LVDS Channel A for Type 6 and Type 10 Modules

wide input voltage range for Mini size Module

tion 4.5 'Signals Requiring Module Termination'

DIO Section 4.3.26 'SDIO', Table 4.31 'SD card interface signals' and Table 4.32 'SDIO Signals, Pin Types, and Descriptions
RESET# and PWR_OK usage

utors
companies were members of the COM Express® subcommittee and participated in developing this specification:

Technology

grated Products
Elektronik GmbH

ms

ologies

Name and Logo Usage

ustrial Computer Manufacturers Group policies regarding the use of its logos and trademarks are as follows:

o use the PICMG® organization logo is automatically granted to designated members only as stipulated on the most recent Membership
riod of time for which their membership dues are paid. Nonmembers may not use the PICMG® organization logo.

® organization logo must be printed in black or color as shown in the files available for download from the member’s side of the Web site
set horizontally and the aspect ratio of the entire logo must be maintained, but the size may be varied. Nothing may be added or delete

rs’ distributors and sales representatives may use the COM Express® logo (but not the PICMG® organization logo) in promoting produc
OM Express® logo is a privilege granted by the PICMG® organization to companies who have purchased the relevant specifications (or
products comply with these specifications. Use of the logos by either members or non-members implies such compliance. PICMG® ma

e COM Express logo is a privilege granted by the PICMG® organization to companies who have purchased the relevant specifications
heir products comply with these specifications. Manufacturers' distributors and sales representatives may use the COM Express logo in
urer. Use of the logos by either members or nonmembers implies such compliance. Only PICMG Executive and Associate members ma
ssion to use logos if they are misused.

press logo can be found on the PICMG web site, www.picmg.org.

press® logo must be used exactly as shown in the files available for download from the PICMG® Web site. The aspect ratios of the log
ng may be added to or deleted from the COM Express® logo.

® name and logo are registered trademarks of PICMG® . Registered trademarks must be followed by the ® symbol, and the following st
ng material in which the logo appears:

COM Express name and logo and the PICMG logo are registered trademarks of the PCI Industrial Computers Manufacturers Group.

press® name and logo are trademarks of PICMG® in process of registration. These trademarks must be followed by the ®
symbol, and
rature and advertising material in which the logo appears:

s and the COM Express logo are trademarks of the PCI Industrial Computers Manufacturers Group.

um draws attention to the fact that it is claimed that compliance with this specification may involve the use of a patent claim(s) ("IPR"). T
idity or scope of this IPR.
ntellectual Property
f this IPR has assured the Consortium that it is willing to license or sublicense all such IPR to those licensees (Members and non-Memb
nt of the holder of this IPR to such effect has been filed with the Consortium.

lso drawn to the possibility that some of the elements of this specification may be the subject of IPR other than those identified below. T
ny or all such IPR.

ation is made as to the availability of any license rights for use of any IPR inherent in this specification for any purpose other than to imp

ation conforms to the current PICMG® Intellectual Property Rights Policy and the Policies and Procedures for Specification Developmen
is not
1 available for licensing
Necessary Claimsunder Reasonable
(referring toand Non-discriminatory
mandatory terms. In the course offeatures)
or recommended Membership Review the following disclo
 following patents, which may cover some aspects of the PICMG® COM Express® Module and Carrier Board Connector as detailed in

6,095,832 “Cap housing for electrical connectors”

6,159,021 “Electrical connector for printed circuit boards”
6,558,195 “Electrical connector for printed circuit boards”
nt 11-040243 “ELECTRICAL CONNECTOR CAP AND ELECTRICAL CONNECTOR ASSEMBLY”
nt 11-074027 “BOARD-MOUNTING TYPE CONNECTOR”
nt 11-260464 “CAP ON ELECTRIC CONNECTOR”
nt 11-354227 “BASE BOARD INSTALLING TYPE CONNECTOR ASSEMBLY”
nt 2000-003751 “SUBSTRATE MOUNTING TYPE CONNECTOR ASSEMBLY”
nt 2000-048876 “ELECTRICAL CONNECTOR FOR CONNECTING MUTUAL BOARDS”

2 Unnecessary Claims(referring to optional features or non-normative elements)

es in this category were made during subcommittee review.
3 Third Party Disclosures
rd party IPR submissions do not contain any claim of willingness to license the IPR.)

es in this category were made during subcommittee review.

MG® IPR Policies and Procedures and the company owner of the patent for terms and conditions of usage.

kes no judgment as to the validity of these claims or the licensing terms offered by the claimants.

FICATION IS BEING OFFERED WITHOUT ANY WARRANTY WHATSOEVER, AND IN PARTICULAR, ANY WARRANTY OF NON-INF
S SPECIFICATION SHALL BE MADE ENTIRELY AT THE IMPLEMENTER'S OWN RISK, AND NEITHER THE CONSORTIUM, NOR A
IABILITY WHATSOEVER TO ANY IMPLEMENTER OR THIRD PARTY FOR ANY DAMAGES OF ANY NATURE WHATSOEVER, DIR
S SPECIFICATION.

with this specification does not absolve manufacturers of COM Express® equipment from the requirements of safety and regulatory age

d the COM Express® logos are trademarks of the PCI Industrial Computer Manufacturers Group.

nd or product names may be trademarks or registered trademarks of their respective holder.

Copyright Notice
0, 2011, 2012 PICMG. All rights reserved. All text, pictures and graphics are protected by copyrights. No copying is permitted without wr

made every attempt to ensure that the information in this document is accurate yet the information contained within is supplied “as-is”.

ntium are registered trademarks of Intel Corporation. ExpressCard is a (PCMCIA). PCI Express is a registered trademark of Peripheral C
xpress is a registered trademark of PCI Industrial Computer Manufacturers Group (PICMG). I2C is a registered trademark of NXP Sem
lash Association.

registered trademark of Winbond Electronics Corp. AVR is a registered trademark of Atmel Corporation. Microsoft®, Windows®, Windo
demarks of Microsoft Corporation. VxWorks is a registered trademark of WindRiver. All product names and logos are property of their o

Special Word Usage

atures are indicated by the use of the word “shall.”

ed features are indicated by the use of the word “should.”

ures are indicated by the use of the word “may.”

Acronyms / Definitions
erms and Definitions
Definition
Audio CODEC (Coder-Decoder)
Advanced Configuration Power Interface – software standard to implement power saving modes in PC-AT systems
COM Express®125mm x 95mm module form factor.
Basic Input Output System – acronym describing the firmware in PC-AT system that is used to initialize system components before han
Controller-area network (CAN or CAN-bus) is a vehicle bus standard designed to allow microcontrollers to communicate w
computer.
An application specific circuit board that accepts a COM Express®module.
Closed Circuit Television
Composite Video Baseband Signal
COM Express™ 95x95 Module form factor
Display Data Control – VESA (Video Electronics Standards Association) standard to allow identification of the capabilities of a VGA mon
Digital Display Interface – containing DisplayPort, HDMI and SDVO
Dual In-line Memory Module
DisplayPort is a digital display interface standard put forth by the Video Electronics Standards Association (VESA). It defin
audio/video interconnect, intended to be used primarily between a computer and its display monitor.
Dynamic Random Access Memory

Digital Visual Interface - a Digital Display Working Group (DDWG) standard that defines a standard video interface supporting both digit

Embedded Application Programming Interface

Software interface for COM Express specific industrial functions
• System information
• Watchdog timer
• I2C Bus
• Flat Panel brightness control
• User storage area
• GPIO
Electrically Erasable Programmable Read-Only Memory
Display Port (eDP) is a digital display interface standard produced by the Video Electronics Standards Association (VESA
COM Express®155mm x 110mm module form factor.
A type of fiber-glass laminate commonly used for printed circuit boards.
Gigabit
Gigabit Ethernet
General Purpose Input
General Purpose Input Output
General Purpose Output
Intel High Definition Audio (HD Audio) refers to the specification released by Intel in 2004 for delivering high definition aud
higher quality than AC97.
High Definition Multimedia Interface
Inter Integrated Circuit – 2 wire (clock and data) signaling scheme allowing communication between integrated circuits, primarily used to
Integrated Device Electronics – parallel interface for hard disk drives – also known as PATA
Relics from the PC-AT computer that are not in use in contemporary PC systems: primarily the ISA bus, UART-based serial ports, paral
vary as to what constitutes a legacy device. Some definitions include IDE as a legacy device.
Local Area Network
Low Pin-Count Interface: a low speed interface used for peripheral circuits such as Super I/O controllers, which typically combine legacy
Least Significant
Low Voltage Differential Signaling – widely used as a physical interface for TFT flat panels. LVDS can be used for many high-speed sig
flat-panel applications.
Management Engine
COM Express® 84x55mm Module form factor
Most Significant
Not Available
 No Connect
National Television Standards Committee – video broadcast standard used in North America
Original Equipment Manufacturer
Phase Alternating Line – video broadcast standard used in many European countries.
Parallel AT Attachment – parallel interface standard for hard-disk drives – also known as IDE, AT Attachment, and as ATA
“Personal Computer – Advanced Technology” – an IBM trademark term used to refer to Intel x86 based personal computers in the 1990
Printed Circuit Board
Peripheral Component Interface
Peripheral Component Interface Express – next-generation high speed Serialized I/O bus
PCI Express Graphics
Ethernet controller physical layer device
A reference to one of five COM Express®definitions for what signals appear on the COM Express®module connector pins
“Personal System 2” - an IBM trademark term used to refer to Intel x86 based personal computers in the 1990s. The term survives as a
that were introduced with the PS2 system.
Roughness Average – a measure of surface roughness, expressed in units of length.
Read Only Memory – a legacy term – often the device referred to as a ROM can actually be written to, in a special mode. Such writable
in ROM or Flash ROM.
Real Time Clock – battery backed circuit in PC-AT systems that keeps system time and date as well as certain system setup parameter
Serial Attached SCSI – high speed serial version of SCSI
Small Computer System Interface – an interface standard for high end disk drives and other computer peripherals
Serial Presence Detect – refers to serial EEPROM on DRAMs that has DRAM module configuration information
Serial Peripheral Interface
Small Outline Dual In-line Memory Module
System states describing the power and activity level S0 Full power, all devices powered S1 S2 S3 Suspend to RAM System context sto
System context stored on disk S5 Soft Off Main power rail off, only standby power rail present
Serial AT Attachment: serial-interface standard for hard disks
Serialized Digital Video Output – Intel defined format for digital video output that can be used with Carrier Board conversion ICs to creat
NTSC and PAL TV outputs
System Management Bus

An integrated circuit, typically interfaced via the LPC bus that provides legacy PC I/O functions including PS2 keyboard and mouse port

Thin Film Transistor – refers to technology used in active matrix flat-panel displays, in which there is one thin film transistor per display p
Transition Minimized Differential Signaling - a digital signaling protocol between the graphics subsystem and display. TMDS is used for
Trusted Platform Module, chip to enhance the security features of a computer system.
Universal Serial Bus
Video Graphics Adapter – PC-AT graphics adapter standard defined by IBM.
Watch Dog Timer.
10 Gigabit / sec Attachment Unit Interface.

Applicable Documents and Standards

 publications are used in conjunction with this standard. When any of the referenced specifications are superseded by an approved rev
m their respective organizations.

Configuration and Power Interface Specification Revision 2.0c, August 25, 2003 Copyright © 1996-2003 Compaq Computer Corporation
s Ltd., Toshiba Corporation. All rights reserved.
nfo/
Configuration and Power Interface Specification Revision 4.0, June 16, 2009 Copyright © 1996-2003 Compaq Computer Corporation, In
s Ltd., Toshiba Corporation. All rights reserved.
cpi.info/
IA-644-A-2001: Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, January 1, 2001.
nsi.org/
S 361-2002: AT Attachment with Packet Interface - 6 (ATA/ATAPI-6), November 1, 2002.
nsi.org/
S 376-2003: American National Standard for Information Technology – Serial Attached SCSI (SAS), October 30, 2003.
nsi.org/
c ’97 Revision 2.3 Revision 1.0, April 2002 Copyright © 2002 Intel Corporation. All rights reserved.
tel.com/labs/media/audio/
a Channel Command Interface (DDC/CI) Standard (formerly DDC2Bi) Version 1, August 14, 1998 Copyright © 1998 Video Electronics S
esa.org/summary/sumddcci.htm
d Standard Release 1.0, December 2003 Copyright © 2003 PCMCIA. All rights reserved.
xpresscard.org/
d® Standard 2.0, June 2009 Copyright © 2009 PCMCIA. All rights reserved.
xpresscard.org/
Definition Audio Specification, Revision 1.0, April 15, 2004 Copyright © 2002 Intel Corporation. All rights reserved.
tel.com/standards/hdaudio/
-2002, IEEE Standard for Information technology, Telecommunications and information exchange between systems—Local and metrop
er Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications.”
ee.org
-2005, IEEE Standard for Information technology, Telecommunications and information exchange between systems-Local and metropo
er Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications.”
ee.org
ae (Amendment to IEEE 802.3-2002), Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and P
s Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation.
ee.org
ae (Amendment to IEEE 802.3-2005), Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and P
s Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation.
ee.org
n Count (LPC) Interface Specification Revision 1.1, August 2002 Copyright © 2002 Intel Corporation. All rights reserved.
per.intel.com/design/chipsets/industry/lpc.htm
s Base Specification Revision 1.1, March 28, 2005, Copyright © 2002-2005 PCI Special Interest Group. All rights reserved.
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s Base Specification Revision 2.0, December 20, 2006, Copyright © 2002- 2006 PCI Special Interest Group. All rights reserved.
cisig.com/
s Card Electromechanical Specification Revision 1.1, March 28, 2005, Copyright © 2002-2005 PCI Special Interest Group. All rights res
cisig.com/
s Card Electromechanical Specification Revision 2.0, April 11, 2007, Copyright © 2002-2007 PCI Special Interest Group. All rights reser
cisig.com/
Bus Specification Revision 2.3, March 29, 2002 Copyright © 1992, 1993, 1995, 1998, 2002 PCI Special Interest Group. All rights reserve
cisig.com/
Bus Specification Revision 3.0, February 3, 2004 Copyright © 1992, 1993, 1995, 1998, and 2004 PCI Special Interest Group. All rights re
cisig.com/
olicies and Procedures for Specification Development, Revision 2.0, September 14, 2004, PCI Industrial Computer Manufacturers Grou
A 01880 USA, Tel: 781.224.1100, Fax: 781.224.1239.
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API - Embedded Application Software Interface Specification, Revision 1.0, 2009, PCI Industrial Computer Manufacturers Group (PICM
SA, Tel: 781.224.1100, Fax: 781.224.1239.
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ure Digital Input/Output SD Specifications Part E1 SDIO Specification Version 2.00, February 8, 2007 Copyright 2007 SD Card Associat
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High Speed Serialized AT Attachment Revision 1.0a January 7, 2003 Copyright © 2000-2003, APT Technologies, Inc., Dell Computer
Seagate Technology LLC. All rights reserved.
ata-io.org/
ery Data Specification Revision 1.1, December 11, 1998.
bs-forum.org
nagement Bus (SMBus) Specification Version 2.0, August 3, 2000 Copyright © 1994, 1995, 1998, 2000 Duracell, Inc., Energizer Power
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tform Module (TPM), Trusted Computing Group Specification 1.2 Revision 103, July 9, 2007,
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ion Multimedia Interface specification version 1.3
dmi.org

1 Statement of Compliance
of compliance with this specification take the form specified in the PICMG® Policies and Procedures for Specification Development:

complies with PICMG® COM.0 Revision 1.0.”

complies with PICMG® COM.0 Revision 2.0 2.1.”

king this simple claim of compliance must provide, at a minimum, all features defined in this specification as being mandatory by the use
Such products may also provide recommended features associated with the keyword “should” and permitted features associated with
specification provides for a number of recommended and permitted features beyond the mandatory minimum set and a wide range of p
mpliance are encouraged.
2 Module Overview
2.1 Module Configuration
Two Three Four module sizes are defined: the Mini Module, Compact Module, Basic Module and the Extended Module. Th
size Module is the over-all physical size and the performance envelope supported by each. The Extended Module is larger
Module, Basic Module and Extended Module use the same connectors and pin-outs whereas the 84x55 Mini Module targe
Type 1 pin-outs. In addition the Mini Module allows for wide range power supply operation. The different size Modules sha
compatibility allows that a carrier board can be designed to accommodate an Extended Module can also support a Basic M
Up to 440 pins of connectivity are available between COM Express® modules and the Carrier Board. Legacy buses such a
serial interconnects such as PCI Express, Serial ATA or SAS, USB 2.0/ 3.0 and Gigabit Ethernet. To enhance interoperab
seven common signaling configurations (Pin-out Types) have been defined to ease system integration. Some Pin-out Type
both 220-pin connectors to supply all the defined signaling.
All Pin-out Type definitions apply to either Compact Module, Basic Module or Extended Module sizes.

2.2 Feature Overview — Size

2.2.1 Mini Module
The Mini Module targets the next generation of mobile applications that require energy saving processors, high-end graphi
• Module size: 84mm x 55mm
• 5mm and 8mm stack height options (Module bottom to Carrier Board top)
• Wide-range power supply input (4.75-20V)
• Suggested pin-out: single 220 pin connector, Type 10
• Reduced Z height for components (optional)
Although not a requirement, Mini Modules are often implemented with memory and SSD storage soldered down on the Mo
systems.

2.2.1 2.2.2 Compact Module

The Compact Module is intended for mobile systems and space-constrained stationary systems. Key features of the Comp
• Module size: 95mm x 95mm
• 5mm and 8mm stack height options (Module bottom to Carrier Board top)
• 18mm ‘z’ height with heat-spreader (using the 5mm stack option)
• Accommodates a single (or two stacked) horizontal mount SO-DIMM
• Single 220 pin or dual 220 pin connectors for up to 440 pins

2.2.2 2.2.3 Basic Module

The Basic Module is intended for mobile systems and space-constrained stationary systems. Key features of the Basic Mo
• Module size: 125 mm x 95 mm
• 5mm and 8 mm stack height options (Module bottom to Carrier Board top)
• 18 mm ‘z’ height with heat-spreader (with 5 mm stack option)
• Accommodates a single (or two stacked) horizontal mount SO-DIMM
• Single 220 pin or dual 220 pin connectors for up to 440 pins

2.2.3 2.2.4 Extended Module

The Extended Module, which targets OEM applications that require larger amounts of system memory, features a larger m
packages.

The key features of the Extended Module include:

• Module size: 155 mm x 110 mm

• 5mm and 8 mm stack height options (Module bottom to Carrier Board top)
• 18 mm ‘z’ height with heat-spreader (using 5 mm stack option)
• Accommodates 2 full-size DIMM or mini DIMM memories or 2 right-angle mount or vertical mount SO-DIMMs
• Single 220 pin or dual 220 pin connectors for up to 440 pins
• Allows for the use of higher performance CPUs that can not be supported on the Compact Module or Basic Module
2.3 Feature Overview - Pin-out Types
2.3.1 Pin-out Type 1
• Single 220 pin connector (A-B connector)
• Up to 8 USB 2.0 ports; 4 shared over-current lines
• Up to 4 Serial ATA or SAS ports
• Up to 6 PCI Express Gen1/Gen2 signaling lanes
• Support pins for up to 2 ExpressCards
• Dual 24-bit LVDS channels
• Analog VGA
• TV Out: Composite Video, S-Video, Component Video (YPbPr)
• AC '97 / HDA digital audio interface (external CODEC(s) required)
• Single Ethernet interface with integrated PHY – pinned for Gigabit Ethernet
• LPC interface
• SPI (SPI support starts with COM.0 R2.0)
• 8 GPIO pins
• 120W 68W maximum input power over module connector pins
• +12V primary power supply input
• +5V standby and 3.3V RTC power supply inputs

2.3.2 Pin-out Type 10

The type 10 (Pin-out Type 10 is not compatible to Type 1-6) Pin-out was introduced with COM Express Rev. 2.0.
• Single 220 pin connector (A-B connector)
• Up to 8 USB 2.0 ports; 4 shared over-current lines
• USB 3.0 support
• USB Client support
• Up to 2 Serial ATA or SAS ports
• Up to 4 PCI Express Gen1/Gen2 signaling lanes
• Support pins for up to 2 ExpressCards
• Single 24-bit LVDS channel with option to overlay with eDP
• One Digital Display Interface configurable asSDVO, DP, or TMDS
• AC '97 / HDA digital audio interface (external CODEC(s) required)
• Single Ethernet interface with integrated PHY – pinned for Gigabit Ethernet
• LPC interface
• Two TX/RX serial pairsts with option to overlay CAN interface
• SPI
• Fan control
• TPM support
• 8 GPIO pins
• 68W maximum input power over Module connector pins
• +12V primary power supply input for Compact, Basic and Extended form factor
• Wide input voltage range for Mini form factor
• +5V standby and 3.3V RTC power supply inputs

2.3.3 Pin-out Type 2

All Pin-out Type 1 features plus the following:
• Dual 220 pin connectors (A-B and C-D, 440 pins total)
• 32 bit PCI interface
• IDE port (to support legacy ATA devices such as CD-ROM drives and Compact Flash storage cards)
• Up to 22 PCI Express lanes (up to 6 on A-B and up to 16 on C-D)
• 16 of 22 PCI Express lanes commonly used for PCI Express Graphics
• SDVO option (pins shared with PCI Express Graphics)
• Maximum module input power capability extended to 188W 137W

2.3.4 Pin-out Type 3

All Pin-out Type 2 features with the exception of the following:
• IDE pins are reallocated to provide additional Gigabit Ethernet capability: no IDE
• Up to 3 Gigabit Ethernet channels
• Option to implement 10 Gigabit Ethernet channel instead of additional 2 Gigabit Ethernet ports

2.3.5 Pin-out Type 4

All Pin-out Type 2 features with the exception of the following:
• PCI pins are reallocated to provide additional PCI Express lanes: no PCI
• Up to 32 PCI Express lanes

2.3.6 Pin-out Type 5

All Pin-out Type 2 features with the exception of the following:
• Both IDE and PCI pins are reallocated: no IDE and no PCI
• Up to 32 PCI Express lanes
• Up to 3 Gigabit Ethernet channels
• Option to implement 10 Gigabit Ethernet channel instead of two additional Gigabit Ethernet ports

2.3.7 Pin-out Type 6

All Pin-out Type 2 features with the exception of the following:
• Both IDE and PCI pins are reallocated: no IDE and no PCI
• Up to 24 PCI Express lanes (16 on the PEG port)
• Reserved 16 pins to support the two extra differential pairs required for SuperSpeed 3.0. The 16 pins will allow SuperSpe
time, there is not enough information and silicon available for this subcommittee to determine the appropriate trace length
in a future version of this document
• Up to 3 Digital Display Interfaces
• Allow eDP overlay of LVDS Channel A
• Two TX/RX serial pairs with option to overlay CAN interface
 Row A Row B
A1 GND (FIXED) B1 GND (FIXED)
A2 GBE0_MDI3- B2 GBE0_ACT#
A3 GBE0_MDI3+ B3 LPC_FRAME#
A4 GBE0_LINK100# B4 LPC_AD0
A5 GBE0_LINK1000# B5 LPC_AD1
A6 GBE0_MDI2- B6 LPC_AD2
A7 GBE0_MDI2+ B7 LPC_AD3
A8 GBE0_LINK# B8 LPC_DRQ0#
A9 GBE0_MDI1- B9 LPC_DRQ1#
A10 GBE0_MDI1+ B10 LPC_CLK
A11 GND (FIXED) B11 GND (FIXED)
A12 GBE0_MDI0- B12 PWRBTN#
A13 GBE0_MDI0+ B13 SMB_CK
A14 GBE0_CTREF B14 SMB_DAT
A15 SUS_S3# B15 SMB_ALERT#
A16 SATA0_TX+ B16 SATA1_TX+
A17 SATA0_TX- B17 SATA1_TX-
A18 SUS_S4# B18 SUS_STAT#
A19 SATA0_RX+ B19 SATA1_RX+
A20 SATA0_RX- B20 SATA1_RX-
A21 GND (FIXED) B21 GND (FIXED)
A22 SATA2_TX+ B22 SATA3_TX+
A23 SATA2_TX- B23 SATA3_TX-
A24 SUS_S5# B24 PWR_OK
A25 SATA2_RX+ B25 SATA3_RX+
A26 SATA2_RX- B26 SATA3_RX-
A27 BATLOW# B27 WDT
A28 ATA_ACT# B28 AC_SDIN2
A29 AC_SYNC B29 AC_SDIN1
A30 AC_RST# B30 AC_SDIN0
A31 GND (FIXED) B31 GND (FIXED)
A32 AC_BITCLK B32 SPKR
A33 AC_SDOUT B33 I2C_CK
A34 BIOS_DISABLE# B34 I2C_DAT
A35 THRMTRIP# B35 THRM#
A36 USB6- B36 USB7-
A37 USB6+ B37 USB7+
A38 USB_6_7_OC# B38 USB_4_5_OC#
A39 USB4- B39 USB5-
A40 USB4+ B40 USB5+
A41 GND (FIXED) B41 GND (FIXED)
A42 USB2- B42 USB3-
A43 USB2+ B43 USB3+
A44 USB_2_3_OC# B44 USB_0_1_OC#
A45 USB0- B45 USB1-
A46 USB0+ B46 USB1+
A47 VCC_RTC B47 EXCD1_PERST#
A48 EXCD0_PERST# B48 EXCD1_CPPE#
A49 EXCD0_CPPE# B49 SYS_RESET#
A50 LPC_SERIRQ B50 CB_RESET#
A51 GND (FIXED) B51 GND (FIXED)
A52 PCIE_TX5+ B52 PCIE_RX5+
A53 PCIE_TX5- B53 PCIE_RX5-
A54 GPI0 B54 GPO1
A55 PCIE_TX4+ B55 PCIE_RX4+
A56 PCIE_TX4- B56 PCIE_RX4-
A57 GND B57 GPO2
A58 PCIE_TX3+ B58 PCIE_RX3+
A59 PCIE_TX3- B59 PCIE_RX3-
A60 GND (FIXED) B60 GND (FIXED)
A61 PCIE_TX2+ B61 PCIE_RX2+
A62 PCIE_TX2- B62 PCIE_RX2-
A63 GPI1 B63 GPO3
A64 PCIE_TX1+ B64 PCIE_RX1+
A65 PCIE_TX1- B65 PCIE_RX1-
A66 GND B66 WAKE0#
A67 GPI2 B67 WAKE1#
A68 PCIE_TX0+ B68 PCIE_RX0+
A69 PCIE_TX0- B69 PCIE_RX0-
A70 GND (FIXED) B70 GND (FIXED)
A71 LVDS_A0+ B71 LVDS_B0+
A72 LVDS_A0- B72 LVDS_B0-
A73 LVDS_A1+ B73 LVDS_B1+
A74 LVDS_A1- B74 LVDS_B1-
A75 LVDS_A2+ B75 LVDS_B2+
A76 LVDS_A2- B76 LVDS_B2-
A77 LVDS_VDD_EN B77 LVDS_B3+
A78 LVDS_A3+ B78 LVDS_B3-
A79 LVDS_A3- B79 LVDS_BKLT_EN
A80 GND (FIXED) B80 GND (FIXED)
A81 LVDS_A_CK+ B81 LVDS_B_CK+
A82 LVDS_A_CK- B82 LVDS_B_CK-
A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL
A84 LVDS_I2C_DAT B84 VCC_5V_SBY
A85 GPI3 B85 VCC_5V_SBY
A86 KBD_RST# B86 VCC_5V_SBY
A87 KBD_A20GATE B87 VCC_5V_SBY
A88 PCIE0_CK_REF+ B88 RSVD
A89 PCIE0_CK_REF- B89 VGA_RED
A90 GND (FIXED) B90 GND (FIXED)
A91 RSVD B91 VGA_GRN
A92 RSVD B92 VGA_BLU
A93 GPO0 B93 VGA_HSYNC
A94 RSVD B94 VGA_VSYNC
A95 RSVD B95 VGA_I2C_CK
A96 GND B96 VGA_I2C_DAT
A97 VCC_12V B97 TV_DAC_A
A98 VCC_12V B98 TV_DAC_B
A99 VCC_12V B99 TV_DAC_C
A100 GND (FIXED) B100 GND (FIXED)
A101 VCC_12V B101 VCC_12V
A102 VCC_12V B102 VCC_12V
A103 VCC_12V B103 VCC_12V
A104 VCC_12V B104 VCC_12V
A105 VCC_12V B105 VCC_12V
A106 VCC_12V B106 VCC_12V
A107 VCC_12V B107 VCC_12V
A108 VCC_12V B108 VCC_12V
A109 VCC_12V B109 VCC_12V
A110 GND (FIXED) B110 GND (FIXED)
 Row A Row B Row C
A1 GND (FIXED) B1 GND (FIXED) C1
A2 GBE0_MDI3- B2 GBE0_ACT# C2
A3 GBE0_MDI3+ B3 LPC_FRAME# C3
A4 GBE0_LINK100# B4 LPC_AD0 C4
A5 GBE0_LINK1000# B5 LPC_AD1 C5
A6 GBE0_MDI2- B6 LPC_AD2 C6
A7 GBE0_MDI2+ B7 LPC_AD3 C7
A8 GBE0_LINK# B8 LPC_DRQ0# C8
A9 GBE0_MDI1- B9 LPC_DRQ1# C9
A10 GBE0_MDI1+ B10 LPC_CLK C10
A11 GND (FIXED) B11 GND (FIXED) C11
A12 GBE0_MDI0- B12 PWRBTN# C12
A13 GBE0_MDI0+ B13 SMB_CK C13
A14 GBE0_CTREF B14 SMB_DAT C14
A15 SUS_S3# B15 SMB_ALERT# C15
A16 SATA0_TX+ B16 SATA1_TX+ C16
A17 SATA0_TX- B17 SATA1_TX- C17
A18 SUS_S4# B18 SUS_STAT# C18
A19 SATA0_RX+ B19 SATA1_RX+ C19
A20 SATA0_RX- B20 SATA1_RX- C20
A21 GND (FIXED) B21 GND (FIXED) C21
A22 SATA2_TX+ B22 SATA3_TX+ C22
A23 SATA2_TX- B23 SATA3_TX- C23
A24 SUS_S5# B24 PWR_OK C24
A25 SATA2_RX+ B25 SATA3_RX+ C25
A26 SATA2_RX- B26 SATA3_RX- C26
A27 BATLOW# B27 WDT C27
A28 ATA_ACT# B28 AC_SDIN2 C28
A29 AC_SYNC B29 AC_SDIN1 C29
A30 AC_RST# B30 AC_SDIN0 C30
A31 GND (FIXED) B31 GND (FIXED) C31
A32 AC_BITCLK B32 SPKR C32
A33 AC_SDOUT B33 I2C_CK C33
A34 BIOS_DISABLE# B34 I2C_DAT C34
A35 THRMTRIP# B35 THRM# C35
A36 USB6- B36 USB7- C36
A37 USB6+ B37 USB7+ C37
A38 USB_6_7_OC# B38 USB_4_5_OC# C38
A39 USB4- B39 USB5- C39
A40 USB4+ B40 USB5+ C40
A41 GND (FIXED) B41 GND (FIXED) C41
A42 USB2- B42 USB3- C42
A43 USB2+ B43 USB3+ C43
A44 USB_2_3_OC# B44 USB_0_1_OC# C44
A45 USB0- B45 USB1- C45
A46 USB0+ B46 USB1+ C46
A47 VCC_RTC B47 EXCD1_PERST# C47
A48 EXCD0_PERST# B48 EXCD1_CPPE# C48
A49 EXCD0_CPPE# B49 SYS_RESET# C49
A50 LPC_SERIRQ B50 CB_RESET# C50
A51 GND (FIXED) B51 GND (FIXED) C51
A52 PCIE_TX5+ B52 PCIE_RX5+ C52
A53 PCIE_TX5- B53 PCIE_RX5- C53
A54 GPI0 B54 GPO1 C54
A55 PCIE_TX4+ B55 PCIE_RX4+ C55
A56 PCIE_TX4- B56 PCIE_RX4- C56
A57 GND B57 GPO2 C57
A58 PCIE_TX3+ B58 PCIE_RX3+ C58
A59 PCIE_TX3- B59 PCIE_RX3- C59
A60 GND (FIXED) B60 GND (FIXED) C60
A61 PCIE_TX2+ B61 PCIE_RX2+ C61
A62 PCIE_TX2- B62 PCIE_RX2- C62
A63 GPI1 B63 GPO3 C63
A64 PCIE_TX1+ B64 PCIE_RX1+ C64
A65 PCIE_TX1- B65 PCIE_RX1- C65
A66 GND B66 WAKE0# C66
A67 GPI2 B67 WAKE1# C67
A68 PCIE_TX0+ B68 PCIE_RX0+ C68
A69 PCIE_TX0- B69 PCIE_RX0- C69
A70 GND (FIXED) B70 GND (FIXED) C70
A71 LVDS_A0+ B71 LVDS_B0+ C71
A72 LVDS_A0- B72 LVDS_B0- C72
A73 LVDS_A1+ B73 LVDS_B1+ C73
A74 LVDS_A1- B74 LVDS_B1- C74
A75 LVDS_A2+ B75 LVDS_B2+ C75
A76 LVDS_A2- B76 LVDS_B2- C76
A77 LVDS_VDD_EN B77 LVDS_B3+ C77
A78 LVDS_A3+ B78 LVDS_B3- C78
A79 LVDS_A3- B79 LVDS_BKLT_EN C79
A80 GND (FIXED) B80 GND (FIXED) C80
A81 LVDS_A_CK+ B81 LVDS_B_CK+ C81
A82 LVDS_A_CK- B82 LVDS_B_CK- C82
A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL C83
A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84
A85 GPI3 B85 VCC_5V_SBY C85
A86 KBD_RST# B86 VCC_5V_SBY C86
A87 KBD_A20GATE B87 VCC_5V_SBY C87
A88 PCIE0_CK_REF+ B88 RSVD C88
A89 PCIE0_CK_REF- B89 VGA_RED C89
A90 GND (FIXED) B90 GND (FIXED) C90
A91 RSVD B91 VGA_GRN C91
A92 RSVD B92 VGA_BLU C92
A93 GPO0 B93 VGA_HSYNC C93
A94 RSVD B94 VGA_VSYNC C94
A95 RSVD B95 VGA_I2C_CK C95
A96 GND B96 VGA_I2C_DAT C96
A97 VCC_12V B97 TV_DAC_A C97
A98 VCC_12V B98 TV_DAC_B C98
A99 VCC_12V B99 TV_DAC_C C99
A100 GND (FIXED) B100 GND (FIXED) C100
A101 VCC_12V B101 VCC_12V C101
A102 VCC_12V B102 VCC_12V C102
A103 VCC_12V B103 VCC_12V C103
A104 VCC_12V B104 VCC_12V C104
A105 VCC_12V B105 VCC_12V C105
A106 VCC_12V B106 VCC_12V C106
A107 VCC_12V B107 VCC_12V C107
A108 VCC_12V B108 VCC_12V C108
A109 VCC_12V B109 VCC_12V C109
A110 GND (FIXED) B110 GND (FIXED) C110
 Row C Row D
GND (FIXED) D1 GND (FIXED)
IDE_D7 D2 IDE_D5
IDE_D6 D3 IDE_D10
IDE_D3 D4 IDE_D11
IDE_D15 D5 IDE_D12
IDE_D8 D6 IDE_D4
IDE_D9 D7 IDE_D0
IDE_D2 D8 IDE_REQ
IDE_D13 D9 IDE_IOW#
IDE_D1 D10 IDE_ACK#
GND (FIXED) D11 GND (FIXED)
IDE_D14 D12 IDE_IRQ
IDE_IORDY D13 IDE_A0
IDE_IOR# D14 IDE_A1
PCI_PME# D15 IDE_A2
PCI_GNT2# D16 IDE_CS1#
PCI_REQ2# D17 IDE_CS3#
PCI_GNT1# D18 IDE_RESET#
PCI_REQ1# D19 PCI_GNT3#
PCI_GNT0# D20 PCI_REQ3#
GND (FIXED) D21 GND (FIXED)
PCI_REQ0# D22 PCI_AD1
PCI_RESET# D23 PCI_AD3
PCI_AD0 D24 PCI_AD5
PCI_AD2 D25 PCI_AD7
PCI_AD4 D26 PCI_C/BE0#
PCI_AD6 D27 PCI_AD9
PCI_AD8 D28 PCI_AD11
PCI_AD10 D29 PCI_AD13
PCI_AD12 D30 PCI_AD15
GND (FIXED) D31 GND (FIXED)
PCI_AD14 D32 PCI_PAR
PCI_C/BE1# D33 PCI_SERR#
PCI_PERR# D34 PCI_STOP#
PCI_LOCK# D35 PCI_TRDY#
PCI_DEVSEL# D36 PCI_FRAME#
PCI_IRDY# D37 PCI_AD16
PCI_C/BE2# D38 PCI_AD18
PCI_AD17 D39 PCI_AD20
PCI_AD19 D40 PCI_AD22
GND (FIXED) D41 GND (FIXED)
PCI_AD21 D42 PCI_AD24
PCI_AD23 D43 PCI_AD26
PCI_C/BE3# D44 PCI_AD28
PCI_AD25 D45 PCI_AD30
PCI_AD27 D46 PCI_IRQC#
PCI_AD29 D47 PCI_IRQD#
PCI_AD31 D48 PCI_CLKRUN#
PCI_IRQA# D49 PCI_M66EN
PCI_IRQB# D50 PCI_CLK
GND (FIXED) D51 GND (FIXED)
PEG_RX0+ D52 PEG_TX0+
PEG_RX0- D53 PEG_TX0-
TYPE0# D54 PEG_LANE_RV#
PEG_RX1+ D55 PEG_TX1+
PEG_RX1- D56 PEG_TX1-
TYPE1# D57 TYPE2#
PEG_RX2+ D58 PEG_TX2+
PEG_RX2- D59 PEG_TX2-
GND (FIXED) D60 GND (FIXED)
PEG_RX3+ D61 PEG_TX3+
PEG_RX3- D62 PEG_TX3-
RSVD D63 RSVD
RSVD D64 RSVD
PEG_RX4+ D65 PEG_TX4+
PEG_RX4- D66 PEG_TX4-
RSVD D67 GND
PEG_RX5+ D68 PEG_TX5+
PEG_RX5- D69 PEG_TX5-
GND (FIXED) D70 GND (FIXED)
PEG_RX6+ D71 PEG_TX6+
PEG_RX6- D72 PEG_TX6-
SDVO_DATA D73 SDVO_CLK
PEG_RX7+ D74 PEG_TX7+
PEG_RX7- D75 PEG_TX7-
GND D76 GND
RSVD D77 IDE_CBLID#
PEG_RX8+ D78 PEG_TX8+
PEG_RX8- D79 PEG_TX8-
GND (FIXED) D80 GND (FIXED)
PEG_RX9+ D81 PEG_TX9+
PEG_RX9- D82 PEG_TX9-
RSVD D83 RSVD
GND D84 GND
PEG_RX10+ D85 PEG_TX10+
PEG_RX10- D86 PEG_TX10-
GND D87 GND
PEG_RX11+ D88 PEG_TX11+
PEG_RX11- D89 PEG_TX11-
GND (FIXED) D90 GND (FIXED)
PEG_RX12+ D91 PEG_TX12+
PEG_RX12- D92 PEG_TX12-
GND D93 GND
PEG_RX13+ D94 PEG_TX13+
PEG_RX13- D95 PEG_TX13-
GND D96 GND
RSVD D97 PEG_ENABLE#
PEG_RX14+ D98 PEG_TX14+
PEG_RX14- D99 PEG_TX14-
GND (FIXED) D100 GND (FIXED)
PEG_RX15+ D101 PEG_TX15+
PEG_RX15- D102 PEG_TX15-
GND D103 GND
VCC_12V D104 VCC_12V
VCC_12V D105 VCC_12V
VCC_12V D106 VCC_12V
VCC_12V D107 VCC_12V
VCC_12V D108 VCC_12V
VCC_12V D109 VCC_12V
GND (FIXED) D110 GND (FIXED)
 Row A Row B
A1 GND (FIXED) B1 GND (FIXED)
A2 GBE0_MDI3- B2 GBE0_ACT#
A3 GBE0_MDI3+ B3 LPC_FRAME#
A4 GBE0_LINK100# B4 LPC_AD0
A5 GBE0_LINK1000# B5 LPC_AD1
A6 GBE0_MDI2- B6 LPC_AD2
A7 GBE0_MDI2+ B7 LPC_AD3
A8 GBE0_LINK# B8 LPC_DRQ0#
A9 GBE0_MDI1- B9 LPC_DRQ1#
A10 GBE0_MDI1+ B10 LPC_CLK
A11 GND (FIXED) B11 GND (FIXED)
A12 GBE0_MDI0- B12 PWRBTN#
A13 GBE0_MDI0+ B13 SMB_CK
A14 GBE0_CTREF B14 SMB_DAT
A15 SUS_S3# B15 SMB_ALERT#
A16 SATA0_TX+ B16 SATA1_TX+
A17 SATA0_TX- B17 SATA1_TX-
A18 SUS_S4# B18 SUS_STAT#
A19 SATA0_RX+ B19 SATA1_RX+
A20 SATA0_RX- B20 SATA1_RX-
A21 GND (FIXED) B21 GND (FIXED)
A22 RSVD* B22 RSVD*
A23 RSVD* B23 RSVD*
A24 SUS_S5# B24 PWR_OK
A25 RSVD* B25 RSVD*
A26 RSVD* B26 RSVD*
A27 BATLOW# B27 WDT
A28 (S)ATA_ACT# B28 AC/HDA_SDIN2
A29 AC/HDA_SYNC B29 AC/HDA_SDIN1
A30 AC/HDA_RST# B30 AC/HDA_SDIN0
A31 GND (FIXED) B31 GND (FIXED)
A32 AC/HDA_BITCLK B32 SPKR
A33 AC/HDA_SDOUT B33 I2C_CK
A34 BIOS_DIS0# B34 I2C_DAT
A35 THRMTRIP# B35 THRM#
A36 USB6- B36 USB7-
A37 USB6+ B37 USB7+
A38 USB_6_7_OC# B38 USB_4_5_OC#
A39 USB4- B39 USB5-
A40 USB4+ B40 USB5+
A41 GND (FIXED) B41 GND (FIXED)
A42 USB2- B42 USB3-
A43 USB2+ B43 USB3+
A44 USB_2_3_OC# B44 USB_0_1_OC#
A45 USB0- B45 USB1-
A46 USB0+ B46 USB1+
A47 VCC_RTC B47 EXCD1_PERST#
A48 EXCD0_PERST# B48 EXCD1_CPPE#
A49 EXCD0_CPPE# B49 SYS_RESET#
A50 LPC_SERIRQ B50 CB_RESET#
A51 GND (FIXED) B51 GND (FIXED)
A52 RSVD* B52 RSVD*
A53 RSVD* B53 RSVD*
A54 GPI0 B54 GPO1
A55 RSVD* B55 RSVD*
A56 RSVD* B56 RSVD*
A57 GND B57 GPO2
A58 PCIE_TX3+ B58 PCIE_RX3+
A59 PCIE_TX3- B59 PCIE_RX3-
A60 GND (FIXED) B60 GND (FIXED)
A61 PCIE_TX2+ B61 PCIE_RX2+
A62 PCIE_TX2- B62 PCIE_RX2-
A63 GPI1 B63 GPO3
A64 PCIE_TX1+ B64 PCIE_RX1+
A65 PCIE_TX1- B65 PCIE_RX1-
A66 GND B66 WAKE0#
A67 GPI2 B67 WAKE1#
A68 PCIE_TX0+ B68 PCIE_RX0+
A69 PCIE_TX0- B69 PCIE_RX0-
A70 GND (FIXED) B70 GND (FIXED)
A71 LVDS_A0+ B71 DDI0_PAIR0+
A72 LVDS_A0- B72 DDI0_PAIR0-
A73 LVDS_A1+ B73 DDI0_PAIR1+
A74 LVDS_A1- B74 DDI0_PAIR1-
A75 LVDS_A2+ B75 DDI0_PAIR2+
A76 LVDS_A2- B76 DDI0_PAIR2-
A77 LVDS_VDD_EN B77 DDI0_PAIR4+
A78 LVDS_A3+ B78 DDI0_PAIR4-
A79 LVDS_A3- B79 LVDS_BKLT_EN
A80 GND (FIXED) B80 GND (FIXED)
A81 LVDS_A_CK+ B81 DDI0_PAIR3+
A82 LVDS_A_CK- B82 DDI0_PAIR3-
A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL
A84 LVDS_I2C_DAT B84 VCC_5V_SBY
A85 GPI3 B85 VCC_5V_SBY
A86 RSVD* B86 VCC_5V_SBY
A87 RSVD* B87 VCC_5V_SBY
A88 PCIE_CLK_REF+ B88 BIOS_DIS1#
A89 PCIE_CLK_REF- B89 DD0_HPD
A90 GND (FIXED) B90 GND (FIXED)
A91 SPI_POWER B91 DDI0_PAIR5+
A92 SPI_MISO B92 DDI0_PAIR5-
A93 GPO0 B93 DDI0_PAIR6+
A94 SPI_CLK B94 DDI0_PAIR6-
A95 SPI_MOSI B95 DDI0_DDC_AUX_SEL
A96 TPM_PP B96 RSVD*
A97 TYPE10# B97 SPI_CS#
A98 SER0_TX B98 DDI0_CTRLCLK_AUX+
A99 SER0_RX B99 DDI0_CTRLDATA_AUX-
 A100 GND (FIXED) B100 GND (FIXED)
A101 SER1_TX B101 FAN_PWMOUT
A102 SER1_RX B102 FAN_TACHIN
A103 LID# B103 SLEEP#
A104 VCC_12V B104 VCC_12V
A105 VCC_12V B105 VCC_12V
A106 VCC_12V B106 VCC_12V
A107 VCC_12V B107 VCC_12V
A108 VCC_12V B108 VCC_12V
A109 VCC_12V B109 VCC_12V
A110 GND (FIXED) B110 GND (FIXED)
* RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD
pins together.
 Row A Row B
A1 GND (FIXED) B1 GND (FIXED)
A2 GBE0_MDI3- B2 GBE0_ACT#
A3 GBE0_MDI3+ B3 LPC_FRAME#
A4 GBE0_LINK100# B4 LPC_AD0
A5 GBE0_LINK1000# B5 LPC_AD1
A6 GBE0_MDI2- B6 LPC_AD2
A7 GBE0_MDI2+ B7 LPC_AD3
A8 GBE0_LINK# B8 LPC_DRQ0#
A9 GBE0_MDI1- B9 LPC_DRQ1#
A10 GBE0_MDI1+ B10 LPC_CLK
A11 GND (FIXED) B11 GND (FIXED)
A12 GBE0_MDI0- B12 PWRBTN#
A13 GBE0_MDI0+ B13 SMB_CK
A14 GBE0_CTREF B14 SMB_DAT
A15 SUS_S3# B15 SMB_ALERT#
A16 SATA0_TX+ B16 SATA1_TX+
A17 SATA0_TX- B17 SATA1_TX-
A18 SUS_S4# B18 SUS_STAT#
A19 SATA0_RX+ B19 SATA1_RX+
A20 SATA0_RX- B20 SATA1_RX-
A21 GND (FIXED) B21 GND (FIXED)
A22 SATA2_TX+ B22 SATA3_TX+
A23 SATA2_TX- B23 SATA3_TX-
A24 SUS_S5# B24 PWR_OK
A25 SATA2_RX+ B25 SATA3_RX+
A26 SATA2_RX- B26 SATA3_RX-
A27 BATLOW# B27 WDT
A28 (S)ATA_ACT# B28 AC/HDA_SDIN2
A29 AC/HDA_SYNC B29 AC/HDA_SDIN1
A30 AC/HDA_RST# B30 AC/HDA_SDIN0
A31 GND (FIXED) B31 GND (FIXED)
A32 AC/HDA_BITCLK B32 SPKR
A33 AC/HDA_SDOUT B33 I2C_CK
A34 BIOS_DIS0# B34 I2C_DAT
A35 THRMTRIP# B35 THRM#
A36 USB6- B36 USB7-
A37 USB6+ B37 USB7+
A38 USB_6_7_OC# B38 USB_4_5_OC#
A39 USB4- B39 USB5-
A40 USB4+ B40 USB5+
A41 GND (FIXED) B41 GND (FIXED)
A42 USB2- B42 USB3-
A43 USB2+ B43 USB3+
A44 USB_2_3_OC# B44 USB_0_1_OC#
A45 USB0- B45 USB1-
A46 USB0+ B46 USB1+
A47 VCC_RTC B47 EXCD1_PERST#
A48 EXCD0_PERST# B48 EXCD1_CPPE#
A49 EXCD0_CPPE# B49 SYS_RESET#
A50 LPC_SERIRQ B50 CB_RESET#
A51 GND (FIXED) B51 GND (FIXED)
A52 PCIE_TX5+ B52 PCIE_RX5+
A53 PCIE_TX5- B53 PCIE_RX5-
A54 GPI0 B54 GPO1
A55 PCIE_TX4+ B55 PCIE_RX4+
A56 PCIE_TX4- B56 PCIE_RX4-
A57 GND B57 GPO2
A58 PCIE_TX3+ B58 PCIE_RX3+
A59 PCIE_TX3- B59 PCIE_RX3-
A60 GND (FIXED) B60 GND (FIXED)
A61 PCIE_TX2+ B61 PCIE_RX2+
A62 PCIE_TX2- B62 PCIE_RX2-
A63 GPI1 B63 GPO3
A64 PCIE_TX1+ B64 PCIE_RX1+
A65 PCIE_TX1- B65 PCIE_RX1-
A66 GND B66 WAKE0#
A67 GPI2 B67 WAKE1#
A68 PCIE_TX0+ B68 PCIE_RX0+
A69 PCIE_TX0- B69 PCIE_RX0-
A70 GND (FIXED) B70 GND (FIXED)
A71 LVDS_A0+ B71 LVDS_B0+
A72 LVDS_A0- B72 LVDS_B0-
A73 LVDS_A1+ B73 LVDS_B1+
A74 LVDS_A1- B74 LVDS_B1-
A75 LVDS_A2+ B75 LVDS_B2+
A76 LVDS_A2- B76 LVDS_B2-
A77 LVDS_VDD_EN B77 LVDS_B3+
A78 LVDS_A3+ B78 LVDS_B3-
A79 LVDS_A3- B79 LVDS_BKLT_EN
A80 GND (FIXED) B80 GND (FIXED)
A81 LVDS_A_CK+ B81 LVDS_B_CK+
A82 LVDS_A_CK- B82 LVDS_B_CK-
A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL
A84 LVDS_I2C_DAT B84 VCC_5V_SBY
A85 GPI3 B85 VCC_5V_SBY
A86 KBD_RST# B86 VCC_5V_SBY
A87 KBD_A20GATE B87 VCC_5V_SBY
A88 PCIE_CLK_REF+ B88 BIOS_DIS1#
A89 PCIE_CLK_REF- B89 VGA_RED
A90 GND (FIXED) B90 GND (FIXED)
A91 SPI_POWER B91 VGA_GRN
A92 SPI_MISO B92 VGA_BLU
A93 GPO0 B93 VGA_HSYNC
A94 SPI_CLK B94 VGA_VSYNC
A95 SPI_MOSI B95 VGA_I2C_CK
A96 GND B96 VGA_I2C_DAT
A97 TYPE10# B97 SPI_CS#
A98 RSVD* B98 RSVD*
A99 RSVD* B99 RSVD*
A100 GND (FIXED) B100 GND (FIXED)
 A101 RSVD* B101 RSVD*
A102 RSVD* B102 RSVD*
A103 RSVD *
B103 RSVD*
A104 VCC_12V B104 VCC_12V
A105 VCC_12V B105 VCC_12V
A106 VCC_12V B106 VCC_12V
A107 VCC_12V B107 VCC_12V
A108 VCC_12V B108 VCC_12V
A109 VCC_12V B109 VCC_12V
A110 GND (FIXED) B110 GND (FIXED)
* RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD
pins together.
 Row A Row B Row C
A1 GND (FIXED) B1 GND (FIXED) C1
A2 GBE0_MDI3- B2 GBE0_ACT# C2
A3 GBE0_MDI3+ B3 LPC_FRAME# C3
A4 GBE0_LINK100# B4 LPC_AD0 C4
A5 GBE0_LINK1000# B5 LPC_AD1 C5
A6 GBE0_MDI2- B6 LPC_AD2 C6
A7 GBE0_MDI2+ B7 LPC_AD3 C7
A8 GBE0_LINK# B8 LPC_DRQ0# C8
A9 GBE0_MDI1- B9 LPC_DRQ1# C9
A10 GBE0_MDI1+ B10 LPC_CLK C10
A11 GND (FIXED) B11 GND (FIXED) C11
A12 GBE0_MDI0- B12 PWRBTN# C12
A13 GBE0_MDI0+ B13 SMB_CK C13
A14 GBE0_CTREF B14 SMB_DAT C14
A15 SUS_S3# B15 SMB_ALERT# C15
A16 SATA0_TX+ B16 SATA1_TX+ C16
A17 SATA0_TX- B17 SATA1_TX- C17
A18 SUS_S4# B18 SUS_STAT# C18
A19 SATA0_RX+ B19 SATA1_RX+ C19
A20 SATA0_RX- B20 SATA1_RX- C20
A21 GND (FIXED) B21 GND (FIXED) C21
A22 SATA2_TX+ B22 SATA3_TX+ C22
A23 SATA2_TX- B23 SATA3_TX- C23
A24 SUS_S5# B24 PWR_OK C24
A25 SATA2_RX+ B25 SATA3_RX+ C25
A26 SATA2_RX- B26 SATA3_RX- C26
A27 BATLOW# B27 WDT C27
A28 (S)ATA_ACT# B28 AC/HDA_SDIN2 C28
A29 AC/HDA_SYNC B29 AC/HDA_SDIN1 C29
A30 AC/HDA_RST# B30 AC/HDA_SDIN0 C30
A31 GND (FIXED) B31 GND (FIXED) C31
A32 AC/HDA_BITCLK B32 SPKR C32
A33 AC/HDA_SDOUT B33 I2C_CK C33
A34 BIOS_DIS0# B34 I2C_DAT C34
A35 THRMTRIP# B35 THRM# C35
A36 USB6- B36 USB7- C36
A37 USB6+ B37 USB7+ C37
A38 USB_6_7_OC# B38 USB_4_5_OC# C38
A39 USB4- B39 USB5- C39
A40 USB4+ B40 USB5+ C40
A41 GND (FIXED) B41 GND (FIXED) C41
A42 USB2- B42 USB3- C42
A43 USB2+ B43 USB3+ C43
A44 USB_2_3_OC# B44 USB_0_1_OC# C44
A45 USB0- B45 USB1- C45
A46 USB0+ B46 USB1+ C46
A47 VCC_RTC B47 EXCD1_PERST# C47
A48 EXCD0_PERST# B48 EXCD1_CPPE# C48
A49 EXCD0_CPPE# B49 SYS_RESET# C49
A50 LPC_SERIRQ B50 CB_RESET# C50
A51 GND (FIXED) B51 GND (FIXED) C51
A52 PCIE_TX5+ B52 PCIE_RX5+ C52
A53 PCIE_TX5- B53 PCIE_RX5- C53
A54 GPI0 B54 GPO1 C54
A55 PCIE_TX4+ B55 PCIE_RX4+ C55
A56 PCIE_TX4- B56 PCIE_RX4- C56
A57 GND B57 GPO2 C57
A58 PCIE_TX3+ B58 PCIE_RX3+ C58
A59 PCIE_TX3- B59 PCIE_RX3- C59
A60 GND (FIXED) B60 GND (FIXED) C60
A61 PCIE_TX2+ B61 PCIE_RX2+ C61
A62 PCIE_TX2- B62 PCIE_RX2- C62
A63 GPI1 B63 GPO3 C63
A64 PCIE_TX1+ B64 PCIE_RX1+ C64
A65 PCIE_TX1- B65 PCIE_RX1- C65
A66 GND B66 WAKE0# C66
A67 GPI2 B67 WAKE1# C67
A68 PCIE_TX0+ B68 PCIE_RX0+ C68
A69 PCIE_TX0- B69 PCIE_RX0- C69
A70 GND (FIXED) B70 GND (FIXED) C70
A71 LVDS_A0+ B71 LVDS_B0+ C71
A72 LVDS_A0- B72 LVDS_B0- C72
A73 LVDS_A1+ B73 LVDS_B1+ C73
A74 LVDS_A1- B74 LVDS_B1- C74
A75 LVDS_A2+ B75 LVDS_B2+ C75
A76 LVDS_A2- B76 LVDS_B2- C76
A77 LVDS_VDD_EN B77 LVDS_B3+ C77
A78 LVDS_A3+ B78 LVDS_B3- C78
A79 LVDS_A3- B79 LVDS_BKLT_EN C79
A80 GND (FIXED) B80 GND (FIXED) C80
A81 LVDS_A_CK+ B81 LVDS_B_CK+ C81
A82 LVDS_A_CK- B82 LVDS_B_CK- C82
A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL C83
A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84
A85 GPI3 B85 VCC_5V_SBY C85
A86 KBD_RST# B86 VCC_5V_SBY C86
A87 KBD_A20GATE B87 VCC_5V_SBY C87
A88 PCIE_CLK_REF+ B88 BIOS_DIS1# C88
A89 PCIE_CLK_REF- B89 VGA_RED C89
A90 GND (FIXED) B90 GND (FIXED) C90
A91 SPI_POWER B91 VGA_GRN C91
A92 SPI_MISO B92 VGA_BLU C92
A93 GPO0 B93 VGA_HSYNC C93
A94 SPI_CLK B94 VGA_VSYNC C94
A95 SPI_MOSI B95 VGA_I2C_CK C95
A96 GND B96 VGA_I2C_DAT C96
A97 TYPE10# B97 SPI_CS# C97
A98 RSVD* B98 RSVD* C98
A99 RSVD* B99 RSVD* C99
A100 GND (FIXED) B100 GND (FIXED) C100
 A101 RSVD* B101 RSVD* C101
A102 RSVD* B102 RSVD* C102
A103 RSVD *
B103 RSVD *
C103
A104 VCC_12V B104 VCC_12V C104
A105 VCC_12V B105 VCC_12V C105
A106 VCC_12V B106 VCC_12V C106
A107 VCC_12V B107 VCC_12V C107
A108 VCC_12V B108 VCC_12V C108
A109 VCC_12V B109 VCC_12V C109
A110 GND (FIXED) B110 GND (FIXED) C110
* RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.
 Row C Row D
GND (FIXED) D1 GND (FIXED)
IDE_D7 D2 IDE_D5
IDE_D6 D3 IDE_D10
IDE_D3 D4 IDE_D11
IDE_D15 D5 IDE_D12
IDE_D8 D6 IDE_D4
IDE_D9 D7 IDE_D0
IDE_D2 D8 IDE_REQ
IDE_D13 D9 IDE_IOW#
IDE_D1 D10 IDE_ACK#
GND (FIXED) D11 GND (FIXED)
IDE_D14 D12 IDE_IRQ
IDE_IORDY D13 IDE_A0
IDE_IOR# D14 IDE_A1
PCI_PME# D15 IDE_A2
PCI_GNT2# D16 IDE_CS1#
PCI_REQ2# D17 IDE_CS3#
PCI_GNT1# D18 IDE_RESET#
PCI_REQ1# D19 PCI_GNT3#
PCI_GNT0# D20 PCI_REQ3#
GND (FIXED) D21 GND (FIXED)
PCI_REQ0# D22 PCI_AD1
PCI_RESET# D23 PCI_AD3
PCI_AD0 D24 PCI_AD5
PCI_AD2 D25 PCI_AD7
PCI_AD4 D26 PCI_C/BE0#
PCI_AD6 D27 PCI_AD9
PCI_AD8 D28 PCI_AD11
PCI_AD10 D29 PCI_AD13
PCI_AD12 D30 PCI_AD15
GND (FIXED) D31 GND (FIXED)
PCI_AD14 D32 PCI_PAR
PCI_C/BE1# D33 PCI_SERR#
PCI_PERR# D34 PCI_STOP#
PCI_LOCK# D35 PCI_TRDY#
PCI_DEVSEL# D36 PCI_FRAME#
PCI_IRDY# D37 PCI_AD16
PCI_C/BE2# D38 PCI_AD18
PCI_AD17 D39 PCI_AD20
PCI_AD19 D40 PCI_AD22
GND (FIXED) D41 GND (FIXED)
PCI_AD21 D42 PCI_AD24
PCI_AD23 D43 PCI_AD26
PCI_C/BE3# D44 PCI_AD28
PCI_AD25 D45 PCI_AD30
PCI_AD27 D46 PCI_IRQC#
PCI_AD29 D47 PCI_IRQD#
PCI_AD31 D48 PCI_CLKRUN#
PCI_IRQA# D49 PCI_M66EN
PCI_IRQB# D50 PCI_CLK
GND (FIXED) D51 GND (FIXED)
PEG_RX0+ D52 PEG_TX0+
PEG_RX0- D53 PEG_TX0-
TYPE0# D54 PEG_LANE_RV#
PEG_RX1+ D55 PEG_TX1+
PEG_RX1- D56 PEG_TX1-
TYPE1# D57 TYPE2#
PEG_RX2+ D58 PEG_TX2+
PEG_RX2- D59 PEG_TX2-
GND (FIXED) D60 GND (FIXED)
PEG_RX3+ D61 PEG_TX3+
PEG_RX3- D62 PEG_TX3-
RSVD* D63 RSVD*
RSVD* D64 RSVD*
PEG_RX4+ D65 PEG_TX4+
PEG_RX4- D66 PEG_TX4-
RSVD* D67 GND
PEG_RX5+ D68 PEG_TX5+
PEG_RX5- D69 PEG_TX5-
GND (FIXED) D70 GND (FIXED)
PEG_RX6+ D71 PEG_TX6+
PEG_RX6- D72 PEG_TX6-
SDVO_DATA D73 SDVO_CLK
PEG_RX7+ D74 PEG_TX7+
PEG_RX7- D75 PEG_TX7-
GND D76 GND
RSVD* D77 IDE_CBLID#
PEG_RX8+ D78 PEG_TX8+
PEG_RX8- D79 PEG_TX8-
GND (FIXED) D80 GND (FIXED)
PEG_RX9+ D81 PEG_TX9+
PEG_RX9- D82 PEG_TX9-
RSVD* D83 RSVD*
GND D84 GND
PEG_RX10+ D85 PEG_TX10+
PEG_RX10- D86 PEG_TX10-
GND D87 GND
PEG_RX11+ D88 PEG_TX11+
PEG_RX11- D89 PEG_TX11-
GND (FIXED) D90 GND (FIXED)
PEG_RX12+ D91 PEG_TX12+
PEG_RX12- D92 PEG_TX12-
GND D93 GND
PEG_RX13+ D94 PEG_TX13+
PEG_RX13- D95 PEG_TX13-
GND D96 GND
RSVD* D97 PEG_ENABLE#
PEG_RX14+ D98 PEG_TX14+
PEG_RX14- D99 PEG_TX14-
GND (FIXED) D100 GND (FIXED)
 PEG_RX15+ D101 PEG_TX15+
PEG_RX15- D102 PEG_TX15-
GND D103 GND
VCC_12V D104 VCC_12V
VCC_12V D105 VCC_12V
VCC_12V D106 VCC_12V
VCC_12V D107 VCC_12V
VCC_12V D108 VCC_12V
VCC_12V D109 VCC_12V
GND (FIXED) D110 GND (FIXED)
VD pins together.
 Row A Row B Row C
A1 GND (FIXED) B1 GND (FIXED) C1
A2 GBE0_MDI3- B2 GBE0_ACT# C2
A3 GBE0_MDI3+ B3 LPC_FRAME# C3
A4 GBE0_LINK100# B4 LPC_AD0 C4
A5 GBE0_LINK1000# B5 LPC_AD1 C5
A6 GBE0_MDI2- B6 LPC_AD2 C6
A7 GBE0_MDI2+ B7 LPC_AD3 C7
A8 GBE0_LINK# B8 LPC_DRQ0# C8
A9 GBE0_MDI1- B9 LPC_DRQ1# C9
A10 GBE0_MDI1+ B10 LPC_CLK C10
A11 GND (FIXED) B11 GND (FIXED) C11
A12 GBE0_MDI0- B12 PWRBTN# C12
A13 GBE0_MDI0+ B13 SMB_CK C13
A14 GBE0_CTREF B14 SMB_DAT C14
A15 SUS_S3# B15 SMB_ALERT# C15
A16 SATA0_TX+ B16 SATA1_TX+ C16
A17 SATA0_TX- B17 SATA1_TX- C17
A18 SUS_S4# B18 SUS_STAT# C18
A19 SATA0_RX+ B19 SATA1_RX+ C19
A20 SATA0_RX- B20 SATA1_RX- C20
A21 GND (FIXED) B21 GND (FIXED) C21
A22 SATA2_TX+ B22 SATA3_TX+ C22
A23 SATA2_TX- B23 SATA3_TX- C23
A24 SUS_S5# B24 PWR_OK C24
A25 SATA2_RX+ B25 SATA3_RX+ C25
A26 SATA2_RX- B26 SATA3_RX- C26
A27 BATLOW# B27 WDT C27
A28 (S)ATA_ACT# B28 AC/HDA_SDIN2 C28
A29 AC/HDA_SYNC B29 AC/HDA_SDIN1 C29
A30 AC/HDA_RST# B30 AC/HDA_SDIN0 C30
A31 GND (FIXED) B31 GND (FIXED) C31
A32 AC/HDA_BITCLK B32 SPKR C32
A33 AC/HDA_SDOUT B33 I2C_CK C33
A34 BIOS_DIS0# B34 I2C_DAT C34
A35 THRMTRIP# B35 THRM# C35
A36 USB6- B36 USB7- C36
A37 USB6+ B37 USB7+ C37
A38 USB_6_7_OC# B38 USB_4_5_OC# C38
A39 USB4- B39 USB5- C39
A40 USB4+ B40 USB5+ C40
A41 GND (FIXED) B41 GND (FIXED) C41
A42 USB2- B42 USB3- C42
A43 USB2+ B43 USB3+ C43
A44 USB_2_3_OC# B44 USB_0_1_OC# C44
A45 USB0- B45 USB1- C45
A46 USB0+ B46 USB1+ C46
A47 VCC_RTC B47 EXCD1_PERST# C47
A48 EXCD0_PERST# B48 EXCD1_CPPE# C48
A49 EXCD0_CPPE# B49 SYS_RESET# C49
A50 LPC_SERIRQ B50 CB_RESET# C50
A51 GND (FIXED) B51 GND (FIXED) C51
A52 PCIE_TX5+ B52 PCIE_RX5+ C52
A53 PCIE_TX5- B53 PCIE_RX5- C53
A54 GPI0 B54 GPO1 C54
A55 PCIE_TX4+ B55 PCIE_RX4+ C55
A56 PCIE_TX4- B56 PCIE_RX4- C56
A57 GND B57 GPO2 C57
A58 PCIE_TX3+ B58 PCIE_RX3+ C58
A59 PCIE_TX3- B59 PCIE_RX3- C59
A60 GND (FIXED) B60 GND (FIXED) C60
A61 PCIE_TX2+ B61 PCIE_RX2+ C61
A62 PCIE_TX2- B62 PCIE_RX2- C62
A63 GPI1 B63 GPO3 C63
A64 PCIE_TX1+ B64 PCIE_RX1+ C64
A65 PCIE_TX1- B65 PCIE_RX1- C65
A66 GND B66 WAKE0# C66
A67 GPI2 B67 WAKE1# C67
A68 PCIE_TX0+ B68 PCIE_RX0+ C68
A69 PCIE_TX0- B69 PCIE_RX0- C69
A70 GND (FIXED) B70 GND (FIXED) C70
A71 LVDS_A0+ B71 LVDS_B0+ C71
A72 LVDS_A0- B72 LVDS_B0- C72
A73 LVDS_A1+ B73 LVDS_B1+ C73
A74 LVDS_A1- B74 LVDS_B1- C74
A75 LVDS_A2+ B75 LVDS_B2+ C75
A76 LVDS_A2- B76 LVDS_B2- C76
A77 LVDS_VDD_EN B77 LVDS_B3+ C77
A78 LVDS_A3+ B78 LVDS_B3- C78
A79 LVDS_A3- B79 LVDS_BKLT_EN C79
A80 GND (FIXED) B80 GND (FIXED) C80
A81 LVDS_A_CK+ B81 LVDS_B_CK+ C81
A82 LVDS_A_CK- B82 LVDS_B_CK- C82
A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL C83
A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84
A85 GPI3 B85 VCC_5V_SBY C85
A86 RSVD* B86 VCC_5V_SBY C86
A87 RSVD* B87 VCC_5V_SBY C87
A88 PCIE_CLK_REF+ B88 BIOS_DIS1# C88
A89 PCIE_CLK_REF- B89 VGA_RED C89
A90 GND (FIXED) B90 GND (FIXED) C90
A91 SPI_POWER B91 VGA_GRN C91
A92 SPI_MISO B92 VGA_BLU C92
A93 GPO0 B93 VGA_HSYNC C93
A94 SPI_CLK B94 VGA_VSYNC C94
A95 SPI_MOSI B95 VGA_I2C_CK C95
A96 TPM_PP B96 VGA_I2C_DAT C96
A97 TYPE10# B97 SPI_CS# C97
 A98 SER0_TX B98 RSVD* C98
A99 SER0_RX B99 RSVD* C99
A100 GND (FIXED) B100 GND (FIXED) C100
A101 SER1_TX B101 FAN_PWMOUT C101
A102 SER1_RX B102 FAN_TACHIN C102
A103 LID# B103 SLEEP# C103
A104 VCC_12V B104 VCC_12V C104
A105 VCC_12V B105 VCC_12V C105
A106 VCC_12V B106 VCC_12V C106
A107 VCC_12V B107 VCC_12V C107
A108 VCC_12V B108 VCC_12V C108
A109 VCC_12V B109 VCC_12V C109
A110 GND (FIXED) B110 GND (FIXED) C110
* RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.
 Row C Row D
GND (FIXED) D1 GND (FIXED)
GND D2 GND
USB_SSRX0- D3 USB_SSTX0-
USB_SSRX0+ D4 USB_SSTX0+
GND D5 GND
USB_SSRX1- D6 USB_SSTX1-
USB_SSRX1+ D7 USB_SSTX1+
GND D8 GND
USB_SSRX2- D9 USB_SSTX2-
USB_SSRX2+ D10 USB_SSTX2+
GND (FIXED) D11 GND (FIXED)
USB_SSRX3- D12 USB_SSTX3-
USB_SSRX3+ D13 USB_SSTX3+
GND D14 GND
DDI1_PAIR6+ D15 DDI1_CTRLCLK_AUX+
DDI1_PAIR6- D16 DDI1_CTRLDATA_AUX-
RSVD* D17 RSVD*
RSVD* D18 RSVD*
PCIE_RX6+ D19 PCIE_TX6+
PCIE_RX6- D20 PCIE_TX6-
GND (FIXED) D21 GND (FIXED)
PCIE_RX7+ D22 PCIE_TX7+
PCIE_RX7- D23 PCIE_TX7-
DDI1_HPD D24 RSVD*
DDI1_PAIR4 + D25 RSVD*
DDI1_PAIR4- D26 DDI1_PAIR0+
RSVD* D27 DDI1_PAIR0-
RSVD* D28 RSVD*
DDI1_PAIR5+ D29 DDI1_PAIR1+
DDI1_PAIR5- D30 DDI1_PAIR1-
GND (FIXED) D31 GND (FIXED)
DDI2_CTRLCLK_AUX+ D32 DDI1_PAIR2+
DDI2_CTRLDATA_AUX- D33 DDI1_PAIR2-
DDI2_DDC_AUX_SEL D34 DDI1_DDC_AUX_SEL
RSVD* D35 RSVD*
DDI3_CTRLCLK_AUX+ D36 DDI1_PAIR3+
DDI3_CTRLDATA_AUX- D37 DDI1_PAIR3-
DDI3_DDC_AUX_SEL D38 RSVD*
DDI3_PAIR0+ D39 DDI2_PAIR0+
DDI3_PAIR0- D40 DDI2_PAIR0-
GND (FIXED) D41 GND (FIXED)
DDI3_PAIR1+ D42 DDI2_PAIR1+
DDI3_PAIR1- D43 DDI2_PAIR1-
DDI3_HPD D44 DDI2_HPD
RSVD* D45 RSVD*
DDI3_PAIR2+ D46 DDI2_PAIR2+
DDI3_PAIR2- D47 DDI2_PAIR2-
RSVD* D48 RSVD*
DDI3_PAIR3+ D49 DDI2_PAIR3+
DDI3_PAIR3- D50 DDI2_PAIR3-
GND (FIXED) D51 GND (FIXED)
PEG_RX0+ D52 PEG_TX0+
PEG_RX0- D53 PEG_TX0-
TYPE0# D54 PEG_LANE_RV#
PEG_RX1+ D55 PEG_TX1+
PEG_RX1- D56 PEG_TX1-
TYPE1# D57 TYPE2#
PEG_RX2+ D58 PEG_TX2+
PEG_RX2- D59 PEG_TX2-
GND (FIXED) D60 GND (FIXED)
PEG_RX3+ D61 PEG_TX3+
PEG_RX3- D62 PEG_TX3-
RSVD* D63 RSVD*
RSVD* D64 RSVD*
PEG_RX4+ D65 PEG_TX4+
PEG_RX4- D66 PEG_TX4-
RSVD* D67 GND
PEG_RX5+ D68 PEG_TX5+
PEG_RX5- D69 PEG_TX5-
GND (FIXED) D70 GND (FIXED)
PEG_RX6+ D71 PEG_TX6+
PEG_RX6- D72 PEG_TX6-
GND D73 GND
PEG_RX7+ D74 PEG_TX7+
PEG_RX7- D75 PEG_TX7-
GND D76 GND
RSVD* D77 RSVD*
PEG_RX8+ D78 PEG_TX8+
PEG_RX8- D79 PEG_TX8-
GND (FIXED) D80 GND (FIXED)
PEG_RX9+ D81 PEG_TX9+
PEG_RX9- D82 PEG_TX9-
RSVD* D83 RSVD*
GND D84 GND
PEG_RX10+ D85 PEG_TX10+
PEG_RX10- D86 PEG_TX10-
GND D87 GND
PEG_RX11+ D88 PEG_TX11+
PEG_RX11- D89 PEG_TX11-
GND (FIXED) D90 GND (FIXED)
PEG_RX12+ D91 PEG_TX12+
PEG_RX12- D92 PEG_TX12-
GND D93 GND
PEG_RX13+ D94 PEG_TX13+
PEG_RX13- D95 PEG_TX13-
GND D96 GND
RSVD* D97 RSVD*
 PEG_RX14+ D98 PEG_TX14+
PEG_RX14- D99 PEG_TX14-
GND (FIXED) D100 GND (FIXED)
PEG_RX15+ D101 PEG_TX15+
PEG_RX15- D102 PEG_TX15-
GND D103 GND
VCC_12V D104 VCC_12V
VCC_12V D105 VCC_12V
VCC_12V D106 VCC_12V
VCC_12V D107 VCC_12V
VCC_12V D108 VCC_12V
VCC_12V D109 VCC_12V
GND (FIXED) D110 GND (FIXED)
VD pins together.
 Row A Row B
A1 GND (FIXED) B1 GND (FIXED)
A2 GBE0_MDI3- B2 GBE0_ACT#
A3 GBE0_MDI3+ B3 LPC_FRAME#
A4 GBE0_LINK100# B4 LPC_AD0
A5 GBE0_LINK1000# B5 LPC_AD1
A6 GBE0_MDI2- B6 LPC_AD2
A7 GBE0_MDI2+ B7 LPC_AD3
A8 GBE0_LINK# B8 LPC_DRQ0#
A9 GBE0_MDI1- B9 LPC_DRQ1#
A10 GBE0_MDI1+ B10 LPC_CLK
A11 GND (FIXED) B11 GND (FIXED)
A12 GBE0_MDI0- B12 PWRBTN#
A13 GBE0_MDI0+ B13 SMB_CK
A14 GBE0_CTREF B14 SMB_DAT
A15 SUS_S3# B15 SMB_ALERT#
A16 SATA0_TX+ B16 SATA1_TX+
A17 SATA0_TX- B17 SATA1_TX-
A18 SUS_S4# B18 SUS_STAT#
A19 SATA0_RX+ B19 SATA1_RX+
A20 SATA0_RX- B20 SATA1_RX-
A21 GND (FIXED) B21 GND (FIXED)
A22 USB_SSRX0-RSVD* B22 USB_SSTX0-RSVD*
A23 USB_SSRX0+RSVD* B23 USB_SSTX0+RSVD*
A24 SUS_S5# B24 PWR_OK
A25 USB_SSRX1-RSVD* B25 USB_SSTX1-RSVD*
A26 USB_SSRX1+RSVD* B26 USB_SSTX1+RSVD*
A27 BATLOW# B27 WDT
A28 (S)ATA_ACT# B28 AC/HDA_SDIN2
A29 AC/HDA_SYNC B29 AC/HDA_SDIN1
A30 AC/HDA_RST# B30 AC/HDA_SDIN0
A31 GND (FIXED) B31 GND (FIXED)
A32 AC/HDA_BITCLK B32 SPKR
A33 AC/HDA_SDOUT B33 I2C_CK
A34 BIOS_DIS0# B34 I2C_DAT
A35 THRMTRIP# B35 THRM#
A36 USB6- B36 USB7-
A37 USB6+ B37 USB7+
A38 USB_6_7_OC# B38 USB_4_5_OC#
A39 USB4- B39 USB5-
A40 USB4+ B40 USB5+
A41 GND (FIXED) B41 GND (FIXED)
A42 USB2- B42 USB3-
A43 USB2+ B43 USB3+
A44 USB_2_3_OC# B44 USB_0_1_OC#
A45 USB0- B45 USB1-
A46 USB0+ B46 USB1+
A47 VCC_RTC B47 EXCD1_PERST#
A48 EXCD0_PERST# B48 EXCD1_CPPE#
A49 EXCD0_CPPE# B49 SYS_RESET#
A50 LPC_SERIRQ B50 CB_RESET#
A51 GND (FIXED) B51 GND (FIXED)
A52 RSVD* B52 RSVD*
A53 RSVD* B53 RSVD*
A54 GPI0 B54 GPO1
A55 RSVD* B55 RSVD*
A56 RSVD* B56 RSVD*
A57 GND B57 GPO2
A58 PCIE_TX3+ B58 PCIE_RX3+
A59 PCIE_TX3- B59 PCIE_RX3-
A60 GND (FIXED) B60 GND (FIXED)
A61 PCIE_TX2+ B61 PCIE_RX2+
A62 PCIE_TX2- B62 PCIE_RX2-
A63 GPI1 B63 GPO3
A64 PCIE_TX1+ B64 PCIE_RX1+
A65 PCIE_TX1- B65 PCIE_RX1-
A66 GND B66 WAKE0#
A67 GPI2 B67 WAKE1#
A68 PCIE_TX0+ B68 PCIE_RX0+
A69 PCIE_TX0- B69 PCIE_RX0-
A70 GND (FIXED) B70 GND (FIXED)
A71 LVDS_A0+ B71 DDI0_PAIR0+
A72 LVDS_A0- B72 DDI0_PAIR0-
A73 LVDS_A1+ B73 DDI0_PAIR1+
A74 LVDS_A1- B74 DDI0_PAIR1-
A75 LVDS_A2+ B75 DDI0_PAIR2+
A76 LVDS_A2- B76 DDI0_PAIR2-
A77 LVDS_VDD_EN B77 DDI0_PAIR4+
A78 LVDS_A3+ B78 DDI0_PAIR4-
A79 LVDS_A3- B79 LVDS_BKLT_EN
A80 GND (FIXED) B80 GND (FIXED)
A81 LVDS_A_CK+ B81 DDI0_PAIR3+
A82 LVDS_A_CK- B82 DDI0_PAIR3-
A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL
A84 LVDS_I2C_DAT B84 VCC_5V_SBY
A85 GPI3 B85 VCC_5V_SBY
A86 RSVD* B86 VCC_5V_SBY
A87 eDP_HPDRSVD* B87 VCC_5V_SBY
A88 PCIE_CLK_REF+ B88 BIOS_DIS1#
A89 PCIE_CLK_REF- B89 DD0_HPD
A90 GND (FIXED) B90 GND (FIXED)
A91 SPI_POWER B91 DDI0_PAIR5+
A92 SPI_MISO B92 DDI0_PAIR5-
A93 GPO0 B93 DDI0_PAIR6+
A94 SPI_CLK B94 DDI0_PAIR6-
A95 SPI_MOSI B95 DDI0_DDC_AUX_SEL
A96 TPM_PP B96 USB_HOST_PRSNTRSVD*
A97 TYPE10# B97 SPI_CS#
A98 SER0_TX B98 DDI0_CTRLCLK_AUX+
A99 SER0_RX B99 DDI0_CTRLDATA_AUX-
 A100 GND (FIXED) B100 GND (FIXED)
A101 SER1_TX B101 FAN_PWMOUT
A102 SER1_RX B102 FAN_TACHIN
A103 LID# B103 SLEEP#
A104 VCC_12V B104 VCC_12V
A105 VCC_12V B105 VCC_12V
A106 VCC_12V B106 VCC_12V
A107 VCC_12V B107 VCC_12V
A108 VCC_12V B108 VCC_12V
A109 VCC_12V B109 VCC_12V
A110 GND (FIXED) B110 GND (FIXED)
* RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD
pins together.
 Row A Row B
A1 GND (FIXED) B1 GND (FIXED)
A2 GBE0_MDI3- B2 GBE0_ACT#
A3 GBE0_MDI3+ B3 LPC_FRAME#
A4 GBE0_LINK100# B4 LPC_AD0
A5 GBE0_LINK1000# B5 LPC_AD1
A6 GBE0_MDI2- B6 LPC_AD2
A7 GBE0_MDI2+ B7 LPC_AD3
A8 GBE0_LINK# B8 LPC_DRQ0#
A9 GBE0_MDI1- B9 LPC_DRQ1#
A10 GBE0_MDI1+ B10 LPC_CLK
A11 GND (FIXED) B11 GND (FIXED)
A12 GBE0_MDI0- B12 PWRBTN#
A13 GBE0_MDI0+ B13 SMB_CK
A14 GBE0_CTREF B14 SMB_DAT
A15 SUS_S3# B15 SMB_ALERT#
A16 SATA0_TX+ B16 SATA1_TX+
A17 SATA0_TX- B17 SATA1_TX-
A18 SUS_S4# B18 SUS_STAT#
A19 SATA0_RX+ B19 SATA1_RX+
A20 SATA0_RX- B20 SATA1_RX-
A21 GND (FIXED) B21 GND (FIXED)
A22 SATA2_TX+ B22 SATA3_TX+
A23 SATA2_TX- B23 SATA3_TX-
A24 SUS_S5# B24 PWR_OK
A25 SATA2_RX+ B25 SATA3_RX+
A26 SATA2_RX- B26 SATA3_RX-
A27 BATLOW# B27 WDT
A28 (S)ATA_ACT# B28 AC/HDA_SDIN2
A29 AC/HDA_SYNC B29 AC/HDA_SDIN1
A30 AC/HDA_RST# B30 AC/HDA_SDIN0
A31 GND (FIXED) B31 GND (FIXED)
A32 AC/HDA_BITCLK B32 SPKR
A33 AC/HDA_SDOUT B33 I2C_CK
A34 BIOS_DIS0# B34 I2C_DAT
A35 THRMTRIP# B35 THRM#
A36 USB6- B36 USB7-
A37 USB6+ B37 USB7+
A38 USB_6_7_OC# B38 USB_4_5_OC#
A39 USB4- B39 USB5-
A40 USB4+ B40 USB5+
A41 GND (FIXED) B41 GND (FIXED)
A42 USB2- B42 USB3-
A43 USB2+ B43 USB3+
A44 USB_2_3_OC# B44 USB_0_1_OC#
A45 USB0- B45 USB1-
A46 USB0+ B46 USB1+
A47 VCC_RTC B47 EXCD1_PERST#
A48 EXCD0_PERST# B48 EXCD1_CPPE#
A49 EXCD0_CPPE# B49 SYS_RESET#
A50 LPC_SERIRQ B50 CB_RESET#
A51 GND (FIXED) B51 GND (FIXED)
A52 PCIE_TX5+ B52 PCIE_RX5+
A53 PCIE_TX5- B53 PCIE_RX5-
A54 GPI0 B54 GPO1
A55 PCIE_TX4+ B55 PCIE_RX4+
A56 PCIE_TX4- B56 PCIE_RX4-
A57 GND B57 GPO2
A58 PCIE_TX3+ B58 PCIE_RX3+
A59 PCIE_TX3- B59 PCIE_RX3-
A60 GND (FIXED) B60 GND (FIXED)
A61 PCIE_TX2+ B61 PCIE_RX2+
A62 PCIE_TX2- B62 PCIE_RX2-
A63 GPI1 B63 GPO3
A64 PCIE_TX1+ B64 PCIE_RX1+
A65 PCIE_TX1- B65 PCIE_RX1-
A66 GND B66 WAKE0#
A67 GPI2 B67 WAKE1#
A68 PCIE_TX0+ B68 PCIE_RX0+
A69 PCIE_TX0- B69 PCIE_RX0-
A70 GND (FIXED) B70 GND (FIXED)
A71 LVDS_A0+ B71 LVDS_B0+
A72 LVDS_A0- B72 LVDS_B0-
A73 LVDS_A1+ B73 LVDS_B1+
A74 LVDS_A1- B74 LVDS_B1-
A75 LVDS_A2+ B75 LVDS_B2+
A76 LVDS_A2- B76 LVDS_B2-
A77 LVDS_VDD_EN B77 LVDS_B3+
A78 LVDS_A3+ B78 LVDS_B3-
A79 LVDS_A3- B79 LVDS_BKLT_EN
A80 GND (FIXED) B80 GND (FIXED)
A81 LVDS_A_CK+ B81 LVDS_B_CK+
A82 LVDS_A_CK- B82 LVDS_B_CK-
A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL
A84 LVDS_I2C_DAT B84 VCC_5V_SBY
A85 GPI3 B85 VCC_5V_SBY
A86 RSVD* B86 VCC_5V_SBY
A87 eDP_HPDRSVD* B87 VCC_5V_SBY
A88 PCIE_CLK_REF+ B88 BIOS_DIS1#
A89 PCIE_CLK_REF- B89 VGA_RED
A90 GND (FIXED) B90 GND (FIXED)
A91 SPI_POWER B91 VGA_GRN
A92 SPI_MISO B92 VGA_BLU
A93 GPO0 B93 VGA_HSYNC
A94 SPI_CLK B94 VGA_VSYNC
A95 SPI_MOSI B95 VGA_I2C_CK
A96 TPM_PP B96 VGA_I2C_DAT
A97 TYPE10# B97 SPI_CS#
 A98 SER0_TX B98 RSVD*
A99 SER0_RX B99 RSVD*
A100 GND (FIXED) B100 GND (FIXED)
A101 SER1_TX B101 FAN_PWMOUT
A102 SER1_RX B102 FAN_TACHIN
A103 LID# B103 SLEEP#
A104 VCC_12V B104 VCC_12V
A105 VCC_12V B105 VCC_12V
A106 VCC_12V B106 VCC_12V
A107 VCC_12V B107 VCC_12V
A108 VCC_12V B108 VCC_12V
A109 VCC_12V B109 VCC_12V
A110 GND (FIXED) B110 GND (FIXED)
* RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.
 Row C Row D
C1 GND (FIXED) D1 GND (FIXED)
C2 GND D2 GND
C3 USB_SSRX0- D3 USB_SSTX0-
C4 USB_SSRX0+ D4 USB_SSTX0+
C5 GND D5 GND
C6 USB_SSRX1- D6 USB_SSTX1-
C7 USB_SSRX1+ D7 USB_SSTX1+
C8 GND D8 GND
C9 USB_SSRX2- D9 USB_SSTX2-
C10 USB_SSRX2+ D10 USB_SSTX2+
C11 GND (FIXED) D11 GND (FIXED)
C12 USB_SSRX3- D12 USB_SSTX3-
C13 USB_SSRX3+ D13 USB_SSTX3+
C14 GND D14 GND
C15 DDI1_PAIR6+ D15 DDI1_CTRLCLK_AUX+
C16 DDI1_PAIR6- D16 DDI1_CTRLDATA_AUX-
C17 RSVD* D17 RSVD*
C18 RSVD* D18 RSVD*
C19 PCIE_RX6+ D19 PCIE_TX6+
C20 PCIE_RX6- D20 PCIE_TX6-
C21 GND (FIXED) D21 GND (FIXED)
C22 PCIE_RX7+ D22 PCIE_TX7+
C23 PCIE_RX7- D23 PCIE_TX7-
C24 DDI1_HPD D24 RSVD*
C25 DDI1_PAIR4 + D25 RSVD*
C26 DDI1_PAIR4- D26 DDI1_PAIR0+
C27 RSVD* D27 DDI1_PAIR0-
C28 RSVD* D28 RSVD*
C29 DDI1_PAIR5+ D29 DDI1_PAIR1+
C30 DDI1_PAIR5- D30 DDI1_PAIR1-
C31 GND (FIXED) D31 GND (FIXED)
C32 DDI2_CTRLCLK_AUX+ D32 DDI1_PAIR2+
C33 DDI2_CTRLDATA_AUX- D33 DDI1_PAIR2-
C34 DDI2_DDC_AUX_SEL D34 DDI1_DDC_AUX_SEL
C35 RSVD* D35 RSVD*
C36 DDI3_CTRLCLK_AUX+ D36 DDI1_PAIR3+
C37 DDI3_CTRLDATA_AUX- D37 DDI1_PAIR3-
C38 DDI3_DDC_AUX_SEL D38 RSVD*
C39 DDI3_PAIR0+ D39 DDI2_PAIR0+
C40 DDI3_PAIR0- D40 DDI2_PAIR0-
C41 GND (FIXED) D41 GND (FIXED)
C42 DDI3_PAIR1+ D42 DDI2_PAIR1+
C43 DDI3_PAIR1- D43 DDI2_PAIR1-
C44 DDI3_HPD D44 DDI2_HPD
C45 RSVD* D45 RSVD*
C46 DDI3_PAIR2+ D46 DDI2_PAIR2+
C47 DDI3_PAIR2- D47 DDI2_PAIR2-
C48 RSVD* D48 RSVD*
C49 DDI3_PAIR3+ D49 DDI2_PAIR3+
C50 DDI3_PAIR3- D50 DDI2_PAIR3-
C51 GND (FIXED) D51 GND (FIXED)
C52 PEG_RX0+ D52 PEG_TX0+
C53 PEG_RX0- D53 PEG_TX0-
C54 TYPE0# D54 PEG_LANE_RV#
C55 PEG_RX1+ D55 PEG_TX1+
C56 PEG_RX1- D56 PEG_TX1-
C57 TYPE1# D57 TYPE2#
C58 PEG_RX2+ D58 PEG_TX2+
C59 PEG_RX2- D59 PEG_TX2-
C60 GND (FIXED) D60 GND (FIXED)
C61 PEG_RX3+ D61 PEG_TX3+
C62 PEG_RX3- D62 PEG_TX3-
C63 RSVD* D63 RSVD*
C64 RSVD* D64 RSVD*
C65 PEG_RX4+ D65 PEG_TX4+
C66 PEG_RX4- D66 PEG_TX4-
C67 RSVD* D67 GND
C68 PEG_RX5+ D68 PEG_TX5+
C69 PEG_RX5- D69 PEG_TX5-
C70 GND (FIXED) D70 GND (FIXED)
C71 PEG_RX6+ D71 PEG_TX6+
C72 PEG_RX6- D72 PEG_TX6-
C73 GND D73 GND
C74 PEG_RX7+ D74 PEG_TX7+
C75 PEG_RX7- D75 PEG_TX7-
C76 GND D76 GND
C77 RSVD* D77 RSVD*
C78 PEG_RX8+ D78 PEG_TX8+
C79 PEG_RX8- D79 PEG_TX8-
C80 GND (FIXED) D80 GND (FIXED)
C81 PEG_RX9+ D81 PEG_TX9+
C82 PEG_RX9- D82 PEG_TX9-
C83 RSVD* D83 RSVD*
C84 GND D84 GND
C85 PEG_RX10+ D85 PEG_TX10+
C86 PEG_RX10- D86 PEG_TX10-
C87 GND D87 GND
C88 PEG_RX11+ D88 PEG_TX11+
C89 PEG_RX11- D89 PEG_TX11-
C90 GND (FIXED) D90 GND (FIXED)
C91 PEG_RX12+ D91 PEG_TX12+
C92 PEG_RX12- D92 PEG_TX12-
C93 GND D93 GND
C94 PEG_RX13+ D94 PEG_TX13+
C95 PEG_RX13- D95 PEG_TX13-
C96 GND D96 GND
C97 RSVD* D97 RSVD*
 C98 PEG_RX14+ D98 PEG_TX14+
C99 PEG_RX14- D99 PEG_TX14-
C100 GND (FIXED) D100 GND (FIXED)
C101 PEG_RX15+ D101 PEG_TX15+
C102 PEG_RX15- D102 PEG_TX15-
C103 GND D103 GND
C104 VCC_12V D104 VCC_12V
C105 VCC_12V D105 VCC_12V
C106 VCC_12V D106 VCC_12V
C107 VCC_12V D107 VCC_12V
C108 VCC_12V D108 VCC_12V
C109 VCC_12V D109 VCC_12V
C110 GND (FIXED) D110 GND (FIXED)
ins together.
3 Required and Optional Features
3.1 Module Pin-out Type Definitions
Five Six pin-out types are defined. Pin-out Type 1 and Type 10 modules have a single 220-pin connector, the A-B connect
designated A-B and C-D, for a total of 440 pins. The variations in Pin-out Type definitions are summarized in the table belo
Table 3.1: Module Pin-out Type Overview
Types Connector Rows PCI Express Lanes PEG / SDVO PCI
Type 1 A-B Up to 6 - -
Type 2 A-B C-D Up to 22 1/2 32 bit

Type 3 A-B C-D Up to 22 1/2 32 bit

Type 4 A-B C-D Up to 32 1/2 -

Type 5 A-B C-D Up to 32 1/2 -

Type 6 A-B C-D Up to 24 1 / NA -

Type 10 A-B Up to 4 -/1 -

For module Pin-out Types 2 through 5 6, a subset of the PCI Express lanes are commonly used as PCI Express Graphics
Types 2-5. In Type 6 SDVO is moved from the PEG to Digital Display Interface DDI1.Type 10 does feature one Digital Dis
Type 1 modules allow for a minimal possible feature set using two of the four available connector rows. Type 1 represents
Board to allow a lower layer count board.
Type 10 Modules are similar but not compatible completely to Type 1 Modules. These Modules feature less PCI Express a
panel interface , and a single Digital Display Interface DDI and an DP overlayed on LVDS Channel A and an option to allow
USB 3.0.

Type 2 modules include PCI and IDE interfaces. These modules either use on board graphics capabilities or may use 16 P
graphics, PEG pins may be alternatively used for two SDVO ports.
Type 3 modules trade IDE port pins for two additional LAN ports, allowing up to three GBE interfaces, or one GBE and on
Type 4 modules drop the PCI interface, to allow up to 32 PCI Express lanes for applications with large I/O bandwidth requ
Type 5 modules trade IDE and PCI pins for up to 32 PCI Express lanes and up to three GBE interfaces, or one GBE and o
applications with large I/O bandwidth requirements.
Type 6 Modules trade IDE and PCI pins for up to 8 PCI Express lanes, up to three Digital Display Interfaces DDI and 4 of
a single or dual channel 18/24 bit LVDS panel interface, three DDIs and an eDP overlayed on LVDS Channel A and an op
* The SuperSpeed USB ports are not in addition to the USB 2.0 ports. Up to 4 of the USB 2.0 ports can support SuperSpe
** Digital Display Interface
gle 220-pin connector, the A-B connector. Module Pin-out Types 2 through 5 6 use a pair of 220 pin connectors,
itions are summarized in the table below.
.1: Module Pin-out Type Overview
USB 2.0 / Display
IDE Ports SATA Ports LAN Ports
SuperSpeed USB Interfaces
- 4 1 8/0 VGA, LVDS
VGA, LVDS,
1 4 1 8/0
PEG/SDVO
VGA, LVDS,
- 4 3 8/0
PEG/SDVO
VGA, LVDS,
1 4 1 8/0
PEG/SDVO
VGA, LVDS,
- 4 3 8/0
PEG/SDVO
VGA, LVDS/eDP,
- 4 1 8 / 4*
PEG,3xDDI**
LVDS/ eDP,
- 2 1 8/02
1xDDI

mmonly used as PCI Express Graphics (PEG) lanes. SDVO functions may be pin-shared with PEG lanes on
1.Type 10 does feature one Digital Display Interface DDI but no PEG lanes.
ble connector rows. Type 1 represents a basic feature set with the benefit of simplified routing of the Carrier

se Modules feature less PCI Express and SATA interfaces. Type 10 Modules support a single 24 bit LVDS
LVDS Channel A and an option to allow a CAN bus to share SER1 pins. 2 of the 8 USB ports can be used as

d graphics capabilities or may use 16 PEG lanes to connect to an external video controller. In case of on board

e GBE interfaces, or one GBE and one 10 Gigabit LAN interface.

lications with large I/O bandwidth requirements. IDE support is still available.
ree GBE interfaces, or one GBE and one 10 Gigabit LAN interface. These modules are intended for

Digital Display Interfaces DDI and 4 of the 8 USB ports can be used as USB 3.0. Type 6 Modules support
erlayed on LVDS Channel A and an option to allow a CAN bus to share SER1 pins.
USB 2.0 ports can support SuperSpeed USB
3.2 Module Pin-out Types 1-5 6 & 10 — Required and Optional Features
COM Express® Required and Optional features are summarized in the following table. The features identified as Minimum (Min.) shall be implemented by all modules. Features id
be additionally implemented by a module.
Table 3.2: Module Pin-out Types 1-5 — Required and Optional Features
Type 1
(Single Type 2
Note connector)
Min / Max Min / Max
System I/O
1 PCI Express Graphics (PEG) NA 0/1
2 PCI Express Lanes 0 - 5 2/6 2/6
2 PCI Express Lanes 6-15 NA NA
2 PCI Express Lanes 16-31 (same as PEG pins) NA 0 / 16
3 SDVO Channels NA 0/2
4 LVDS Channels 0/2 0/2
5 VGA Port 0/1 0/1
6 TV-Out 0/1 0/1
7 PATA Port NA 1/1
8 SATA / SAS Ports 2/4 2/4
9 AC’97 Digital Interface 0/1 0/1
10 USB 2.0 Ports 4/8 4/8
11 LAN 0 (10/100Base-T min) 1/1 1/1
11 LAN 1 (10/100Base-T min) NA NA
11 LAN 2 (10/100Base-T min) NA NA
12 PCI Bus - 32 Bit NA 1/1
13 Express Card Support 1/2 1/2
14 LPC Bus 1/1 1/1
System Management
15 General Purpose Inputs 4/4 4/4
15 General Purpose Outputs 4/4 4/4
16 SMBus 1/1 1/1
17 I2C 1/1 1/1
18 Watch Dog Timer 0/1 0/1
19 Speaker Out 1/1 1/1
20 External BIOS ROM support 0/1 0/1
21 Reset Functions 1/1 1/1
Power Management
22 Thermal Protection 0/1 0/1
23 Battery Low Alarm 0/1 0/1
24 Suspend 0/1 0/1
 25 Wake 0/2 0/2
26 Power Button Support 1/1 1/1
27 Power Good 1/1 1/1
1. PCI Express Graphics (PEG). These signals may be multiplexed with SDVO signals or defined as ordinary PCI Express signals. The PEG lanes are the same lanes as PCI Exp
2. The number of available PCI Express lanes varies with the module Pin-out Type. If the module supports off-module x16 PCI Express Graphics, then PCI Express Lanes 16-31
3. SDVO. Serial Digital Video Output to LVDS or TMDS transmitters on the Carrier Board. These signals, if implemented, shall be multiplexed with PEG signals.

4. LVDS. Low voltage differential signaling flat-panel interface. The module pin-out allows two single channel display interfaces (each with 1 pixel per clock) with up to 24 bits per c
channel display (2 pixels per clock) with up to 24 bits per color, 48 bits per clock is allowed. Includes panel backlight control and EDID support.

5. VGA. Analog RGB interface for CRT monitor and DDC support.
6. If TV-Out is supported, then Composite Video shall be available. Component and S-Video may also be available.
7. PATA. Parallel ATA support for up to 2 devices in a master/slave configuration. This signaling interface is limited to ATA100 speeds. Higher (ATA133) speeds are not defined. P
out Type 3 and 5 modules for 2 additional GB Ethernet interfaces.

8. SATA / SAS. Serial ATA links for support of existing SATA-150 and emerging SATA-300 devices. Alternatively, this interface may be used for Serial Attached SCSI (SAS). SAS
byte in the Carrier Board configuration EE-PROM (see Section 5.3).
9. AC ’97. The AC ’97 audio codec interface is limited to support a single AC ’97 link. High Definition Audio may be supported.
10. USB. All USB interfaces shall be USB 2.0 compliant. The minimum of 4 USB channels provides support for keyboard, mouse, CD/DVD drive, and one additional device. Note
the actual carrier usage of the USB port is undefined by this specification.

11. LAN. Up to 3 Gigabit Ethernet ports are defined, designated GBE0 through GBE2. The ports may operate in 10, 100, or 1000 Mbit/sec modes. The ports are analog-encoded
isolation magnetics. Magnetics are assumed to be on the Carrier Board. All COM Express® modules shall implement at least one 10/100 Ethernet port on the GBE0 pin slot. Port
combined to form a 10 Gigabit / sec Ethernet interface.
12. PCI. The PCI bus interface is specified to be a 32-bit PCI 2.3 compliant bus with speed options of 33MHz or 66MHz.
13. ExpressCard is a small form factor expansion card for mobile systems that uses PCI Express or USB as the interface. It is similar in concept and scope to CardBus. COM Exp
support functions for at least one ExpressCard. This does not mean that a module PCI Express lane or USB link are specifically allocated to ExpressCard use, but it does mean th
ExpressCard detection and support are present.
14. LPC bus. The LPC bus provides legacy I/O support on a Carrier Board via a Super I/O and system-management devices.
15. General Purpose Input and Output pins. GPI and GPO pins may be implemented as GPIO (module specific).

16. SMBus. The SMBus port is specified for system management functions. It is used on the module to mange system functions such as reading the DRAM SPD EEPROM and s
parameters. Off module, the SMBus should be used carefully. It may be useful for implementation on the Carrier Board of standards such as Smart Battery.

17. I2C. The I2C port shall be available in addition to the SMBus.
18. Watch Dog Timer (WDT). Refer to Section 5.8 for details.
19. Speaker Out. This port provides the PC beep signal and is mostly intended for debugging purposes.
20. External BIOS ROM. A module pin, BIOS_DISABLE#, may be provided by the module hardware. If the function is supported, then the Carrier Board may pull the BIOS_DISAB
module BIOS ROM, allowing the module to boot from a BIOS ROM implemented on the Carrier Board.
21. Resets. This function includes reset signals to and from the module. Signals SYS_RESET#, CB_RESET# and KBD_RST# shall be supported for all module pin-out types. Sig
supported for pin-out types 2 and 3. Signal IDE_RESET# shall be supported for pin-out types 2 and 4. Additionally, signal PWR_OK should be an input term that keeps the modu

22. Thermal Protection. This port provides thermal signaling to protect critical components on the module and the Carrier Board.
23. Battery Low Alarm. This port provides a battery-low signal to the module for orderly transitioning to power saving or power cut-off ACPI modes.

24. Suspend. This port defines the signaling to indicate that the module has entered the ACPI power-saving mode S3 (Suspend-To-RAM or STR), S4 (Suspend-To-Disk or STD),

25. Wake. This port defines the signaling to wake up the module from a power saving mode. Most prevalent choices for these signals are RING# and LID#, although other choices

26. Power Button. This port defines the signaling for powering down the module.
27. Power Good. This port defines the signaling for the correct power conditions to proceed with normal startup of the module.
COM Express® Required and Optional features are summarized in the following table. The features identified as Minimum (Min.) shall be implemented by all modules. Features id
be additionally implemented by a module.
Change Key: Green = Generic R2.0, Blue = Type 10 only, Violet = Type 10 & Type 6 only , Red = Type 6 only
Table 3.2: Module Pin-out Types 1-6 - Required and Optional Features A-B Connector
Type 10 Type 1 Type 2 Type 3
Connector Feature (Single connector) (Single connector) (IDE + PCI) (No IDE)
Min / Max Min / Max Min / Max Min / Max
A-B System I/O
A-B PCI Express Lanes 0 -5 1/4 1/6 1/6 1/6
A-B LVDS Channel A 0/1 0/1 0/1 0/1
A-B LVDS Channel B NA 0/1 0/1 0/1
A-B eDP on LVDS CH A pins 0/1 NA NA NA
A-B VGA Port NA 0/1 0/1 0/1
A-B TV-Out NA NA NA NA
A-B Digital Display Interface DDI 0 0/1 NA NA NA
A-B* Serial Ports 1 -2 ** 0/2 NA NA NA
A-B CAN interface on SER1 0/1 NA NA NA
A-B SATA / SAS Ports 1/2 1/4 1/4 1/4
A-B AC’97 / HDA Digital Interface 0/1 0/1 0/1 0/1
A-B USB 2.0 Ports 4/8 4/8 4/8 4/8
A-B USB Client 0/1 0/1 0/1 0/1
A-B USB 3.0 Ports 0/2 NA NA NA
A-B LAN Port 0 1/1 1/1 1/1 1/1
A-B Express Card Support 0/2 1/2 1/2 1/2
A-B LPC Bus 1/1 1/1 1/1 1/1
A-B SPI 1/2 1/2 1/2 1/2
A-B System Management
 SDIO (muxed on GPIO) 0/1 NA NA NA
A-B**
General Purpose I/O 8/8 8/8 8/8 8/8
A-B SMBus 1/1 1/1 1/1 1/1
A-B I2C 1/1 1/1 1/1 1/1
A-B Watchdog Timer 0/1 0/1 0/1 0/1
A-B Speaker Out 1/1 1/1 1/1 1/1
A-B External BIOS ROM Support 0/2 0/2 0/2 0/2
A-B Reset Functions 1/1 1/1 1/1 1/1
A-B Power Management
A-B Thermal Protection 0/1 0/1 0/1 0/1
A-B Battery Low Alarm 0/1 0/1 0/1 0/1
A-B Suspend/Wake Signals 0/3 0/3 0/3 0/3
A-B Power Button Support 1/1 1/1 1/1 1/1
A-B Power Good 1/1 1/1 1/1 1/1
A-B VCC_5V_SBY Contacts 4/4 4/4 4/4 4/4
A-B* Sleep Inputs 0/1 NA NA NA
A-B* Lid Inputs 0/1 NA NA NA
A-B* Fan PWM/Tachometer 0/2 NA NA NA
A-B Trusted Platform Modules 0/1 NA NA NA

A-B Power
A-B VCC_12V Contacts 12 / 12 12 / 12 12 / 12 12 / 12
Module Pin-out Types 1-6 - Required and Optional Features C-D Connector
Type 1
Feature Type 10 Type 2 Type 3
(Single
Connector (** indicates 12V-tolerant features on former (Single connector) (IDE + PCI) (No IDE)
connector)
VCC_12V signals)
Min / Max Min / Max Min / Max Min / Max
C-D System I/O
PCI Express Lanes 16 -31 NA NA 0 /16 0 /16
C-D** PCI Express Graphics (PEG) NA NA 0/1 0/1
Muxed SDVO Channels 1 -2 NA NA 0/2 0/2
PCI Express Lanes 6 -15 NA NA NA NA
PCI Bus -32 Bit NA NA 1/1 1/1
PATA Port NA NA 1/1 NA
C-D**
LAN Ports 1 -2 NA NA NA 0/2
Digital Display Interfaces DDIs 1 -3 NA NA NA NA
USB 3.0 Ports NA NA NA NA

C-D Power
C-D VCC_12V Contacts NA NA 12 / 12 12 / 12
* Indicates 12V-tolerant features on former VCC_12V signals.
** Cells in the Connector column spanning rows provide a rough approximation of features sharing connector pins.
emented by all modules. Features identified up to Maximum (Max) may

es
Type 3 Type 4 Type 5
(No IDE) (No PCI) (No IDE, No PCI)
Min / Max Min / Max Min / Max

0/1 0/1 0/1

2/6 2/6 2/6
NA 0 / 10 0 / 10
0 / 16 0 / 16 0 / 16
0/2 0/2 0/2
0/2 0/2 0/2
0/1 0/1 0/1
0/1 0/1 0/1
NA 1/1 NA
2/4 2/4 2/4
0/1 0/1 0/1
4/8 4/8 4/8
1/1 1/1 1/1
0/1 NA 0/1
0/1 NA 0/1
1/1 NA NA
1/2 1/2 1/2
1/1 1/1 1/1

4/4 4/4 4/4

4/4 4/4 4/4
1/1 1/1 1/1
1/1 1/1 1/1
0/1 0/1 0/1
1/1 1/1 1/1
0/1 0/1 0/1
1/1 1/1 1/1

0/1 0/1 0/1

0/1 0/1 0/1
0/1 0/1 0/1
 0/2 0/2 0/2
1/1 1/1 1/1
1/1 1/1 1/1
anes are the same lanes as PCI Express lanes 16-31.
cs, then PCI Express Lanes 16-31 shall be used to implement this.
with PEG signals.

xel per clock) with up to 24 bits per color. Alternatively, one dual

(ATA133) speeds are not defined. PATA signal pins are reused in Pin-

or Serial Attached SCSI (SAS). SAS operation may be indicated by a

ve, and one additional device. Note that this usage is not required and

des. The ports are analog-encoded GBE signals, post PHY but without
rnet port on the GBE0 pin slot. Ports GBE1 and GBE2 may be

pt and scope to CardBus. COM Express® modules shall provide

xpressCard use, but it does mean that the module pins for

ng the DRAM SPD EEPROM and setting clock synthesizer

Smart Battery.

ier Board may pull the BIOS_DISABLE# pin low to disable the on-
ted for all module pin-out types. Signal PCI_RESET# shall be
e an input term that keeps the module in a reset condition if low.

des.

R), S4 (Suspend-To-Disk or STD), or S5 (Soft-Off).

G# and LID#, although other choices can be implemented.

emented by all modules. Features identified up to Maximum (Max) may

onnector
Type 5 Type 6
Type 4
(No IDE, No PCI) (No IDE or PCI,
(No PCI)
add DDI + USB3)
Min / Max Min / Max Min / Max

1/6 1/6 1/6

0/1 0/1 0/1
0/1 0/1 0/1
NA NA 0/1
0/1 0/1 0/1
NA NA NA
NA NA NA
NA NA 0/2
NA NA 0/1
1/4 1/4 1/4
0/1 0/1 0/1
4/8 4/8 4/8
0/1 0/1 0/1
NA NA NA
1/1 1/1 1/1
1/2 1/2 1/2
1/1 1/1 1/1
1/2 1/2 1/2
 NA NA 0/1
8/8 8/8 8/8
1/1 1/1 1/1
1/1 1/1 1/1
0/1 0/1 0/1
1/1 1/1 1/1
0/2 0/2 0/2
1/1 1/1 1/1

0/1 0/1 0/1

0/1 0/1 0/1
0/3 0/3 0/3
1/1 1/1 1/1
1/1 1/1 1/1
4/4 4/4 4/4
NA NA 0/1
NA NA 0/1
NA NA 0/2
NA NA 0/1

12 / 12 12 / 12 12 / 12
ctor
Type 5 Type 6
Type 4
(No IDE, No PCI) (No IDE or PCI,
(No PCI)
add DDI + USB3)
Min / Max Min / Max Min / Max

0 /16 0 /16 0 /16

0/1 0/1 0/1
0/2 0/2 NA
0 / 10 0 / 10 0/2
NA NA NA
1/1 NA NA
NA 0/2 NA
NA NA 0/3
NA NA 0/4

12 / 12 12 / 12 12 / 12
3.3 COM Express® Module Feature Fill Order
COM Express® allows a variable number of ports to be implemented for several interfaces, per Table 3.2 and Table 3.3 ab
Table 3.4: Module Feature Fill Order
Feature

Express Card Support

LAN

LVDS

SATA / SAS

SDVO

USB 2.0 Host

USB 2.0 Client

USB 3.0 SuperSpeed (The number of USB 2.0 channels must be equal
to or greater than the number of USB 3.0 channels)

Digital Display InterfaceDDI

The COM Express® PCI Express lanes also have a prescribed fill order, described in Section 5.2, “PCI Express Link Confi
7The number of USB 2.0 channels must be equal to or greater than the number of USB 3.0 channels
ill Order
ented for several interfaces, per Table 3.2 and Table 3.3 above. Ports shall be populated in a “low to high” manner, per the following ta
Table 3.4: Module Feature Fill Order
Number of Ports

1
2

1
2
3

1
2

2
3
4

1
2

4
5
6
7
8

1
2
3
4

1
2
3
fill order, described in Section 5.2, “PCI Express Link Configuration Guidelines.”
than the number of USB 3.0 channels
le 3.3 above. Ports shall be populated in a “low to high” manner, per the following table.
Order
Fill Order

EXCD 0
EXCD 0,1

GBE channel 0
GBE channels 0,1
GBE channels 0,1,2

LVDS channel A
LVDS channels A,B

SATA / SAS channels 0,1

SATA / SAS channels 0,1,2
SATA / SAS channels 0,1,2,3

SDVO channel B
SDVO channels B,C

USB channels 0,1,2,3

USB channels 0,1,2,3,4
USB channels 0,1,2,3,4,5
USB channels 0,1,2,3,4,5,6
USB channels 0,1,2,3,4,5,6,7

USB channel 7

USB channel 0
USB channels 0,1
USB channels 0,1,2
USB channels 0,1,2,3

Digital Display InterfaceDDI 1

Digital Display InterfaceDDI 2
Digital Display InterfaceDDI 3
nk Configuration Guidelines.” on page 78 96.
3.3 EAPI - Embedded Application Programming Interface
All COM Express modules should should support the Revision 1.0 of the PICMG defined Software API EAPI. This API allows f
Addressed functions are:
• System information
• Watchdog timer
• I2C Bus
• Flat Panel brightness control
• User storage area
• GPIO
4 Signal Descriptions
4.1 Signal Naming Convention
REQ#
TX+, TX-
A[0:31]
CBE[0:3]#
4.2 Pin and Signal Buffer Types
Pin and Buffer type definitions apply to the signals in the Signal List
4.2.1 Pin Types
I
O
I/O
OD
4.2.2 Buffer Types
CMOS

PCIE

PCI
SATA
LVDS
USB
REF
PDS
Analog
Power
4.2.3 Power Rails and Tolerances
Pins are marked in the following table Section section 4.3 'Signal List' with the power rail associated with the pin, and, for i
pin input voltage tolerance may be different. For example, the PCI group is defined as having a 3.3V power rail, meaning t
signals.

An additional label, “Suspend” indicates that the pin is active during suspend states (S3,S4,S5). If suspend modes are use
suspend to avoid excessive suspend mode current draw.

4.3 Signal List

COM Express® signal descriptions are described in the following table. The Pin Availability column in the table indicates in
6 and 10 are designated T1,T2,T3,T4,T5,T6,T10 in the Pin Availability column. A notation of “All” indicates that the signal i
4.4 Signals Requiring Carrier Board Termination
Some signals, detailed below, require Carrier Board termination for proper operation. If the signals and the feature are not

4.5 Signals Requiring Module Termination

The signals below might require Module termination if used. They are mentioned to provide guidance to both the Module a
feature is not implemented on the Module.
4.5.1 AC coupled on the Module
The following signals shall be AC coupled on the Module.
• SDVO[B:C]_RED+/-
• SDVO[B:C]_GRN+/-
• SDVO[B:C]_BLU+/-
• SDVO[B:C]_CK+/-
• SATA[0:3]TX+/-
• SATA[0:3]RX+/-
• PCIE_TX[0:31]+/-
• PEG_TX[0:15]+/-
• USB_SSTX[0:3]+/-

4.5.2 Misc
The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 2
• LVDS_I2C_CK
• LVDS_I2C_DAT
• I2C_CK
• I2C_DAT
• VGA_I2C_CK
• VGA_I2C_DAT
The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 4
• IDE_IORDY

The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 8
• PCI_IRQ[A:D]#
• PCI_IRDY#
• PCI_LOCK#
• PCI_PERR#
• PCI_REQ[0:3]#
• PCI_SERR#
• PCI_STOP#
• PCI_TRDY#
• PCI_FRAME#
• PCI_CLKRUN#
• LPC_SERIRQ

The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 1
• KBD_A20GATE
• KBD_RST#
• BIOS_[0:1]DISABLE#
• EXCD[0:1]_CPPE#
• FAN_TACHIN

The Module shall provide the termination for the signals below. The following signal should be pulled-up to 3.3V Standby
• WAKE0#
The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V Standb
• I2C_CK
• I2C_DAT
• SMB_CK
• SMB_DAT
The Module shall provide the termination for the signals below. The following signalsn should be pulled-up to 3.3V Stand
• USB_[0,2,4,6]_[1,3,5,7]_OC#
• SYS_RESET#
• BATLOW#
• PWRBTN
• WAKE0#
• WAKE1#
• PCI_PME#
• PWRBTN#
• SLEEP#
• LID#
Module termination of IDE_IRQ is dependent on the controller used. The Module
When supporting Carrier Board based SPI devices, the SPI_MISO line
Modules implementing a TPM shall pull down TPM_PP. The value of the pull down resistor will be mModule specific. Carr
features that require physical presence detection should be activated are implemented.
The PWR_OK signal should be terminated by the Module designer. If the signal is driven low by the Carrier Board the Mo
high by the Carrier Board, and Module hardware determines that the incoming power is good then the Module power supp

4.6 Pin-out Tables

Pin-out information for Module pin-out Types 1–
al Descriptions
nal Naming Convention
Active-low signals are indicated by a trailing ‘#’ sign:
Differential pairs are indicated by trailing ‘+’ and ‘-‘ signs:
Bused signals are indicated by brackets, with LS bit first, MS bit last:
Bus brackets may appear anywhere in the signal name:
and Signal Buffer Types
er type definitions apply to the signals in the Signal List Section section below.
Types
Input to the module
Output from the module
Bi-directional input / output signal
Open drain output
fer Types
Logic input or output. Input thresholds and output levels shall be 80% of supply rail for high side and 20% of the relevant s
PCI Express compatible differential signal. Please refer to the PCI Express Specification for details. PCIE transmit pins (m
PCIE receive pins (module inputs) shall be DC coupled on the COM Express® module and shall be assumed to be AC co
target PCI Express device resides on the Carrier Board, the module PCIE receive lanes (target PCIE device transmit lanes
Board. If the Carrier Board implements a PCIE slot, then these signals shall be AC coupled on the add-in card, not on the
PCI 2.3 compatible signal. Please refer to the PCI Rev. 2.3 Specification for details.
SATA compatible differential signal. Please refer to the SATA Specification for details. All COM Express® SATA signals sh
Low Voltage Differential Signal – 330mV nominal; 450mV maximum differential signal.
USB 2.0 compatible differential signal. Please refer to the USB 2.0 Specification for details.
Reference voltage output. May be sourced from a module power plane.
Pull-down strap. A module output pin that is either tied to GND or is not connected. Used to signal module capabilities to th
Inputs and Outputs used for LAN, VGA and TV OUT are analog signals.
Inputs used for power delivery to the module electronics.
wer Rails and Tolerances
ked in the following table Section section 4.3 'Signal List' with the power rail associated with the pin, and, for input and I/O pins, with the
age tolerance may be different. For example, the PCI group is defined as having a 3.3V power rail, meaning that the output signals will

label, “Suspend” indicates that the pin is active during suspend states (S3,S4,S5). If suspend modes are used, then care must be take
void excessive suspend mode current draw.

nal List
s® signal descriptions are described in the following table. The Pin Availability column in the table indicates in which Pin-out Types the
designated T1,T2,T3,T4,T5,T6,T10 in the Pin Availability column. A notation of “All” indicates that the signal is available to all module P
nals Requiring Carrier Board Termination
s, detailed below, require Carrier Board termination for proper operation. If the signals and the feature are not used, no Carrier Board te

nals Requiring Module Termination

below might require Module termination if used. They are mentioned to provide guidance to both the Module and Carrier designer. Thes
implemented on the Module.
coupled on the Module
 signals shall be AC coupled on the Module.
_RED+/-
_GRN+/-
_BLU+/-
_CK+/-
X+/-
RX+/-
:31]+/-
15]+/-
[0:3]+/-

c
shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 2.2kΩ resistor
_CK
_DAT

CK
DAT
shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 4.7kΩ resistor
Y

shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 8.2kΩ resistor
D]#

#
#
:3]#
#
#
#
E#
UN#
RQ

shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 10kΩ resistor
ATE

DISABLE#
_CPPE#
HIN

shall provide the termination for the signals below. The following signal should be pulled-up to 3.3V Standby with a 1.2kΩ resistor

shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V Standby with a 2.2kΩ resistor
shall provide the termination for the signals below. The following signalsn should be pulled-up to 3.3V Standby with a 10kΩ resistor
,6]_[1,3,5,7]_OC#
ET#

nation of IDE_IRQ is dependent on the controller used. The Module shall provide the necessary termination.
rting Carrier Board based SPI devices, the SPI_MISO line shall have a series resistor of 33Ω.
ementing a TPM shall pull down TPM_PP. The value of the pull down resistor will be mModule specific. Carriers Boards that support T
require physical presence detection should be activated are implemented.
K signal should be terminated by the Module designer. If the signal is driven low by the Carrier Board the Module power supplies do no
Carrier Board, and Module hardware determines that the incoming power is good then the Module power supplies proceed with their star

out Tables
mation for Module pin-out Types 1–5 6 and 10 are provided in the five seven tables on the following pages.
5 Module and Carrier Board Implementation Specifications
5.1 PCI Express Link Configuration Definitions
Lane: A “lane” or “PCI Express lane” is a set of 4 pins on the COM Express® connector that can be used for a single PCI Express transmit pair and a single receive pair. Clocking
data stream.
Link: A “link” or “PCI Express link” is a group of PCI Express lanes between two PCI Express agents. Allowable link widths are x1, x2, x4, x8, x16 and x32. An x1 link utilizes 1 lan
bandwidth scales up proportionally with the link width.
Link Configuration: The COM Express® connector allows up to 32 PCI Express lanes to be used. The count varies with the module Pin-out Type. Chipsets used on COM Expre
Express lane and link capabilities. On some chipsets, the PCI Express lanes can be grouped into various links under software control; on other chipsets, the PCI Express links are
the chipset PCI Express lanes to the COM Express® lanes and the grouping of the lanes into links is referred to as “link configuration.”
Bucket: A “bucket” is a group of 8 PCI Express lanes on the COM Express® connector. The 32 PCI Express lanes on the COM Express® connector are conceptually divided into
facilitate a description of how the available PCI Express lanes should be assigned to COM Express® connector pins. The “bucket” terminology is only a vehicle to facilitate the de
orderly mapping of chipset PCI Express lanes to COM Express® connector PCI Express lanes. A bucket is not a link.

5.2 PCI Express Link Configuration Guidelines

The COM Express® connector PCI Express lanes are conceptually divided into four “buckets,” labeled B1, B2, B3, and B4. The buckets shall be filled according to the following r
• The fill starts from the lowest lane number in a bucket and proceeds upwards.
• The largest links go into the lower lane numbers in a bucket.
• Links that are 16 lanes wide shall span buckets B3 and B4 or buckets B1 and B2.
• PCI Express Graphics (PEG) link(s) shall use B3 and B4 for the first link and shall use B1 and B2 for a 2nd link.
• Links that span more than one bucket shall start in the bucket with the lowest lane number.
 Table 5.1: PCI Express Lane Numbers and Bucket Groupings
COM Express® Bucket
Lane Number
Pin Label Reference
PCIE 31PEG15 31
PCIE 30PEG14 30
PCIE 29PEG13 29
PCIE 28PEG12 28
Bucket B4
PCIE 27PEG11 27
PCIE 26PEG10 26
PCIE 25PEG9 25
PCIE 24PEG8 24
PCIE 23PEG7 23
PCIE 22PEG6 22
PCIE 21PEG5 21
PCIE 20PEG4 20
Bucket B3
PCIE 19PEG3 19
PCIE 18PEG2 18
PCIE 17PEG1 17
PCIE 16PEG0 16
PCIE 15 15
PCIE 14 14
PCIE 13 13
PCIE 12 12
Bucket B2
PCIE 11 11
PCIE 10 10
PCIE 9 9
PCIE 8 8
PCIE 7 7
PCIE 6 6
PCIE 5 5
PCIE 4 4
Bucket B1
PCIE 3 3
PCIE 2 2
PCIE 1 1
PCIE 0 0

While many permutations are possible, the set of tables below indicate the preferred mappings of chipset PCI Express lanes and links to COM Express® connector lanes and link
On most module designs, a portion of available COM Express® PCI Express lanes are used.
rd Implementation Specifications
ration Definitions
pins on the COM Express® connector that can be used for a single PCI Express transmit pair and a single receive pair. Clocking information is embedded into the

CI Express lanes between two PCI Express agents. Allowable link widths are x1, x2, x4, x8, x16 and x32. An x1 link utilizes 1 lane; a x2 link 2 lanes, etc. The link
dth.
tor allows up to 32 PCI Express lanes to be used. The count varies with the module Pin-out Type. Chipsets used on COM Express® modules have a variety of PCI
ets, the PCI Express lanes can be grouped into various links under software control; on other chipsets, the PCI Express links are of a fixed width. The mapping of
s® lanes and the grouping of the lanes into links is referred to as “link configuration.”
nes on the COM Express® connector. The 32 PCI Express lanes on the COM Express® connector are conceptually divided into 4 buckets to
press lanes should be assigned to COM Express® connector pins. The “bucket” terminology is only a vehicle to facilitate the description of an
COM Express® connector PCI Express lanes. A bucket is not a link.

ration Guidelines
are conceptually divided into four “buckets,” labeled B1, B2, B3, and B4. The buckets shall be filled according to the following rules:
bucket and proceeds upwards.
in a bucket.
B3 and B4 or buckets B1 and B2.
3 and B4 for the first link and shall use B1 and B2 for a 2nd link.
t in the bucket with the lowest lane number.
Express Lane Numbers and Bucket Groupings

Availability By Module Pin-out Type

Module Pin-out Types 2,3,4,5

(PCI Express Graphics)
Module Pin-out Types 2,3,4,5
(PCI Express, general I/O)

Module Pin-out Type 4,5

Module Pin-out Type 4,5,6

Module Pin-out Types 1,2,3,4,5,6

Module Pin-out Types 1,2,3,4,5,6,10

tables below indicate the preferred mappings of chipset PCI Express lanes and links to COM Express® connector lanes and links.
OM Express® PCI Express lanes are used.
 COM Express®
Lane Number Bucket Reference Preferred
Pin Label
PCIE 31PEG15 31
PCIE 30PEG14 30
PCIE 29PEG13 29
PCIE 28PEG12 28
B4
PCIE 27PEG11 27
PCIE 26PEG10 26
PCIE 25PEG9 25
PCIE 24PEG8 24
PCIE 23PEG7 23
PCIE 22PEG6 22
PCIE 21PEG5 21
PCIE 20PEG4 20
B3
PCIE 19PEG3 19
PCIE 18PEG2 18
PCIE 17PEG1 17
PCIE 16PEG0 16
PCIE 15 15
PCIE 14 14
PCIE 13 13
PCIE 12 12
B2
PCIE 11 11
PCIE 10 10
PCIE 9 9
PCIE 8 8
PCIE 7 7
PCIE 6 6
PCIE 5 5
PCIE 4 4
B1
PCIE 3 3
PCIE 2 2 X1
PCIE 1 1 X1 X1
PCIE 0 0 X1 X1

Note: Grey shaded lanes are not available in Pin-out Type 1.

 Preferred Link Configurations

X1 X1
X1 X1 X1 X1
X1 X1 X1
X1 X1 X1
X4 X4 X4
X1 X1 X1
X1 X1 X1
COM Express® Lane Bucket
Preferred Link Configurations
Pin Label Number Reference
PCIE 31PEG15 31
PCIE 30PEG14 30
PCIE 29PEG13 29
PCIE 28PEG12 28
B4
PCIE 27PEG11 27
PCIE 26PEG10 26
PCIE 25PEG9 25
PCIE 24PEG8 24 X16
PCIE 23PEG7 23 (PEG)
PCIE 22PEG6 22
PCIE 21PEG5 21
PCIE 20PEG4 20
B3
PCIE 19PEG3 19
PCIE 18PEG2 18
PCIE 17PEG1 17
PCIE 16PEG0 16
PCIE 15 15
PCIE 14 14
PCIE 13 13
PCIE 12 12
B2
PCIE 11 11
PCIE 10 10
PCIE 9 9
PCIE 8 8
PCIE 7 7
PCIE 6 6
PCIE 5 5 X1 X1
PCIE 4 4 X1 X1 X1 X1
B1
PCIE 3 3 X1 X1 X1
PCIE 2 2 X1 X1 X1 X1
X4 X4 X4
PCIE 1 1 X1 X1 X1 X1 X1
PCIE 0 0 X1 X1 X1 X1 X1

1) Grey shaded lanes are not available in Pin-out Types 2 and 3.

2) If upper lanes (buckets B3 and B4) are not used for PCI Express Graphics (PEG), then lanes mapped into buckets B3 and B4 should be grouped
per Table 5-4.
COM Express® Lane Bucket
Preferred Link Configurations
Pin Label Number Reference
PCIE 31PEG15 31
PCIE 30PEG14 30
X4 X4
PCIE 29PEG13 29
PCIE 28PEG12 28
B4 X8
PCIE 27PEG11 27
PCIE 26PEG10 26
X4 X4
PCIE 25PEG9 25
PCIE 24PEG8 24 X16
PCIE 23PEG7 23 (PEG)
PCIE 22PEG6 22
X4
PCIE 21PEG5 21
PCIE 20PEG4 20
B3 X8 X8
PCIE 19PEG3 19
PCIE 18PEG2 18
X4
PCIE 17PEG1 17
PCIE 16PEG0 16
PCIE 15 15
PCIE 14 14
PCIE 13 13
PCIE 12 12
B2
PCIE 11 11
PCIE 10 10
PCIE 9 9
PCIE 8 8
PCIE 7 7
PCIE 6 6
PCIE 5 5
PCIE 4 4
B1
PCIE 3 3
SeeRefer to bucket B1
PCIE 2 2
PCIE 1 1
PCIE 0 0

1) Grey shaded lanes are not available in Pin-out Types 2 and 3.

2) Bucket B1 groupings for Pin-out Types 2 and 3 covered in Table 5-3.
3) X16 link may be used for PCI Express Graphics (PEG) or for general purpose I/O.
 COM Express® Lane Bucket
Preferred Link Configura
Pin Label Number Reference
PEG15 31
PEG14 30
PEG13 29
PEG12 28
B4
PEG11 27
PEG10 26
PEG9 25
PEG8 24 X16
PEG7 23 (PEG)
PEG6 22
PEG5 21
PEG4 20
B3
PEG3 19
PEG2 18
PEG1 17
PEG0 16
PCIE 15 15
PCIE 14 14
PCIE 13 13
PCIE 12 12
B2
PCIE 11 11
PCIE 10 10
PCIE 9 9
PCIE 8 8
PCIE 7 7
PCIE 6 6
PCIE 5 5
PCIE 4 4 X1
B1
PCIE 3 3 X1 X1
PCIE 2 2 X1 X1 X1
X4
PCIE 1 1 X1 X1 X1 X1
PCIE 0 0 X1 X1 X1 X1
Notes:
3) Lanes 6 and 7 only available on Type 6
4) Grey shaded lanes are not available in Pin-out Types 2 and 3.
5) If upper lanes (buckets B3 and B4) are not used for PCI Express Graphics (PEG), then lanes mapped into buckets B3 and B
Type 6 - Preferred Lane Groupings: Buckets B3 and B4' on page 85103.
 COM Express® Lane
Preferred Link Configurations
Pin Label Number
PEG15 31
PEG14 30
PEG13 29
PEG12 28
PEG11 27
PEG10 26
PEG9 25
X16 PEG8 24
(PEG) PEG7 23
PEG6 22
PEG5 21
PEG4 20
PEG3 19
PEG2 18
PEG1 17
PEG0 16
PCIE 15 15
PCIE 14 14
PCIE 13 13
PCIE 12 12
PCIE 11 11
PCIE 10 10
PCIE 9 9
PCIE 8 8
X1 X1 PCIE 7 7
X1 X1 X1 PCIE 6 6
X4
X1 X1 X1 X1 PCIE 5 5
X1 X1 X1 X1 X1 PCIE 4 4
X8
X1 X1 X1 PCIE 3 3
X1 X1 X1 PCIE 2 2
X4 X4 X4
X1 X1 X1 PCIE 1 1
X1 X1 X1 PCIE 0 0
Notes:
1) Grey shaded lanes are not available in Pin-o
2) Bucket B1 groupings for Pin-out Types 2, 3
anes mapped into buckets B3 and B4 should be grouped per Table 5.7 'Module Pin-out
3) X16 link may be used for PCI Express Grap
 Bucket
Preferred Link Configurations
Reference

X4 X4

B4 X8

X4 X4

X4

B3 X8 X8

X4

B2

B1 SeeRefer to bucket B1 in Table 5.6

are not available in Pin-out Types 2 and 3.

gs for Pin-out Types 2, 3 and 6 covered in Table 5.6 'Module Pin-out Type 6 - Preferred Lane Groupings: Bucket B1' on page
sed for PCI Express Graphics (PEG) or for general purpose I/O.
ations

X8

X16
(PEG)

X8

able 5.6

: Bucket B1' on page 84102.

4.3.15 Digital Display Interface (DDI) - Modules Type 6 and Type 10
Module Types 6 and 10 use Digital Display Interfaces (DDI) to provide DisplayPort, HDMI/DVI, and SDVO interfaces. Type 10
Modules can contain up to 3 DDIs (DDI[1:3]) of which DDI[1:3] can support DisplayPort, HDMI/DVI and DDI[1] can support Dis
Modules and DDI[1] for Type 6 Modules.

This specification leverages the work done by VESA to provide guidance on how a Carrier might support DP or HDMI/DVI from
same circuit that VESA shows in the cable adapter for a direct connect HDMI/DVI interface. The DisplayPort Interoperability G
at http://www.vesa.org/Standards/free.htmhttp://www.vesa.org/vesa-standards/free-standards. The VESA specification uses th
this is equivalent to a Module DDI. Figure 4-1 shows an example of a possible circuit that can be used on a Moduleshows a co

Figure 4-1: Dual-Mode COM Express M

Table 4.16 'Module and Carrier Combinations' provides an idea of the type orof circuit that might be necessary for Carriers sup
Table 4.16: Module and Carrier Combinatio
Module Carrier / Cable Adapter Requirements
None -Straight through to DP receptacle
DP only
N/A – not a valid combination
N/A – not a valid combination
DVI/HDMI
None -Straight through to DVI/HDMI receptacle
None -Straight through to DP receptacle
Dual Mode
Level shifters on DDC before DVI/HDMI connector. (Optional level shifters on data, per module requ
Requirements
Module DDI[0] may support any combination of DisplayPort, DVI/HDMI and SDVO.
Module DDI[1] may support any combination of DisplayPort, DVI/HDMI and SDVO.
Module DDI[2:3] may support any combination of DisplayPort and DVI/HDMI.
Module DDI ports should support more than DVI/HDMI.
Module that support Dual-Mode DDI interface shall implement the necessary muxing
circuitry and control logic to ensure that the module works properly with carriers expecting
DisplayPort or DVI/HDMI.
Modules shall meet the voltage and tolerance requirements as defined in the Signals, Pin
Types, and Descriptions. This may require that a Module contain level shifters.

The pin map uses a generic name for the Digital Display InterfaceDDI pins. Table 4.19 below, details the mapping between the
Table 4.17: Type 6 DDI Signals, Pin Ty
Digital display InterfaceDDI Pin Type Pwr Rail / Tolerance
DDI[1:3]_PAIR[0:3]+ O
AC coupled off Module
DDI[1:3]_PAIR[0:3]- PCIE

I
DDI[1:3]_DDC_AUX_SEL 3.3V / 3.3V
CMOS

I/O
AC coupled on Module
PCIE
DDI[1:3]_CLTRCLK_AUX+
I/O OD
3.3V / 3.3V
CMOS
I/O
AC coupled on Module
PCIE
DDI[1:3]_CTRLDATA_AUX-
I/O OD
3.3V / 3.3V
CMOS
I
DDI[1:3]_HPD 3.3V / 3.3V
CMOS
Table 4.18: Type 10 DDI Signals, Pin Ty
Digital display InterfaceDDI Pin Type Pwr Rail / Tolerance
DDI0_PAIR[0:3]+ O
AC coupled off Module
DDI0_PAIR[0:3]- PCIE

I
DDI[0]_DDC_AUX_SEL 3.3V / 3.3V
CMOS

I/O
AC coupled on Module
PCIE
DDI[0]_CLTRCLK_AUX+
I/O OD
3.3V / 3.3V
CMOS
I/O
AC coupled on Module
PCIE
DDI[0]_CTRLDATA_AUX-
I/O OD
3.3V / 3.3V
CMOS
I
DDI0_HPD 3.3V / 3.3V
CMOS
Table 4.19: Type 6
Type 6
Pin Name SDVO
Pin Number
 DDI1_PAIR0+ D26 SDVO1_RED+
DDI1_PAIR0- D27 SDVO1_RED-
DDI1_PAIR1+ D29 SDVO1_GRN+
DDI1_PAIR1- D30 SDVO1_GRN-
DDI1_PAIR2+ D32 SDVO1_BLU+
DDI1_PAIR2- D33 SDVO1_BLU-
DDI1_PAIR3+ D36 SDVO1_CK+
DDI1_PAIR3- D37 SDVO1_CK-
DDI1_PAIR4+ C25 SDVO1_INT+
DDI 1
DDI1_PAIR4- C26 SDVO1_INT-
DDI1_PAIR5+ C29 SDVO1_TVCLKIN+
DDI1_PAIR5- C30 SDVO1_TVCLKIN-
DDI1_PAIR6+ C15 SDVO1_FLDSTALL+
DDI1_PAIR6- C16 SDVO1_FLDSTALL-
DDI1_HPD C24
DDI1_CTRLCLK_AUX+ D15 SDVO1_CTRLCLK
DDI1_CTRLDATA _AUX- D16 SDVO1_CTRLDATA
DDI1_DDC_AUX_SEL D34
DDI2_PAIR0+ D39
DDI2_PAIR0- D40
DDI2_PAIR1+ D42
DDI2_PAIR1- D43
DDI2_PAIR2+ D46
DDI2_PAIR2- D47
DDI 2
DDI2_PAIR3+ D49
DDI2_PAIR3- D50
DDI2_HPD D44
DDI2_CTRLCLK_AUX+ C32
DDI2_CTRLDATA_AUX- C33
DDI2_DDC_AUX_SEL C34
DDI3_PAIR0+ C39
DDI3_PAIR0- C40
DDI3_PAIR1+ C42
DDI3_PAIR1- C43
DDI3_PAIR2+ C46
DDI3_PAIR2- C47
DDI 3
DDI3_PAIR3+ C49
DDI3_PAIR3- C50
DDI3_HPD C44
DDI3_CTRLCLK_AUX+ C36
DDI3_CTRLDATA_AUX- C37
DDI3_DDC_AUX_SEL C38
Table 4.20: Type 10 Digital Display Interface
Type 10
Pin Name SDVO
Pin Number
DDI0_PAIR0+ B71 SDVO1_RED+
DDI0_PAIR0- B72 SDVO1_RED-
DDI0_PAIR1+ B73 SDVO1_GRN+
DDI0_PAIR1- B74 SDVO1_GRN-
DDI0_PAIR2+ B75 SDVO1_BLU+
DDI0_PAIR2- B76 SDVO1_BLU-

DDI 0
 DDI0_PAIR3+ B81 SDVO1_CK+
DDI0_PAIR3- B82 SDVO1_CK-
DDI0_PAIR4+ B77 SDVO1_INT+
DDI 0
DDI0_PAIR4- B78 SDVO1_INT-
DDI0_PAIR5+ B91 SDVO1_TVCLKIN+
DDI0_PAIR5- B92 SDVO1_TVCLKIN-
DDI0_PAIR6+ B93 SDVO1_FLDSTALL+
DDI0_PAIR6- B94 SDVO1_FLDSTALL-
DDI0_HPD B89
DDI0_CTRLCLK _AUX+ B98 SDVO1_CTRLCLK
DDI0_CTRLDATA_AUX- B99 SDVO1_CTRLDATA
DDI0_DDC_AUX_SEL B95

4.4.6 Digital Display Interfaces (DDI)

The cCarrier based termination requirements are dependent on the video interfaces supported by the Module’s DDI implemen
following interfaces: SDVO, DP, TMDS(DVI/HDMI), or Dual-Mode (DisplayPort and TMDS). Refer to the VESA DisplayPort Int
http://www.vesa.org/vesa-standards/ http://www.vesa.org/Standards/free.htm for more information on supporting TMDS (DVI/H

5.4.65.4.7 Digital Display InterfaceDDI Loss Budget

The DDI signals can be used to support a variety of video interfaces. The circuits required to realize the different video interfac
requirement placed on Modules for the DDI signals is the maximum trace length specified below.
Figure 5-65-7: DDI Loss Budget

Figure 5-65-7 above shows a DisplayPort implementation. The DDI can also support SDVO and TMDS. Depending on the typ
Requirements:
• DDI[n]_PAIR[0..3] LA should be less than 4.0”. LA is defined as the total Module trace length from the silicon to the COM E
• DDI[n]_PAIR[0..3] LB should be less than 5.0”. LB is defined as the total trace length on the Carrier from the COM Express
• DDI[n]_CTRLDATA_AUX- / DDI[n]_CTRLCLK_AUX+ LA should be less than 7.0”. LA is defined as the total Module trace le
required.
• DDI[n]_CTRLDATA_AUX- / DDI[n]_CTRLCLK_AUX+ LB should be less than 5.0”. LB is defined as the total trace length on
capacitors that might be required.
nd Type 10
HDMI/DVI, and SDVO interfaces. Type 10 Modules can contain a single DDI (DDI[0]) that can support DisplayPort, HDMI/DVI, and SDVO.
Port, HDMI/DVI and DDI[1] can support DisplayPort, HDMI/DVI, and SDVO. The main difference is that SDVO is only supported on DDI[0] f

Carrier might support DP or HDMI/DVI from a DDI using a cable adapter to convert from DisplayPort to HDMI/DVI. Note that a Carrier can c
nterface. The DisplayPort Interoperability Guideline Version 1.1a dated February 5, 2009 can be downloaded from the VESA website after r
-standards. The VESA specification uses the term Dual-Mode Source to define a source that can be configured for DisplayPort or TMDS (H
it that can be used on a Moduleshows a conceptual example circuit that could be used on a module Actual circuit implementations will vary

Figure 4-1: Dual-Mode COM Express Module Implementation

uit that might be necessary for Carriers supporting DisplayPort, HDMI/DVI.

ble 4.16: Module and Carrier Combinations

onal level shifters on data, per module requirements.)Level shifters on data and DDC before DVI/HDMI connector
ng
pecting

als, Pin

.19 below, details the mapping between the Digital Display InterfaceDDI pins and the different types of video interfaces supported.
Table 4.17: Type 6 DDI Signals, Pin Types, and Descriptions
Description

Digital Display InterfaceDDI 1 to 3 Pair[0:3] differential pairs

Selects the function of DDI[1:3]_CTRLCLK_AUX+ and DDI[1:3]_CTRLDATA_AUX-. This pin shall have a 1M
pull-down to logic ground on the Module. If this input is floating the AUX pair is used for the DP AUX+/- signals.
If pulled-high the AUX pair contains the CRTLCLK and CTRLDATA signals.

DP AUX+ function if DDI[1:3]_DDC_AUX_SEL is no connect

HDMI/DVI I2C CTRLCLK if DDI[1:3]_DDC_AUX_SEL is pulled high

DP AUX- function if DDI[1:3]_DDC_AUX_SEL is no connect

HDMI/DVI I2C CTRLDATA if DDI[1:3]_DDC_AUX_SEL is pulled high

Digital Display InterfaceDDI Hot-Plug Detect

Table 4.18: Type 10 DDI Signals, Pin Types, and Descriptions
Description

Digital Display InterfaceDDI 0 Pair[0:3] differential pairs

Selects the function of DDI[0]_CTRLCLK_AUX+ and DDI[0]_CTRLDATA_AUX-. This pin shall have a 1M pull-
down to logic ground on the Module. If this input is floating the AUX pair is used for the DP AUX+/- signals. If
pulled-high the AUX pair contains the CRTLCLK and CTRLDATA signals.

DP AUX+ function if DDI[0]_DDC_AUX_SEL is no connect

HDMI/DVI I2C CTRLCLK if DDI[0]_DDC_AUX_SEL is pulled high

DP AUX- function if DDI[0]_DDC_AUX_SEL is no connect

HDMI/DVI I2C CTRLDATA if DDI[0]_DDC_AUX_SEL is pulled high

Digital Display InterfaceDDI Hot-Plug Detect

Table 4.19: Type 6 Digital Display InterfaceDDI
DP
DP1_LANE0+
DP1_LANE0-
DP1_LANE1+
DP1_LANE1-
DP1_LANE2+
DP1_LANE2-
DP1_LANE3+
DP1_LANE3-

DP1_HPD
DP1_AUX+
DP1_AUX-

DP2_LANE0+
DP2_LANE0-
DP2_LANE1+
DP2_LANE1-
DP2_LANE2+
DP2_LANE2-
DP2_LANE3+
DP2_LANE3-
DP2_HPD
DP2_AUX+
DP2_AUX-

DP3_LANE0+
DP3_LANE0-
DP3_LANE1+
DP3_LANE1-
DP3_LANE2+
DP3_LANE2-
DP3_LANE3+
DP3_LANE3-
DP3_HPD
DP3_AUX+
DP3_AUX-

DP
DP1_LANE0+
DP1_LANE0-
DP1_LANE1+
DP1_LANE1-
DP1_LANE2+
DP1_LANE2-
 DP1_LANE3+
DP1_LANE3-

DP1_HPD
DP1_AUX+
DP1_AUX-

s supported by the Module’s DDI implementation as well as the display type connected to the cCarrier. A DDI can be used to support one o
TMDS). Refer to the VESA DisplayPort Interoperability Guideline Version 1.1a dated February 5, 2009 available at the VESA website after
ore information on supporting TMDS (DVI/HDMI) from a Dual-Mode Module.

quired to realize the different video interfaces will be determined by a future PICMG Carrier Design Guide subcommittee. At this time, thew
ecified below.

rt SDVO and TMDS. Depending on the type of video interface desired, there may be level shifters on the Carrier.
 trace length from the silicon to the COM Express connector including any blocking capacitors that might be required.
ngth on the Carrier from the COM Express connector to the display connector or level shifter including any blocking capacitors that might be
0”. LA is defined as the total Module trace length from the silicon to the COM Express connector including any blocking capacitors that migh

0”. LB is defined as the total trace length on the Carrier from the COM Express connector to the display connector or level shifter including a
t, HDMI/DVI, and SDVO. Type 6
nly supported on DDI[0] for Type 10

. Note that a Carrier can contain the

the VESA website after registration
r DisplayPort or TMDS (HDMI/DVI) -
implementations will vary.

Destination
DisplayPort
DVI/HDMI
DisplayPort
DVI/HDMI
DisplayPort
DVI/HDMI
faces supported.

Pin Availability

T6

T6

T6

T6

T6

T6

T6

Pin Availability

T10

T10

T10

T10

T10

T10

T10

HDMI/DVI
(TMDS Signaling)
TMDS1_DATA2+
TMDS1_DATA2-
TMDS1_DATA1+
TMDS1_DATA1-
TMDS1_DATA0+
TMDS1_DATA0-
TMDS1_CLK+
TMDS1_CLK-

HDMI1_HPD
HMDI1_CTRLCLK
HMDI1_CTRLDATA

TMDS2_DATA2+
TMDS2_DATA2-
TMDS2_DATA1+
TMDS2_DATA1-
TMDS2_DATA0+
TMDS2_DATA0-
TMDS2_CLK+
TMDS2_CLK-
HDMI2_HPD
HDMI2_CTRLCLK
HDMI2_CTRLDATA

TMDS3_DATA2+
TMDS3_DATA2-
TMDS3_DATA1+
TMDS3_DATA1-
TMDS3_DATA0+
TMDS3_DATA0-
TMDS3_CLK+
TMDS3_CLK-
HDMI3_HPD
HDMI3_CTRLCLK
HDMI3_CTRLDATA

HDMI/DVI
(TMDS Signaling)
TMDS1_DATA2+
TMDS1_DATA2-
TMDS1_DATA1+
TMDS1_DATA1-
TMDS1_DATA0+
TMDS1_DATA0-
 TMDS1_CLK+
TMDS1_CLK-

HDMI1_HPD
HMDI1_CTRLCLK
HMDI1_CTRLDATA

be used to support one or more of the

at the VESA website after registration

mmittee. At this time, thew only

ed.
g capacitors that might be required.
king capacitors that might be

or level shifter including any blocking

5.4 Loss Budgets for High Speed Differential Interfaces
COM Express® Module and Carrier Board insertion loss budgets for the PCI Express, SATA, USB and GBE interfaces are
The COM Express® Module and Carrier Board insertion loss budgets were formulated to be compatible with the relevant s
insertion loss parameters. For example, the PCI Express Card Electromechanical Specification factors cross talk losses in
specifications do not.
For frequency dependent material losses, a rule-of-thumb insertion loss value of 0.28 dB per inch per GHz is used in all ca
consistent with the PCI Express Card Electromechanical Specification usage (which calls out a 1.4 dB material loss for 4 in
specifications that use values slightly above and below this value.

Module and Carrier Board vendors may elect to use PCB laminates with better characteristics than common FR4. If this is
be extended as long as the net insertion loss budgets are met.
Loss budgets for future generations of PCI Express (Gen 2), Ethernet (10 Gbps) and SATA (Gen 3) will be addressed in fu
There is no explicit COM Express® jitter budget for the high speed differential interfaces. Designers are referred to the rele
budgets.

To develop guidelines for PCI Express Gen 2 (5 GT/s) operation, a series of simulations that modeled PCIe Gen2 operatio
recommendations given in the PCI-SIG PCI Express® Base Specification, Rev 2.1, Section 4.3.6, “Channel Specifications
Section 4.3.6.2, “Channel Characteristics at 5.0 GT/s” may serve as an overview of the PCI-SIG recommendations:

At 5.0 GT/s a more accurate method of comprehending the effects of channel loss is required in order to avoid excessive
parameters into a simulation environment that includes worst case models for Transmitters and data patterns.
The resulting time domain simulation yields eye diagrams from which voltage and timing margins may be obtained and co
Note: The methodology described in Sections 4.3.6.2 through 4.3.6.2.7 must be applied to 5.0 GT/s designs, and may be

A channel's characteristics are completely defined by its s-parameters, in particular: insertion loss, return loss, and aggres
sufficient to completely quantize all channel-induced phenomena affecting eye margins including I/O-channel impedance m
crosstalk. Long channels tend to be dominated by insertion loss and crosstalk, while short channels tend to dominated by
Express implementations, it is necessary provide a means of characterizing the channel that comprehends all possible cha

All relevant elements of the COM Express® environment were included in the simulations: a PCIe Gen 2 source, package
Carrier Board trace, and Carrier Board target device, for the “Device Down” case.

The “Device Up” case was also simulated, adding in the effects of a Slot Card connector and trace. Cross-talk, jitter and in
common clocked and data clocked PCIe operations were considered. The simulations were carried out assuming that the
dielectrics. Full details of these simulations may be found in the document titled 'PCIe Gen2 COM Express Hardware Sim
The conclusions drawn from the simulations are that the eye margins are dominated by the trace length in the various sect
minor roles. For Gen 2 operation, the maximum allowed PCIe trace lengths need to be shorter than those that were allowe
5.3 Carrier Board Configuration EEPROM
The Carrier Board should implement a serial EEPROM that describes the expected PCI Express link configuration. In addition this EEPROM may describe the
expected link presence for SATA, SAS, Express Card, USB, TV-Out, VGA, LVDS, SDVO, LAN, audio, and the expected presence of miscellaneous I/O signals.
The Carrier Board Configuration EEPROM allows the COM Express® module BIOS to set up any software configurable module features in a way that is appropriate
for the Carrier board. If there is an incompatibility between the expected Carrier Board configuration and the module capabilities, an error message may be
generated. The error messaging is module vendor specific and is not defined by this standard.
The COM Express® EEPROM content is define in the PICMG COMExpress companion document EeeP(Embedded EEPROM) Specification. The COM Express®
R1.0 Carrier board configuration EEPROM content and layout is supperceeded by the EeeP Specification. All new designs implementing either the Module or
Carrier EEPROM shall exclusively use the new EeeP styled layout.

5.3.1 EEPROM Device Information

If the Module and or Carrier Board serial EEPROM is implemented, a two-wire serial interface device operating at a supply voltage of 3.3V shall be used. The two-
wire interface shall be I2C compatible. The device shall have a capacity of at least 2048 bits, and shall have three address inputs. A suitable device is the Atmel
AT24C02-2.7 or equivalent. Suitable devices include the Atmel AT24C32C, the ST M24C32 and other compatible devices.
The Carrier Board EEPROM device, if implemented, shall interface to the module over the general purpose I2C interface (COM Express® pin names I2C_DAT and
I2C_CK). The device address lines, A2, A1 and A0 shall be pulled to a logic high, placing the device at address 7.
Serial devices with capacity greater than 2048 bits may be used. If this is done, the COM Express® Carrier Board Configuration EEPROM data structure
(summarized in Table below) shall occupy the top 2048 bits of the EEPROM device.

EEPROM PCI Express Lane Descriptor Data Structure

Lane numbers 0 through 31 refer to the 32 possible COM Express® lanes. Each COM Express® connector PCI Express lane is allocated four bytes to describe how
the lanes are grouped on the module to form PCI Express links.

Of the four bytes, or 32 bits, per lane, the two most significant bytes (bit 31 down through bit 16) are reserved for link attribute information. The two least significant
bytes (bit 15 through bit 0) describe the width and starting lane number of the link. This data structure allows all conceivable lane configurations to be described.

Bit 31
Bit 30
Bit 29
Bit 28
Link Attribute LSB
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Link Attribute MSB
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Link Width
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Link Starting Lane Number
Bit 3
Bit 2
Bit 1
Bit 0
5.3.2 COM Express® Module EEPROM
The Module Board should implement a serial EEPROM that Identifies the Module using the Unique Device Id.
The Module EPROM allows the COM Express™ Carrier Board to set up any software configurable Carrier Board features in a way that is appropriate for the Module
board.
The Module EEPROM device, if implemented, shall interface to the Carrier Board over the general purpose I2C interface (COM Express™ pin names I2C_DAT and
I2C_CK). The device address lines, A2, A1 and A0 shall be pulled to a logic low, placing the device at address 0x50(0xA0) (A6-A3 = 1010b for I2C EEPROM
devices).
SATA / SAS Device Descriptor Byte
The configuration EEPROM shall use a byte to indicate how many SATA and SAS devices the Carrier Board uses, per the following table.
SATA / SAS Device Descriptor Byte
Bit Description
7
SATA / SAS Channel 3
6

5
SATA / SAS Channel 2
4

3
SATA / SAS Channel 1
2
1
SATA / SAS Channel 0
0

5.3.3 COM Express® Carrier Board EEPROM

The Carrier Board should implement a serial EEPROM that identifies the Carrier using the Unique Device Id and describe the expected PCI Express link
configuration. In addition this EEPROM may describe the expected link presence for SATA, SAS, Express Card, USB, DDI, VGA, LAN, audio, and the expected
presence of miscellaneous I/O signals.
The Carrier EEPROM allows the COM Express™ Module BIOS to set up any software configurable Module features in a way that is appropriate for the Carrier
board.
If there is an incompatibility between the expected Carrier Board configuration and the Module capabilities, an error message may be generated. The error
messaging is Module vendor specific and is not defined by this standard.
The Carrier Board EEPROM device, if implemented, shall interface to the Module over the general purpose I2C interface (COM Express™ pin names I2C_DAT and
I2C_CK). The device address lines, A2, A1 and A0 shall be pulled to a logic high, placing the device at address 0x57(0xAE) (A6-A3 = 1010b for I2C EEPROM
devices).
Express Card Descriptor Byte
The configuration EEPROM shall use two bytes to indicate if the Carrier Board supports up to 2 Express Card slots. The following table shows the Express Card
Descriptor Byte definition.
Express Card Descriptor Byte
Bit Description
7 Express Card Support
6-4 Express Card USB Port Mapping
3 Reserved
2-0 Express Card PCI Express Lane Mapping
USB Descriptor Byte
The configuration EEPROM shall use one byte to indicate how many USB ports the Carrier Board uses. Note that per the module fill order, described in Section 3.3
of this document, the USB ports shall be populated in a low to high manner.
USB Descriptor Byte
Bit Description
7-4 Reserved
3-0 USB Port Count
Display Descriptor Byte
The configuration EEPROM shall use one byte to indicate the display options used by the Carrier Board. The following table shows the Display Descriptor Byte
definition.
Display Descriptor Byte
Bit Description
7 TV-Out Component Video

6 TV-Out S-Video

5 TV-Out Composite Video

4 VGA

3 LVDS Channel B

2 LVDS Channel A

1 SDVO Channel C

0 SDVO Channel B
Note: further details about the type of video signals (i.e. PAL/NTSC/ SECAM, 480p/ 720p/1080i/1080p, etc.) are beyond the scope and purpose of the configuration
EEPROM.
LAN Descriptor Byte
The configuration EEPROM shall use one byte to indicate the LAN options used by the Carrier Board. The following table shows the LAN Descriptor Byte definition.
LAN Descriptor Byte
Bit Description
7-4 Reserved

3 10 GBE

2 GBE 2

1 GBE 1

0 GBE 0
Miscellaneous I/O Descriptor Byte
The configuration EEPROM shall use one byte to indicate usage by the Carrier Board of the following miscellaneous I/O signals.
• AC ’97 Digital Interface
• Watchdog Timer
• External BIOS ROM
• Thermal Protection
• Battery Low
• Suspend
• Wake
The following table shows the Miscellaneous I/O Descriptor Byte definition.
Miscellaneous I/O Descriptor Byte
Bit Description
7 AC ’97 (AC_**** pins)

6 Watchdog Timer (WDT)

5 External BIOS ROM (BIOS_DISABLE#)

4 Thermal Protection (THRM#, THERMTRIP#)

3 (BATLOW#)

2 Suspend (SUS_**** pins)

1 Wake 1 (WAKE1#)

0 Wake 0 (WAKE0#)
EEPROM Memory Map
COM Express® Carrier Board Configuration EEPROM Memory Map
EEPROM Address (Hex)
FF - FE
FD - F0
EF - E0
DF
DE
DD
DC
DB
DA
D9
D8
D7 - 80
7C
78
74
70
6C
68
64
60
5C
58
54
50
4C
48
44
40
3C
38
34
30
2C
28
24
20
1C
18
14
10
0C
08
04
00
The EEPROM data is filled in “Little-Endian” fashion (least significant, or rightmost, byte in a multi-byte value goes to lower address).
ation EEPROMCOM Express® EEPROMs
EEPROM that describes the expected PCI Express link configuration. In addition this EEPROM may describe the
ss Card, USB, TV-Out, VGA, LVDS, SDVO, LAN, audio, and the expected presence of miscellaneous I/O signals.
ows the COM Express® module BIOS to set up any software configurable module features in a way that is appropriate
lity between the expected Carrier Board configuration and the module capabilities, an error message may be
ndor specific and is not defined by this standard.
e in the PICMG COMExpress companion document EeeP(Embedded EEPROM) Specification. The COM Express®
ntent and layout is supperceeded by the EeeP Specification. All new designs implementing either the Module or
w EeeP styled layout.

ion
ROM is implemented, a two-wire serial interface device operating at a supply voltage of 3.3V shall be used. The two-
vice shall have a capacity of at least 2048 bits, and shall have three address inputs. A suitable device is the Atmel
nclude the Atmel AT24C32C, the ST M24C32 and other compatible devices.
ented, shall interface to the module over the general purpose I2C interface (COM Express® pin names I2C_DAT and
d A0 shall be pulled to a logic high, placing the device at address 7.
bits may be used. If this is done, the COM Express® Carrier Board Configuration EEPROM data structure
top 2048 bits of the EEPROM device.

a Structure EEPROM Data Example - four PCI Express x1 lanes and one x16 P

ssible COM Express® lanes. Each COM Express® connector PCI Express lane is allocated four bytes to describe how
PCI Express links. Address Offset PCI Express
most significant bytes (bit 31 down through bit 16) are reserved for link attribute information. The two least significant
and starting lane number of the link. This data structure allows all conceivable lane configurations to be described.
Hex Dec Hex Dec
0: Gen 1 PCI Express link; 1: Gen 2 PCI Express link 7C 124 1F 31
Reserved 78 120 1E 30
Reserved 74 116 1D 29
Reserved 70 112 1C 26
Reserved 6C 108 1B 27
Reserved 68 104 1A 26
Reserved 64 100 19 25
Reserved 60 96 18 24
Reserved 5C 92 17 23
Reserved 58 88 16 22
Reserved 54 84 15 21
Reserved 50 80 14 20
Reserved 4C 76 13 19
Reserved 48 72 12 18
Reserved 44 68 11 17
Reserved 40 64 10 16
3C 60 F 15
Descriptor bits 15..8 describe the width of the PCI Express link. Possible values are
00 - 0 38 56 E 14
01 - 1 34 52 D 13
02 - 2 30 48 C 12
04 - 4 2C 44 B 11
08 - 8 28 40 A 10
10 - 16 24 36 9 9
20 - 32.
20 32 8 8
1C 28 7 7
18 24 6 6
14 20 5 5
Descriptor bits 7..0 describe the starting lane number of the link. If a lane is not used, then a value 10 16 4 4
of 0000 0000 hex is entered for that lane number. C 12 3 3
8 8 2 2
4 4 1 1
0 0 0 0
EPROM
EEPROM that Identifies the Module using the Unique Device Id.
™ Carrier Board to set up any software configurable Carrier Board features in a way that is appropriate for the Module

shall interface to the Carrier Board over the general purpose I2C interface (COM Express™ pin names I2C_DAT and
d A0 shall be pulled to a logic low, placing the device at address 0x50(0xA0) (A6-A3 = 1010b for I2C EEPROM

o indicate how many SATA and SAS devices the Carrier Board uses, per the following table.
Device Descriptor Byte
Value
1: SAS device
0: SATA device
1: Connector implemented on Carrier Board
0: Not implemented
1: SAS device
0: SATA device
1: Connector implemented on Carrier Board
0: Not implemented
1: SAS device
0: SATA device
1: Connector implemented on Carrier Board
0: Not implemented
 1: SAS device
0: SATA device
1: Connector implemented on Carrier Board
0: Not implemented
oard EEPROM
EEPROM that identifies the Carrier using the Unique Device Id and describe the expected PCI Express link
escribe the expected link presence for SATA, SAS, Express Card, USB, DDI, VGA, LAN, audio, and the expected

s™ Module BIOS to set up any software configurable Module features in a way that is appropriate for the Carrier

cted Carrier Board configuration and the Module capabilities, an error message may be generated. The error
ot defined by this standard.
ented, shall interface to the Module over the general purpose I2C interface (COM Express™ pin names I2C_DAT and
d A0 shall be pulled to a logic high, placing the device at address 0x57(0xAE) (A6-A3 = 1010b for I2C EEPROM

es to indicate if the Carrier Board supports up to 2 Express Card slots. The following table shows the Express Card

rd Descriptor Byte
Value
1: Express Card slot implemented 0: Express Card slot not implemented
000b – 111b indicating the USB port number mapped to this Express Card site
0
000b – 101b indicating the PCI Express Lane that is mapped to this Express Card site

e to indicate how many USB ports the Carrier Board uses. Note that per the module fill order, described in Section 3.3
ated in a low to high manner.
ptor Byte
Value
0
0 - 8 indicating the number of USB ports implemented

e to indicate the display options used by the Carrier Board. The following table shows the Display Descriptor Byte

scriptor Byte
Value
1: Component Video implemented
0: Component Video not implemented
1: S-Video implemented
0: S-Video not implemented
1: Composite Video implemented
0: Composite Video not implemented
1: VGA implemented
0: VGA not implemented
1: LVDS channel implemented
0: LVDS channel not implemented
1: LVDS channel implemented
0: LVDS channel not implemented
1: SDVO channel implemented
0: SDVO channel not implemented
1: SDVO channel implemented
0: SDVO channel not implemented
gnals (i.e. PAL/NTSC/ SECAM, 480p/ 720p/1080i/1080p, etc.) are beyond the scope and purpose of the configuration

e to indicate the LAN options used by the Carrier Board. The following table shows the LAN Descriptor Byte definition.
ptor Byte
Value
0
Reserved for future usage
1: 10 Gigabit Ethernet port implemented
0: 10 Gigabit Ethernet port not implemented
1: Ethernet port implemented
0: Ethernet port not implemented
1: Ethernet port implemented
0: Ethernet port not implemented
1: Ethernet port implemented
0: Ethernet port not implemented

e to indicate usage by the Carrier Board of the following miscellaneous I/O signals.

O Descriptor Byte definition.

ous I/O Descriptor Byte
Value
1: Implemented
0: Not implemented
1: Implemented
0: Not implemented
 1: Implemented
0: Not implemented
1: Implemented
0: Not implemented
1: Implemented
0: Not implemented
1: Implemented
0: Not implemented
1: Implemented
0: Not implemented
1: Implemented
0: Not implemented

ss® Carrier Board Configuration EEPROM Memory Map

Content
Unsigned 16 bit checksum over the unsigned bytes at addresses 00 through FD
Reserved: fill with ‘00’
ASCII ID string: “COMExpressConfig”
 Reserved: fill with ‘00’
SAS Device Descriptor Byte
Express Card 1 Descriptor Byte
Express Card 0 Descriptor Byte
USB Descriptor Byte
Display Descriptor Byte
LAN Descriptor Byte
Miscellaneous I/O Descriptor Byte
Reserved: fill with ‘00’
PCIE Lane 31 Descriptor: 4 bytes
PCIE Lane 30 Descriptor: 4 bytes
PCIE Lane 29 Descriptor: 4 bytes
PCIE Lane 28 Descriptor: 4 bytes
PCIE Lane 27 Descriptor: 4 bytes
PCIE Lane 26 Descriptor: 4 bytes
PCIE Lane 25 Descriptor: 4 bytes
PCIE Lane 24 Descriptor: 4 bytes
PCIE Lane 23 Descriptor: 4 bytes
PCIE Lane 22 Descriptor: 4 bytes
PCIE Lane 21 Descriptor: 4 bytes
PCIE Lane 20 Descriptor: 4 bytes
PCIE Lane 19 Descriptor: 4 bytes
PCIE Lane 18 Descriptor: 4 bytes
PCIE Lane 17 Descriptor: 4 bytes
PCIE Lane 16 Descriptor: 4 bytes
PCIE Lane 15 Descriptor: 4 bytes
PCIE Lane 14 Descriptor: 4 bytes
PCIE Lane 13 Descriptor: 4 bytes
PCIE Lane 12 Descriptor: 4 bytes
PCIE Lane 11 Descriptor: 4 bytes
PCIE Lane 10 Descriptor: 4 bytes
PCIE Lane 9 Descriptor: 4 bytes
PCIE Lane 8 Descriptor: 4 bytes
PCIE Lane 7 Descriptor: 4 bytes
PCIE Lane 6 Descriptor: 4 bytes
PCIE Lane 5 Descriptor: 4 bytes
PCIE Lane 4 Descriptor: 4 bytes
PCIE Lane 3 Descriptor: 4 bytes
PCIE Lane 2 Descriptor: 4 bytes
PCIE Lane 1 Descriptor: 4 bytes
PCIE Lane 0 Descriptor: 4 bytes
shion (least significant, or rightmost, byte in a multi-byte value goes to lower address).
- four PCI Express x1 lanes and one x16 PEG interface.

COM Express®
EEPROM Data
Label

Hex
PCIE 31 0000 1010 16thof 16 lanes, starting at lane 16
PCIE 30 0000 1010 15th of 16 lanes, starting at lane 16
PCIE 29 0000 1010 14thof 16 lanes, starting at lane 16
PCIE 28 0000 1010 13th of 16 lanes, starting at lane 16
PCIE 27 0000 1010 12th of 16 lanes, starting at lane 16
PCIE 26 0000 1010 11thof 16 lanes, starting at lane 16
PCIE 25 0000 1010 10thof 16 lanes, starting at lane 16
PCIE 24 0000 1010 9thof 16 lanes, starting at lane 16
PCIE 23 0000 1010 8thof 16 lanes, starting at lane 16
PCIE 22 0000 1010 7thof 16 lanes, starting at lane 16
PCIE 21 0000 1010 6thof 16 lanes, starting at lane 16
PCIE 20 0000 1010 5thof 16 lanes, starting at lane 16
PCIE 19 0000 1010 4rdof 16 lanes, starting at lane 16
PCIE 18 0000 1010 3rdof 16 lanes, starting at lane 16
PCIE 17 0000 1010 2ndof 16 lanes, starting at lane 16
PCIE 16 0000 1010 1stof 16 lanes, starting at lane 16
PCIE 17 0000 0000 Lane not used
PCIE 14 0000 0000 Lane not used
PCIE 13 0000 0000 Lane not used
PCIE 12 0000 0000 Lane not used
PCIE 11 0000 0000 Lane not used
PCIE 10 0000 0000 Lane not used
PCIE 9 0000 0000 Lane not used
PCIE 8 0000 0000 Lane not used
PCIE 7 0000 0000 Lane not used
PCIE 6 0000 0000 Lane not used
PCIE 5 0000 0000 Lane not used
PCIE 4 0000 0000 Lane not used
PCIE 3 0000 0103 1 lane, starting at lane 3
PCIE 2 0000 0102 1 lane, starting at lane 2
PCIE 1 0000 0101 1 lane, starting at lane 1
PCIE 0 0000 0100 1 lane, starting at lane 0
6.86.96.10 Heat-Spreader
Modules should be equipped with a heat-spreader. This heat-spreader by itself does not constitute the complete thermal
implementation-specific thermal solutions.
If implemented, a heat-spreader for the Compact, Basic and Extended form factor shall should use and the Mini form fac
heat-spreader to the mModule. These implementation specific holes are in addition to the mModule mounting holes specifi
For the Compact, Basic and Extended form factor aA heat-spreader should not use the mModule mounting holes as the
mModule and heat-spreader as an assembly that can then be mounted to a cCarrier without having to break the thermal in
The standoffs shown in Figure 6-9 should be mounted on the Carrier Board. The height of the standoff is dependent on th
The overall Module height from the bottom surface of the module board to the heat-spreader top surface shall be 13 mm

The module PCB and heat-spreader plate thickness are vendor implementation specific, however, a 2- mm PCB with a 3-
standoffs.
Figure 6-86-96-10: Overall Height for Heat-Spreader in Mini, Compact, Basic and Ex
 All dimensions in mm.
Tolerances (unless otherwise specified):
Z (height) dimensions should be ± 0.8mm [±0.031”] from top of Carrier Board to top of heatspreader.
Heat-spreader surface should be flat within 0.2mm [.008"] after assembly.
Interface surface finish should have a maximum roughness average (Ra) of 1.6µm [63µin].
The critical dimension in Figure 6-86-96-10 is the module PCB bottom side to heat-spreader top side. This dimension sha
Figure 6-86-96-10 shows a cross section of a module and heat-spreader assembled to a Carrier Board using the 5mm st
assembly height increases from 18.00mm to 21.00mm.
Figure 6-11: Mini Module Heat-Spreader

All dimensions are in mm.

X-Y tolerances shall be ± 0.3mm [±0.012"].
If a heat-spreader is supported, it shall provide the mounting hole attachment points dimensioned in Figure 6-11.
Figure 6-106-12: Compact Module Heat-Spreader
All dimensions are in mm.
X-Y tolerances shall be ± 0.3mm [±0.012"].
If a heat-spreader is supported, it shall provide the mounting hole attachment points dimensioned in Figure 6-106-12.
Figure 6-96-116-13: Basic Module Heat-Spreader

All dimensions are in mm.

X-Y tolerances shall be ± 0.3mm [±0.012"].
The interior holes at coordinates (40, 40) and (80, 40) are tapped through holes with a M2.5 thread.
The interior holes do not receive standoffs. These holes may be sealed on the module side by an adhesive backed foil, or
They are intended to allow additional attachment points to the heat-spreader from outside the module.
If a heat-spreader is supported, it shall provide the mounting hole attachment points dimensioned in Figure 6-116-13.

Figure 6-106-126-14: Heat-Spreader Specification for Extended Module

 All dimensions are in mm.
X-Y tolerances shall be ± 0.3mm [±0.012"].
The Extended Module heat-spreader shall have minimum X-Y dimensions of 155 mm x 74 mm, as per the clear area in th
for memory modules. The Extended Module heat-spreader may extend into the memory area. This extension is vendor sp
be 155mm x 110mm.
The interior hole at coordinates (40, 40), (80, 40) and (120,40) are tapped through holes with a M2.5 thread. The interior h
side by an adhesive backed foil, or they may be blind tapped holes with a minimum thread depth of 2.5 mm. They are inte
the module.
If a heat-spreader is supported, it shall provide the mounting hole attachment points dimensioned in Figure 6-126-14.

6.96.106.11 Component Height — Module Back and Carrier Board Top

Parts mounted on the backside of the module (in the space between the bottom surface of the module PCB and the Carrie
116-136-15).
It is likely that Mini size Modules will be used in space constrained applications such as hand held devices. In these applic
Heatspreader. These applications would benefit from a reduced height that is possible with the lower power processors us
height on both the top and bottom of the Module. The Mini Module maximum top side and back side component height sho
With the 5 mm stack option, the clearance between the Carrier Board and the bottom surface of the module’s PCB is 5 mm
components placed on the Carrier Board topside under the module envelope shall be limited to a maximum height of 1 mm
connectors. Using Carrier Board topside components up to 1mm allows a gap of 0.2 mm between Carrier Board module bo
Carrier Board applications in which vibration or board flex is a concern, then the Carrier Board component height should b
for the application.
If the Carrier Board uses the 8 mm stack option (dimension ‘A’ in Figure 6-116-136-15), then the Carrier Board componen
‘C’ in Figure 6-116-136-15), with the exception of the mating connectors. Using Carrier Board topside components up to 4m
module bottom side components. This may not be sufficient in some situations. In Carrier Board applications in which vibr
height should be restricted to a value less than 4 mm that yields a clearance that is sufficient for the application.
Figure 6-116-136-15: Component Clearances Underneath Module
6 Mechanical Specifications
6.1 Module Size – Mini Module
The PCB size for the Mini Module shall be 84mm x 55mm. The PCB thickness should be 2mm to allow high layer count s
and the top of the heat-spreader (refer to Section 6.10 “Heat-Spreader“).
The holes shown in this drawing are intended for mounting the Module / heat-spreader combination to the Carrier Board. A
used to attach the heat-spreader to the Module.
Figure 6-1: Mini Module Form Factor

All dimensions are shown in millimeters.

Tolerances shall be ± 0.25mm [±0.010"], unless noted otherwise.
The 220 pin connector pair shall be mounted on the backside of the PCB and is seen “through” the board in this view.
The four mounting holes shown shall use 6 mm diameter pads and have 2.7 mm plated holes, for use with 2.5 mm hardwa
Modules shall include the 4 mounting holes as shown in Figure 6-1 above. These holes are primarily used to attach the M

6.16.2 Module Size - Compact Module

The PCB size for the Compact Module shall be 95mm x 95mm. The PCB thickness should be 2mm to allow high layer co
Board and the top of the heat-spreader (Seerefer to Section 6.96.10 “Heat-Spreader“).
The holes shown in this drawing are intended for mounting the Module / heat-spreader combination to the Carrier Board. A
used to attach the heat-spreader to the Module.
Figure 6-16-2: Compact Module Form Factor
All dimensions are shown in millimeters.
Tolerances shall be ± 0.25mm [±0.010"], unless noted otherwise.
The 440 pin connector pair shall be mounted on the backside of the PCB and is seen “through” the board in this view.
The four mounting holes shown shall use 6 mm diameter pads and have 2.7 mm plated holes, for use with 2.5 mm hardw
Modules shall include the 4 mounting holes as shown in Figure 6-1 above. These holes are primarily used to attach the m

6.16.26.3 Module Size — Basic Module

The PCB size for the Basic Module shall be 125mm x 95mm. The PCB thickness should be 2mm to allow high layer cou
and the top of the heat-spreader. (Seerefer to Section 6.86.96.10, “Heat-Spreader”).
The holes shown in this drawing are intended for mounting the module / heat-spreader combination to the Carrier Board. A
used to attach the heat-spreader to the module.
Figure 6-16-26-3: Basic Module Form Factor
All dimensions are shown in millimeters.
Tolerances shall be ± 0.25mm [±0.010"], unless noted otherwise.
The 440 pin connector pair shall be mounted on the backside of the PCB and is seen “through” the board in this view.
The 5 mounting holes shown shall use 6mm diameter pads and shall have 2.7mm plated holes, for use with 2.5mm hard
Modules shall include the 5 mounting holes as shown in Figure 6-2 above. These holes areprimarily used to attach the mM

6.26.36.4 Module Size — Extended Module

The PCB size for the Extended Module shall be 155mm x 110mm. The PCB thickness should be 2mm to allow high laye
Board and the top of the heat-spreader. (Seerefer to Section 6.89, “Heat-Spreader”).
The holes shown in this drawing are intended for mounting the module / heat-spreader combination to the Carrier Board. A
used to attach the heat-spreader to the module.
Figure 6-26-36-4: Extended Module Form Factor
All dimensions are shown in millimeters
Tolerances shall be ± 0.25mm [±0.010"], unless noted otherwise.
The 440 pin connector pair shall be mounted on the backside of the PCB and is seen “through” the board in this view.
The seven mounting holes shown shall use 6 mm diameter pads and have 2.7 mm plated holes, for use with 2.5 mm hard
Modules shall include the 7 mounting holes as shown in Figure 6-3 above. These holes are primarily used to attach the m

6.36.46.5 Module Connector

The module connector for Pin-out Types 2 through 56 shall be a 440-pin receptacle that is composed of 2 pieces of a 220
by a plastic carrier during assembly to allow handling by automated assembly equipment. Module Pin-out Type 1 or 10 sh
qualified for LVDS operation up to 6.25GHz, to support PCI Express Generation 2 signaling speeds.
Sources for the individual 220-pin receptacle are
AMP / Tyco 3-1318490-6 0.5 mm pitch Free Height 220 pin 4H Receptacle, or equivalent
AMP / Tyco 8-1318490-6 0.5 mm pitch Free Height 220 pin 4H Receptacle, or equivalent (same as previous part, b
Tyco Electronics 3-6318490-6
Foxconn QT012206-1031-2H
ept21
or equivalent 0.5 mm pitch Free Height 220 pin 4H Receptacle
Source for the combined 440-pin receptacle (composed of 2 pieces of the 220 pin receptacle held by a carrier) are:
AMP / Tyco 3-1827231-6 0.5mm pitch Free Height 440 pin 4H Receptacle or equivalent.
Tyco Electronics 3-1827231-6
Foxconn QT012206-1041-3H
ept21
or equivalent 0.5 mm pitch Free Height 440 pin 4H Receptacle
Note: the part number above shown with a leading ‘8’ has an anti-wicking solution applied that may help in processing wit
available with this solution by the vendor.
The module connector is a receptacle by virtue of the vendor’s technical definition of a receptacle, and to some users it lo

21 At the time of this writing, EPT is developing a COM Express compatible connector set.
 Figure 6-36-46-5: Module Receptacle

6.46.56.6 Carrier Board Connector

 The Carrier Board connector for module Pin-out Types 2 through 56 shall be a 440-pin plug that is composed of 2 pieces
by a plastic carrier during assembly to allow handling by automated assembly equipment. Carrier Boards intended only for
pitch plug. The connectors shall be qualified for LVDS operation up to 6.25GHz, to support PCI Express Generation 2 sign
The Carrier Board shall use either the 5mm or 8mm heights.
Source for the individual 5 mm stack height 220 pin plug are:
AMP / Tyco 3-1827253-6 0.5 mm pitch Free Height 220 pin 5H Plug or equivalent
Tyco Electronics 3-1827253-6
Foxconn QT002206-2131-3H
ept22
or equivalent 0.5 mm pitch Free Height 220 pin 5H Plug
Source for the combined 5mm stack height 440-pin plug (composed of 2 pieces of the 220 pin plug held by a carrier) are:
AMP / Tyco 3-1827233-6 0.5 mm pitch Free Height 440 pin 5H Plug or equivalent.
Tyco Electronics 3-1827233-6
Foxconn QT002206-2141-3H
ept22
or equivalent 0.5 mm pitch Free Height 440 pin 5H Plug .
Source for the individual 8 mm stack height 220 pin plug are:
AMP / Tyco 3-1318491-6 0.5 mm pitch Free Height 220 pin 8H Plug or equivalent
AMP / Tyco 8-1318491-6 0.5 mm pitch Free Height 220 pin 8H Plug or equivalent (same as previous part, but with anti-wi
Tyco Electronics 3-6318491-6
Foxconn QT002206-4131-3H
ept22
or equivalent 0.5 mm pitch Free Height 220 pin 8H Plug
Source for the combined 8 mm stack height 440 pin plug (composed of 2 pieces of the 220 pin plug held by a carrier) is:
AMP / Tyco 3-5353652-6 0.5 mm Free Height 440 pin 8H Plug or equivalent.
Tyco Electronics 3-5353652-6
Foxconn QT002206-4141-3H
ept22
or equivalent 0.5 mm Free Height 440 pin 8H Plug .

Note: the part number above shown with a leading ‘8’ has an anti-wicking solution applied that may help in processing wit
available with this solution by the vendor.
The Carrier Board connector is a plug by virtue of the vendor’s technical definition of a plug, and to some users it looks lik
22 At the time of this writing, EPT is developing a COM Express compatible connector set.
Figure 6-46-56-6: Carrier Board Plug (8-mm Version)
6.56.66.7 Connector PCB Pattern
Figure 6-56-66-7: Connector PCB Pattern

All dimensions in mm.

6.66.76.8 Module Connector Pin Numbering

Pin numbering for 440-pin module receptacle. This is a top view of the receptacle, looking into the receptacle, as mounted
Figure 6-66-76-8: Module Connector Pin Numbering
All dimensions in mm.

6.76.86.9 Carrier Board Connector Pin Numbering

Pin numbering for 440-pin carrier-board plug. This is a top view, looking into the plug as mounted on the Carrier Board.
Figure 6-76-86-9: Carrier Board Connector Pin Numbering

All dimensions in mm.

7 Electrical Specifications
7.1 Input Power — General Considerations
The Compact, Basic and Extended Module modules shall use a single main power rail with a nominal value of +12V.
The Mini Module shall support a wide range power supply of 4.75V to 20.0V.
In addition the Mini Module shall be optimized for 5V operation and Module vendors should report Module power figures
Two additional rails are specified: a +5V standby power rail and a +3V battery input to power the module Real-time Clock
Carrier Board if the standby functions are not required by the application. Likewise, the +3V battery input may be left open
There may be module specific concerns regarding storage of system setup parameters that may be affected by the absen
The rationale for this power-delivery scheme is:
• Module pins are scarce. It is more pin-efficient to bring power in on a higher voltage rail.
• Single supply operation is attractive to many users.
• Lithium ion battery packs for mobile systems are most prevalent with a +14.4V output.
This is well suited for the +12V main power rail.
• Contemporary chipsets have no power requirements for +5V other than to provide a reference voltage for +5V tolerant in
In the case of an ATX supply, the switched (non standby) +5V line would not be used for the COM Express® module, but

7.2 Input Power — Basic and Extended ModulesCurrent Load

The module connector pins limit the amount of power that can be brought into the COM Express® modules. The limits are
power pins as Pin-out Types 1 and 10 have fewer pins available.
Table 7.1: Input Power — Pin-out Type 1,/10 Modules (Single Connector, 220 pins)
Module Pin Current
Power Rail Nominal Input (Volts) Input Range (Volts)
Capability (Amps)

10.5
VCC_12V 12 11.4 - 12.6
6
Wide input
6 4.75 – 20.0
(Mini)
VCC_5V_SBY 2 5 4.75 – 5.25
VCC_RTC 0.5 3 2.0 - 3.3
Table 7.2: Input Power — Pin-out Type 2,/3,/4,/5,/6 Modules (Dual Connector, 440 p
Module Pin Current
Rail Nominal Input (Volts) Input Range (Volts)
Capability (Amps)

16.5
VCC_12V 12 11.4 - 12.6
12
VCC_5V_SBY 2 5 4.75 – 5.25
VCC_RTC 0.5 3 2.0 - 3.3
The ripple voltage, if present, must not cause the input voltage range to be exceeded.
7.3 Input Power — Sequencing
COM Express® input power sequencing requirements are as follows:

VCC_RTC shall come up at the same time or before VCC_5V_SBY comes up23.
VCC_5V_SBY shall come up at the same time or before VCC_12V comes up23.
PWROK shall be active at the same time or after VCC_12V comes up23.

PWROK shall be inactive at the same time or before VCC_12V goes down 23.
VCC_12V shall go down at the same time or before VCC_5V_SBY goes down 23.
VCC_5V_SBY shall go down at the same time or before VCC_RTC goes down23.

Wide input (Mini) shall hall follow the Power sequencing of the VCC_12V
23 If used

Figure 7-1: Power Sequencing

 Table 7.3: Power Sequencing
T1 VCC_RTC rise to VCC_5V_SBY rise
T2 VCC_5V_SBY rise to VCC_12V rise
T3 VCC_12V rise to PWROK rise
T4 PWROK fall to VCC_12V fall
T5 VCC_12V fall to VCC_5V_SBY fall
T6 VCC_5V_SBY fall to VCC_RTC fall
7.4 Input Power - Rise Time
The input voltages to the COM Express® mModule VCC_12V, wide input (Mini) and VCC_5V_SBY if used shall rise from
a smooth and continuous ramp of each DC output voltage from 10% to 90% of its final set point within the regulation band.
waveform must be positive and have a value of between 0 V/ms and [Vout, nominal / 0.1] V/ms. Also, for any 5ms segmen
segment must have a slope ≥ [Vout, nominal / 20] V/ms.
Figure 7-2: Input Power Rise Time
T1,min = 0.1ms
T1,max = 20ms
T2 ≥ 0ms
T3 ≥ 0ms
The values chosen were selected to be compatible and enable use of ATX specification R2.2

7.47.5 Signal Integrity Requirements

The signal groups listed in the following table have signal-integrity concerns that should be accounted for in module and c
consult the relevant interface specification documents for complete information.
Table 7.4: Signal Integrity Requirements
Signal Group General Description
Analog VGA 75-ohm single ended ground-referenced lines. Generous isolation rec
Component and Composite video 75-ohm single ended ground-referenced lines. Generous isolation rec
Gigabit Ethernet Differential pairs
LVDS 100-ohm edge coupled differential pairs
PCI Bus Circa 60 ohm single-ended
PCI and LPC clocks 50-ohm single ended ground-referenced
PCI Express Differential pairs
PCI Express clocks 100 ohm edge couple differential pair, ground-referenced
Serial ATA Differential pairs
USB Differential pairs
h a nominal value of +12V.

ld report Module power figures at 5V, 12V and 18V input voltages.
er the module Real-time Clock (RTC) circuit in the absence of other power sources. The +5V standby rail may be left unconnected on t
V battery input may be left open if the application does not require the RTC to keep time in the absence of the main and standby source
t may be affected by the absence of the +5V standby and / or the +3V battery.

ence voltage for +5V tolerant inputs. No COM Express® module pins are allocated to accept +5V except for the +5V standby pins.
e COM Express® module, but it might be used elsewhere on the Carrier Board.

ent Load
press® modules. The limits are different for module Pin-out Types 1, and 10 vs. Pin-out Types 2 through 56, based on the number of 12

(Single Connector, 220 pins)

Max Module Input
Assumed Conversion
Derated Input (Volts) Max Input Ripple (mV) Power (w. derated
Efficiency
input) (Watts)
120
11.4 +/- 100 85%
68
4.75 +/- 100 28
4.75 +/- 50 9
+/- 20
dules (Dual Connector, 440 pins)
Max Module Input
Assumed Conversion
Derated Input Max Input Ripple Power (w. derated
Efficiency
input) (Watts)
188
11.4 +/- 100 85%
137
4.75 +/- 50 9
+/- 20
5V_SBY if used shall rise from ≤10% of nominal to within the regulation ranges within 0.1 ms to 20 ms (0.1 ms ≤ T2 ≤ 20 ms). There m
point within the regulation band. The smooth turn-on requires that, during the 10% to 90% portion of the rise time, the slope of the turn-o
V/ms. Also, for any 5ms segment of the 10% to 90% rise time waveform, a straight line drawn between the end points of the waveform
 .2

e accounted for in module and carrier-board designs. A general description is shown in the table for reference only. The designer shoul

General Description Source Spec Reference

ed lines. Generous isolation recommended.
ed lines. Generous isolation recommended.
IEEE 802.3 Specification
rs National Semiconductor LVDS web site
PCI SIG - PCI Local Bus Spec. Rev. 2.3
ed
PCI SIG - PCI Express Specification
ground-referenced
SATA Specification
USB 2.0 Specification
 il may be left unconnected on the
of the main and standby sources.

t for the +5V standby pins.

h 56, based on the number of 12V

Max Load Power

(Watts)

101
58

Max Load Power

(Watts)

160
116
 ≥0 ms
≥0 ms
≥0 ms
≥0 ms
≥0 ms
≥0 ms

0.1 ms ≤ T2 ≤ 20 ms). There must be

rise time, the slope of the turn-on
he end points of the waveform
ence only. The designer should

Reference

e
.3
8 Environmental Specifications
8.1 Thermal Specification
8.1.1 Objectives
Thermal specification requirements set forth here serve two objectives:
1.To provide a method through which any COM Express® module’s thermal performance can be specified and verified aga
2. To provide a method of thermal specification that is independent of the particular components used on the module.
These objectives are limited to the modules’ heat-spreader interface, and primary heat sources are limited to the module i
8.1.2 Definitions

Tcase. This is the temperature of the outside surface of the module heat-spreader plate.
Tcase_max. This is defined as the maximum temperature allowed for the heat-spreader of the module at point M (defined
junction temperatures of the chips that are in contact with the heat-spreader
Tcase_min. This is defined as the minimum temperature allowed for the heat-spreader of the module. This temperature is
in contact with the heat-spreader.
M. This is defined as the point on the heat-spreader where the maximum case temperature must be measured. The modu
heat-spreader and/or in its product documentation.
Tambient_max. This is defined as the maximum temperature of the air directly surrounding the module, allowed for the o
Tambient_min. This is defined as the minimum temperature of the air directly surrounding the module, allowed for the op
TDPmax. This is defined as the maximum power dissipation of the module for design of a thermal solution to guarantee th
stands for thermal design power.
Tcpu_junction. The junction temperature of the processor. Tcpu_junction can be measured in many processors by acces
information on how to access the thermal diode. In some instances, software provided by the processor manufacturer or a
carrier assembly to monitor the temperature of the processor. Verification of an internal thermal diode accuracy should be
validation with software can then be done by end users.
Tcpu_junction_max. The maximum junction temperature for the processor as specified in the silicon manufacturer's data
shall keep the processor junction temperature at or below the Tcpu_junction_max. Note that some manufacturers do not s
temperatures instead.
Tcpu_case. The CPU package case temperature, as specified in the silicon vendor’s data sheet. Note that Tcpu_case an
module system.
Tcpu_case_max. The maximum CPU package case temperature for the processor as specified in the silicon manufacture
heatsink) shall keep the processor case temperature at or below the Tcpu_case_max. Note that some manufacturers do n
temperatures instead.
The ultimate goal of the system thermal solution is to ensure that Tcpu_junction or Tcpu_case, whichever applies to the C
vendor. Similar concerns apply to other high dissipation components in the module system.

8.1.3 Tcase_max Measurement Setup

Measurements for Tcase_max should be performed according to a standardized method and under TDPmax conditions.
Tcase_max measurements.
Figure 8-1: Tcase_Max Measurement Point
 This schematic illustration shows the module heat-spreader, the module, and the Carrier Board. Not shown is the user-spe
normally operated without a cooling solution attached.
The measurement point (M) should be specified, either through a permanent marker on the module’s heat-spreader, or th
8.1.4 Module Thermal Specification Requirements
A module manufacturer should specify Tcase_max, Tcase_min, Tambient_max, Tambient_min, TDPmax and M (the Tcas
A module manufacturer may specify Tcpu_junction_max and maximum junction temperatures of other critical chips on the
junction temperature of the CPU and may do the same for the other critical chips. In that case, the module vendor shall en
readings are accurate.
The efficiency of the module thermal characteristics has an impact on the module’s MTBF (Mean Time Between Failure).
should provide MTBF information.

8.2 Humidity
The module humidity tolerance shall be 0 to 95% humidity, non-condensing.
8.38.1.5 Shock and Vibration
The shock and vibration characteristics of a system built with a COM Express® module will vary depending on system-imp
configuration of the Carrier Board and the thermal solution. There is no explicit shock and vibration specification that COM
If all available COM Express® module and heat-spreader attachment points are used, then a COM Express® based syste
9 Appendix
9.1 Mounting positions and connector location for Carrier Boards
Figure 9-1: Carrier Board mounting positions

9.2 Comparison of single connector types 1 and 10

Bold text indicates a difference to the previous listed type.
Table 9.1: Comparison of Type 1 and Type 10 Pin-Out
Type 1 Rev. 1.0 Type 1 Rev. 2.0
Pin Row A Row B Row A
1 GND(FIXED) GND(FIXED) GND(FIXED)
2 GBE0_MDI3- GBE0_ACT# GBE0_MDI3-
3 GBE0_MDI3+ LPC_FRAME# GBE0_MDI3+
4 GBE0_LINK100# LPC_AD0 GBE0_LINK100#
5 GBE0_LINK1000# LPC_AD1 GBE0_LINK1000#
6 GBE0_MDI2- LPC_AD2 GBE0_MDI2-
7 GBE0_MDI2+ LPC_AD3 GBE0_MDI2+
8 GBE0_LINK# LPC_DRQ0# GBE0_LINK#
9 GBE0_MDI1- LPC_DRQ1# GBE0_MDI1-
10 GBE0_MDI1+ LPC_CLK GBE0_MDI1+
11 GND(FIXED) GND(FIXED) GND(FIXED)
12 GBE0_MDI0- PWRBTN# GBE0_MDI0-
13 GBE0_MDI0+ SMB_CK GBE0_MDI0+
14 GBE0_CTREF SMB_DAT GBE0_CTREF
15 SUS_S3# SMB_ALERT# SUS_S3#
16 SATA0_TX+ SATA1_TX+ SATA0_TX+
17 SATA0_TX- SATA1_TX- SATA0_TX-
18 SUS_S4# SUS_STAT# SUS_S4#
19 SATA0_RX+ SATA1_RX+ SATA0_RX+
20 SATA0_RX- SATA1_RX- SATA0_RX-
21 GND(FIXED) GND(FIXED) GND(FIXED)
22 SATA2_TX+ SATA3_TX+ SATA2_TX+
23 SATA2_TX- SATA3_TX- SATA2_TX-
24 SUS_S5# PWR_OK SUS_S5#
25 SATA2_RX+ SATA3_RX+ SATA2_RX+
26 SATA2_RX- SATA3_RX- SATA2_RX-
27 BATLOW# WDT BATLOW#
28 ATA_ACT# AC_SDIN2 (S)ATA_ACT#
29 AC_SYNC AC_SDIN1 AC/HDA_SYNC
30 AC_RST# AC_SDIN0 AC/HDA_RST#
31 GND(FIXED) GND(FIXED) GND(FIXED)
32 AC_BITCLK SPKR AC/HDA_BITCLK
33 AC_SDOUT I2C_CK AC/HDA_SDOUT
34 BIOS_DISABLE# I2C_DAT BIOS_DIS0#
35 THRMTRIP# THRM# THRMTRIP#
36 USB6- USB7- USB6-
37 USB6+ USB7+ USB6+
38 USB_6_7_OC# USB_4_5_OC# USB_6_7_OC#
39 USB4- USB5- USB4-
40 USB4+ USB5+ USB4+
41 GND(FIXED) GND(FIXED) GND(FIXED)
42 USB2- USB3- USB2-
43 USB2+ USB3+ USB2+
44 USB_2_3_OC# USB_0_1_OC# USB_2_3_OC#
45 USB0- USB1- USB0-
46 USB0+ USB1+ USB0+
47 VCC_RTC EXCD1_PERST# VCC_RTC
48 EXCD0_PERST# EXCD1_CPPE# EXCD0_PERST#
49 EXCD0_CPPE# SYS_RESET# EXCD0_CPPE#
50 LPC_SERIRQ CB_RESET# LPC_SERIRQ
51 GND(FIXED) GND(FIXED) GND(FIXED)
52 PCIE_TX5+ PCIE_RX5+ PCIE_TX5+
53 PCIE_TX5- PCIE_RX5- PCIE_TX5-
54 GPI0 GPO1 GPI0
55 PCIE_TX4+ PCIE_RX4+ PCIE_TX4+
56 PCIE_TX4- PCIE_RX4- PCIE_TX4-
57 GND GPO2 GND
58 PCIE_TX3+ PCIE_RX3+ PCIE_TX3+
59 PCIE_TX3- PCIE_RX3- PCIE_TX3-
60 GND(FIXED) GND(FIXED) GND(FIXED)
61 PCIE_TX2+ PCIE_RX2+ PCIE_TX2+
62 PCIE_TX2- PCIE_RX2- PCIE_TX2-
63 GPI1 GPO3 GPI1
64 PCIE_TX1+ PCIE_RX1+ PCIE_TX1+
65 PCIE_TX1- PCIE_RX1- PCIE_TX1-
66 GND WAKE0# GND
67 GPI2 WAKE1# GPI2
68 PCIE_TX0+ PCIE_RX0+ PCIE_TX0+
69 PCIE_TX0- PCIE_RX0- PCIE_TX0-
70 GND(FIXED) GND(FIXED) GND(FIXED)
71 LVDS_A0+ LVDS_B0+ LVDS_A0+
72 LVDS_A0- LVDS_B0- LVDS_A0-
73 LVDS_A1+ LVDS_B1+ LVDS_A1+
74 LVDS_A1- LVDS_B1- LVDS_A1-
75 LVDS_A2+ LVDS_B2+ LVDS_A2+
76 LVDS_A2- LVDS_B2- LVDS_A2-
77 LVDS_VDD_EN LVDS_B3+ LVDS_VDD_EN
78 LVDS_A3+ LVDS_B3- LVDS_A3+
79 LVDS_A3- LVDS_BKLT_EN LVDS_A3-
80 GND(FIXED) GND(FIXED) GND(FIXED)
81 LVDS_A_CK+ LVDS_B_CK+ LVDS_A_CK+
82 LVDS_A_CK- LVDS_B_CK- LVDS_A_CK-
83 LVDS_I2C_CK LVDS_BKLT_CTRL LVDS_I2C_CK
84 LVDS_I2C_DAT VCC_5V_SBY LVDS_I2C_DAT
85 GPI3 VCC_5V_SBY GPI3
86 KBD_RST# VCC_5V_SBY KBD_RST#
87 KBD_A20GATE VCC_5V_SBY KBD_A20GATE
88 PCIE_CLK_REF+ RSVD PCIE_CLK_REF+
89 PCIE_CLK_REF- VGA_RED PCIE_CLK_REF-
90 GND(FIXED) GND(FIXED) GND(FIXED)
91 RSVD VGA_GRN SPI_POWER
92 RSVD VGA_BLU SPI_MISO
93 GPO0 VGA_HSYNC GPO0
94 RSVD VGA_VSYNC SPI_CLK
95 RSVD VGA_I2C_CK SPI_MOSI
96 GND VGA_I2C_DAT GND
97 VCC_12V TV_DAC_A TYPE10#
98 VCC_12V TV_DAC_B RSVD
99 VCC_12V TV_DAC_C RSVD
100 GND(FIXED) GND(FIXED) GND(FIXED)
101 VCC_12V VCC_12V RSVD
102 VCC_12V VCC_12V RSVD
103 VCC_12V VCC_12V RSVD
104 VCC_12V VCC_12V VCC_12V
105 VCC_12V VCC_12V VCC_12V
106 VCC_12V VCC_12V VCC_12V
107 VCC_12V VCC_12V VCC_12V
108 VCC_12V VCC_12V VCC_12V
109 VCC_12V VCC_12V VCC_12V
110 GND(FIXED) GND(FIXED) GND(FIXED)
9.3 Comparison of Types 2 and 6
Bold text indicates a difference to Type 2 Rev. 1.0
Table 9.2: Comparison of Type 2 and Type 6 Pin-Out
TYPE 2 Rev. 1.0 TYPE 2 Rev. 2.0
Pin Row A Row B Row A
1 GND(FIXED) GND(FIXED) GND(FIXED)
2 GBE0_MDI3- GBE0_ACT# GBE0_MDI3-
3 GBE0_MDI3+ LPC_FRAME# GBE0_MDI3+
4 GBE0_LINK100# LPC_AD0 GBE0_LINK100#
5 GBE0_LINK1000# LPC_AD1 GBE0_LINK1000#
6 GBE0_MDI2- LPC_AD2 GBE0_MDI2-
7 GBE0_MDI2+ LPC_AD3 GBE0_MDI2+
8 GBE0_LINK# LPC_DRQ0# GBE0_LINK#
9 GBE0_MDI1- LPC_DRQ1# GBE0_MDI1-
10 GBE0_MDI1+ LPC_CLK GBE0_MDI1+
11 GND(FIXED) GND(FIXED) GND(FIXED)
12 GBE0_MDI0- PWRBTN# GBE0_MDI0-
13 GBE0_MDI0+ SMB_CK GBE0_MDI0+
14 GBE0_CTREF SMB_DAT GBE0_CTREF
15 SUS_S3# SMB_ALERT# SUS_S3#
16 SATA0_TX+ SATA1_TX+ SATA0_TX+
17 SATA0_TX- SATA1_TX- SATA0_TX-
18 SUS_S4# SUS_STAT# SUS_S4#
19 SATA0_RX+ SATA1_RX+ SATA0_RX+
20 SATA0_RX- SATA1_RX- SATA0_RX-
21 GND(FIXED) GND(FIXED) GND(FIXED)
22 SATA2_TX+ SATA3_TX+ SATA2_TX+
23 SATA2_TX- SATA3_TX- SATA2_TX-
24 SUS_S5# PWR_OK SUS_S5#
25 SATA2_RX+ SATA3_RX+ SATA2_RX+
26 SATA2_RX- SATA3_RX- SATA2_RX-
27 BATLOW# WDT BATLOW#
28 ATA_ACT# AC_SDIN2 (S)ATA_ACT#
29 AC_SYNC AC_SDIN1 AC/HDA_SYNC
30 AC_RST# AC_SDIN0 AC/HDA_RST#
31 GND(FIXED) GND(FIXED) GND(FIXED)
32 AC_BITCLK SPKR AC/HDA_BITCLK
33 AC_SDOUT I2C_CK AC/HDA_SDOUT
34 BIOS_DISABLE# I2C_DAT BIOS_DIS0#
35 THRMTRIP# THRM# THRMTRIP#
36 USB6- USB7- USB6-
37 USB6+ USB7+ USB6+
38 USB_6_7_OC# USB_4_5_OC# USB_6_7_OC#
39 USB4- USB5- USB4-
40 USB4+ USB5+ USB4+
41 GND(FIXED) GND(FIXED) GND(FIXED)
42 USB2- USB3- USB2-
43 USB2+ USB3+ USB2+
44 USB_2_3_OC# USB_0_1_OC# USB_2_3_OC#
45 USB0- USB1- USB0-
46 USB0+ USB1+ USB0+
47 VCC_RTC EXCD1_PERST# VCC_RTC
48 EXCD0_PERST# EXCD1_CPPE# EXCD0_PERST#
49 EXCD0_CPPE# SYS_RESET# EXCD0_CPPE#
50 LPC_SERIRQ CB_RESET# LPC_SERIRQ
51 GND(FIXED) GND(FIXED) GND(FIXED)
52 PCIE_TX5+ PCIE_RX5+ PCIE_TX5+
53 PCIE_TX5- PCIE_RX5- PCIE_TX5-
54 GPI0 GPO1 GPI0
55 PCIE_TX4+ PCIE_RX4+ PCIE_TX4+
56 PCIE_TX4- PCIE_RX4- PCIE_TX4-
57 GND GPO2 GND
58 PCIE_TX3+ PCIE_RX3+ PCIE_TX3+
59 PCIE_TX3- PCIE_RX3- PCIE_TX3-
60 GND(FIXED) GND(FIXED) GND(FIXED)
61 PCIE_TX2+ PCIE_RX2+ PCIE_TX2+
62 PCIE_TX2- PCIE_RX2- PCIE_TX2-
63 GPI1 GPO3 GPI1
64 PCIE_TX1+ PCIE_RX1+ PCIE_TX1+
65 PCIE_TX1- PCIE_RX1- PCIE_TX1-
66 GND WAKE0# GND
67 GPI2 WAKE1# GPI2
68 PCIE_TX0+ PCIE_RX0+ PCIE_TX0+
69 PCIE_TX0- PCIE_RX0- PCIE_TX0-
70 GND(FIXED) GND(FIXED) GND(FIXED)
71 LVDS_A0+ LVDS_B0+ LVDS_A0+
72 LVDS_A0- LVDS_B0- LVDS_A0-
73 LVDS_A1+ LVDS_B1+ LVDS_A1+
74 LVDS_A1- LVDS_B1- LVDS_A1-
75 LVDS_A2+ LVDS_B2+ LVDS_A2+
76 LVDS_A2- LVDS_B2- LVDS_A2-
77 LVDS_VDD_EN LVDS_B3+ LVDS_VDD_EN
78 LVDS_A3+ LVDS_B3- LVDS_A3+
79 LVDS_A3- LVDS_BKLT_EN LVDS_A3-
80 GND(FIXED) GND(FIXED) GND(FIXED)
81 LVDS_A_CK+ LVDS_B_CK+ LVDS_A_CK+
82 LVDS_A_CK- LVDS_B_CK- LVDS_A_CK-
83 LVDS_I2C_CK LVDS_BKLT_CTRL LVDS_I2C_CK
84 LVDS_I2C_DAT VCC_5V_SBY LVDS_I2C_DAT
85 GPI3 VCC_5V_SBY GPI3
86 KBD_RST# VCC_5V_SBY KBD_RST#
87 KBD_A20GATE VCC_5V_SBY KBD_A20GATE
88 PCIE_CLK_REF+ RSVD PCIE_CLK_REF+
89 PCIE_CLK_REF- VGA_RED PCIE_CLK_REF-
90 GND(FIXED) GND(FIXED) GND(FIXED)
91 RSVD VGA_GRN SPI_POWER
92 RSVD VGA_BLU SPI_MISO
93 GPO0 VGA_HSYNC GPO0
94 RSVD VGA_VSYNC SPI_CLK
95 RSVD VGA_I2C_CK SPI_MOSI
96 GND VGA_I2C_DAT GND
97 VCC_12V TV_DAC_A TYPE10#
98 VCC_12V TV_DAC_B RSVD
99 VCC_12V TV_DAC_C RSVD
100 GND(FIXED) GND(FIXED) GND(FIXED)
101 VCC_12V VCC_12V RSVD
102 VCC_12V VCC_12V RSVD
103 VCC_12V VCC_12V RSVD
104 VCC_12V VCC_12V VCC_12V
105 VCC_12V VCC_12V VCC_12V
106 VCC_12V VCC_12V VCC_12V
107 VCC_12V VCC_12V VCC_12V
108 VCC_12V VCC_12V VCC_12V
109 VCC_12V VCC_12V VCC_12V
110 GND(FIXED) GND(FIXED) GND(FIXED)

TYPE 2 Rev. 1.0 TYPE 2 Rev. 2.0

Pin Row C Row D Row C
1 GND(FIXED) GND(FIXED) GND(FIXED)
2 IDE_D7 IDE_D5 IDE_D7
3 IDE_D6 IDE_D10 IDE_D6
4 IDE_D3 IDE_D11 IDE_D3
5 IDE_D15 IDE_D12 IDE_D15
6 IDE_D8 IDE_D4 IDE_D8
7 IDE_D9 IDE_D0 IDE_D9
8 IDE_D2 IDE_REQ IDE_D2
9 IDE_D13 IDE_IOW# IDE_D13
10 IDE_D1 IDE_ACK# IDE_D1
11 GND(FIXED) GND(FIXED) GND(FIXED)
12 IDE_D14 IDE_IRQ IDE_D14
13 IDE_IORDY IDE_A0 IDE_IORDY
14 IDE_IOR# IDE_A1 IDE_IOR#
15 PCI_PME# IDE_A2 PCI_PME#
16 PCI_GNT2# IDE_CS1# PCI_GNT2#
17 PCI_REQ2# IDE_CS3# PCI_REQ2#
18 PCI_GNT1# IDE_RESET# PCI_GNT1#
19 PCI_REQ1# PCI_GNT3# PCI_REQ1#
20 PCI_GNT0# PCI_REQ3# PCI_GNT0#
21 GND(FIXED) GND(FIXED) GND(FIXED)
22 PCI_REQ0# PCI_AD1 PCI_REQ0#
23 PCI_RESET# PCI_AD3 PCI_RESET#
24 PCI_AD0 PCI_AD5 PCI_AD0
25 PCI_AD2 PCI_AD7 PCI_AD2
26 PCI_AD4 PCI_C/BE0# PCI_AD4
27 PCI_AD6 PCI_AD9 PCI_AD6
28 PCI_AD8 PCI_AD11 PCI_AD8
29 PCI_AD10 PCI_AD13 PCI_AD10
30 PCI_AD12 PCI_AD15 PCI_AD12
31 GND(FIXED) GND(FIXED) GND(FIXED)
32 PCI_AD14 PCI_PAR PCI_AD14
33 PCI_C/BE1# PCI_SERR# PCI_C/BE1#
34 PCI_PERR# PCI_STOP# PCI_PERR#
35 PCI_LOCK# PCI_TRDY# PCI_LOCK#
36 PCI_DEVSEL# PCI_FRAME# PCI_DEVSEL#
37 PCI_IRDY# PCI_AD16 PCI_IRDY#
38 PCI_C/BE2# PCI_AD18 PCI_C/BE2#
39 PCI_AD17 PCI_AD20 PCI_AD17
40 PCI_AD19 PCI_AD22 PCI_AD19
41 GND(FIXED) GND(FIXED) GND(FIXED)
42 PCI_AD21 PCI_AD24 PCI_AD21
43 PCI_AD23 PCI_AD26 PCI_AD23
44 PCI_C/BE3# PCI_AD28 PCI_C/BE3#
45 PCI_AD25 PCI_AD30 PCI_AD25
46 PCI_AD27 PCI_IRQC# PCI_AD27
47 PCI_AD29 PCI_IRQD# PCI_AD29
48 PCI_AD31 PCI_CLKRUN# PCI_AD31
49 PCI_IRQA# PCI_M66EN PCI_IRQA#
50 PCI_IRQB# PCI_CLK PCI_IRQB#
51 GND(FIXED) GND(FIXED) GND(FIXED)
52 PEG_RX0+ PEG_TX0+ PEG_RX0+
53 PEG_RX0- PEG_TX0- PEG_RX0-
54 TYPE0# PEG_LANE_RV# TYPE0#
55 PEG_RX1+ PEG_TX1+ PEG_RX1+
56 PEG_RX1- PEG_TX1- PEG_RX1-
57 TYPE1# TYPE2# TYPE1#
58 PEG_RX2+ PEG_TX2+ PEG_RX2+
59 PEG_RX2- PEG_TX2- PEG_RX2-
60 GND(FIXED) GND(FIXED) GND(FIXED)
61 PEG_RX3+ PEG_TX3+ PEG_RX3+
62 PEG_RX3- PEG_TX3- PEG_RX3-
63 RSVD RSVD RSVD
64 RSVD RSVD RSVD
65 PEG_RX4+ PEG_TX4+ PEG_RX4+
66 PEG_RX4- PEG_TX4- PEG_RX4-
67 RSVD GND RSVD
68 PEG_RX5+ PEG_TX5+ PEG_RX5+
69 PEG_RX5- PEG_TX5- PEG_RX5-
70 GND(FIXED) GND(FIXED) GND(FIXED)
71 PEG_RX6+ PEG_TX6+ PEG_RX6+
72 PEG_RX6- PEG_TX6- PEG_RX6-
73 SDVO_DATA SDVO_CLK SDVO_DATA
74 PEG_RX7+ PEG_TX7+ PEG_RX7+
75 PEG_RX7- PEG_TX7- PEG_RX7-
76 GND GND GND
77 RSVD IDE_CBLID# RSVD
78 PEG_RX8+ PEG_TX8+ PEG_RX8+
79 PEG_RX8- PEG_TX8- PEG_RX8-
80 GND(FIXED) GND(FIXED) GND(FIXED)
81 PEG_RX9+ PEG_TX9+ PEG_RX9+
82 PEG_RX9- PEG_TX9- PEG_RX9-
83 RSVD RSVD RSVD
84 GND GND GND
85 PEG_RX10+ PEG_TX10+ PEG_RX10+
86 PEG_RX10- PEG_TX10- PEG_RX10-
87 GND GND GND
88 PEG_RX11+ PEG_TX11+ PEG_RX11+
89 PEG_RX11- PEG_TX11- PEG_RX11-
90 GND(FIXED) GND(FIXED) GND(FIXED)
91 PEG_RX12+ PEG_TX12+ PEG_RX12+
92 PEG_RX12- PEG_TX12- PEG_RX12-
93 GND GND GND
94 PEG_RX13+ PEG_TX13+ PEG_RX13+
95 PEG_RX13- PEG_TX13- PEG_RX13-
96 GND GND GND
97 RSVD PEG_ENABLE# RSVD
98 PEG_RX14+ PEG_TX14+ PEG_RX14+
99 PEG_RX14- PEG_TX14- PEG_RX14-
100 GND(FIXED) GND(FIXED) GND(FIXED)
101 PEG_RX15+ PEG_TX15+ PEG_RX15+
102 PEG_RX15- PEG_TX15- PEG_RX15-
103 GND GND GND
104 VCC_12V VCC_12V VCC_12V
105 VCC_12V VCC_12V VCC_12V
106 VCC_12V VCC_12V VCC_12V
107 VCC_12V VCC_12V VCC_12V
108 VCC_12V VCC_12V VCC_12V
109 VCC_12V VCC_12V VCC_12V
110 GND(FIXED) GND(FIXED) GND(FIXED)
9.4 Comparison of Types 2 to 5
Bold text indicates a difference to Type 2.
Table 9.3: Comparison of Type 2, Type 3, Type 4 and Type 5 Pin-Out
 TYPE 2 Rev. 2.0 TYPE 3 Rev. 2.0
Pin Row A Row B Row A
1 GND(FIXED) GND(FIXED) GND(FIXED)
2 GBE0_MDI3- GBE0_ACT# GBE0_MDI3-
3 GBE0_MDI3+ LPC_FRAME# GBE0_MDI3+
4 GBE0_LINK100# LPC_AD0 GBE0_LINK100#
5 GBE0_LINK1000# LPC_AD1 GBE0_LINK1000#
6 GBE0_MDI2- LPC_AD2 GBE0_MDI2-
7 GBE0_MDI2+ LPC_AD3 GBE0_MDI2+
8 GBE0_LINK# LPC_DRQ0# GBE0_LINK#
9 GBE0_MDI1- LPC_DRQ1# GBE0_MDI1-
10 GBE0_MDI1+ LPC_CLK GBE0_MDI1+
11 GND(FIXED) GND(FIXED) GND(FIXED)
12 GBE0_MDI0- PWRBTN# GBE0_MDI0-
13 GBE0_MDI0+ SMB_CK GBE0_MDI0+
14 GBE0_CTREF SMB_DAT GBE0_CTREF
15 SUS_S3# SMB_ALERT# SUS_S3#
16 SATA0_TX+ SATA1_TX+ SATA0_TX+
17 SATA0_TX- SATA1_TX- SATA0_TX-
18 SUS_S4# SUS_STAT# SUS_S4#
19 SATA0_RX+ SATA1_RX+ SATA0_RX+
20 SATA0_RX- SATA1_RX- SATA0_RX-
21 GND(FIXED) GND(FIXED) GND(FIXED)
22 SATA2_TX+ SATA3_TX+ SATA2_TX+
23 SATA2_TX- SATA3_TX- SATA2_TX-
24 SUS_S5# PWR_OK SUS_S5#
25 SATA2_RX+ SATA3_RX+ SATA2_RX+
26 SATA2_RX- SATA3_RX- SATA2_RX-
27 BATLOW# WDT BATLOW#
28 (S)ATA_ACT# AC/HDA_SDIN2 (S)ATA_ACT#
29 AC/HDA_SYNC AC/HDA_SDIN1 AC/HDA_SYNC
30 AC/HDA_RST# AC/HDA_SDIN0 AC/HDA_RST#
31 GND(FIXED) GND(FIXED) GND(FIXED)
32 AC/HDA_BITCLK SPKR AC/HDA_BITCLK
33 AC/HDA_SDOUT I2C_CK AC/HDA_SDOUT
34 BIOS_DIS0# I2C_DAT BIOS_DIS0#
35 THRMTRIP# THRM# THRMTRIP#
36 USB6- USB7- USB6-
37 USB6+ USB7+ USB6+
38 USB_6_7_OC# USB_4_5_OC# USB_6_7_OC#
39 USB4- USB5- USB4-
40 USB4+ USB5+ USB4+
41 GND(FIXED) GND(FIXED) GND(FIXED)
42 USB2- USB3- USB2-
43 USB2+ USB3+ USB2+
44 USB_2_3_OC# USB_0_1_OC# USB_2_3_OC#
45 USB0- USB1- USB0-
46 USB0+ USB1+ USB0+
47 VCC_RTC EXCD1_PERST# VCC_RTC
48 EXCD0_PERST# EXCD1_CPPE# EXCD0_PERST#
49 EXCD0_CPPE# SYS_RESET# EXCD0_CPPE#
50 LPC_SERIRQ CB_RESET# LPC_SERIRQ
51 GND(FIXED) GND(FIXED) GND(FIXED)
52 PCIE_TX5+ PCIE_RX5+ PCIE_TX5+
53 PCIE_TX5- PCIE_RX5- PCIE_TX5-
54 GPI0 GPO1 GPI0
55 PCIE_TX4+ PCIE_RX4+ PCIE_TX4+
56 PCIE_TX4- PCIE_RX4- PCIE_TX4-
57 GND GPO2 GND
58 PCIE_TX3+ PCIE_RX3+ PCIE_TX3+
59 PCIE_TX3- PCIE_RX3- PCIE_TX3-
60 GND(FIXED) GND(FIXED) GND(FIXED)
61 PCIE_TX2+ PCIE_RX2+ PCIE_TX2+
62 PCIE_TX2- PCIE_RX2- PCIE_TX2-
63 GPI1 GPO3 GPI1
64 PCIE_TX1+ PCIE_RX1+ PCIE_TX1+
65 PCIE_TX1- PCIE_RX1- PCIE_TX1-
66 GND WAKE0# GND
67 GPI2 WAKE1# GPI2
68 PCIE_TX0+ PCIE_RX0+ PCIE_TX0+
69 PCIE_TX0- PCIE_RX0- PCIE_TX0-
70 GND(FIXED) GND(FIXED) GND(FIXED)
71 LVDS_A0+ LVDS_B0+ LVDS_A0+
72 LVDS_A0- LVDS_B0- LVDS_A0-
73 LVDS_A1+ LVDS_B1+ LVDS_A1+
74 LVDS_A1- LVDS_B1- LVDS_A1-
75 LVDS_A2+ LVDS_B2+ LVDS_A2+
76 LVDS_A2- LVDS_B2- LVDS_A2-
77 LVDS_VDD_EN LVDS_B3+ LVDS_VDD_EN
78 LVDS_A3+ LVDS_B3- LVDS_A3+
79 LVDS_A3- LVDS_BKLT_EN LVDS_A3-
80 GND(FIXED) GND(FIXED) GND(FIXED)
81 LVDS_A_CK+ LVDS_B_CK+ LVDS_A_CK+
82 LVDS_A_CK- LVDS_B_CK- LVDS_A_CK-
83 LVDS_I2C_CK LVDS_BKLT_CTRL LVDS_I2C_CK
84 LVDS_I2C_DAT VCC_5V_SBY LVDS_I2C_DAT
85 GPI3 VCC_5V_SBY GPI3
86 KBD_RST# VCC_5V_SBY KBD_RST#
87 KBD_A20GATE VCC_5V_SBY KBD_A20GATE
88 PCIE_CLK_REF+ BIOS_DIS1# PCIE_CLK_REF+
89 PCIE_CLK_REF- VGA_RED PCIE_CLK_REF-
90 GND(FIXED) GND(FIXED) GND(FIXED)
91 SPI_POWER VGA_GRN SPI_POWER
92 SPI_MISO VGA_BLU SPI_MISO
93 GPO0 VGA_HSYNC GPO0
94 SPI_CLK VGA_VSYNC SPI_CLK
95 SPI_MOSI VGA_I2C_CK SPI_MOSI
96 GND VGA_I2C_DAT GND
97 TYPE10# SPI_CS# TYPE10#
98 RSVD RSVD RSVD
99 RSVD RSVD RSVD
100 GND(FIXED) GND(FIXED) GND(FIXED)
101 RSVD RSVD RSVD
102 RSVD RSVD RSVD
103 RSVD RSVD RSVD
104 VCC_12V VCC_12V VCC_12V
105 VCC_12V VCC_12V VCC_12V
106 VCC_12V VCC_12V VCC_12V
107 VCC_12V VCC_12V VCC_12V
108 VCC_12V VCC_12V VCC_12V
109 VCC_12V VCC_12V VCC_12V
110 GND(FIXED) GND(FIXED) GND(FIXED)

TYPE 2 Rev. 2.0 TYPE 3 Rev. 2.0

Pin Row C Row D Row C
1 GND(FIXED) GND(FIXED) GND (FIXED)
2 IDE_D7 IDE_D5 GBE1_ACT#
3 IDE_D6 IDE_D10 GBE1_MDI3-
4 IDE_D3 IDE_D11 GBE1_MDI3+
5 IDE_D15 IDE_D12 GBE1_LINK100#
6 IDE_D8 IDE_D4 GBE1_MDI2-
7 IDE_D9 IDE_D0 GBE1_MDI2+
8 IDE_D2 IDE_REQ GBE1_LINK1000#
9 IDE_D13 IDE_IOW# GBE1_MDI1-
10 IDE_D1 IDE_ACK# GBE1_MDI1+
11 GND(FIXED) GND(FIXED) GND (FIXED)
12 IDE_D14 IDE_IRQ GBE1_MDI0-
13 IDE_IORDY IDE_A0 GBE1_MDI0+
14 IDE_IOR# IDE_A1 GBE1_LINK#
15 PCI_PME# IDE_A2 PCI_PME#
16 PCI_GNT2# IDE_CS1# PCI_GNT2#
17 PCI_REQ2# IDE_CS3# PCI_REQ2#
18 PCI_GNT1# IDE_RESET# PCI_GNT1#
19 PCI_REQ1# PCI_GNT3# PCI_REQ1#
20 PCI_GNT0# PCI_REQ3# PCI_GNT0#
21 GND(FIXED) GND(FIXED) GND (FIXED)
22 PCI_REQ0# PCI_AD1 PCI_REQ0#
23 PCI_RESET# PCI_AD3 PCI_RESET#
24 PCI_AD0 PCI_AD5 PCI_AD0
25 PCI_AD2 PCI_AD7 PCI_AD2
26 PCI_AD4 PCI_C/BE0# PCI_AD4
27 PCI_AD6 PCI_AD9 PCI_AD6
28 PCI_AD8 PCI_AD11 PCI_AD8
29 PCI_AD10 PCI_AD13 PCI_AD10
30 PCI_AD12 PCI_AD15 PCI_AD12
31 GND(FIXED) GND(FIXED) GND (FIXED)
32 PCI_AD14 PCI_PAR PCI_AD14
33 PCI_C/BE1# PCI_SERR# PCI_C/BE1#
34 PCI_PERR# PCI_STOP# PCI_PERR#
35 PCI_LOCK# PCI_TRDY# PCI_LOCK#
36 PCI_DEVSEL# PCI_FRAME# PCI_DEVSEL#
37 PCI_IRDY# PCI_AD16 PCI_IRDY#
38 PCI_C/BE2# PCI_AD18 PCI_C/BE2#
39 PCI_AD17 PCI_AD20 PCI_AD17
40 PCI_AD19 PCI_AD22 PCI_AD19
41 GND(FIXED) GND(FIXED) GND (FIXED)
42 PCI_AD21 PCI_AD24 PCI_AD21
43 PCI_AD23 PCI_AD26 PCI_AD23
44 PCI_C/BE3# PCI_AD28 PCI_C/BE3#
45 PCI_AD25 PCI_AD30 PCI_AD25
46 PCI_AD27 PCI_IRQC# PCI_AD27
47 PCI_AD29 PCI_IRQD# PCI_AD29
48 PCI_AD31 PCI_CLKRUN# PCI_AD31
49 PCI_IRQA# PCI_M66EN PCI_IRQA#
50 PCI_IRQB# PCI_CLK PCI_IRQB#
51 GND(FIXED) GND(FIXED) GND (FIXED)
52 PEG_RX0+ PEG_TX0+ PEG_RX0+
53 PEG_RX0- PEG_TX0- PEG_RX0-
54 TYPE0# PEG_LANE_RV# TYPE0#
55 PEG_RX1+ PEG_TX1+ PEG_RX1+
56 PEG_RX1- PEG_TX1- PEG_RX1-
57 TYPE1# TYPE2# TYPE1#
58 PEG_RX2+ PEG_TX2+ PEG_RX2+
59 PEG_RX2- PEG_TX2- PEG_RX2-
60 GND(FIXED) GND(FIXED) GND (FIXED)
61 PEG_RX3+ PEG_TX3+ PEG_RX3+
62 PEG_RX3- PEG_TX3- PEG_RX3-
63 RSVD RSVD RSVD
64 RSVD RSVD RSVD
65 PEG_RX4+ PEG_TX4+ PEG_RX4+
66 PEG_RX4- PEG_TX4- PEG_RX4-
67 RSVD GND RSVD
68 PEG_RX5+ PEG_TX5+ PEG_RX5+
69 PEG_RX5- PEG_TX5- PEG_RX5-
70 GND(FIXED) GND(FIXED) GND (FIXED)
71 PEG_RX6+ PEG_TX6+ PEG_RX6+
72 PEG_RX6- PEG_TX6- PEG_RX6-
73 SDVO_DATA SDVO_CLK SDVO_DATA
74 PEG_RX7+ PEG_TX7+ PEG_RX7+
75 PEG_RX7- PEG_TX7- PEG_RX7-
76 GND GND GND
77 RSVD IDE_CBLID# RSVD
78 PEG_RX8+ PEG_TX8+ PEG_RX8+
79 PEG_RX8- PEG_TX8- PEG_RX8-
80 GND(FIXED) GND(FIXED) GND (FIXED)
81 PEG_RX9+ PEG_TX9+ PEG_RX9+
82 PEG_RX9- PEG_TX9- PEG_RX9-
83 RSVD RSVD RSVD
84 GND GND GND
85 PEG_RX10+ PEG_TX10+ PEG_RX10+
86 PEG_RX10- PEG_TX10- PEG_RX10-
87 GND GND GND
88 PEG_RX11+ PEG_TX11+ PEG_RX11+
89 PEG_RX11- PEG_TX11- PEG_RX11-
90 GND(FIXED) GND(FIXED) GND (FIXED)
91 PEG_RX12+ PEG_TX12+ PEG_RX12+
92 PEG_RX12- PEG_TX12- PEG_RX12-
93 GND GND GND
94 PEG_RX13+ PEG_TX13+ PEG_RX13+
95 PEG_RX13- PEG_TX13- PEG_RX13-
96 GND GND GND
97 RSVD PEG_ENABLE# RSVD
98 PEG_RX14+ PEG_TX14+ PEG_RX14+
99 PEG_RX14- PEG_TX14- PEG_RX14-
100 GND(FIXED) GND(FIXED) GND (FIXED)
101 PEG_RX15+ PEG_TX15+ PEG_RX15+
102 PEG_RX15- PEG_TX15- PEG_RX15-
103 GND GND GND
104 VCC_12V VCC_12V VCC_12V
105 VCC_12V VCC_12V VCC_12V
106 VCC_12V VCC_12V VCC_12V
107 VCC_12V VCC_12V VCC_12V
108 VCC_12V VCC_12V VCC_12V
109 VCC_12V VCC_12V VCC_12V
110 GND(FIXED) GND(FIXED) GND (FIXED)
ation for Carrier Boards
positions

1 and 10
d Type 10 Pin-Out vs. 84X55 (Mini)
2.0 Type 10 Rev. 2.0
Row B Row A Row B
GND(FIXED) GND(FIXED) GND(FIXED)
GBE0_ACT# GBE0_MDI3- GBE0_ACT#
LPC_FRAME# GBE0_MDI3+ LPC_FRAME#
LPC_AD0 GBE0_LINK100# LPC_AD0
LPC_AD1 GBE0_LINK1000# LPC_AD1
LPC_AD2 GBE0_MDI2- LPC_AD2
LPC_AD3 GBE0_MDI2+ LPC_AD3
LPC_DRQ0# GBE0_LINK# LPC_DRQ0#
LPC_DRQ1# GBE0_MDI1- LPC_DRQ1#
LPC_CLK GBE0_MDI1+ LPC_CLK
GND(FIXED) GND(FIXED) GND(FIXED)
PWRBTN# GBE0_MDI0- PWRBTN#
SMB_CK GBE0_MDI0+ SMB_CK
SMB_DAT GBE0_CTREF SMB_DAT
SMB_ALERT# SUS_S3# SMB_ALERT#
SATA1_TX+ SATA0_TX+ SATA1_TX+
SATA1_TX- SATA0_TX- SATA1_TX-
SUS_STAT# SUS_S4# SUS_STAT#
SATA1_RX+ SATA0_RX+ SATA1_RX+
SATA1_RX- SATA0_RX- SATA1_RX-
GND(FIXED) GND(FIXED) GND(FIXED)
SATA3_TX+ RSVD RSVD
SATA3_TX- RSVD RSVD
PWR_OK SUS_S5# PWR_OK
SATA3_RX+ RSVD RSVD
SATA3_RX- RSVD RSVD
WDT BATLOW# WDT
AC/HDA_SDIN2 (S)ATA_ACT# AC/HDA_SDIN2
AC/HDA_SDIN1 AC/HDA_SYNC AC/HDA_SDIN1
AC/HDA_SDIN0 AC/HDA_RST# AC/HDA_SDIN0
GND(FIXED) GND(FIXED) GND(FIXED)
SPKR AC/HDA_BITCLK SPKR
I2C_CK AC/HDA_SDOUT I2C_CK
I2C_DAT BIOS_DIS0# I2C_DAT
THRM# THRMTRIP# THRM#
USB7- USB6- USB7-
USB7+ USB6+ USB7+
USB_4_5_OC# USB_6_7_OC# USB_4_5_OC#
USB5- USB4- USB5-
USB5+ USB4+ USB5+
GND(FIXED) GND(FIXED) GND(FIXED)
USB3- USB2- USB3-
USB3+ USB2+ USB3+
USB_0_1_OC# USB_2_3_OC# USB_0_1_OC#
USB1- USB0- USB1-
USB1+ USB0+ USB1+
EXCD1_PERST# VCC_RTC EXCD1_PERST#
EXCD1_CPPE# EXCD0_PERST# EXCD1_CPPE#
SYS_RESET# EXCD0_CPPE# SYS_RESET#
CB_RESET# LPC_SERIRQ CB_RESET#
GND(FIXED) GND(FIXED) GND(FIXED)
PCIE_RX5+ RSVD RSVD
PCIE_RX5- RSVD RSVD
GPO1 GPI0 GPO1
PCIE_RX4+ RSVD RSVD
PCIE_RX4- RSVD RSVD
GPO2 GND GPO2
PCIE_RX3+ PCIE_TX3+ PCIE_RX3+
PCIE_RX3- PCIE_TX3- PCIE_RX3-
GND(FIXED) GND(FIXED) GND(FIXED)
PCIE_RX2+ PCIE_TX2+ PCIE_RX2+
PCIE_RX2- PCIE_TX2- PCIE_RX2-
GPO3 GPI1 GPO3
PCIE_RX1+ PCIE_TX1+ PCIE_RX1+
PCIE_RX1- PCIE_TX1- PCIE_RX1-
WAKE0# GND WAKE0#
WAKE1# GPI2 WAKE1#
PCIE_RX0+ PCIE_TX0+ PCIE_RX0+
PCIE_RX0- PCIE_TX0- PCIE_RX0-
GND(FIXED) GND(FIXED) GND(FIXED)
LVDS_B0+ LVDS_A0+ DDI0_PAIR0+
 LVDS_B0- LVDS_A0- DDI0_PAIR0-
LVDS_B1+ LVDS_A1+ DDI0_PAIR1+
LVDS_B1- LVDS_A1- DDI0_PAIR1-
LVDS_B2+ LVDS_A2+ DDI0_PAIR2+
LVDS_B2- LVDS_A2- DDI0_PAIR2-
LVDS_B3+ LVDS_VDD_EN DDI0_PAIR4+
LVDS_B3- LVDS_A3+ DDI0_PAIR4-
LVDS_BKLT_EN LVDS_A3- LVDS_BKLT_EN
GND(FIXED) GND(FIXED) GND(FIXED)
LVDS_B_CK+ LVDS_A_CK+ DDI0_PAIR3+
LVDS_B_CK- LVDS_A_CK- DDI0_PAIR3-
LVDS_BKLT_CTRL LVDS_I2C_CK LVDS_BKLT_CTRL
VCC_5V_SBY LVDS_I2C_DAT VCC_5V_SBY
VCC_5V_SBY GPI3 VCC_5V_SBY
VCC_5V_SBY RSVD VCC_5V_SBY
VCC_5V_SBY RSVD VCC_5V_SBY
BIOS_DIS1# PCIE_CLK_REF+ BIOS_DIS1#
VGA_RED PCIE_CLK_REF- DD0_HPD
GND(FIXED) GND(FIXED) GND(FIXED)
VGA_GRN SPI_POWER DDI0_PAIR5+
VGA_BLU SPI_MISO DDI0_PAIR5-
VGA_HSYNC GPO0 DDI0_PAIR6+
VGA_VSYNC SPI_CLK DDI0_PAIR6-
VGA_I2C_CK SPI_MOSI DDI0_DDC_AUX_SEL
VGA_I2C_DAT TPM_PP RSVD
SPI_CS# TYPE10# SPI_CS#
RSVD SER0_TX DDI0_CTRLCLK_AUX+
RSVD SER0_RX DDI0_CTRLDATA_AUX-
GND(FIXED) GND(FIXED) GND(FIXED)
RSVD SER1_TX FAN_PWMOUT
RSVD SER1_RX FAN_TACHIN
RSVD LID# SLEEP#
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
GND(FIXED) GND(FIXED) GND(FIXED)

d Type 6 Pin-Out
. 2.0 TYPE 6 Rev. 2.0
Row B Row A Row B
GND(FIXED) GND(FIXED) GND(FIXED)
GBE0_ACT# GBE0_MDI3- GBE0_ACT#
LPC_FRAME# GBE0_MDI3+ LPC_FRAME#
LPC_AD0 GBE0_LINK100# LPC_AD0
LPC_AD1 GBE0_LINK1000# LPC_AD1
LPC_AD2 GBE0_MDI2- LPC_AD2
LPC_AD3 GBE0_MDI2+ LPC_AD3
LPC_DRQ0# GBE0_LINK# LPC_DRQ0#
LPC_DRQ1# GBE0_MDI1- LPC_DRQ1#
LPC_CLK GBE0_MDI1+ LPC_CLK
GND(FIXED) GND(FIXED) GND(FIXED)
PWRBTN# GBE0_MDI0- PWRBTN#
SMB_CK GBE0_MDI0+ SMB_CK
SMB_DAT GBE0_CTREF SMB_DAT
SMB_ALERT# SUS_S3# SMB_ALERT#
SATA1_TX+ SATA0_TX+ SATA1_TX+
SATA1_TX- SATA0_TX- SATA1_TX-
SUS_STAT# SUS_S4# SUS_STAT#
SATA1_RX+ SATA0_RX+ SATA1_RX+
SATA1_RX- SATA0_RX- SATA1_RX-
GND(FIXED) GND(FIXED) GND(FIXED)
SATA3_TX+ SATA2_TX+ SATA3_TX+
SATA3_TX- SATA2_TX- SATA3_TX-
PWR_OK SUS_S5# PWR_OK
SATA3_RX+ SATA2_RX+ SATA3_RX+
SATA3_RX- SATA2_RX- SATA3_RX-
WDT BATLOW# WDT
AC/HDA_SDIN2 (S)ATA_ACT# AC/HDA_SDIN2
AC/HDA_SDIN1 AC/HDA_SYNC AC/HDA_SDIN1
AC/HDA_SDIN0 AC/HDA_RST# AC/HDA_SDIN0
GND(FIXED) GND(FIXED) GND(FIXED)
SPKR AC/HDA_BITCLK SPKR
I2C_CK AC/HDA_SDOUT I2C_CK
I2C_DAT BIOS_DIS0# I2C_DAT
THRM# THRMTRIP# THRM#
USB7- USB6- USB7-
USB7+ USB6+ USB7+
USB_4_5_OC# USB_6_7_OC# USB_4_5_OC#
USB5- USB4- USB5-
USB5+ USB4+ USB5+
GND(FIXED) GND(FIXED) GND(FIXED)
USB3- USB2- USB3-
USB3+ USB2+ USB3+
USB_0_1_OC# USB_2_3_OC# USB_0_1_OC#
USB1- USB0- USB1-
USB1+ USB0+ USB1+
EXCD1_PERST# VCC_RTC EXCD1_PERST#
EXCD1_CPPE# EXCD0_PERST# EXCD1_CPPE#
SYS_RESET# EXCD0_CPPE# SYS_RESET#
CB_RESET# LPC_SERIRQ CB_RESET#
GND(FIXED) GND(FIXED) GND(FIXED)
PCIE_RX5+ PCIE_TX5+ PCIE_RX5+
PCIE_RX5- PCIE_TX5- PCIE_RX5-
GPO1 GPI0 GPO1
PCIE_RX4+ PCIE_TX4+ PCIE_RX4+
PCIE_RX4- PCIE_TX4- PCIE_RX4-
GPO2 GND GPO2
PCIE_RX3+ PCIE_TX3+ PCIE_RX3+
PCIE_RX3- PCIE_TX3- PCIE_RX3-
GND(FIXED) GND(FIXED) GND(FIXED)
PCIE_RX2+ PCIE_TX2+ PCIE_RX2+
PCIE_RX2- PCIE_TX2- PCIE_RX2-
GPO3 GPI1 GPO3
PCIE_RX1+ PCIE_TX1+ PCIE_RX1+
 PCIE_RX1- PCIE_TX1- PCIE_RX1-
WAKE0# GND WAKE0#
WAKE1# GPI2 WAKE1#
PCIE_RX0+ PCIE_TX0+ PCIE_RX0+
PCIE_RX0- PCIE_TX0- PCIE_RX0-
GND(FIXED) GND(FIXED) GND(FIXED)
LVDS_B0+ LVDS_A0+ LVDS_B0+
LVDS_B0- LVDS_A0- LVDS_B0-
LVDS_B1+ LVDS_A1+ LVDS_B1+
LVDS_B1- LVDS_A1- LVDS_B1-
LVDS_B2+ LVDS_A2+ LVDS_B2+
LVDS_B2- LVDS_A2- LVDS_B2-
LVDS_B3+ LVDS_VDD_EN LVDS_B3+
LVDS_B3- LVDS_A3+ LVDS_B3-
LVDS_BKLT_EN LVDS_A3- LVDS_BKLT_EN
GND(FIXED) GND(FIXED) GND(FIXED)
LVDS_B_CK+ LVDS_A_CK+ LVDS_B_CK+
LVDS_B_CK- LVDS_A_CK- LVDS_B_CK-
LVDS_BKLT_CTRL LVDS_I2C_CK LVDS_BKLT_CTRL
VCC_5V_SBY LVDS_I2C_DAT VCC_5V_SBY
VCC_5V_SBY GPI3 VCC_5V_SBY
VCC_5V_SBY RSVD VCC_5V_SBY
VCC_5V_SBY RSVD VCC_5V_SBY
BIOS_DIS1# PCIE_CLK_REF+ BIOS_DIS1#
VGA_RED PCIE_CLK_REF- VGA_RED
GND(FIXED) GND(FIXED) GND(FIXED)
VGA_GRN SPI_POWER VGA_GRN
VGA_BLU SPI_MISO VGA_BLU
VGA_HSYNC GPO0 VGA_HSYNC
VGA_VSYNC SPI_CLK VGA_VSYNC
VGA_I2C_CK SPI_MOSI VGA_I2C_CK
VGA_I2C_DAT TPM_PP VGA_I2C_DAT
SPI_CS# TYPE10# SPI_CS#
RSVD SER0_TX RSVD
RSVD SER0_RX RSVD
GND(FIXED) GND(FIXED) GND(FIXED)
RSVD SER1_TX FAN_PWMOUT
RSVD SER1_RX FAN_TACHIN
RSVD LID# SLEEP#
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
GND(FIXED) GND(FIXED) GND(FIXED)

. 2.0 TYPE 6 Rev. 2.0

Row D Row C Row D
GND(FIXED) GND(FIXED) GND(FIXED)
IDE_D5 GND GND
IDE_D10 USB_SSRX0- USB_SSTX0-
IDE_D11 USB_SSRX0+ USB_SSTX0+
IDE_D12 GND GND
IDE_D4 USB_SSRX1- USB_SSTX1-
IDE_D0 USB_SSRX1+ USB_SSTX1+
IDE_REQ GND GND
IDE_IOW# USB_SSRX2- USB_SSTX2-
IDE_ACK# USB_SSRX2+ USB_SSTX2+
GND(FIXED) GND(FIXED) GND(FIXED)
IDE_IRQ USB_SSRX3- USB_SSTX3-
IDE_A0 USB_SSRX3+ USB_SSTX3+
IDE_A1 GND GND
IDE_A2 DDI1_PAIR6+ DDI1_CTRLCLK_AUX+
IDE_CS1# DDI1_PAIR6- DDI1_CTRLDATA_AUX-
IDE_CS3# RSVD RSVD
IDE_RESET# RSVD RSVD
PCI_GNT3# PCIE_RX6+ PCIE_TX6+
PCI_REQ3# PCIE_RX6- PCIE_TX6-
GND(FIXED) GND(FIXED) GND(FIXED)
PCI_AD1 PCIE_RX7+ PCIE_TX7+
PCI_AD3 PCIE_RX7- PCIE_TX7-
PCI_AD5 DDI1_HPD RSVD
PCI_AD7 DDI1_PAIR4 + RSVD
PCI_C/BE0# DDI1_PAIR4- DDI1_PAIR0+
PCI_AD9 RSVD DDI1_PAIR0-
PCI_AD11 RSVD RSVD
PCI_AD13 DDI1_PAIR5+ DDI1_PAIR1+
PCI_AD15 DDI1_PAIR5- DDI1_PAIR1-
GND(FIXED) GND(FIXED) GND(FIXED)
PCI_PAR DDI2_CTRLCLK_AUX+ DDI1_PAIR2+
PCI_SERR# DDI2_CTRLDATA_AUX- DDI1_PAIR2-
PCI_STOP# DDI2_DDC_AUX_SEL DDI1_DDC_AUX_SEL
PCI_TRDY# RSVD RSVD
PCI_FRAME# DDI3_CTRLCLK_AUX+ DDI1_PAIR3+
PCI_AD16 DDI3_CTRLDATA_AUX- DDI1_PAIR3-
PCI_AD18 DDI3_DDC_AUX_SEL RSVD
PCI_AD20 DDI3_PAIR0+ DDI2_PAIR0+
PCI_AD22 DDI3_PAIR0- DDI2_PAIR0-
GND(FIXED) GND(FIXED) GND(FIXED)
PCI_AD24 DDI3_PAIR1+ DDI2_PAIR1+
PCI_AD26 DDI3_PAIR1- DDI2_PAIR1-
PCI_AD28 DDI3_HPD DDI2_HPD
PCI_AD30 RSVD RSVD
PCI_IRQC# DDI3_PAIR2+ DDI2_PAIR2+
PCI_IRQD# DDI3_PAIR2- DDI2_PAIR2-
PCI_CLKRUN# RSVD RSVD
PCI_M66EN DDI3_PAIR3+ DDI2_PAIR3+
PCI_CLK DDI3_PAIR3- DDI2_PAIR3-
GND(FIXED) GND(FIXED) GND(FIXED)
PEG_TX0+ PEG_RX0+ PEG_TX0+
PEG_TX0- PEG_RX0- PEG_TX0-
PEG_LANE_RV# TYPE0# PEG_LANE_RV#
PEG_TX1+ PEG_RX1+ PEG_TX1+
PEG_TX1- PEG_RX1- PEG_TX1-
TYPE2# TYPE1# TYPE2#
PEG_TX2+ PEG_RX2+ PEG_TX2+
PEG_TX2- PEG_RX2- PEG_TX2-
 GND(FIXED) GND(FIXED) GND(FIXED)
PEG_TX3+ PEG_RX3+ PEG_TX3+
PEG_TX3- PEG_RX3- PEG_TX3-
RSVD RSVD RSVD
RSVD RSVD RSVD
PEG_TX4+ PEG_RX4+ PEG_TX4+
PEG_TX4- PEG_RX4- PEG_TX4-
GND RSVD GND
PEG_TX5+ PEG_RX5+ PEG_TX5+
PEG_TX5- PEG_RX5- PEG_TX5-
GND(FIXED) GND(FIXED) GND(FIXED)
PEG_TX6+ PEG_RX6+ PEG_TX6+
PEG_TX6- PEG_RX6- PEG_TX6-
SDVO_CLK GND GND
PEG_TX7+ PEG_RX7+ PEG_TX7+
PEG_TX7- PEG_RX7- PEG_TX7-
GND GND GND
IDE_CBLID# RSVD RSVD
PEG_TX8+ PEG_RX8+ PEG_TX8+
PEG_TX8- PEG_RX8- PEG_TX8-
GND(FIXED) GND(FIXED) GND(FIXED)
PEG_TX9+ PEG_RX9+ PEG_TX9+
PEG_TX9- PEG_RX9- PEG_TX9-
RSVD TPM_PP RSVD RSVD
GND GND GND
PEG_TX10+ PEG_RX10+ PEG_TX10+
PEG_TX10- PEG_RX10- PEG_TX10-
GND GND GND
PEG_TX11+ PEG_RX11+ PEG_TX11+
PEG_TX11- PEG_RX11- PEG_TX11-
GND(FIXED) GND(FIXED) GND(FIXED)
PEG_TX12+ PEG_RX12+ PEG_TX12+
PEG_TX12- PEG_RX12- PEG_TX12-
GND GND GND
PEG_TX13+ PEG_RX13+ PEG_TX13+
PEG_TX13- PEG_RX13- PEG_TX13-
GND GND GND
PEG_ENABLE# RSVD RSVD
PEG_TX14+ PEG_RX14+ PEG_TX14+
PEG_TX14- PEG_RX14- PEG_TX14-
GND(FIXED) GND(FIXED) GND(FIXED)
PEG_TX15+ PEG_RX15+ PEG_TX15+
PEG_TX15- PEG_RX15- PEG_TX15-
GND GND GND
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
GND(FIXED) GND(FIXED) GND(FIXED)

ype 3, Type 4 and Type 5 Pin-Out

. 2.0 TYPE 4 Rev. 2.0
Row B Row A Row B
GND(FIXED) GND(FIXED) GND(FIXED)
GBE0_ACT# GBE0_MDI3- GBE0_ACT#
LPC_FRAME# GBE0_MDI3+ LPC_FRAME#
LPC_AD0 GBE0_LINK100# LPC_AD0
LPC_AD1 GBE0_LINK1000# LPC_AD1
LPC_AD2 GBE0_MDI2- LPC_AD2
LPC_AD3 GBE0_MDI2+ LPC_AD3
LPC_DRQ0# GBE0_LINK# LPC_DRQ0#
LPC_DRQ1# GBE0_MDI1- LPC_DRQ1#
LPC_CLK GBE0_MDI1+ LPC_CLK
GND(FIXED) GND(FIXED) GND(FIXED)
PWRBTN# GBE0_MDI0- PWRBTN#
SMB_CK GBE0_MDI0+ SMB_CK
SMB_DAT GBE0_CTREF SMB_DAT
SMB_ALERT# SUS_S3# SMB_ALERT#
SATA1_TX+ SATA0_TX+ SATA1_TX+
SATA1_TX- SATA0_TX- SATA1_TX-
SUS_STAT# SUS_S4# SUS_STAT#
SATA1_RX+ SATA0_RX+ SATA1_RX+
SATA1_RX- SATA0_RX- SATA1_RX-
GND(FIXED) GND(FIXED) GND(FIXED)
SATA3_TX+ SATA2_TX+ SATA3_TX+
SATA3_TX- SATA2_TX- SATA3_TX-
PWR_OK SUS_S5# PWR_OK
SATA3_RX+ SATA2_RX+ SATA3_RX+
SATA3_RX- SATA2_RX- SATA3_RX-
WDT BATLOW# WDT
AC/HDA_SDIN2 (S)ATA_ACT# AC/HDA_SDIN2
AC/HDA_SDIN1 AC/HDA_SYNC AC/HDA_SDIN1
AC/HDA_SDIN0 AC/HDA_RST# AC/HDA_SDIN0
GND(FIXED) GND(FIXED) GND(FIXED)
SPKR AC/HDA_BITCLK SPKR
I2C_CK AC/HDA_SDOUT I2C_CK
I2C_DAT BIOS_DIS0# I2C_DAT
THRM# THRMTRIP# THRM#
USB7- USB6- USB7-
USB7+ USB6+ USB7+
USB_4_5_OC# USB_6_7_OC# USB_4_5_OC#
USB5- USB4- USB5-
USB5+ USB4+ USB5+
GND(FIXED) GND(FIXED) GND(FIXED)
USB3- USB2- USB3-
USB3+ USB2+ USB3+
USB_0_1_OC# USB_2_3_OC# USB_0_1_OC#
USB1- USB0- USB1-
USB1+ USB0+ USB1+
EXCD1_PERST# VCC_RTC EXCD1_PERST#
EXCD1_CPPE# EXCD0_PERST# EXCD1_CPPE#
SYS_RESET# EXCD0_CPPE# SYS_RESET#
CB_RESET# LPC_SERIRQ CB_RESET#
GND(FIXED) GND(FIXED) GND(FIXED)
PCIE_RX5+ PCIE_TX5+ PCIE_RX5+
PCIE_RX5- PCIE_TX5- PCIE_RX5-
GPO1 GPI0 GPO1
PCIE_RX4+ PCIE_TX4+ PCIE_RX4+
PCIE_RX4- PCIE_TX4- PCIE_RX4-
GPO2 GND GPO2
PCIE_RX3+ PCIE_TX3+ PCIE_RX3+
PCIE_RX3- PCIE_TX3- PCIE_RX3-
GND(FIXED) GND(FIXED) GND(FIXED)
PCIE_RX2+ PCIE_TX2+ PCIE_RX2+
PCIE_RX2- PCIE_TX2- PCIE_RX2-
GPO3 GPI1 GPO3
PCIE_RX1+ PCIE_TX1+ PCIE_RX1+
PCIE_RX1- PCIE_TX1- PCIE_RX1-
WAKE0# GND WAKE0#
WAKE1# GPI2 WAKE1#
PCIE_RX0+ PCIE_TX0+ PCIE_RX0+
PCIE_RX0- PCIE_TX0- PCIE_RX0-
GND(FIXED) GND(FIXED) GND(FIXED)
LVDS_B0+ LVDS_A0+ LVDS_B0+
LVDS_B0- LVDS_A0- LVDS_B0-
LVDS_B1+ LVDS_A1+ LVDS_B1+
LVDS_B1- LVDS_A1- LVDS_B1-
LVDS_B2+ LVDS_A2+ LVDS_B2+
LVDS_B2- LVDS_A2- LVDS_B2-
LVDS_B3+ LVDS_VDD_EN LVDS_B3+
LVDS_B3- LVDS_A3+ LVDS_B3-
LVDS_BKLT_EN LVDS_A3- LVDS_BKLT_EN
GND(FIXED) GND(FIXED) GND(FIXED)
LVDS_B_CK+ LVDS_A_CK+ LVDS_B_CK+
LVDS_B_CK- LVDS_A_CK- LVDS_B_CK-
LVDS_BKLT_CTRL LVDS_I2C_CK LVDS_BKLT_CTRL
VCC_5V_SBY LVDS_I2C_DAT VCC_5V_SBY
VCC_5V_SBY GPI3 VCC_5V_SBY
VCC_5V_SBY KBD_RST# VCC_5V_SBY
VCC_5V_SBY KBD_A20GATE VCC_5V_SBY
BIOS_DIS1# PCIE_CLK_REF+ BIOS_DIS1#
VGA_RED PCIE_CLK_REF- VGA_RED
GND(FIXED) GND(FIXED) GND(FIXED)
VGA_GRN SPI_POWER VGA_GRN
VGA_BLU SPI_MISO VGA_BLU
VGA_HSYNC GPO0 VGA_HSYNC
VGA_VSYNC SPI_CLK VGA_VSYNC
VGA_I2C_CK SPI_MOSI VGA_I2C_CK
VGA_I2C_DAT GND VGA_I2C_DAT
SPI_CS# TYPE10# SPI_CS#
RSVD RSVD RSVD
RSVD RSVD RSVD
GND(FIXED) GND(FIXED) GND(FIXED)
RSVD RSVD RSVD
RSVD RSVD RSVD
RSVD RSVD RSVD
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
 VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
GND(FIXED) GND(FIXED) GND(FIXED)

. 2.0 TYPE 4 Rev. 2.0

Row D Row C Row D
GND (FIXED) GND (FIXED) GND (FIXED)
GBE2_ACT# IDE_D7 IDE_D5
GBE2_MDI3- IDE_D6 IDE_D10
GBE2_MDI3+ IDE_D3 IDE_D11
GBE2_LINK100# IDE_D15 IDE_D12
GBE2_MDI2- IDE_D8 IDE_D4
GBE2_MDI2+ IDE_D9 IDE_D0
GBE2_LINK1000# IDE_D2 IDE_REQ
GBE2_MDI1- IDE_D13 IDE_IOW#
GBE2_MDI1+ IDE_D1 IDE_ACK#
GND (FIXED) GND (FIXED) GND (FIXED)
GBE2_MDI0- IDE_D14 IDE_IRQ
GBE2_MDI0+ IDE_IORDY IDE_A0
GBE2_LINK# IDE_IOR# IDE_A1
GBE2_CTREF RSVD IDE_A2
RSVD RSVD IDE_CS1#
RSVD RSVD IDE_CS3#
RSVD RSVD IDE_RESET#
PCI_GNT3# PCIE_RX6+ PCIE_TX6+
PCI_REQ3# PCIE_RX6- PCIE_TX6-
GND (FIXED) GND (FIXED) GND (FIXED)
PCI_AD1 PCIE_RX7+ PCIE_TX7+
PCI_AD3 PCIE_RX7- PCIE_TX7-
PCI_AD5 RSVD RSVD
PCI_AD7 RSVD RSVD
PCI_C/BE0# PCIE_RX8+ PCIE_TX8+
PCI_AD9 PCIE_RX8- PCIE_TX8-
PCI_AD11 RSVD RSVD
PCI_AD13 PCIE_RX9+ PCIE_TX9+
PCI_AD15 PCIE_RX9- PCIE_TX9-
GND (FIXED) GND (FIXED) GND (FIXED)
PCI_PAR PCIE_RX10+ PCIE_TX10+
PCI_SERR# PCIE_RX10- PCIE_TX10-
PCI_STOP# RSVD RSVD
PCI_TRDY# RSVD RSVD
PCI_FRAME# PCIE_RX11+ PCIE_TX11+
PCI_AD16 PCIE_RX11- PCIE_TX11-
PCI_AD18 RSVD RSVD
PCI_AD20 PCIE_RX12+ PCIE_TX12+
PCI_AD22 PCIE_RX12- PCIE_TX12-
GND (FIXED) GND (FIXED) GND (FIXED)
PCI_AD24 PCIE_RX13+ PCIE_TX13+
PCI_AD26 PCIE_RX13- PCIE_TX13-
PCI_AD28 RSVD RSVD
PCI_AD30 RSVD RSVD
PCI_IRQC# PCIE_RX14+ PCIE_TX14+
PCI_IRQD# PCIE_RX14- PCIE_TX14-
PCI_CLKRUN# RSVD RSVD
PCI_M66EN PCIE_RX15+ PCIE_TX15+
PCI_CLK PCIE_RX15- PCIE_TX15-
GND (FIXED) GND (FIXED) GND (FIXED)
PEG_TX0+ PCIE_RX16+ PCIE_TX16+
PEG_TX0- PCIE_RX16- PCIE_TX16-
PEG_LANE_RV# TYPE0# PEG_LANE_RV#
PEG_TX1+ PCIE_RX17+ PCIE_TX17+
PEG_TX1- PCIE_RX17- PCIE_TX17-
TYPE2# TYPE1# TYPE2#
PEG_TX2+ PCIE_RX18+ PCIE_TX18+
PEG_TX2- PCIE_RX18- PCIE_TX18-
GND (FIXED) GND (FIXED) GND (FIXED)
PEG_TX3+ PCIE_RX19+ PCIE_TX19+
PEG_TX3- PCIE_RX19- PCIE_TX19-
RSVD RSVD RSVD
RSVD RSVD RSVD
PEG_TX4+ PCIE_RX20+ PCIE_TX20+
PEG_TX4- PCIE_RX20- PCIE_TX20-
GND RSVD GND
PEG_TX5+ PCIE_RX21+ PCIE_TX21+
PEG_TX5- PCIE_RX21- PCIE_TX21-
GND (FIXED) GND (FIXED) GND (FIXED)
PEG_TX6+ PCIE_RX22+ PCIE_TX22+
PEG_TX6- PCIE_RX22- PCIE_TX22-
SDVO_CLK SDVO_DATA SDVO_CLK
PEG_TX7+ PCIE_RX23+ PCIE_TX23+
PEG_TX7- PCIE_RX23- PCIE_TX23-
GND GND GND
RSVD RSVD IDE_CBLID#
PEG_TX8+ PCIE_RX24+ PCIE_TX24+
PEG_TX8- PCIE_RX24- PCIE_TX24-
GND (FIXED) GND (FIXED) GND (FIXED)
PEG_TX9+ PCIE_RX25+ PCIE_TX25+
PEG_TX9- PCIE_RX25- PCIE_TX25-
RSVD RSVD RSVD
GND GND GND
PEG_TX10+ PCIE_RX26+ PCIE_TX26+
PEG_TX10- PCIE_RX26- PCIE_TX26-
GND GND GND
PEG_TX11+ PCIE_RX27+ PCIE_TX27+
PEG_TX11- PCIE_RX27- PCIE_TX27-
GND (FIXED) GND (FIXED) GND (FIXED)
PEG_TX12+ PCIE_RX28+ PCIE_TX28+
PEG_TX12- PCIE_RX28- PCIE_TX28-
GND GND GND
PEG_TX13+ PCIE_RX29+ PCIE_TX29+
PEG_TX13- PCIE_RX29- PCIE_TX29-
GND GND GND
PEG_ENABLE# RSVD PEG_ENABLE#
PEG_TX14+ PCIE_RX30+ PCIE_TX30+
PEG_TX14- PCIE_RX30- PCIE_TX30-
GND (FIXED) GND (FIXED) GND (FIXED)
PEG_TX15+ PCIE_RX31+ PCIE_TX31+
PEG_TX15- PCIE_RX31- PCIE_TX31-
GND GND GND
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
VCC_12V VCC_12V VCC_12V
GND (FIXED) GND (FIXED) GND (FIXED)
Type 10 Rev. 2.1
Row A Row B
GND(FIXED) GND(FIXED)
GBE0_MDI3- GBE0_ACT#
GBE0_MDI3+ LPC_FRAME#
GBE0_LINK100# LPC_AD0
GBE0_LINK1000# LPC_AD1
GBE0_MDI2- LPC_AD2
GBE0_MDI2+ LPC_AD3
GBE0_LINK# LPC_DRQ0#
GBE0_MDI1- LPC_DRQ1#
GBE0_MDI1+ LPC_CLK
GND(FIXED) GND(FIXED)
GBE0_MDI0- PWRBTN#
GBE0_MDI0+ SMB_CK
GBE0_CTREF SMB_DAT
SUS_S3# SMB_ALERT#
SATA0_TX+ SATA1_TX+
SATA0_TX- SATA1_TX-
SUS_S4# SUS_STAT#
SATA0_RX+ SATA1_RX+
SATA0_RX- SATA1_RX-
GND(FIXED) GND(FIXED)
USB_SSRX0- USB_SSTX0-
USB_SSRX0+ USB_SSTX0+
SUS_S5# PWR_OK
USB_SSRX1- USB-SSTX1-
USB_SSRX1+ USB-SSTX1+
BATLOW# WDT
(S)ATA_ACT# AC/HDA_SDIN2
AC/HDA_SYNC AC/HDA_SDIN1
AC/HDA_RST# AC/HDA_SDIN0
GND(FIXED) GND(FIXED)
AC/HDA_BITCLK SPKR
AC/HDA_SDOUT I2C_CK
BIOS_DIS0# I2C_DAT
THRMTRIP# THRM#
USB6- USB7-
USB6+ USB7+
USB_6_7_OC# USB_4_5_OC#
USB4- USB5-
USB4+ USB5+
GND(FIXED) GND(FIXED)
USB2- USB3-
USB2+ USB3+
USB_2_3_OC# USB_0_1_OC#
USB0- USB1-
USB0+ USB1+
VCC_RTC EXCD1_PERST#
EXCD0_PERST# EXCD1_CPPE#
EXCD0_CPPE# SYS_RESET#
LPC_SERIRQ CB_RESET#
GND(FIXED) GND(FIXED)
RSVD RSVD
RSVD RSVD
GPI0 GPO1
RSVD RSVD
RSVD RSVD
GND GPO2
PCIE_TX3+ PCIE_RX3+
PCIE_TX3- PCIE_RX3-
GND(FIXED) GND(FIXED)
PCIE_TX2+ PCIE_RX2+
PCIE_TX2- PCIE_RX2-
GPI1 GPO3
PCIE_TX1+ PCIE_RX1+
PCIE_TX1- PCIE_RX1-
GND WAKE0#
GPI2 WAKE1#
PCIE_TX0+ PCIE_RX0+
PCIE_TX0- PCIE_RX0-
GND(FIXED) GND(FIXED)
LVDS_A0+ DDI0_PAIR0+
LVDS_A0- DDI0_PAIR0-
LVDS_A1+ DDI0_PAIR1+
LVDS_A1- DDI0_PAIR1-
LVDS_A2+ DDI0_PAIR2+
LVDS_A2- DDI0_PAIR2-
LVDS_VDD_EN DDI0_PAIR4+
LVDS_A3+ DDI0_PAIR4-
LVDS_A3- LVDS_BKLT_EN
GND(FIXED) GND(FIXED)
LVDS_A_CK+ DDI0_PAIR3+
LVDS_A_CK- DDI0_PAIR3-
LVDS_I2C_CK LVDS_BKLT_CTRL
LVDS_I2C_DAT VCC_5V_SBY
GPI3 VCC_5V_SBY
RSVD VCC_5V_SBY
eDP_HPD VCC_5V_SBY
PCIE_CLK_REF+ BIOS_DIS1#
PCIE_CLK_REF- DD0_HPD
GND(FIXED) GND(FIXED)
SPI_POWER DDI0_PAIR5+
SPI_MISO DDI0_PAIR5-
GPO0 DDI0_PAIR6+
SPI_CLK DDI0_PAIR6-
SPI_MOSI DDI0_DDC_AUX_SEL
TPM_PP USB_HOST_PR
TYPE10# SPI_CS#
SER0_TX DDI0_CTRLCLK_AUX+
SER0_RX DDI0_CTRLDATA_AUX-
GND(FIXED) GND(FIXED)
SER1_TX FAN_PWMOUT
SER1_RX FAN_TACHIN
LID# SLEEP#
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
GND(FIXED) GND(FIXED)

TYPE 6 Rev. 2.1

Row A Row B
GND(FIXED) GND(FIXED)
GBE0_MDI3- GBE0_ACT#
GBE0_MDI3+ LPC_FRAME#
GBE0_LINK100# LPC_AD0
GBE0_LINK1000# LPC_AD1
GBE0_MDI2- LPC_AD2
GBE0_MDI2+ LPC_AD3
GBE0_LINK# LPC_DRQ0#
GBE0_MDI1- LPC_DRQ1#
GBE0_MDI1+ LPC_CLK
GND(FIXED) GND(FIXED)
GBE0_MDI0- PWRBTN#
GBE0_MDI0+ SMB_CK
GBE0_CTREF SMB_DAT
SUS_S3# SMB_ALERT#
SATA0_TX+ SATA1_TX+
SATA0_TX- SATA1_TX-
SUS_S4# SUS_STAT#
SATA0_RX+ SATA1_RX+
SATA0_RX- SATA1_RX-
GND(FIXED) GND(FIXED)
SATA2_TX+ SATA3_TX+
SATA2_TX- SATA3_TX-
SUS_S5# PWR_OK
SATA2_RX+ SATA3_RX+
SATA2_RX- SATA3_RX-
BATLOW# WDT
(S)ATA_ACT# AC/HDA_SDIN2
AC/HDA_SYNC AC/HDA_SDIN1
AC/HDA_RST# AC/HDA_SDIN0
GND(FIXED) GND(FIXED)
AC/HDA_BITCLK SPKR
AC/HDA_SDOUT I2C_CK
BIOS_DIS0# I2C_DAT
THRMTRIP# THRM#
USB6- USB7-
USB6+ USB7+
USB_6_7_OC# USB_4_5_OC#
USB4- USB5-
USB4+ USB5+
GND(FIXED) GND(FIXED)
USB2- USB3-
USB2+ USB3+
USB_2_3_OC# USB_0_1_OC#
USB0- USB1-
USB0+ USB1+
VCC_RTC EXCD1_PERST#
EXCD0_PERST# EXCD1_CPPE#
EXCD0_CPPE# SYS_RESET#
LPC_SERIRQ CB_RESET#
GND(FIXED) GND(FIXED)
PCIE_TX5+ PCIE_RX5+
PCIE_TX5- PCIE_RX5-
GPI0 GPO1
PCIE_TX4+ PCIE_RX4+
PCIE_TX4- PCIE_RX4-
GND GPO2
PCIE_TX3+ PCIE_RX3+
PCIE_TX3- PCIE_RX3-
GND(FIXED) GND(FIXED)
PCIE_TX2+ PCIE_RX2+
PCIE_TX2- PCIE_RX2-
GPI1 GPO3
PCIE_TX1+ PCIE_RX1+
PCIE_TX1- PCIE_RX1-
GND WAKE0#
GPI2 WAKE1#
PCIE_TX0+ PCIE_RX0+
PCIE_TX0- PCIE_RX0-
GND(FIXED) GND(FIXED)
LVDS_A0+ LVDS_B0+
LVDS_A0- LVDS_B0-
LVDS_A1+ LVDS_B1+
LVDS_A1- LVDS_B1-
LVDS_A2+ LVDS_B2+
LVDS_A2- LVDS_B2-
LVDS_VDD_EN LVDS_B3+
LVDS_A3+ LVDS_B3-
LVDS_A3- LVDS_BKLT_EN
GND(FIXED) GND(FIXED)
LVDS_A_CK+ LVDS_B_CK+
LVDS_A_CK- LVDS_B_CK-
LVDS_I2C_CK LVDS_BKLT_CTRL
LVDS_I2C_DAT VCC_5V_SBY
GPI3 VCC_5V_SBY
RSVD VCC_5V_SBY
eDP_HPD VCC_5V_SBY
PCIE_CLK_REF+ BIOS_DIS1#
PCIE_CLK_REF- VGA_RED
GND(FIXED) GND(FIXED)
SPI_POWER VGA_GRN
SPI_MISO VGA_BLU
GPO0 VGA_HSYNC
SPI_CLK VGA_VSYNC
SPI_MOSI VGA_I2C_CK
TPM_PP VGA_I2C_DAT
TYPE10# SPI_CS#
SER0_TX RSVD
SER0_RX RSVD
GND(FIXED) GND(FIXED)
SER1_TX FAN_PWMOUT
SER1_RX FAN_TACHIN
LID# SLEEP#
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
GND(FIXED) GND(FIXED)

TYPE 6 Rev. 2.1

Row C Row D
GND(FIXED) GND(FIXED)
GND GND
USB_SSRX0- USB_SSTX0-
USB_SSRX0+ USB_SSTX0+
GND GND
USB_SSRX1- USB_SSTX1-
USB_SSRX1+ USB_SSTX1+
GND GND
USB_SSRX2- USB_SSTX2-
USB_SSRX2+ USB_SSTX2+
GND(FIXED) GND(FIXED)
USB_SSRX3- USB_SSTX3-
USB_SSRX3+ USB_SSTX3+
GND GND
DDI1_PAIR6+ DDI1_CTRLCLK_AUX+
DDI1_PAIR6- DDI1_CTRLDATA_AUX-
RSVD RSVD
RSVD RSVD
PCIE_RX6+ PCIE_TX6+
PCIE_RX6- PCIE_TX6-
GND(FIXED) GND(FIXED)
PCIE_RX7+ PCIE_TX7+
PCIE_RX7- PCIE_TX7-
DDI1_HPD RSVD
DDI1_PAIR4 + RSVD
DDI1_PAIR4- DDI1_PAIR0+
RSVD DDI1_PAIR0-
RSVD RSVD
DDI1_PAIR5+ DDI1_PAIR1+
DDI1_PAIR5- DDI1_PAIR1-
GND(FIXED) GND(FIXED)
DDI2_CTRLCLK_AUX+ DDI1_PAIR2+
DDI2_CTRLDATA_AUX- DDI1_PAIR2-
DDI2_DDC_AUX_SEL DDI1_DDC_AUX_SEL
RSVD RSVD
DDI3_CTRLCLK_AUX+ DDI1_PAIR3+
DDI3_CTRLDATA_AUX- DDI1_PAIR3-
DDI3_DDC_AUX_SEL RSVD
DDI3_PAIR0+ DDI2_PAIR0+
DDI3_PAIR0- DDI2_PAIR0-
GND(FIXED) GND(FIXED)
DDI3_PAIR1+ DDI2_PAIR1+
DDI3_PAIR1- DDI2_PAIR1-
DDI3_HPD DDI2_HPD
RSVD RSVD
DDI3_PAIR2+ DDI2_PAIR2+
DDI3_PAIR2- DDI2_PAIR2-
RSVD RSVD
DDI3_PAIR3+ DDI2_PAIR3+
DDI3_PAIR3- DDI2_PAIR3-
GND(FIXED) GND(FIXED)
PEG_RX0+ PEG_TX0+
PEG_RX0- PEG_TX0-
TYPE0# PEG_LANE_RV#
PEG_RX1+ PEG_TX1+
PEG_RX1- PEG_TX1-
TYPE1# TYPE2#
PEG_RX2+ PEG_TX2+
PEG_RX2- PEG_TX2-
GND(FIXED) GND(FIXED)
PEG_RX3+ PEG_TX3+
PEG_RX3- PEG_TX3-
RSVD RSVD
RSVD RSVD
PEG_RX4+ PEG_TX4+
PEG_RX4- PEG_TX4-
RSVD GND
PEG_RX5+ PEG_TX5+
PEG_RX5- PEG_TX5-
GND(FIXED) GND(FIXED)
PEG_RX6+ PEG_TX6+
PEG_RX6- PEG_TX6-
GND GND
PEG_RX7+ PEG_TX7+
PEG_RX7- PEG_TX7-
GND GND
RSVD RSVD
PEG_RX8+ PEG_TX8+
PEG_RX8- PEG_TX8-
GND(FIXED) GND(FIXED)
PEG_RX9+ PEG_TX9+
PEG_RX9- PEG_TX9-
RSVD RSVD
GND GND
PEG_RX10+ PEG_TX10+
PEG_RX10- PEG_TX10-
GND GND
PEG_RX11+ PEG_TX11+
PEG_RX11- PEG_TX11-
GND(FIXED) GND(FIXED)
PEG_RX12+ PEG_TX12+
PEG_RX12- PEG_TX12-
GND GND
PEG_RX13+ PEG_TX13+
PEG_RX13- PEG_TX13-
GND GND
RSVD RSVD
PEG_RX14+ PEG_TX14+
PEG_RX14- PEG_TX14-
GND(FIXED) GND(FIXED)
PEG_RX15+ PEG_TX15+
PEG_RX15- PEG_TX15-
GND GND
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
GND(FIXED) GND(FIXED)
TYPE 5 Rev. 2.0
Row A Row B
GND(FIXED) GND(FIXED)
GBE0_MDI3- GBE0_ACT#
GBE0_MDI3+ LPC_FRAME#
GBE0_LINK100# LPC_AD0
GBE0_LINK1000# LPC_AD1
GBE0_MDI2- LPC_AD2
GBE0_MDI2+ LPC_AD3
GBE0_LINK# LPC_DRQ0#
GBE0_MDI1- LPC_DRQ1#
GBE0_MDI1+ LPC_CLK
GND(FIXED) GND(FIXED)
GBE0_MDI0- PWRBTN#
GBE0_MDI0+ SMB_CK
GBE0_CTREF SMB_DAT
SUS_S3# SMB_ALERT#
SATA0_TX+ SATA1_TX+
SATA0_TX- SATA1_TX-
SUS_S4# SUS_STAT#
SATA0_RX+ SATA1_RX+
SATA0_RX- SATA1_RX-
GND(FIXED) GND(FIXED)
SATA2_TX+ SATA3_TX+
SATA2_TX- SATA3_TX-
SUS_S5# PWR_OK
SATA2_RX+ SATA3_RX+
SATA2_RX- SATA3_RX-
BATLOW# WDT
(S)ATA_ACT# AC/HDA_SDIN2
AC/HDA_SYNC AC/HDA_SDIN1
AC/HDA_RST# AC/HDA_SDIN0
GND(FIXED) GND(FIXED)
AC/HDA_BITCLK SPKR
AC/HDA_SDOUT I2C_CK
BIOS_DIS0# I2C_DAT
THRMTRIP# THRM#
USB6- USB7-
USB6+ USB7+
USB_6_7_OC# USB_4_5_OC#
USB4- USB5-
USB4+ USB5+
GND(FIXED) GND(FIXED)
USB2- USB3-
USB2+ USB3+
USB_2_3_OC# USB_0_1_OC#
USB0- USB1-
USB0+ USB1+
VCC_RTC EXCD1_PERST#
EXCD0_PERST# EXCD1_CPPE#
EXCD0_CPPE# SYS_RESET#
LPC_SERIRQ CB_RESET#
GND(FIXED) GND(FIXED)
PCIE_TX5+ PCIE_RX5+
PCIE_TX5- PCIE_RX5-
GPI0 GPO1
PCIE_TX4+ PCIE_RX4+
PCIE_TX4- PCIE_RX4-
GND GPO2
PCIE_TX3+ PCIE_RX3+
PCIE_TX3- PCIE_RX3-
GND(FIXED) GND(FIXED)
PCIE_TX2+ PCIE_RX2+
PCIE_TX2- PCIE_RX2-
GPI1 GPO3
PCIE_TX1+ PCIE_RX1+
PCIE_TX1- PCIE_RX1-
GND WAKE0#
GPI2 WAKE1#
PCIE_TX0+ PCIE_RX0+
PCIE_TX0- PCIE_RX0-
GND(FIXED) GND(FIXED)
LVDS_A0+ LVDS_B0+
LVDS_A0- LVDS_B0-
LVDS_A1+ LVDS_B1+
LVDS_A1- LVDS_B1-
LVDS_A2+ LVDS_B2+
LVDS_A2- LVDS_B2-
LVDS_VDD_EN LVDS_B3+
LVDS_A3+ LVDS_B3-
LVDS_A3- LVDS_BKLT_EN
GND(FIXED) GND(FIXED)
LVDS_A_CK+ LVDS_B_CK+
LVDS_A_CK- LVDS_B_CK-
LVDS_I2C_CK LVDS_BKLT_CTRL
LVDS_I2C_DAT VCC_5V_SBY
GPI3 VCC_5V_SBY
KBD_RST# VCC_5V_SBY
KBD_A20GATE VCC_5V_SBY
PCIE_CLK_REF+ BIOS_DIS1#
PCIE_CLK_REF- VGA_RED
GND(FIXED) GND(FIXED)
SPI_POWER VGA_GRN
SPI_MISO VGA_BLU
GPO0 VGA_HSYNC
SPI_CLK VGA_VSYNC
SPI_MOSI VGA_I2C_CK
GND VGA_I2C_DAT
TYPE10# SPI_CS#
RSVD RSVD
RSVD RSVD
GND(FIXED) GND(FIXED)
RSVD RSVD
RSVD RSVD
RSVD RSVD
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
GND(FIXED) GND(FIXED)

TYPE 5 Rev. 2.0

Row C Row D
GND (FIXED) GND (FIXED)
GBE1_ACT# GBE2_ACT#
GBE1_MDI3- GBE2_MDI3-
GBE1_MDI3+ GBE2_MDI3+
GBE1_LINK100# GBE2_LINK100#
GBE1_MDI2- GBE2_MDI2-
GBE1_MDI2+ GBE2_MDI2+
GBE1_LINK1000# GBE2_LINK1000#
GBE1_MDI1- GBE2_MDI1-
GBE1_MDI1+ GBE2_MDI1+
GND (FIXED) GND (FIXED)
GBE1_MDI0- GBE2_MDI0-
GBE1_MDI0+ GBE2_MDI0+
GBE1_LINK# GBE2_LINK#
RSVD GBE2_CTREF
RSVD RSVD
RSVD RSVD
RSVD RSVD
PCIE_RX6+ PCIE_TX6+
PCIE_RX6- PCIE_TX6-
GND (FIXED) GND (FIXED)
PCIE_RX7+ PCIE_TX7+
PCIE_RX7- PCIE_TX7-
RSVD RSVD
RSVD RSVD
PCIE_RX8+ PCIE_TX8+
PCIE_RX8- PCIE_TX8-
RSVD RSVD
PCIE_RX9+ PCIE_TX9+
PCIE_RX9- PCIE_TX9-
GND (FIXED) GND (FIXED)
PCIE_RX10+ PCIE_TX10+
PCIE_RX10- PCIE_TX10-
RSVD RSVD
RSVD RSVD
PCIE_RX11+ PCIE_TX11+
PCIE_RX11- PCIE_TX11-
RSVD RSVD
PCIE_RX12+ PCIE_TX12+
PCIE_RX12- PCIE_TX12-
GND (FIXED) GND (FIXED)
PCIE_RX13+ PCIE_TX13+
PCIE_RX13- PCIE_TX13-
RSVD RSVD
RSVD RSVD
PCIE_RX14+ PCIE_TX14+
PCIE_RX14- PCIE_TX14-
RSVD RSVD
PCIE_RX15+ PCIE_TX15+
PCIE_RX15- PCIE_TX15-
GND (FIXED) GND (FIXED)
PCIE_RX16+ PCIE_TX16+
PCIE_RX16- PCIE_TX16-
TYPE0# PEG_LANE_RV#
PCIE_RX17+ PCIE_TX17+
PCIE_RX17- PCIE_TX17-
TYPE1# TYPE2#
PCIE_RX18+ PCIE_TX18+
PCIE_RX18- PCIE_TX18-
GND (FIXED) GND (FIXED)
PCIE_RX19+ PCIE_TX19+
PCIE_RX19- PCIE_TX19-
RSVD RSVD
RSVD RSVD
PCIE_RX20+ PCIE_TX20+
PCIE_RX20- PCIE_TX20-
RSVD GND
PCIE_RX21+ PCIE_TX21+
PCIE_RX21- PCIE_TX21-
GND (FIXED) GND (FIXED)
PCIE_RX22+ PCIE_TX22+
PCIE_RX22- PCIE_TX22-
SDVO_DATA SDVO_CLK
PCIE_RX23+ PCIE_TX23+
PCIE_RX23- PCIE_TX23-
GND GND
RSVD RSVD
PCIE_RX24+ PCIE_TX24+
PCIE_RX24- PCIE_TX24-
GND (FIXED) GND (FIXED)
PCIE_RX25+ PCIE_TX25+
PCIE_RX25- PCIE_TX25-
RSVD RSVD
GND GND
PCIE_RX26+ PCIE_TX26+
PCIE_RX26- PCIE_TX26-
GND GND
PCIE_RX27+ PCIE_TX27+
PCIE_RX27- PCIE_TX27-
GND (FIXED) GND (FIXED)
PCIE_RX28+ PCIE_TX28+
PCIE_RX28- PCIE_TX28-
GND GND
PCIE_RX29+ PCIE_TX29+
PCIE_RX29- PCIE_TX29-
GND GND
RSVD PEG_ENABLE#
PCIE_RX30+ PCIE_TX30+
PCIE_RX30- PCIE_TX30-
GND (FIXED) GND (FIXED)
PCIE_RX31+ PCIE_TX31+
PCIE_RX31- PCIE_TX31-
GND GND
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
VCC_12V VCC_12V
GND (FIXED) GND (FIXED)