Journal of Systems Engineering and Electronics (ISSN NO: 1671-1793) Volume 35 ISSUE 2 2025

Design and Analysis of 3- stage Current Starved Ring

Oscillator for EEPROM
Anjali Singh1, Haripriya1, Dr. Yatindra Gaurav2, Sanjeev Gupta2
1
Department of Electronics Engineering, Institute of Engineering and Rural Technology, Prayagraj-211002
2
Assistant Professor, Department of Electronics Engineering, Institute of Engineering and Rural Technology, Prayagraj-
211002

Abstract: The recent developments focus on low A current-starved oscillator is a type of voltage-
power high, speed designs for portability. This paper controlled oscillator (VCO) where the current supplied to
presents a new technique design of a three-stage the oscillator stages is limited or “starved” by
single-ended current-starved ring oscillator (CSRO) additional transistors. This design allows for finer control
to improve frequency performance of CMOS ring over the oscillation frequency and power consumption.
oscillator It is based on the addition of MOS The current-starved approach includes biasing the
transistor to boost switching speed of the oscillator transistors with a continuous current source to reduce
delay cell using Cadence Virtuoso, in GPDK 90nm
their operational current. A control voltage (Vctrl) is
technology. A current-starved ring oscillator (CSRO)
supplied to the ring oscillator to enable it to function as
is a voltage-controlled oscillator (VCO) that uses a
a VCO.
control voltage to limit the current available to the
inverter. The oscillator achieves a tunable frequency
range of 20 MHz to 100 MHz by varying the control 2. RING OSCILLATOR CIRCUIT
voltage Vctrl.
2.1 Ring Oscillator
Keywords: CMOS, CADENCE Virtuoso, Current
Ring oscillators are fundamental building blocks in both
Starved Ring Oscillator
digital and analog circuits. A ring oscillator consists of
an odd number of inverting amplifier stages with
1. INTRODUCTION
feedback to its input (Fig.1). When the input voltage is
applied to the first stage, an odd number of stages
Low power Ring oscillator (RO) are the main constructive
produces an inverted output, causing oscillation to begin.
block of the VLSI circuit systems which are used ROs are
used as VCOs in phase-locked loops (PLLs) for clock If the circuit contains an even number of inverters, it
synthesis and frequency modulation, in EEPROMs by cannot function as a ring oscillator, as the output of the
generating internal clock signals. last stage will be the same as the input of the circuit.

A Voltage controlled oscillator (VCO) is one of the

important, basic building blocks in analog and digital
circuits. Voltage controlled oscillator, or generally
oscillator, is a key element in a lot of electronics systems
such a frequency synthesizer, PLL and telecommunication
systems.

Many works have reported for low power ring oscillator

design using CMOS inverter, current starved (CS) Fig. 1. N-stage ring oscillator
inverter technique to have more delay which in turns
decrease frequency and power efficiently. The delay of
Ring oscillators generate timing signals for synchronous
inverter is increased using various method like voltage
scaling, transmission gate, and inverted inverter. These operation and are frequently used as clock generators in
inverter design techniques can be used to generate lower digital systems. They can also serve as frequency
frequency of oscillation with low power consumption. dividers, separating higher frequencies into lower ones.
Two primary types of oscillators are used in digital
system design: the LC tank oscillator and the CMOS ring
oscillator.

PAGE N0: 54
 Journal of Systems Engineering and Electronics (ISSN NO: 1671-1793) Volume 35 ISSUE 2 2025

of the transistors is always off. Power is mainly used during

Compared to LC tank-based oscillators, CMOS ring the transition between these states, which occurs for a brief
oscillators offer several advantages, including a smaller moment when both transistors conduct simultaneously,
size, higher integration, lower operating voltage, and a resulting in a short spike in current.
wider oscillation range. Due to their low power
dissipation and high synthesizability, n- stage CMOS CMOS inverters exhibit significant noise margins, reflecting
ring oscillators find a wide range of applications, such as their ability to tolerate noise at both high and low logic levels,
modulation, demodulation, SRAM, and high-speed which is determined by the voltage transfer characteristic
input-output modules. (VTC) that indicates the noise tolerability without impacting
The oscillation frequency of a ring oscillator is logic states.
represented as
3-PROPOSED DESIGN
The key aspect of this arrangement is that it should
fosc = 𝟏
, consume less power and exhibit minimal variation in
𝟐𝒏𝑻𝒏
where, n= no. of inverter stages Tn= movement frequency in relation to temperature.
time delay of inverter Therefore, the setup consists of a series of current-starved
inverters combined with a temperature-compensating biasing
2.2 CMOS Circuit circuit. The design so implemented allows for finer control
A CMOS inverter is a basic building block in digital over the performance parameters such as frequency of
electronics, particularly in complementary metal- oxide- oscillation and power consumption.
semiconductor (CMOS) technology. It is a logic gate
3.1 Current Starved oscillator
that implements the NOT function, meaning it inverts
the input signal In CMOS ring oscillator the inverting The current-starved oscillator is a kind of voltage- controlled
stage or the inverter is a circuit which is built from a pair oscillator (VCO) where the current supplied to the oscillator is
of nMOS and pMOS transistors operating as limited or ‘starved’ by addition of transistors. The current-
complementary switches (Fig.3) starved approach includes biasing the transistors with a
continuous current source to reduce their operational current
(Fig.4). A control voltage (Vctrl) is supplied to the ring
oscillator to enable it to function as a VCO(Fig.5).

Fig. 2. Inverter Symbol

Fig. 4. Single inverting stage of current starved RO

Fig. 3. CMOS Inverter stage

CMOS inverters consume very little power when they are in a

steady state, whether at logic 0 or logic 1, because one

PAGE N0: 55
 Journal of Systems Engineering and Electronics (ISSN NO: 1671-1793) Volume 35 ISSUE 2 2025

Integration Capability: Current-starved oscillators are easier

to integrate into CMOS technology, leading to smaller chip
area and lower production cost.

Wide Tuning Range: Current-starved oscillators provide a

wider tuning range, which is beneficial for applications like
phase-locked loops (PLLs) in wireless communication system.

4. SIMULATION RESULT

The proposed CMOS ring oscillator has been simulated using

the Cadence Virtuoso tool in a 90 nm technology process. For
the NMOS transistors, the width (W) is set to 120 nm and the
length (L) is 100 nm, while the PMOS transistors also have a
width of 120 nm and a length of 100 nm. The supply voltage
for the circuit is 1 V. The schematic of the proposed circuit is
Fig.5. Circuit Diagram of current starved VCO shown in (Fig 6)
3.2 How does it work? During the operation of the ring oscillator, when an input is
applied to the first inverter, the output of the ring oscillator
In order to control the oscillation frequency, the current
takes some time to stabilize due to the cascading stages of the
through the transistors is starved using additional transistors &
circuit. The output waveform of the proposed CMOS ring
current sources.
oscillator at a supply voltage of 1V is observed during this
This is done by placing a series of transistors in the direction process (Fig. 7).
of flow of the current, efficiently limiting the amount of
current that can flow through the individual inverters.

To control the frequency of the oscillation we can adjust the

amount of current starvation by changing the biasing current,
the delay through each inverter stage can be varied, which in
return changes the frequency of the oscillation.

The gate terminal of these starving transistors is connected to a

controlled voltage (Vctrl). By adjusting Vctrl, we can regulate
the amount of current that these transistors will allow to pass
through the inverters.

3.3 Advantages over Traditional Ring Oscillator

Power Efficiency: Current-starved oscillators consume less

power compared to traditional oscillators, making them
suitable for low-power application making it ideal for battery-
operated and low-power devices.

Frequency Control: Current-starved oscillators offer better

control over the oscillation frequency, using additional
transistors to limit the current flowing through
Fig.6. Schematic of 3 stage current starved RO
the oscillator stages, the oscillation frequency can be finely
adjusted.

This is because the frequency of oscillation is directly related After simulation, the designed schematic provides a frequency
to the current supplied to the circuit. of 1.001 GHz as observed in Fig.7

PAGE N0: 56
 Journal of Systems Engineering and Electronics (ISSN NO: 1671-1793) Volume 35 ISSUE 2 2025

5. CONCLUSION

A current starved ring is simulated to overcome the challenges

present in the existing VCO in high-frequency applications.
These challenges include leakage current, phase noise, and
limited frequency tuning range. To ensure its robust ness,
extensive simulations are performed under extreme conditions.

The proposed circuit consumes very less power which is 91 %

less than existing circuit due to current starved ring oscillator.
It achieves 80.18 % improvement in oscillation frequency
because of the current starved voltage supply.

This confirms the robustness of the proposed design, making it

a promising solution for high frequency applications. These
improvements are achieved at a supply voltage of 1 V.
Fig.7. Transient Response of 3 stage current starved RO
From the obtained results, it is concluded that the proposed
PARAMETRIC ANALYSIS: design outperforms existing works in various performance
parameters and it is highly suitable for EEPROM applications
Parameters Traditional 3-stage Current including wireless communication and radio frequency.
3-stage Starved oscillator
Ring Oscillator
Technology 90nm 90nm
6. REFERENCES
Frequency 25.02 45.78 [1] R. Das et al., "Multi-objective Optimization for Optimal
(MHz)
Design of CMOS Ring Oscillator," 2023 International
Power (µW) 3.584 1.732 Conference on Recent Advances in Electrical, Electronics,
Ubiquitous Communication, and Computational Intelligence
Supply Voltage 1V 1V (RAEEUCCI), Chennai, India
[2] Ms. Shruti Suman, Ms. Monika Bhardwaj, Prof. B.P. Singh
“An Improved Performance Ring Oscillator Design” in 2012
Second International Conference on Advanced Computing &
TABLE:1 PARAMETRIC ANALYSIS OF DIFFERENT CIRCUITS Communication Technologies DOI 10.1109/ACCT.2012.21
[3] S K Dash et al., “Optimal Design of Current Starved
Oscillator using MOPSO” in 2023 International Conference
on Communication, Circuits, and Systems (IC3S) | 979-8-
3503-2590-4/23/$31.00 ©2023 IEEE | DOI:
10.1109/IC3S57698.2023.10169681M. Sivasakthi, P.
Radhika “Design and analysis of PVT tolerant hybrid current
starved ring VCO, 1434-8411/© 2023 Elsevier GmbH
https://doi.org/10.1016/j.aeue.2023.154987
[4] Kao HL, Chang LC, Fu JS. A wide tuning range and low
phase noise 20 GHz 0.18 μm CMOS voltage-controlled
oscillator. AEU – Int J Electron Commun 2011; 65(9): 763-6
https://doi.org/10.1016/j.aeue.2010.12.003

Fig:8 Layout 3-stage current starved VCO

PAGE N0: 57
 Journal of Systems Engineering and Electronics (ISSN NO: 1671-1793) Volume 35 ISSUE 2 2025

[5] S N Mishra et al., “Design of a Ring Oscillator for

IoT Applications” in 2023 International Conference
on Intelligent Data Communication Technologies
and Internet of Things (IDCIoT) | 978-1-6654-7451-
1/23/$31.00 ©2023 IEEE |
DOI:10.1109/IDCIoT56793.2023.10053537

[6] Rohit Dhiman, Aastha Soni, Rajeevan Chandel

“Design and Performance Analysis of Voltage
Controlled Oscillator” in 2023 3rd International
Conference on Intelligent Technologies (CONIT) |
979-8-3503-3860- 7/23/$31.00 ©2023
IEEE | DOI:
10.1109/CONIT59222.2023.10205

[7] S K Dash, A Bakshi, J R Panda “Design of a

Modified Current Starved Inverter Based Ring
Oscillator for Switched Capacitor Circuit” in 2022
IEEE International Conference on Current
Development in Engineering and Technology
(CCET) | 978-1-6654-5415-5/22/$31.00
©2022 IEEE

[8] Sagi. Sreevibhu et al., “Analyzing Performances of

Ring Oscillator and Current Starved VCO in 90nm
Technology” in March 2023 DOI:
https://dx.doi.org/10.21275/SR2431417240

[9] Suhas Da, Sippee Bharadwajb “New Modified

Current Starved Ring Voltage Controlled Oscillator
and Frequency to Voltage Rectifier for Noise
Suppression from 1– 6 GHz in 180 nm
Technology” in 2017
Procedia Computer Science 115 (2017) 756–763

[10] Sanjay S Tippannvar et al., “Implementation and

Comparison of Different Stages of Current Starved
CMOS Ring Oscillator -A Study” in 2023 DOI:
10.36548/jeea.2023.3.004

[11] Behzad Razavi “The Ring Oscillator” in 2019 IEEE

SOLID-STATE CIRCUITS MAGAZINE

[12] Kavyashree K et al., “Design and Analysis of

Voltage Controlled Oscillators in 45 nm CMOS
Process” in 2020 Second International Conference
on Innovative Mechanisms for Industry Applications
(ICIMIA 2020) | 978-1-7281-4167-1/20/$31.00
©2020 IEEE

PAGE N0: 58