LAB MANUAL

DIGITAL PRINCIPLES AND SYSTEM DESIGN

LABORATORY MANUAL
S.No List of Experiments

1 Construct the stair case two way switch Circuits using Logic Gates.

2 Illustrate as how EX OR gate can be used to Construct a controlled Inverter and digital phase detector.

3 Design a circuit of Coffee / Tea vending Machine and verify using truth table.

4 Design a light detector circuit using NAND gate and verify its working.

5 Derive all basic gates using Universal NAND gate.

For the given switching Circuit derive the swithcing algebra expression, generate the output and verify the same
6 using truth table.
.
Design a circuit using two OR gates and two AND gates to realise the function F= (v+w+x)(v+x+y)(v+z) and verify
7
its output using Truth table.
Design a circuit to realise the function F= (ABC+ A'BC+ AB'C+ ABC'). Use cobination of NOR gate and AND
8
gates.
Use two OR Gates and two AND gates (2 Input) to design a circuit to realise the function
9
F= (ABC+ A'BC+ AB'C+ ABC'). Verify its working using truth table.

10 Design a 1 bit comparator curcuit and implement using Logic Gates.

For the function F= AB + AB'+ A'B' design a circuit with and without minimsation. Analyse the outputs and number
11
of gates required to attain both the outputs.
Minimise the Expression F = AB'C + AB + A'C using boolean laws and verify the reduced expression using truth
12
table.
Illustrate the absorption theorem, Implement using NAND gates and Verify the theorem statement with its truth
13
table.

14 Design a circuit to verify consensus law in SOP form and verify the same using truth table.

15 Construct a circuit to verify distributive law in SOP and POS forms and verify the same using truth tables.

16 Write the statement of first Demorgans law and verify the same using basic logic gates.

17 Design a circuit to prove (A.B)' = A'+B' using NAND gate and Inverters.

18 Design a logic circuit to add two bit binary numbers.

19 Construct a simple logic circuit in calculator to add 3 bit numbers.

20 Construct a logic circuit of Full adder using 2 half adders.

21 Design a logic circuit to subract two bit binary numbers.

22 Construct a simple logic circuit in calculator to subtract 3 bit numbers.

23 Construct a logic circuit of Full subract using half adders.

24 Construct a logic circuit for 2 bit password verification in any login page.

25 Design a logic circuit to compare any 1 bit number.

S.No List of Experiments

26 Design a logic circuit for BCD to 7 segment display.

27 Design a 2 to 4 decoder circuit.

28 Design a logic circuit to print my file in selected output device.

29 Construct and verify 4 X 1 multiplexer truthtable.

30 Design a logic circuit to select a favourite fruit from basket.

31 Construct and verify 1 X 8 demultiplexer truthtable.

32 Design a encoder circuit for toll gate.

33 Construct a 3 bit binary to gray code converter and verify its truth table.

34 Convert 0111 to excess 3 code and implement in logic gates.

35 Design a logic gates to convert BCD to Binary numbers.

36 Design T flipflop using D flipflop.

37 Design a synchronous counter with states 0,1,2,3,0,1......D Flip flop.

38 Implement a 3 bit Counter circuit starts with 000 and ends with 000 using D Flip flop.

39 You are given a 3 bit shift regsiter. Realize an 8 state counter using this.

40 Design 3 bit up counter using 7474 IC.

41 Construct a down counter logic circuit which will be using in traffic signals.

42 Design the customer entry counter in the super market using logic gates.

43 Validate your truthtable of PIPO shit register using logic circuit.

44 Design a logic circuit which 1 bit data will shift 1 position right when 1 clk pulse applied.

45 Validate your truthtable of SISO shit register using logic circuit.

46 Design a hazard free circuit for the given expression SOP (0,1,5,6,7,9,11).

47 For a given Boolean function obtain the hazard free circuit F(A,B,C,D)=(1,3,6,7,13,15).

48 Implement any Boolean expression using PAL.

Illustrate how a PLA can be used for combinational logic design with reference to the given SOP functions
49
F1 (a,b,c) = (0,1,3,4), F2 = (1,2,3,4,5).

50 Implement any combinational circuit using PROM.

 1. CONSTRUCT THE STAIR CASE TWO WAY SWITCH CIRCUITS USING
LOGIC GATES
AIM:
To construct the stair case two way switch circuits using logic gates.
APPARATUS REQUIRED:
S.no Components Specification Quantity
1. AND gate IC-7008 2
2. OR gate IC-7032 1
3. NOT gate IC-7004 2
4. IC Trainer kit - 1
5. Connecting wires As required

THEORY:
AND : It is logical multiplication.It need two inputs and give one output. When both the
inputs are high(1) the output is high(1). If either one input is low(0) the output will be
low(0).The mathematical representation of and gate is A•B.
OR : It is logical addition.It need two inputs and give one output. When both the inputs are
low(0) the output is low(0). If either one input is high(1) the output will be high(1).The
mathematical representation of and gate is A+B.
NOT : It is also called as inverter. It requires 1 input and give one output. When input is high(1)
the output is low(0). Whe input is low(0) the output is high(1). It can be represented as Ā.
AND gate:
SYMBOL TRUTH TABLE

A B A.B
0 0 0
0 1 0
1 0 0
1 1 1

OR gate:
SYMBOL TRUTH TABLE

A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
NOT gate:
SYMBOL TRUTH TABLE

A Ā
0 1
1 0

CIRCUIT DIAGRAM :

PIN DIAGRAM :
AND(IC-7408) OR(IC-7432) NOT(IC-7404)

PROCEDURE :
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logical output and verify the truth table.

RESULT :
The stair case two way switch circuits using logic gates is constructed.
 2. CONSTRUCT A CONTROLLED INVERTER AND DIGITAL PHASE
DETECTOR USING EX-OR

AIM :
To Construct a controlled inverter and digital phase detector using EX-OR.
APPARATUS REQUIRED:
S.no Components Specification Quantity
1. AND gate IC-7008 2
2. OR gate IC-7032 1
3. NOT gate IC-7004 2
4. IC Trainer kit - 1
5. Connecting wires As required

THEORY:
EX-OR gate:
The EX-OR gate has two or more inputs. The output is high(1). When odd numbers of input
is 1.The output from EX-OR gate is written as (A±B).
CIRCUIT DIAGRAM :
EX-OR gate Truth table

PIN DIAGRAM : IC-7486

CONTROLLED INVERTER :
It is also called a programmed inverter a regular inverter always inverts but controlled inverter
will invert according to given condition. In EX-OR gate, when either one input is kept high
(constant) that will invert the output. When either one input is maintain as low (constant) it will
not invert the output. So EX-OR gate is implemented as Controlled inverter.

DIGITAL PHASE DETECTOR :

Digital phase detector is one which will reflect according to given input. Suppose when one
input of EX-OR gate is maintained as low then if we give input as low the output also low vice
versa when input is high the output also high. In such a way the EX-OR gate is implemented
as digital phase detector.

PROCEDURE :
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logical output and verify the truth table.

RESULT:
Using EX-OR gate controlled inverter and digital phase detector are constructed successfully.
 3. DESIGN A CIRCUITE OF COFFEE/TEA VENDING MACHINE AND VERIFY THE
SAME USING TRUTH TABLE

AIM:
To design a circuit of coffee/tea vending machine and verify the same using truth table.
EQUIPMENTS REQUIRED:

S.NO EQUIPMENT RANGE QUANTITY

1 AND gate ic7408 1
2 EX-OR gate ic7486 1
3 IC trainer kit - 1
4 Connecting wires - As required

THEORY

A coffee/tea vending machine circuit uses basic logic gates to control its operation. The goal
of the circuit is to determine whether to dispense coffee or tea based on user input and the
insertion of a coin.
Coffee is dispensed if
The coin is inserted (X1 = 1)
Coffee is selected (X2 = 1)
Tea is not selected (X3 = 0)
Tea is dispensed if
The coin is inserted (X1 = 1)
Tea is selected (X3 = 1)
Coffee is not selected (X2 = 0)
CIRCUIT DIAGRAM:
TRUTH TABLE:

INPUT OUTPUT
Tea(X3) Coin(X1) Coffee(X2) GetTea Getcoffee Wrong input
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 0
0 1 1 0 1 0
1 0 0 0 0 0
1 0 1 0 0 0
1 1 0 1 0 0
1 1 1 0 0 1

PROCEDURE :
•Connections are given as per the circuite diagram.
•Logic inputs are given as per the truth table.
•Observe the logic output and verify the truth table.

RESULT :
Coffee/tea vending machine truth table has been verified.
 4. DESIGN A LIGHT DETECTOR USING NAND GATE AND VERIFY ITS
WORKING

AIM
To design a light detector using NAND gate and verify its working.
EQUIPMENTS REQUIRED

S.NO EQUIPMENT RANGE QUANTITY

1 NAND gate ic7400 1
2 Resistor 33kΩ,330Ω 1
3 LED - 1
4 LDR - 1
5 IC trainer kit - 1
6 Connecting wires - As requied

THEORY
The circuit works by using the properties of the LDR, which changes resistance based on the
amount of light. In low light (darkness), the voltage across the resistor in the voltage divider is
lower, and in bright light, it is higher.
The NAND gate processes this voltage and outputs a signal that controls the LED. The NAND
gate’s role is essentially to switch the state of the LED based on the voltage level at its input.
NAND Gate Function:*
- If both inputs to the NAND gate are high, the output is low (LED off).
- If either input is low, the output is high (LED on).
CIRCUIT DIAGRAM:
TRUTH TABLE

INPUT OUTPUT
0 0 1
0 1 1
1 0 1
1 1 0

PROCEDURE
•Connections are given as per the circuit diagram.
•Logic inputs are given as per the truth table.
•Observe the logic output and verify the truth table.

RESULT
Light detector using NAND has been verified.
 5. DERIVE ALL BASIC GATES USING UNIVRSAL NAND GATE & DRAW
TRUTH TABLE

AIM:
To derive all basic gates using Universal NAND gate and draw the truth table.
APPARATUS REQUIRED:
S.NO COMPONENTS QUANTITY
SPECIFICATION
1. DIGITAL IC TRAINER KIT - 1
2. NAND GATE IC7400 1
3. CONNECTING WIRES - As required

CIRCUIT DIAGRAM:
NOT GATE USING NAND GATE:

TRUTH TABLE:

A Y
0 1
1 0

AND GATE USING NAND GATE:

TRUTH TABLE:
OR GATE USING NAND GATE:

TRUTH TABLE:

EX-OR GATE USING NAND GATE:

TRUTH TABLE :
THEORY:
NAND GATE:
A NAND gate (NOT AND) is a basic digital logic gate that outputs a value of 0 (LOW)
only when both of its inputs are 1 (HIGH). In all other cases, it outputs 1 (HIGH). It is
essentially an AND gate followed by a NOT gate.

AND GATE:
An AND gate is a basic digital logic gate that outputs a value of 1 (HIGH) only when
both of its inputs are 1 (HIGH). If any input is 0 (LOW), the output will also be 0 (LOW).

OR GATE:
An OR gate is a basic digital logic gate that outputs a value of 1 (HIGH) if at least one
of its inputs is 1 (HIGH). The output is 0 (LOW) only when both inputs are 0.

EX-OR GATE:
An exclusive OR gate (XOR gate), on the other hand, is another type of digital logic
gate. It outputs 1 only when the number of 1 inputs is odd, meaning it will output 1 when one
(but not both) of its inputs is 1, and 0 if both inputs are the same (either both 0 and both 1).

NOT GATE:
A NOT gate, also known as an inverter, is a basic logic gate that outputs the opposite (or
inverse) of the input. It performs the logical negation operation. If the input is 1, the NOT gate
outputs 0, and if the input is 0, the output is 1.

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Connect the ground pin to the ground in the ic trainer kit and vcc to the vcc in the ic
trainer kit.
3. By applying the inputs the outputs are observed and operation is verified with the
table of the help of the truth table.
4. The readings are noted and the output is verified.

RESULT:
Thus, all the gates are verified using NAND gate is verified and the truth table is
verified successfully.
 6. IMPLEMENTATION OF SWITCHING CIRCUIT
AIM:
For the given switching Circuit derive the switching algebra expression, generate the
output and verify the same using truth table

F(x,y,z)=(A.B)+(A+B+C)
APPARATUS REQUIRED:
S.NO COMPONENTS SPECIFICATION QUANTITY
1. DIGITAL IC TRAINER KIT - 1
2. AND GATE IC7408 1
3. NOT GATE IC7404 1
4. OR GATE IC7432 3
5. CONNECTING WIRES - AS REQUIRED

CIRCUIT DIAGRAM:

AB+AC=A(B+C)

TRUTH TABLE:

LHS=RHS
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Connect the ground pin to the ground in the IC trainer kit and Vcc to the Vcc in the IC
trainer kit.
3. By applying the inputs the outputs are observed and operation is verified with the
table of the help of the truth table.
4. The readings are noted and check whether LHS is equal to RHS.

RESULT:
The switching algebra expression of the switching circuit is verified using truth table.
7. DESIGN A CIRCUIT USING 2-AND GATE AND 2-OR GATE FOR THE GIVEN
FUNCTION

AIM :
To design a circuit for given function using two AND gate and two OR gates
F =(v+w+x) (v+x+y) (v+z).

APPARATUS REQUIRED:
S.NO COMPONENTS SPECIFICATION QUANTITY
1. AND gate IC-7008 2
2. OR gate IC-7032 2
3. IC Trainer kit - 1
4. Connecting wires As required

THEORY:
AND : It is logical multiplication.It need two inputs and give one output. When both the
inputs are high(1) the output is high(1). If either one input is low(0) the output will be
low(0).The mathematical representation of and gate is A•B.

OR : It is logical addition.It need two inputs and give one output. When both the inputs are
low(0) the output is low(0). If either one input is high(1) the output will be high(1).The
mathematical representation of and gate is A+B.

The given function is

F = (v+w+x) (v+x+y) (v+z)

= (v+vx+vy+vw+wx+wy+xv+x+xy)(v+z)
= (v+wx+wy+x+xy) (v+z)
= (v+x+wy) (v+z)
= v+vz+xb+xz+wyv+wyz
= v+xz+wyz
= v+z (x+wy)
CIRCUIT DIAGRAM:

F = v+z (x+wy)

TRUTH TABLE :
PROCEDURE :
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logical output and verify the truth table.
RESULT:
A circuit for the given function using only 2-AND &2-OR gates is constructed and truth table
is verified.
 8. SIMPLIFICATION OF BOOLEAN EXPRESSION

AIM :
To design a circuit for given function using AND gate and OR gates
F = ABC+A’BC+AB’C+ABC’
APPARATUS REQUIRED:
S.NO COMPONENTS SPECIFICATION QUANTITY
1. AND gate IC-7008 1
2. OR gate IC-7032 1
3. IC Trainer kit - 1
4. Connecting wires As required

THEORY
AND : It is logical multiplication.It need two inputs and give one output. When both the inputs
are high(1) the output is high(1). If either one input is low(0) the output will be low(0).The
mathematical representation of and gate is A•B.

OR : It is logical addition.It need two inputs and give one output. When both the inputs are
low(0) the output is low(0). If either one input is high (1) the output will be high(1).The
mathematical representation of and gate is A+B.

SIMPLIFICATION : TRUTH TABLE

F = ABC +A'BC+AB'C+ABC' A B C AB BC CA F
= BC(A+A')+AB'C+ABC'
0 0 0 0 0 0 0
=BC(1)+AB'C+ABC'
0 0 1 0 0 0 0
=C(B+AB')+ABC'
0 1 0 0 0 0 0
=BC+AC+ABC'
=BC+A(C+BC') 0 1 1 0 1 0 1

=BC+AC+AB 1 0 0 0 0 0 0

1 0 1 0 0 1 1

1 1 0 1 0 0 1

1 1 1 1 1 1 1
CIRCUIT DIAGRAM :

PROCEDURE :
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logical output and verify the truth table.

RESULT :
Thus the given Boolean expression has been simplified and verified.
9. CONSTRUCT A CIRCUIT FOR THE GIVEN FUNCTION USING ONLY (TWO
AND) AND (TWO OR) GATES
AIM:
To design a circuit using two OR gate and two AND gates for the given function
F = (ABC+A’BC +AB’C+ABC’) and verify using truth table.

APPARATUS REQUIRED:
S.NO COMPONENTS SPECIFICATION QUANTITY
1. AND gate IC-7008 2
2. OR gate IC-7032 2
3. IC Trainer kit - 1
4. Connecting wires As required

THEORY:
AND : It is logical multiplication .It need two inputs and give one output. When both the inputs
are high (1) the output is high(1). If either one input is low (0) the output will be low(0).The
mathematical representation of and gate is A•B.

The given function is F= (ABC+A’BC +AB’C+ABC’)

= BC(A+A') +AB'C+ABC' TRUTH TABLE
= BC+AB'C+ABC'
A B C AB BC CA F
= C(B+AB') +ABC'
0 0 0 0 0 0 0
= C(B+A) +ABC'
0 0 1 0 0 0 0
= BC+AC+ABC'
= BC+A(C+BC') 0 1 0 0 0 0 0

= BC+A(C+B) 0 1 1 0 1 0 1
= BC+AC+AB = A(B+C)+BC 1 0 0 0 0 0 0

1 0 1 0 0 1 1

1 1 0 1 0 0 1

1 1 1 1 1 1 1
CIRCUIT DIAGRAM :
F = A(B+C)+BC

OR : It is logical addition.It need two inputs and give one output. When both the inputs are
low(0) the output is low(0). If either one input is high(1) the output will be high(1).The
mathematical representation of and gate is A+B.

PROCEDURE :
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logical output and verify the truth table.

RESULT:
A circuit for the given function using only 2-AND &2-OR gates is constructed and truth table
is verified.
 10. CONSTRUCTION OF 1-BIT COMPARATOR
AIM:
To design a 1 bit comparator circuit and implement the same.
APPARATUS REQUIRED:
S.NO COMPONENTS SPECIFICATION QUANTITY
1. AND gate IC-7008 2
2. EX-OR gate IC-7086 1
3. NOT gate IC-7004 2
4. IC Trainer kit - 1
5. Connecting wires As required

THEORY :
1-Bit Magnitude Comparator :
A comparator used to compare two bits is called a single bit comparator. It consists of two
inputs each for two single bit numbers and three outputs to generate less than, equal to and
greater than between two binary numbers.

CIRCUIT DIAGRAM :

TRUTH TABLE
PIN DIAGRAM :
AND(IC-7408) EX-OR(IC-7486) NOT(IC-7404)

AND :It is logical multiplication .It need two inputs and give one output. When both the inputs
are high(1) the output is high(1). If either one input is low(0) the output will be low(0).The
mathematical representation of and gate is A•B.

EX-OR :The EX-OR gate has two or more inputs .The output high(1) When odd numbers of
inputs is 1.The output from EX-OR gate is written as A ⊕B.

NOT : It is also called as inverter. It requires 1 input and give one output. When input is high(1)
the output is low(0). When input is low(0) the output is high(1). It can be represented as Ā.

PROCEDURE :
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logical output and verify the truth table.

RESULT:
One bit comparator is constructed and the truth table is verified.
11. DESIGNING A CIRCUIT WITH AND WITHOUT MINIMIZATION FOR THE
BOOLEAN FUNCTION

AIM:
To design a circuit with and without minimization for the Boolean function
F=AB+AB’+A’B’.
APPARATUS REQUIRED:
S.NO COMPONENTS SPECIFICATION QUANTITY
1. AND gate IC-7008 4
2. OR gate IC-7032 3
3. NOT gate IC-7004 4
4. IC Trainer kit - 1
5. Connecting wires As required

THEORY:
Circuit Design Without Minimization:
When designing a circuit without minimization:
1. Identify Terms:
Determine the product (AND) and sum (OR) terms of the Boolean function. For F = AB +
AB' + A'B' identify AB, AB', and A'B'.
2. Design the Circuit:
Implement each term using AND gates.
Use NOT gates to create negations as required
Combine the outputs of AND gates using OR gates.
3. GATE COUNT ANALYSIS:
AND Gates: 3
OR Gates: 2
NOT Gates: 2
Total Gates: 7
Complexity:
Higher, as more gates and connections are used.
 13. IMPLEMENT ABSORPTION THEOREM USING NAND GATES AND VERIFY
USING TRUTH TABLE
Aim:
To illustrate and implement the Absorption Theorem using NAND gates, and verify the
theorem using a truth table.
Apparatus Required:
S.no Components Specification Quantity
1. NAND Gate IC 78 2
2. IC trainer kit - 1
3. Connecting - As required
wires

Theory:
Absorption Theorem is a simplification rule in Boolean algebra that states:
A + A·B = A
A·(A + B) = A
In other words, the theorem states that redundant terms can be “absorbed” and do not affect
the final output of a Boolean expression.

For this experiment, we will implement the Absorption Theorem using the first form:
A + A·B = A
The NAND gate is a universal gate, meaning any Boolean function can be implemented using
only NAND gates. To implement the theorem using NAND gates, first derive the logic
expressions for the components of the Boolean equation using NAND gates.
Procedure:
1.Write the Absorption theorem.
2.Connections are given as per the logical diagram using NAND gates.
3.Give the input as per the truth table.
4.Verify the output and check with the truth table.
Circuit Diagram:

Truth Table:

A B A.B A+A.B A

0 0 1 0 0

0 1 1 0 0

1 0 0 1 1

1 1 0 1 1

Result:
The Absorption Theorem (A + A·B = A) has been successfully implemented using NAND
gates and verified using a truth table. The outputs match, confirming the theorem.
14. IMPLEMENT A CIRCUIT TO VERIFY CONSENSUS LAW IN SOP FORM AND
VERIFY USING TRUTH TABLE
Aim:
To design and implement a circuit to verify the Consensus Law in the Sum of Products (SOP)
form and to verify the law using a truth table.

Apparatus Required:
S.no Components Specification Quantity
1. IC trainer kit - 1
2. AND Gate IC 7408 1
3. OR Gate IC 7432 1
4. NOT Gate IC 7404 1
5. Connecting wires - As required

Theory:
Consensus Law in Boolean Algebra states that:
A + A’B = A + B
This law eliminates the redundant term from a Boolean expression. It simplifies Boolean
expressions in logic circuits by reducing the number of terms.
Sum of Products (SOP) form involves the logical OR of several logical AND terms. In the
case of the Consensus Law, we will represent the expression A + A’B and prove that it
simplifies to A + B using a circuit and truth table.
Procedure:
1.Write the Consensus theorem.
2.Connections are given as per the logical diagram.
3.Give the input as per the truth table.
4.Verify the output and check with the truth table.
Circuit Diagram:

Truth Table:

A B A’B A+A’B A+B

0 0 0 0 0
0 1 1 1 1
1 0 0 1 1
1 1 0 1 1

Result:
The Consensus Law (A + A’B = A + B) has been successfully verified using a logic circuit and
truth table. The outputs of both expressions are identical, confirming the law.
15. CONSTRUCT A CIRCUIT TO VERIFY DISTRIBUTIVE LAW IN SOP AND POS
FORMS AND VERIFY THE SAME USING TRUTH TABLE

AIM:
To construct a circuit diagram to verify distributive law in SOP and POS forms and
verify the same using truth table

Components Required:

Components Specification Quantity

AND gate IC 7408 2
OR gate IC7432 2

IC trainer kit - 1
Connecting wires - As required

Circuit diagram:

Formulas
A.(B+C) = A.B + A.C
 A+(B.C) = (A+B).(A+C)

Truth table
A.(B+C)=A.B+A.C
A B C (B+C) A.(B+C) A.B A.C A.B+A.C
0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1

A+(B.C)=(A+B).(A+C)

A B C B.C A+(B.C) A+B A+C (A+B).(A+C)

0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
0 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1
1 0 1 0 1 1 1 1
1 1 0 0 1 1 1 1
1 1 1 1 1 1 1 1
Theory
AND gate

An AND gate is a basic logic gate that implement logical conjunction .It outputs or
true (1) only when all of its inputs are true(1).if any inputs is false (0).
OR gate

An OR gate is a basic logic gate that implements logical disjunction. It outputs true
(1) if any of its input are true (1).The output is false (0) only when all inputs are false(0).

Procedure
*Connections are given as per the logic diagram.
*Logic inputs are given as per the truth table.
*observe the logical output and verify the truth table.

RESULT:
To verified the distributive law in SOP and POS using truth table.
 16 . WRITE THE STATEMENT OF FIRST DE MORGANS LAW AND VERIFY THE
SAME USING BASIC LOGIC GATES

AIM:
To verify the statement of first de morgans law and verify the same using logic gates

APPARATUS REQUIRED:

Components Specification Quantity

AND IC7408 1

NOT IC7404 1

OR IC7432 1

Digital ic trainer - 1

Connecting wires _ As required

Circuit diagram:

𝑻ruth table:

A B (A.B)ʹ A’ B’ A’+B’

0 0 1 1 1 1
0 1 1 1 0 1
1 0 1 0 1 1
1 1 0 0 0 0
Theory:

AND Gate

An AND gate is a fundamental digital logic gate that output a true (1) value only when all of
its inputs are true (1).if any input is false (0) the output will also be false(0).

NOT Gate
A NOT gate also called an inverter is a basic digital logic gate that output the opposite or
complement of its input .it has only one input and output.

Procedure:
 De morgans First law states that the complement of the AND of two variables is equal to
the OR of the complement of the two variables mathematically:
 set up the circuit with logic gates
 create the truth table to verify that the outputs of both the LHS and RHS circuits are the
same for all possible input values A ND B.

Result:
De morgans First law is verified.
 17. DESIGN A CIRCUIT TO PROVE (A.B)’ = A’ + B’ USING NAND GATE AND
INVERTERS

AIM:
To design a circuit to prove (A.B)’ = A’ + B’ using NAND gate and inverters.

COMPONENTS REQUIRED:

S.NO COMPONENTS SPECIFICATION QUANTITY

1. AND Gate IC 7408 1

2. OR Gate IC 7432 1

3. NOT Gate IC 7404 1

4. NAND Gate IC 7400 1

5. IC Trainer Kit - 1

6. Connecting Wires - As required

THEORY:
DeMorgans’s Law states that the complement of the product of all the terms is equal
to the sum of the complement of each term.

AND Gate: It is logical multiplication. It need two inputs and give one output. When
both the inputs are high(1) the output is high(1). If either one input is low(0) the output will be
low(0).The mathematical representation of and gate is A•B.

OR Gate: It is logical addition. It need two inputs and give one output. When both the
inputs are low(0) the output is low(0). If either one input is high(1) the output will be
high(1).The mathematical representation of and gate is A+B.
 NOT Gate: It is also called as inverter. It requires 1 input and give one output. When
input is high(1) the output is low(0). Where input is low(0) the output is high(1). It can be
represented as Ā

CIRCUIT DIAGRAM:

TRUTH TABLE:

A B A.B (A.B)’ A’ B’ A’ + B’
0 0 0 1 1 1 1
0 1 0 1 1 0 1
1 0 0 1 0 1 1
1 1 1 0 0 0 0
PIN DIAGRAM:

AND Gate: OR Gate:

NAND Gate: NOT Gate:

PROCEDURE:

1. Give the connections as per the circuit diagram.

2. Give logical inputs as per the circuit diagram.
3. Observe the logical output and verify the truth table.

RESULT:

Thus, the design of the circuit is constructed and output is verified successfully.
 18. DESIGN A LOGIC CIRCUIT TO ADD TWO BINARY NUMBERS
AIM:
To design a logic circuit to add two binary numbers.

COMPONENTS REQUIRED:

S.NO COMPONENTS SPECIFICATION QUANTITY

1. AND Gate IC 7408 1

2. XOR Gate IC 7486 1

3. IC Trainer Kit - 1

4. Connecting Wires - As required

THEORY:
A half adder is a basic digital circuit used in electronics to perform the addition of two
single-bit binary numbers. It produces two outputs:
1. Sum (S): The result of the binary addition.
2. Carry (C): The carry-out resulting from the addition if the sum exceeds one bit.
Logical Expressions:
Sum (S) = A⊕B (XOR operation)
Carry (C) = A.B (AND operation)

AND Gate: It is logical multiplication. It need two inputs and give one output. When
both the inputs are high(1) the output is high(1). If either one input is low(0) the output will be
low(0).The mathematical representation of and gate is A•B.

XOR Gate: The simplest XOR gate is a two-input digital circuit that outputs a logical
“1” if the two input values differ, i.e., its output is a logical “1” if either of its inputs are 1, but
not at the same time (exclusively).
CIRCUIT DIAGRAM:

TRUTH TABLE:

A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

PIN DIAGRAM:
AND Gate: XOR Gate:
PROCEDURE:

1.Give the connections as per the circuit diagram.

2.Give logical inputs as per the circuit diagram.

3.Observe the logical output and verify the truth table.

RESULT:

Thus, the design of the circuit is to add two binary numbers is constructed and output
is verified successfully.
 19. CONSTRUCT A SIMPLE LOGIC CIRCUIT IN CALCULATOR TO ADD
THREE BIT NUMBERS
AIM:
To construct a simple logic circuit in calculator to add three bit numbers.

COMPONENTS REQUIRED:
S.NO COMPONENTS SPECIFICATION QUANTITY

1. AND Gate IC 7408 1

2. OR Gate IC 7432 1

3. XOR Gate IC 7486 1

4. IC Trainer Kit - 1

5. Connecting Wires - As required

THEORY:
AND Gate: It is logical multiplication. It need two inputs and give one output. When
both the inputs are high(1) the output is high(1). If either one input is low(0) the output will be
low(0).The mathematical representation of and gate is A•B.

OR Gate: It is logical addition. It need two inputs and give one output. When both the
inputs are low(0) the output is low(0). If either one input is high(1) the output will be
high(1).The mathematical representation of and gate is A+B.

XOR Gate: The simplest XOR gate is a two-input digital circuit that outputs a logical
“1” if the two input values differ, i.e., its output is a logical “1” if either of its inputs are 1, but
not at the same time (exclusively).
STEP BY STEP PROCESS :

Let the three bits be A, B, and C. Here's how to perform the addition using basic logic
gates:
Step 1: First Sum (A + B)
Use an XOR gate to find the sum of A and B.

Sum1 = A ⊕ B (XOR of A and B)

Step 2: First Carry (A . B)

Use an AND gate to find the carry of A and B.
Carry1 = A . B (AND of A and B)
Step 3: Second Sum (Sum1 + C)
Now, add the result of Sum1 and the third bit C using another XOR gate.

Sum = Sum1 ⊕ C (XOR of Sum1 and C)

Step 4: Second Carry (Sum1 . C)

Use an AND gate to find the carry between Sum1 and C.
Carry2 = Sum1 . C (AND of Sum1 and C)
Step 5: Final Carry (Carry1 + Carry2)
Combine the two carry outputs using an OR gate.
Carry = Carry1 + Carry2 (OR of Carry1 and Carry2)

Logic Gates Used:

1. Two XOR gates:
One to calculate Sum1 (A ⊕ B).

One to calculate the final Sum (Sum1 ⊕ C).

2. Two AND gates:

One to calculate Carry1 (A + B).
One to calculate Carry2 (Sum1 + C).

3. One OR gate:
To calculate the final Carry (Carry1 + Carry2).
 Final Outputs:
Sum = Sum1 ⊕ C (The final sum of A, B, and C)
Carry = Carry1 + Carry2 (The final carry bit)

CIRCUIT DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTS
A B Cin SUM Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1

1 1 0 0 1
1 1 1 1 1
PIN DIAGRAM:

AND Gate: OR Gate:

OR Gate:

PROCEDURE:

1.Give the connections as per the circuit diagram.

2.Give logical inputs as per the circuit diagram.

3.Observe the logical output and verify the truth table.

RESULT:

Thus, the design of the circuit is to add three bit numbers is constructed and output is
verified successfully.
 20. CONSTRUCT A LOGIC CIRCUIT OF A FULL ADDER USING TWO HALF
ADDERS

AIM:
To construct a logic circuit of a full adder using two half adders.

COMPONENTS REQUIRED:
S.NO COMPONENTS SPECIFICATION QUANTITY

1. AND Gate IC 7408 1

2. OR Gate IC 7432 1

3. XOR Gate IC 7486 1

4. IC Trainer Kit - 1

5. Connecting Wires - As required

THEORY:

A full adder can be built using two half adders and an OR gate. A half adder adds two
single bits and produces two outputs: a sum and a carry. The full adder adds three bits (two
data bits and a carry bit from the previous addition) and also produces a sum and a carry.

Step-by-Step Construction of a Full Adder Using Two Half Adders

Inputs:

A: First input bit

B: Second input bit

Cin: Carry-in bit (from a previous addition)

 Outputs:

Sum: Sum of A, B, and Cin

Cout: Carry-out bit

AND Gate: It is logical multiplication. It need two inputs and give one output. When
both the inputs are high(1) the output is high(1). If either one input is low(0) the output will be
low(0).The mathematical representation of and gate is A•B.

OR Gate: It is logical addition. It need two inputs and give one output. When both the
inputs are low(0) the output is low(0). If either one input is high(1) the output will be
high(1).The mathematical representation of and gate is A+B.

XOR Gate: The simplest XOR gate is a two-input digital circuit that outputs a logical
“1” if the two input values differ, i.e., its output is a logical “1” if either of its inputs are 1, but
not at the same time (exclusively).

CIRCUIT DIAGRAM:
TRUTH TABLE:

INPUTS OUTPUTS
A B Cin SUM Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1

1 1 1 1 1

PIN DIAGRAM:

AND Gate: OR Gate:

OR Gate:
PROCEDURE:

1.Give the connections as per the circuit diagram.

2.Give logical inputs as per the circuit diagram.

3.Observe the logical output and verify the truth table.

RESULT:

Thus, the logic circuit of a full adder using two half adders is constructed and output is
verified successfully.
 21. Designing a Logic Circuit to Subtract Two-Bit Binary Numbers

Aim:

The aim of this project is to design a logic circuit that can subtract two two-bit binary numbers.

Apparatus Required:

1. Logic gates (AND, OR, NOT, XOR)

2. Breadboard
3. Power supply
4. Jumper wires
5. Binary switches (2)
6. LED indicators (2)

Theory:

Binary subtraction can be performed using the same principles as binary addition, with the
exception that the borrow operation is performed instead of the carry operation. The subtraction of
two binary numbers can be represented as:

A (minuend) - B (subtrahend) = Difference

In a two-bit binary system, each bit can have a value of either 0 or 1. The subtraction operation can
be performed using the following rules:

Procedure

 Represent the two-bit binary numbers A and B using binary switches.

 Design a logic circuit that can perform the subtraction operation using the rules mentioned
above.

 Implement the circuit on a breadboard using logic gates and jumper wires.

 Test the circuit using different input combinations and verify the output using LED
indicators.
Truth Table:

A1 A0 B1 B0 Difference Difference0 Borrow Out

0 0 0 0 0 0 0
0 0 0 1 1 1
0 0 1 0 1 0 1
0 0 1 1 1 1 1
0 1 0 0 0 1 0
0 1 0 1 1 0 1
0 1 1 0 1 1 1
0 1 1 1 1 0 1
1 0 0 0 1 0 0
1 0 0 1 0 1 1
1 0 1 0 0 0 1
1 0 1 1 1 1 1
1 1 0 0 1 1 0
1 1 0 1 1 0 1
1 1 1 0 1 1 1
1 1 1 1 0 0 1
Result:

The designed logic circuit can successfully subtract two two-bit binary numbers. The
output of the circuit is displayed using LED indicators, which show the difference and
borrow values. The truth table verifies the correct operation of the circuit for all possible
input combination.
 EX: 22 Construct a Logic Circuit to Subtract Three-Bit Binary Numbers

Aim:

The aim of this project is to design a logic circuit that can

subtract three-bit binary numbers.

Apparatus Required:

Breadboard
IC 7486 (Quad 2-input XOR gate)
IC 7408 (Quad 2-input AND gate)
IC 7432 (Quad 2-input OR gate)
Power supply (5V)
Jumper wires
3-bit binary inputs (A, B) and output (D)
LEDs

Theory:
The subtraction of two binary numbers can be performed using the following steps:

Take the two's complement of the subtrahend (B).

Add the two's complement of B to the minuend (A).
The result is the difference between A and B.
The two's complement of a binary number can be obtained by inverting each bit and
then adding 1 to the result
.
Logic Circuit Design:
The logic circuit to subtract two 3-bit binary numbers can be designed using
the following gates:

o XOR gates to perform the inversion of B and the addition of A and the two's
complement of B.

o AND gates to perform the addition of the carry-in and the sum of A and the two's
complement of B.

o OR gates to perform the calculation of the carry-out.

Procedure

Represent the two-bit binary numbers A and B using binary switches.

Design a logic circuit that can perform the subtraction operation using the rules
mentioned above.

Implement the circuit on a breadboard using logic gates and jumper wires.

Test the circuit using different input combinations and verify the output using LED
indicators.

CIRCUIT DIAGRAM:
Truth Table:
Here is the truth table for the subtraction of two 3-bit binary numbers

A2 A1 A0 B2 B1 B0 D2 D1 D0 Cout
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 1 1 0
0 0 1 0 0 0 1 1 0 0
0 0 1 0 0 1 0 0 1 0
0 1 0 0 0 0 0 1 1 0
0 1 0 0 0 1 1 0 0 0
0 1 1 0 0 0 1 0 1 0
0 1 1 0 0 1 0 1 0 0
1 0 0 0 0 0 1 1 1 0
1 0 0 0 0 1 0 0 0 0
1 0 1 0 0 0 0 1 0 0
1 0 1 0 0 1 1 0 1 0
1 1 0 0 0 0 0 0 1 0
1 1 0 0 0 1 1 1 0 0
1 1 1 0 0 0 1 0 0 0
1 1 1 0 0 1 0 1 1 0

Result:

The output of the logic circuit will be the difference between the two 3-bit binary
numbers A and B. The carry-out (Cout) will be 1 if the result is negative, and 0
otherwise.
 23. Construct a logic circuit of full subtract using half subtractors.

Aim:

To design and implement a full subtractor circuit using half subtractors.

Components Required:

S.No Components Specifications Quantity

1. Logic gates: AND, 7408 (AND gate) – 1.
OR, NOT 7432 (OR gate) – 1.
7404 (NOT gate) – 1.
2. Half subtractor XOR Gate 2
3. Breadboard 1
4. Connecting Wire As Required
5. Power supply 5V DC -
6. Multimeter (DMM) 1

Theory:

Half Subtractor:

A half subtractor has two inputs (A, B) and two outputs (Difference, Borrow):
Difference (D) = A ⊕ B, Borrow (B_out) = ¬A ·B

Full Subtractor:

A full subtractor can be constructed using two half subtractors and an OR gate: First half subtractor
(HS1) processes the minuend and the subtrahend.
Second half subtractor (HS2) processes the output from the first half subtractor and the borrow
input.
 Procedure:

1. Construct the First Half Subtractor (HS1): Connect inputs A and B to HS1
and derive outputs D1 and B1
2. Construct the Second Half Subtractor (HS2): Connect D1 from HS1 and
B_in to HS2, then derive the final difference (D).
3. Combine Outputs: Use an OR gate to combine B1 from HS1 and the product
of B_in and D1 to get B_out.
4. Connect Power Supply: Ensure that all components are powered correctly.
5. Test the Circuit: Use the multimeter to check the outputs against the truth table.

Circuit Diagram:

Truth Table:
Result:

The full subtractor designed using half subtractors operates correctly,

providing accurate difference and borrow outputs according to the truth table.
The circuit effectively demonstrates the principles of binary subtraction using
logical operations.
 24. Construct a logic circuit for 2 Bit password verification in any login page.

Aim:

To design a logic circuit that verifies a 2-bit password input

against a predefined password.

Components Required:

S.No Components Specifications Quantity

1 Logic gates: AND, OR, IC: 7408
NOT IC: 7432
IC: 7404
2 Inputs switches or buttons
3 Outputs LEDs
4 Breadboard
5 Connecting wires As Required
6 Power supply +5V DC -
7 Multimeter (DMM) 1

Theory:

In a 2-bit password verification system, two bits (P1 and P0) are
compared to a predefined 2-bit password (e.g., 11). The system outputs a signal
indicating whether the entered password matches the predefined password.

Password Verification Logic

To verify the password:

The input password must match both bits of the stored password. Use logic gates to

implement this check:

AND gate: To check if both bits match.

NOT gate: To invert the signals where necessary

.
 Procedure:

1. Set Up Inputs and Outputs: Connect switches for P1 and P0 as

input for the user.
2. Connect LEDs for the Match output.
3. Connect the inputs P1 and P0 to an AND gate.
4. Connect the stored bits S1 and S0 to another AND gate.
5. The output of both AND gates should go to an OR gate to generate
the Match output.
6. Connect Power Supply: Ensure the circuit is powered correctly.

7. Test the Circuit: Use different combinations of P1 and P0

and observe the Match output.

Circuit Diagram:
Truth Table:

Result:

The 2-bit password verification circuit accurately determines whether the

input matches the predefined password. When the correct password (11) is
entered, the Match output indicates success. The circuit effectively demonstrates
basic digital logic principles for password verification.
 25. Design a logic circuit for BCD to 7 segment display.

Aim:

To design and implement a logic circuit that converts a Binary-Coded Decimal

(BCD) input to a display output on an 8-segment display.

Components Required:

Components Range Quantity

BCD to 7-Segment 74LS47,74LS47 1
Decoder

7-Segment Display -- 1
Logic gates AND Gate ,OR Gate, 1 each
NOT Gate

Resistors -- 2
Bread board -- 1
Connecting wires --1 1

Theory:

Binary-Coded Decimal (BCD) is a way of encoding decimal numbers where each decimal
digit is represented by its binary equivalent. A 4- bit BCD input represents decimal digits
from 0 to 9. An 8-segment display is similar to a 7-segment display but includes an
additional segment for displaying more complex characters or decimal points. For the
purpose of this design, we will use a 7- segment display, as BCD to 7-segment decoding is
standard. The 8th segment can be used for additional functionalities like a decimal point.
A BCD to 7-segment decoder converts a 4-bit BCD input into the corresponding segments
of a 7-segment display. This decoder has four inputs (representing the BCD value) and
outputs that drive the segments of the display.

Procedure:

 Set Up: Assemble the components on a breadboard.

 Connect BCD Input: Attach the switches or DIP switches to input lines to
represent the BCD value.
 Wire the Decoder: Connect the BCD input lines to the input pins of the
BCD to 7-segment decoder IC.
 Connect the Display: Wire the outputs of the decoder to the
 corresponding segments of the 7-segment display.
 Add Resistors: Place current-limiting resistors between the decoder
outputs and display segments.
 Power Up: Connect the circuit to the power supply and test
different BCD inputs to verify the display output.

Truth Table:

BCD DECIMAL A B C D E F G
INPUT
(4 BITS)
0000 0 1 1 1 1 1 1 0
0001 1 0 1 1 0 0 0 0
0010 2 1 1 0 1 1 0 1
0011 3 1 1 1 1 0 0 1
0100 4 0 0 1 0 0 1 1
0101 5 1 0 1 1 0 1 1
0110 6 1 1 1 1 1 1 1
0111 7 1 1 1 0 0 0 0
1000 8 1 1 1 1 1 1 1
1001 9 1 1 1 1 0 1 1
1010 INVALID - - - - - - -
1111
Result:

Thus the logic circuit that conversion binary-Coded Decimal (BCD) input to a
display output on an 8-segment display is verified.
 26. Design a logic circuit to compare any 1 bit number

Aim:

To design a logic circuit that compares two 1-bit numbers and outputs a
high signal if the numbers are equal and a low signal if they are not.

Components Required:

S.No Components Specifications Quantity

1 IC 7404 NOT Gate 1
2 IC 7402 NOR Gate 1
3 IC 7408 AND Gate 1
4 Connecting wires - As Required
5 IC trainer kit 1

Theory:

1-Bit Magnitude Comparator - The Digital Comparator is another

very useful combinational logic circuit used to compare the value of two binary
digits. A magnitude
digital Comparator is a combinational circuit that compares two digital or
binary numbers in order to find out whether one binary number is equal, less
than or greater than the other binary number. We logically design a circuit for
which we will have two inputs one for A and another for B and have three
output terminals, one for A > B condition, one for A = B condition and one for
A < B condition.

A comparator used to compare two bits is called a single bit comparator. It

consists of two inputs each for two single-bit numbers and three outputs to
generate less than, equal to and greater than between two binary numbers

Procedure:

1. Place the IC on IC Trainer Kit.

2. Connect VCC and ground to respective pins of IC Trainer Kit.

3. Implement the circuit as shown in the circuit diagram.

4. Connect the inputs to the input switches provided in the IC Trainer Kit.

5. Connect the outputs to the switches of O/P LEDs

6. Apply various combinations of inputs according to the truth table and

 observe the condition of LEDs.

7. Note down the corresponding output readings for various combinations of inputs.

8. Power Off Trainer Kit, disconnect all the wire connections and remove
IC's from IC- Base.

Circuit Diagram:

Truth Table:

A B A>B A<B A=B

0 0 0 0 1
0 1 0 1 0
1 0 1 0 0
1 1 0 0 1

Result:

Thus the logic circuit is successfully verified.

 27. DECODER CIRCUIT FOR 2 INPUT AND 4 OUTPUTS

Aim:
To design and implement a 2-to-4 binary decoder circuit using basic logic gates,
and to verify its operation using a truth table.

Components Required:

Components Range Quantity

Logic gates AND gates, NOT 1
gates
Power supply 0-30 V 1
Switches -- 2
LED -- 1
Resistor 220 ohms 1
Bread board -- 1
Connecting wires -- 1

Theory:
A decoder is a combinational logic circuit that decodes binary information
from n input lines to 2^n unique output lines. For a 2-to-4 decoder:
Inputs: 2 (A and B)
Outputs: 4 (O_0, O_1, O_2, O_3)

Procedure:

 Connect the inputs A and B to the NOT gates to obtain overline{A} and overline{B}
 - Connect the outputs of the NOT gates and the inputs directly to the inputs of the
AND gates.

 - Connect the outputs of each AND gate to an LED (with a resistor in

series) to indicate the active output.
Circuit Diagram:

TRUTH TABLE:

INPUT OUTPUT

A B D1 D2 D3 D4
0 0 1 0 0 0

0 1 0 1 0 0
0 1 0 0 1 0

1 1 0 0 0 1

Result:

The experiment successfully demonstrated the functionality of the 2-to-4 decoder. Each
combination of inputs \( A \) and \( B \) resulted in the correct LED lighting up as
predicted by the truth table. The circuit operation was verified to match the expected
outputs based on the given input combinations.
 28. Designing a Logical Circuit to Print on Selected Output Devices

Aim:

To design and implement a logical circuit using a microcontroller that

allows the selection of output devices (e.g., printers) and sends a print
command to the selected device.

Components Required:

S.No Components Specifications Quantity

1. Microcontroller Arduino Uno, Raspberry Pi 1
2. Digital Switches 3.3V to 5V Switch
3. Relays or Electronic SPDT 1
Switches
4. Output Devices
5. Power Supply 5V
6. Breadboard
7. Jumper Wires As Required
8. Connecting Wires As Required
9. LEDs 1.8V to 3.3V (for
red/green/blue LEDs)

Theory:

A microcontroller-based system can control which output device is selected

using digital inputs and relays. The relays act as electronic switches that connect
the print command to the chosen output device. The microcontroller reads input
from switches to determine which device is selected and activates the
corresponding relay to route the print command to the appropriate printer.

Procedure:

1. Connections are given as per the circuit diagram given.

2. Choose a microcontroller (e.g., Arduino) and set up pins for input
(buttons) and output (relays).
3. Use buttons to select which printer will be used, and connect relays to
control each printer.
4. Connect the buttons to the input pins of the microcontroller and the
relays to the output pins.
5. Wire each printer to a relay, allowing the microcontroller to control the
power or print command to each printer.
6. Test the setup by pressing the buttons to ensure the correct relay activates
and the proper printer is selected.
Circuit Diagram:

Truth Table:

A B D1 D2 D3
0 0 0 0 0

0 1 1 0 0
0 1 0 1 0

1 1 0 0 1

Result:

The experiment successfully demonstrated the capability of using a

microcontroller to select and control multiple output devices. The system
correctly routed the print command to the selected printer based on user input,
proving that the designed logical circuit is functional and meets the
requirements.
 29. Construct and verify 4 x 1 Multiplexer

Aim:

To construct a 4-to-1 multiplexer circuit and verify its operation using a truth table.

Components Required:

S.No Components Specifications Quantity

1. 74LS151 IC 4-to-1 Multi-plexer,DIP-16 1
2. Breadboard - 1
3. LED 5mm Red 1
4. Resistors 220 Ohm,1/4 Watt 1
5. Switches SPST 6
6. Power Supply 5V DC Regulated 1
7. Multi-meter Digital Multi-meter 1
8. Connecting Wires - As Required

Theory:

A 4-to-1 multiplexer (MUX) is a digital circuit that routes one of four input
signals to a single output based on two control lines. To build and verify this circuit, use a
74LS151 IC, a breadboard, connecting wires, LEDs, resistors (220Ω), switches, and a 5V
power supply. Start by placing the IC on the breadboard and connecting it to power and
ground. Then, wire the four data inputs and the two select lines, which will determine
which input is routed to the output. Attach an LED with a current-limiting resistor to the
output to visually indicate which input is selected. By adjusting the select lines with
switches and observing the LED, you can verify that the correct input is being routed to
the output. For additional verification, use a multimeter to measure the output voltage
and ensure it corresponds to the selected input.
 Procedure:

1. Connections are given as per the circuit diagram given above.

2. Place the IC on the breadboard. Connect power (5V) and ground. Hook up
data inputs (D0,D1,D2,D3D_0, D_1, D_2, D_3D0,D1,D2,D3) and control
inputs (S0,S1S_0, S_1S0
,S1). Connect the output (YYY) to an LED with a resistor.

3. Test control input 000000: Set S1=0S_1 = 0S1=0 and S0=0S_0 = 0S0=0. Check that the
LED reflects the state of D0D_0D0.
4. Test control input 010101: Set S1=0S_1 = 0S1=0 and S0=1S_0 = 1S0=1. Check that
the LED reflects the state of D1D_1D1.
5. Test control input 101010: Set S1=1S_1 = 1S1=1 and S0=0S_0 = 0S0=0. Check that
the LED reflects the state of D2D_2D2.
6. Test control input 111111: Set S1=1S_1 = 1S1=1 and S0=1S_0 = 1S0=1. Check that
the LED reflects the state of D3D_3D3.
7. Verify results: Ensure the LED correctly shows the data input selected by the
control inputs. If not, double-check the connections.

Circuit Diagram:

Truth table:

Output
S1 S0 I0 I1 I2 I3
YYY
0 0 0 or 1 X X X I0I_0I0
0 1 X 0 or 1 X X I1I_1I1
1 0 X X 0 or 1 X I2I_2I2
1 1 X X X 0 or 1 I3I_3I3
Result:

Hence we construct and verify 4x1 mutliplexer using 74LS151 IC and using truth table.
 30. Design a logic circuit to select a favorite fruit from basket

Aim:

To design a logic circuit to select a favourite fruit from basket and verify its truth table.

Components Required:

S.No Components Specifications Quantity

1. Input Switches Mechanical switches, typically 2
SPST (Single Pole
Single Throw)
2. LEDs 5mm LEDs, any color 4
3. Resistors 220Ω or 330Ω 4
4. Logic Gates Basic logic gates (e.g., AND, 4
OR, NOT) or ICs with
integrated gates
5. Breadboard Standard size 1
6. Connecting Wires Various jumper wires for As
connections Required
7. Power Supply 5V DC or 3.3V DC -

Theory:

To design a logic circuit for selecting a favorite fruit, you will use two switches (S1
and S2) to input a 2-bit binary value that determines which of four LEDs will light up. The
binary combinations correspond to specific fruits: 00 for Apple, 01 for Banana, 10 for
Orange, and 11 for Grape. The circuit uses basic logic gates: NOT gates to invert the inputs
and AND gates to combine these signals appropriately. For each fruit, the circuit
Configuration is as follows: connect S1 and S2 to NOT gates to generate the necessary
Inverted signals, then feed these into AND gates to light up the corresponding LED. Assemble
the components on a breadboard, using resistors to limit current through the LEDs and a 5V
or 3.3V power supply to operate the circuit. This setup allows you to select a fruit by
setting the switches, with the chosen fruit’s LED illuminating to indicate the selection.
Circuit Diagram:

Truth table:

A B C D E Z
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 0
0 1 1 0 0 0
1 0 0 0 0 0
1 0 1 0 1 1
1 1 0 1 0 1
1 1 1 1 1 1

Result:

Therefore the design a logic circuit to select a favorite fruit from the basket and verify its
truth table.
 31. CONSTRUCT AND VERIFY 1X8 DEMULTIPLEXER TRUTH TABLE.

AIM:
To construct and verify 1x8 demultiplexer truth table.

COMPONENTS REQUIRED:

S.NO COMPONENTS QUANTITY

1. IC (74HC138 or 74LS138) 1

2. LEDs (8 units) for output 1

indication
3. Resistors (330Ω – 1kΩ) 1

4. Multi meter 1

5. Oscilloscope 1

6. Breadboard 1

7. Connecting wires As required

THEORY:

A 1x8 Demultiplexer (DEMUX) is a digital device that takes a single input signal and
distributes it to one of the eight possible output lines. The output line that receives the
input signal is determined by a combination of three
select lines. Demultiplexers are commonly used in digital circuits where a single data
source needs to be routed to multiple destinations, such as in
communication systems, data routing, memory addressing, and display drivers.
Demultiplexing is the process of taking a single input signal and selecting one of the
many data-output lines to send it to. Essentially, a demultiplexer acts like a switch that
directs the input to one of the many outputs.
PROCEDURE:
Step 1: Make connection as the per the circuit is given.
Step 2: Connect the input signals and set up the select lines.
Step 3: Attach LEDs to output and apply power.
Step 4: Test the output and verify with the truth table.
Step 5: Tabulate the truth table.

CIRCUIT DIAGRAM:
TRUTH TABLE:

RESULT:

Thus, the 1x8 demultiplexer is constructed and the output is verified with the
truth table.
 32. DESIGN AN ENCODER CIRCUIT FOR TOLL GATE

AIM:

To construct and design a encoder circuit for toll gate.

APPARATUS REQUIRED:

S.NO COMPONENTS QUANTITY

1. Sensor (IR/Inductive) 4

2. OR gate (IC 7432) 2

3. Power supply 1

4. Connecting wires 1

5. Bread board 1

THEORY:

The toll gate encoder circuit is designed to detect vehicles at a toll booth,
encode the detection into a binary signal, and then transmit the encoded
signal to a control system that can automate the toll collection process. The
core concept involves using sensors to detect vehicles and logic gates (OR gates
in this case) to encode the sensor signals into a binary output.

1. Encoder Function:

An encoder is a digital device that converts multiple inputs (from sensors) into a
binary output. In a toll gate system, sensors detect vehicles in different lanes, and
the encoder outputs a binary code representing the highest-priority active sensor.
2. Inputs and Outputs:

 Inputs: Four sensors (S1, S2, S3, S4) detect vehicles in lanes.

 Outputs: Two binary outputs (O1 and O0) encode which lane (sensor) is
active.

3. Priority Encoding:
  The encoder gives priority to sensors, with S4 having the highest priority.

 If multiple sensors are active, the output reflects the highest-

priority active sensor.

4. Boolean Logic:

 The outputs are generated using OR gates based on the

following Boolean expressions:

 O1 = S4 + S3
 O0 = S4 + S2

PROCEDURE:

STEP 1: Place 4 vehicle detection sensors (S1, S2, S3, S4) in different lanes at
the toll gate.
STEP 2: Use two OR gates:

o Connect S4 and S3 to the first OR gate to produce O1.

o Connect S4 and S2 to the second OR gate to produce O0.

STEP 3: Derive the outputs using Boolean expressions:

o O1 = S4 + S3 (OR gate for O1)

o O0 = S4 + S2 (OR gate for O0)

STEP 4: Provide a 5V power supply to the sensors and logic gates.

STEP 5: Trigger each sensor (S1 to S4) and observe the binary output (O1,
O0) to verify correct encoding.
STEP 6: Send the binary output to a microcontroller or toll gate system for
further processing, such as opening the gate or recording vehicle data.
CIRCUIT DIAGRAM:

TRUTH TABLE:

RESULT:

Thus, the designing for toll gate using encoder circuit is don successfully
and the output is verified.
 33. 3-bit Binary to Gray Code Converter

Aim:

To construct a 3-bit binary to Gray code converter and verify its truth table.

Apparatus Required:

S. No Apparatus Quantity

1 Digital Trainer Kit 1

2 XOR Gates (IC 7486) 1(IC)

3 Binary Input Switches 3

4 LEDs (for output display) 3
5 Connecting Wires As required
6 Power Supply (5V DC) 1
7 Breadboard 1

Theory:

A Gray code is a binary system where consecutive values differ by only one bit. This
minimizes errors in digital transitions.

To convert a 3-bit binary number (B2, B1, B0) to Gray code (G2, G1, G0):

 G2 = B2 (The MSB remains the same).

 G1 = B2 ⊕ B1 (XOR of B2 and B1).
 G0 = B1 ⊕ B0 (XOR of B1 and B0).

This ensures that only one bit changes between successive Gray code numbers, making
it useful for error minimization in digital systems.
 Procedure:

 Connections are given as per the circuit diagram.

 The inputs are given as per the truth table.
 Observe the output and verify with the truth table.

Circuit Diagram:

Truth Table:

Binary Input (B2 B1 B0) Gray code Output(G2 G1 G0)

000 000
001 001
010 011
011 010
100 110
101 111
110 101
111 100

Result

The Gray code outputs were successfully verified for all 3-bit binary input
combinations as per the truth table.
 34. Binary to Excess-3 code conversion

Aim:

To convert the binary number 0111 (7 in decimal) to Excess-3 code and implement
the logic using basic logic gates.

Apparatus Required:

S. No Apparatus Quantity

1 Digital Trainer Kit 1

2 AND Gates (IC 7408) 1

3 OR Gates (IC 7432) 1

4 NOT Gates (IC 7404) 1

5 Binary Input Switches 3

6 LEDs (for output display) 4

7 Connecting Wires As required

8 Power Supply (5V DC) 1

9 Breadboard 1

Theory:

Excess-3 is a binary-coded decimal system where each decimal digit is represented by its
corresponding binary value plus 3.
This avoids negative numbers and simplifies certain digital circuits.
Steps to Convert 0111 (7 in Decimal) to Excess-3:
Binary of 7 = 0111
Add 3 (which is 0011 in binary) to the binary number:
0111 (binary for 7)
Add 0011 (binary for 3)
Result = 1010 (Excess-3 code) Thus, the Excess-3 code for 0111 is 1010.
Procedure:

 Using K-Map Boolean expressions are formed.

 Circuit diagram is constructed using K-Map.

 Connections are given as per the circuit diagram.

 Inputs are given as per the requirement.

 The output Excess-3 code is obtained.

Circuit Diagram:
Corresponding minimized Boolean expressions for Excess-3 code bits –
w = A + BC + BDx = B′C + B′D + BC′D′y = CD + C′D′z = D′
W = A + BC + BDx = B′C + B′D + BC′D′y = CD + C′D′z = D′

Truth Table:

Decimal Digit BCD Code Excess-3 Code

A B C D w x y z
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0

Result:

The binary number 0111 (7 in decimal) is successfully converted into Excess-3 code
and implemented using logic gates.
 35. DESIGN A LOGIC GATE TO CONVERT BCD TO BINARY NUMBERS

Aim

To design and implement a logic gate circuit that converts Binary-Coded

Decimal (BCD) inputs into their corresponding binary outputs.

Apparatus Required

1. Logic gates (AND, OR, NOT, NAND, NOR, XOR, XNOR)

2. Breadboard
3. Connecting wires
4. Power supply (5V)
5. Logic gate ICs
6. Digital multimeter or logic analyzer
7. Input switches (for BCD inputs)
8. Output LEDs (for binary
outputs) 9.

Theory

Binary-Coded Decimal (BCD): BCD is a binary-encoded representation of integer values

that uses a 4- bit nibble to represent each digit of a decimal number. In BCD, each decimal
digit (0-9) is represented by its equivalent 4-bit binary value.
Binary Conversion: To convert a BCD input into a binary output, you need to interpret
the 4-bit BCD input as a decimal number and then output its binary equivalent.
Logic Gate Functions: Logic gates perform basic logical functions that are fundamental to
digital circuits. These include:
 AND: Output is high if all inputs are high.
 OR: Output is high if at least one input is high.
 NOT: Output is the inverse of the input.
 NAND: Output is low only if all inputs are high.
 NOR: Output is high only if all inputs are low.
 XOR: Output is high if inputs are different.
 XNOR: Output is high if inputs are the same.
Procedure

1. Design the Circuit:

o Determine the logic expressions required to convert BCD to binary.
o Use Karnaugh maps or Boolean algebra to simplify the logic expressions.
2. Construct the Circuit:
o Build the circuit on a breadboard using the required logic gates
based on the simplified expressions.
o Connect the input switches to represent the BCD input.
o Connect the output LEDs to display the binary result.
3. Testing:
o Apply different BCD inputs and verify that the correct binary output is
displayed.
Measure and record the outputs using a multimeter or logic analyzer.

Circuit Diagram
Truth Table

Result

The logic gate circuit successfully converts BCD inputs (ranging from 0000 to 1001) into
their corresponding binary values. Inputs beyond the BCD range are identified as invalid,
ensuring the circuit operates within the expected BCD range.
 36. Design a T Flip-Flop Using a D Flip-Flop

Aim:

To design and implement a T flip-flop using a D flip-flop and verify its

functionality through simulation and testing.

Apparatus Required

1. D flip-flop IC 7474
2. Trainer Kit
3. Connecting wires
4. Logic gate ICs (AND, OR, NOT)

Theory

T Flip-Flop: A T flip-flop (Toggle flip-flop) is a type of flip-flop where the output

toggles between high and low states on each clock pulse when the T input is high. When
T is low, the output remains unchanged.
D Flip-Flop: A D flip-flop (Data or Delay flip-flop) is a type of flip-flop where the
output follows the input D on the edge of the clock signal.
Conversion: To use a D flip-flop as a T flip-flop, the D input of the D flip-flop must
be connected to the XOR of the T input and the Q output of the flip-flop. This
configuration ensures that the D flip- flop toggles its output on each clock pulse when
T is high.
Logic Gate Functions:
 AND: Output is high if all inputs are high.
 OR: Output is high if at least one input is high.
 NOT: Output is the inverse of the input.
 XOR: Output is high if inputs are different.

Procedure

1. Design the Circuit:

o Use the truth table for a T flip-flop to derive the necessary logic for the
D flip-flop input.
o Create a circuit where the D input is connected to an XOR gate, which
 takes T and Q as inputs.
2. Construct the Circuit:
o Build the circuit on a breadboard.
o Connect the XOR gate to the D input of the D flip-flop.
o Connect input switches for T and Clock signals.
o Use LEDs to indicate the Q and Q' outputs.
3. Testing:
o Apply different T and Clock signals and observe the Q output to ensure
it toggles correctly.
o Record the output states for different combinations of T and Clock inputs.

Circuit Diagram

Result

The T flip-flop implemented using a D flip-flop successfully toggles its output on

each clock pulse when T is high, and maintains its state when T is low. The circuit
demonstrates correct functionality as per the designed logic.
 37. SYNCHRONOUS CIRCUIT

AIM:
To design and implement a synchronous counter that cycles through the sequence 0,1,2,3,0,1

using JK flip-flops.

APPARATUS REQUIRED:

SNO COMPONENTS QUANTITY

1. JK flipflop 1

2. Logic gates As required

Clock pulse generator

3. 1

4. Power supply -

5. Connecting wires As required

6. Bread board 1

7. LED 1

8. Resistors 1

THEORY:
A JK flip-flop is a basic electronic component used to store and manage binary data. It has

two inputs, J and K, and two outputs, Q and its opposite̅ Q. Depending on the combination of J and

K inputs, the flip-flop can set its output to high (1), reset it to low (0), toggle between high and low,

or hold its current state. It changes its output based on the clock signal, which means it updates its

state at specific times. This makes it useful for things like counters and memory in digital circuits.
PROCEDURE:

 Circuits are made as per the circuit diagram.

 Logical inputs are given as per the truth table.
 Observe the output and verify using the trith table.

CIRCUIT DIAGRAM:

TABULAR COLUMN:

Clock Decimal
Q1 Q2 State
pulse
equivalent

1 0 0 00 0

2 1 0 01 1

3 0 1 10 2

4 1 1 11 3

5 0 0 00 0

6 1 0 01 1
 State Transition Table:

Present
Next state J1 K1 J2 K2
state

00 01 1 X 1 X

01 10 X 1 1 X
10 11 1 X X 1

11 00 X 1 X 1

RESULT :

Hence the synchronous circuit is designed and implemented using JK flipflops and output is verified
 39. 8-STATE COUNTER USING 4-BIT SHIFT REGISTER

AIM:

To design and implement an 8-state counter using a 4-bit shift register.

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1 4-bit shift register IC 7474 4

2 Clock pulse generator 10 Hz to 1 kHz 1
3 Trainer Kit 1
4 Connecting wires - As Required

THEORY:

An 8-state counter using a 4-bit shift register functions by leveraging the shift register's
ability to store and shift binary data through its flip-flops on each clock pulse. The shift
register advances its state from 0000 to 0111, representing an 8-state sequence, on each
clock pulse applied to the SRCLK input. The data is shifted from the SER input through
the flip-flops to the Q0-Q3 outputs. This setup allows for counting in binary, cycling
through eight distinct states (0 to 7), and can be visualized using LEDs connected to the
output pins. This basic digital circuit is fundamental for understanding binary counting
and data storage in digital systems.

PROCEDURE:

1. Connections are given as per circuit diagram.

2. Turn on the 5V power supply and check that the circuit is powered
correctly.
3. Observe the LEDs to ensure they cycle through the binary states (0000 to 0111)
with each clock pulse. Test the manual reset functionality to
ensure it resets the counter to 0000.
CIRCUIT DIAGRAM:

4-bit Serial-in to Parallel-out Shift Register

4-bit Serial-in to Serial-out Shift Register

4-bit Parallel-in to Serial-out Shift Register

4-bit Parallel-in to Parallel-out Shift Register

 TRUTH TABLE:

CLOCK PULSE Q3 Q2 Q1 Q0 BINAR

Y
VALUE
0 0 0 0 0 0000
1 0 0 0 1 0001
2 0 0 1 0 0010
3 0 0 1 1 0011
4 0 1 0 0 0100
5 0 1 0 1 0101
6 0 1 1 0 0110
7 0 1 1 1 0111
8 1 0 0 0 1000

RESULT:

Hence designed and implemented an 8-state counter using a 4-bit shift register.
 40. 3 BIT UP-COUNTER USING 7474 IC

AIM:

To design and implement a 3-bit up counter using 7474 IC .

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1 4-bit shift register IC 7474 4

2 Clock pulse generator 10 Hz to 1 kHz 1
3 Trainer Kit 1
4 Connecting wires - As Required

THEORY:

A 3-bit up-counter using 7474 D-type flip-flops counts in binary from 000 to 111.
Each flip-flop represents one bit of the count. The circuit employs three 7474 ICs, with
each flip-flop connected in series such that the output of one flip-flop provides the clock
input for the next. This cascading arrangement ensures that the least significant bit
toggles with every clock pulse, while the other bits toggle in response to changes in
preceding flip-flops. The counter increments with each clock pulse, producing a binary
sequence that demonstrates how digital sequential logic can count in binary.

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. Turn on the power supply and start the clock pulse generator.

3.Use a logic probe or oscilloscope to verify that the outputs Q3, Q2, and Q1 count in binary
from 000 to 111
 CIRCUIT DIAGRAM:

TRUTH TABLE:

Clock Pulses Q3 (MSB) Q2 Q1 (LSB)

0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

RESULT:

Hence designed and implemented a 3-bit up counter using 7474 IC .

 Ex: 41 Construct A Down Counter Traffic Signals
AIM:
To design and construct a down counter logic circuit that simulates traffic signals, where the
traffic lights change at regular intervals based on the countdown.
Apparatus Required:
S.no Apparatus Range Quantity
1 Decade counter IC 74LS190/74LS191 1
2 IC 555 Timer IC 1
3 Logic Gates AND, OR, NOT As required
4 LEDs Red, Yellow, Green 3
5 Resistors Use appropriate values -
6 Capacitors Use appropriate values -
7 Breadboard - 1
8 Jumper wires - As required
9 Power supply (0-12 )V 1

Theory:
A down counter is a sequential digital circuit that counts in reverse order. It decreases its count
value on each clock pulse. In this project, the down counter will be connected to a 555 timer
which generates clock pulses at regular intervals. The counter will drive traffic signal LEDs
(Red, Yellow, and Green), where each light remains on for a specific count, and the sequence
repeats to simulate a traffic signal system.

Components Breakdown:
1. 74LS190/191 Counter IC : A 3-bit synchronous up/down counter that can be set to
count down from a preset value. The counter decrements with every clock pulse from
the 555 Timer.
2. 555 Timer IC : This generates clock pulses at a regular interval to control the count-
down speed.
3. LEDs : Used to display the traffic signal with Red, Yellow, and Green lights, with each
light indicating a different traffic condition.
4. Resistors : Used to limit the current through the LEDs.
5. Logic Gates : If needed, logic gates can control the transitions between different LEDs
based on the counter value.
Procedure:
1. Design the Timer Circuit : - Configure the 555 Timer in astable mode to generate
continuous clock pulses. The time interval can be adjusted by varying the resistor and
capacitor values. - Connect the output pin of the 555 Timer to the clock input (CLK)
of the 74LS190/191 counter .
2. Connect the Counter : - Connect the preset inputs of the 74LS190/191 to initialize a
starting count value (for example, 7 for a 3-bit count). - Set the counter to "count
down" mode by connecting the relevant control pin.
3. Connect the LEDs : - Based on the counter’s output, connect the LEDs in the following
sequence: - Red LED : Turns on when the counter output is between 6 to 4.
4. Yellow LED : Turns on when the counter output is between 3 to 2.
5. Green LED : Turns on when the counter output is between 1 to 0.
6. Logic Implementation : - If necessary, use AND/OR/NOT gates to control which
LED should be on based on the counter's output.
7. For example: - Red LED can be activated when the counter outputs 110, 101, or 100
(binary for 6, 5, and - Yellow LED when the output is 011 or 010.
8. Green LED when the output is 001 or 000.
9. Power the Circuit : - Provide the required power supply (e.g., 5V DC) to the circuit.
- Observe the traffic signal simulation as the counter decrements, and LEDs change
according to the traffic light logic.

CIRCUIT DIAGRAM
TRUTH TABLE:

Result:
The down-counter logic circuit successfully simulates traffic signal operation, where
the LEDs (Red, Yellow, Green) change according to the count down from the counter.
Each LED stays on for a specified duration before transitioning to the next, representing
the traffic light sequence.
Ex. 42: Design the Customer Entry Counter In The Super Market Using Logic Gates
Aim:
To design and construct a customer entry counter for a supermarket using logic gates, where
the system counts the number of customers entering the store.

Apparatus Required:
S.no Apparatus Range Quantity
1 Sensors IR or LDR 1
2 Decade Counter IC 74LS90/74LS93 1
3 Logic Gates AND, OR, NOT 3
4 7-Segment Display - As required
5 Decoder 74LS47 BCD to 7-Segment 1
Decoder
6 Resistors Use appropriate values As required
7 Capacitors Use appropriate values As required
8 Breadboard - As required
9 Jumper wires - As required
10 Power supply (0 to 12)V 1

Theory:
A customer entry counter is a digital system that counts the number of people entering a
supermarket. This can be implemented using sensors and logic gates to create a counting
mechanism. The IR or LDR sensors detect the customer passing through the entrance, and the
count is incremented each time a customer is detected. The counter IC stores the count, and the
result is displayed on a 7-segment display using a BCD to 7-segment decoder .

Components Breakdown:
1. IR or LDR Sensor : Detects the presence of a customer. The sensor generates a pulse
whenever a customer enters, which triggers the counter.
2. 74LS90/74LS93 Decade Counter : Counts in binary and increments the count by one
for each pulse received from the sensor.
3. Logic Gates : Used to control the conditions for counting, ensuring that the count only
increases when a customer enters, and preventing false triggers.
4. 7-Segment Display : Displays the count value for easy reading by the supermarket staff.
5. BCD to 7-Segment Decoder (74LS47) : Converts the binary output of the counter to a
format suitable for driving the 7-segment display.
 Procedure:

1. Design the Sensor Circuit : Place an IR sensor or LDR at the entrance of the supermarket.
When a person crosses the sensor's path, it will generate a low-to-high signal (pulse).
2. Condition the sensor signal using a NOT gate if necessary to ensure that the output logic level
matches the counter input requirements.
3. Counter Setup : Connect the sensor's output to the clock input (CLK) of the 74LS90/74LS93
counter IC. The counter IC will increment its count by 1 each time a rising edge (pulse) is
detected.
4. Logic Gate Implementation : Use AND/OR gates to ensure that only valid pulses (entry
events) are counted. For example, you could place two sensors (one for entry and one for exit)
and only count when the AND gate conditions (entry sensor active, exit sensor inactive) are
met. Alternatively, use a debounce circuit or logic to eliminate noise and prevent false counts.
5. Connect the Display : Connect the output of the 74LS90/93 counter to the BCD to 7-segment
decoder (74LS47) . The decoder will convert the binary count to a format suitable for
displaying on the 7-segment display. Connect the outputs of the decoder to the inputs of the 7-
segment display .
6. Test the System : Provide a 5V DC power supply to the circuit. As customers pass through the
sensor at the entrance, observe the count on the 7-segment display increment. Verify that the
logic gates are preventing false counts (e.g., a customer standing at the entrance without
entering should not trigger the count).
Circuit Diagram:

The diagram should include:

- IR/LDR sensor connections to the counter input .
- Logic gates for filtering and controlling valid entries.
- The counter connections to the BCD to 7-segment decoder and the 7-segment display .
TRUTH TABLE:

Result:
The customer entry counter successfully counts the number of people entering the supermarket.
Each time a customer passes through the sensor, the count displayed on the 7-segment display
increments by one. The use of logic gates ensures that only valid entry events are counted,
avoiding false triggers.
Ex. 43. VALIDATE YOUR TRUTHTABLE OF PIPO SHIFT REGISTER USING LOGIC
GATES

AIM:
To validate the truthtable of PIPO shift register using logic gates.

APPARATUS REQUIRED:

S.No Components Specification Quantity

1 AND Gate IC IC 7408 1
2 OR Gate IC IC 7432 1
3 NOT Gate IC IC 7404 1
4 NAND Gate IC IC 7400 1
5 EX-OR Gate IC IC 7486 1
6 Patch cards - 1
7 IC Trainer Kit - 1
8 Connecting wires - As required

CIRCUIT DIAGRAM:
TRUTHTABLE:

CLK Pulse QA QB QC QD
0 0 0 0 0
1 1 1 1 1

THEORY:
A PIPO shift register is a collection of flip-flops arranged in a series, with each flip-flop capable
of storing one bit of data. The primary c.haracteristic that distinguishes a PIPO shift register is its
ability to load data and output it in parallel. Unlike other shift registers that deal with serial input
and output, the parallel loading and output capabilities of a PIPO shift register make it a powerful
tool in many digital systems.

Test cases:
Case 1:Set D3,D2,D1 and D0 to 0.

Case 2:Set D3=0,D2=0,D1=0,D0=1.

Case 3:Set D3=1,D2=0,D1=0,D0=1.

Case 4:Set D3=1,D2=1,D1=0,D0=1.

Case 5:Set D3,D2,D1 and D0 to 1.

PROCEDURE:
1.Understand the shift registers function and components.
2.Draw and set up the Circuit diagram with D flip-flops and control logic.

3.Create and refer to the truthtable.

4.Apply test cases,measure outputs and compare them with expected results.

5.Optionally,use simulation tools for more complex validate.

RESULT:
Thus, the truthtable of PIPO Shift register using logic gates is experimentally verified successfully.
 Ex.44. DESIGN A LOGIC CIRCUIT WITH 1 BIT DATA WILL SHIFT 1 POSITION
RIGHT WHEN 1 CLK PULSE APPLIED.

AIM:
To design a logic circuit with 1 bit data will shift 1 position right when 1 clk pulse applied.

APPARATUS REQUIRED:

S.No Components Specification Quantity

1 D-Flip Flop
2 AND Gate IC IC 7432 1
3 OR Gate IC IC 7408 1
4 NOT Gate IC IC 7404 1
5 Breadboard - 1
6 IC Trainer Kit - 1
7 Connecting - As required
wires

THEORY:
The objective of this project is to design a logic circuit that shifts a 1-bit data signal one position
to the right with each clock pulse. This operation is fundamental in digital systems, particularly in
data manipulation tasks such as arithmetic operations and bitwise transformations.

The design of a 1-bit right shift logic circuit using D flip-flops and clock pulses provides a
fundamental example of sequential logic in digital systems. This circuit can be expanded for multi-
bit shifting by cascading additional flip-flops, illustrating the scalability of digital design
principles.

CIRCUIT DIAGRAM:
TRUTHTABLE:

CLK D Q(OUTPUT)
0 0 0
0 1 1
1 0 0
1 1 0

PROCEDURE:
STEP 1:Understand the Functionality.

STEP 2:Create the Truth Table.

STEP 3: Connect the Circuit diagram with the components.

STEP 4:Switch on the Circuit and verify the truth table, analysis the output.

RESULT:
Thus, the logic circuit with 1 bit data will shift 1 position right when 1 clk pulse applied and
the output is verified successfully.
 Ex. 45. HAZARD FREE CIRCUIT USING K-MAP
Aim:
To design a hazard-free combinational logic circuit for the given Sum of Products (SOP)
expression using the minterms (0, 1, 5, 6, 7, 9, 11)

Apparatus Required:
S.no Equipments Quantity
1 Bread Board 1
2 Connecting wires As required
3 Power supply -
4 NOT Gate 1
5 OR gate 1
6 AND gate 1
7 LED 3
8 Digital trainer IC kit 1
9 Resistor (220ohm) 3
10 Push button or switch 3

Theory:
 A hazard is an unwanted transient change in the output of a logic circuit caused by
delays in the switching of logic gates. Hazards are classified into:
 Static 1-hazard: The output briefly switches to 0 when it should remain 1.
 Static 0-hazard: The output briefly switches to 1 when it should remain 0.
 Elimination of hazards is crucial for ensuring the circuit operates without glitches,
especially in high-speed digital systems. To achieve this, redundant logic terms are
added to the simplified Boolean expression. These redundant terms ensure smooth
transitions between logic states.
 CIRCUIT DIAGRAM:

Procedure:

● Analyze the given SOP expression:

● Identify the minterms corresponding to the binary values of the input variables
● List the binary combinations of the input variables and the corresponding output for the
given minterms.
● Use a K-map to minimize the logic expression and obtain a simplified SOP expression.
● Use logic gates to design the circuit based on the simplified, hazard-free expression.
● Connect the gates according to the circuit diagram and verify the output using LEDs

Truth Table:
For 3 input variables (A, B, C), the truth table
for the minterms (0, 1, 5, 6, 7, 9, 11) would be:
A B C Output

0 0 0 1

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 1
Result:

A hazard-free circuit has been successfully designed and implemented for the given SOP
expression (0, 1, 5, 6, 7, 9, 11). The circuit operates correctly without glitches.
 Ex. 46. SISO SHIFT REGISTER USING LOGIC CIRCUITS
Aim:

To validate the truth table of a SISO (Serial-In, Serial-Out) shift Register using logic circuits.

Apparatus Required:

S.no Equipments Quantity

1 Bread Board 1
2 Connecting wires As required
3 Power supply -
4 D Flip Flop IC 4
5 Clock Pulse Generator 1
6 SISO SHIFT Generator 1
7 LED 4
8 Push button 1
9 Resistor (220ohm,1k ohm) 4
10 Logic pulse analyzer 3

Theory:
● A SISO (Serial-In, Serial-Out) shift register is a sequential Logic circuit that shifts the
input data serially through the Register from one flip-flop to the next with each clock
Pulse.
● It stores and transfers the data one bit at a time And the output is also in serial form.
CIRCUIT DIAGRAM:

Procedure:

● Connect the clock pulse generator to the clock input of the SISO shift register.
● Connect the data input to the serial input (D) of the first flip-Flop.
● Connect the Q outputs of the flip-flops to LEDs or logic Analyzers to visualize the shifting
data
● Provide power to the circuit (typically 5V for most ICs).
● Feed a serial input to the Data input pin.
● Monitor the outputs (Q0 to Q3) to see how the data shifts

Through the register on each clock pulse

Truth Table:

Clock pulse Input D Q0 Q1 Q2 Q3

1 1 1 0 0 0

2 1 1 1 0 0

3 1 1 1 1 0

4 1 1 1 1 1

Result:
The truth table of the SISO shift register has been successfully validated using the logic
circuit.
 Ex. 47. Obtain the hazard free circuit E(A,B,C,D)=(1,3,6,7,13,15)
AIM:
To design a hazard-free circuit for the given Boolean function E(A,B,C,D) =
∑m(1,3,6,7,13,15)

APPARATUS REQUIRED:

S:NO COMPONENTS SPECIFICATION QUANTITY

1 AND gate IC7408 1
2 OR gate IC7432 1
3 NOT gate IC7404 1
4 RESISTOR 330Ω 1
5 POWER SUPPLY 5V DC 1
6 BREAD BOAD - 1
7 CONNECTING WIRES - As required

THEORY:
Boolean algebra is a branch of mathematics that deals with variables that have two possible
values: true (1) and false (0). It is fundamental in digital logic design, enabling the creation of
logical expressions that represent the behavior of electronic circuits.

In Boolean expressions, a minterm is a product (AND operation) of all variables in the function,
each of which appears either in true form or complemented form.
 TRUTH TABLE:
A B C D E
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

K map:
CD 00 01 11 10
AB
00 0 1 1 0
01 0 0 1 1
11 0 1 1 0
10 0 0 0 0
CIRCUIT DIAGRAM:

PROCEDURE:
 Connections are given as per the circuit diagram
 Turn ON the power supply
 Test all combinations of A,B, C,D using switches.
 Verify the connections with its truth table

RESULT:
Hence the hazard free circuit is design for the given Boolean function
E=(A,B,C,D)=(1,3,6,7,13,15)
 Ex.48. Implement any Boolean expression using PAL

AIM:
To Implementing a Boolean expression using a Programmable Array Logic (PAL)

APPARATUS REQUIRED:

S:NO COMPONENTS SPECIFICATION QUANTITY

1 PAL Device 16V8 1
2 RPS 5V DC 1
3 Programming Cable - 1
4 Connecting wires - As required

5 Bread board - 1
6 Programming software Specific to PAL chip -
7 PC Specified software 1
8 NOT gate IC7404 1

THEORY:
Programmable Array Logic (PAL) devices are used to implement combinational logic
functions. They consist of a programmable AND array followed by a fixed OR array. PALs
offer a flexible and efficient way to design logic circuits without needing extensive wiring or
multiple discrete components.

Inputs: The PAL device accepts multiple inputs (A, B, C, etc.).

Programmable AND Array: This is where you define the logic for each product term. You
can configure which inputs connect to each AND gate.

Fixed OR Array: The outputs of the AND gates feed into a fixed OR gate configuration to
generate the final output(s).
TRUTH TABLE:
A B C A’ AB ÁC F(A,B,C)

0 0 0 1 0 0 0
0 0 1 1 0 1 1
0 1 0 1 0 0 0
0 1 1 1 0 1 1
1 0 0 0 0 0 0
1 0 1 0 0 0 0
1 1 0 0 1 0 1
1 1 1 0 1 0 1

CIRCUIT DIAGRAM:

PROCEDURE:
 Select the PAL Device
 Connect the PAL to the Programming Interface
 Load Programming Software
 Define Inputs and Outputs
 Assemble Components
 Power the Circuit
 Power the Circuit
 Observe Outputs
RESULT:
The PAL successfully implements the Boolean expression, demonstrating the correct logic.
And the outputs are verified with truth table.
 Ex. 49 ILLUSTRATE A PLA COMBINATION LOGIC DESIGN

Aim:

To design and implement a combination logic circuit using a Programmable Logic Array
(PLA) for the given SOP functions:

F1(a,b,c) = Σ(0,1.3.4)
F2(a,b,c) = Σ(1,2,3,4,5)

Apparatus Required:

S,NO COMPONENTS QUANTITY

1 PLA IC(16 V) 1
2 LOGIC TRAINER KIT 1
3 PATCH CORDS/WIRES AS REQ
4 DC POWER SUPPLY(5V) 1
5 DIGITAL MULTIMETER OR 1
PROBE
6 SWITCHES 5
7 LEDS 5
8 DATA SHEET OF PLA IC 1

Theory:

A PLA is a type of programmable logic device used to implement combinational logic circuits.
It contains a programmable AND array to generate product terms and a programmable OR
array to sum these product terms to implement the desired logic functions.
Circuit diagram:

Truth Table:
Procedure:
 F1(a, b, c) includes minterms: 0, 1, 3, 4.
 F2(a, b, c) includes minterms: 1, 2, 3, 4, 5.
 Construct the truth table for all possible combinations of inputs (a, b, c) with
corresponding outputs for F1 and F2 based on the given minterms.
 Identify and program the AND (product terms) and OR gates for F1 and F2 in the
PLA using the SOP expressions.
 Place the PLA on the breadboard, connect inputs (a, b, c), and link the output lines to
LEDs for F1 and F2.
 Adjust the input switches, observe the outputs, and confirm they match the truth table.

Result:
The combination logic circuit has been successfully implemented using a PLA for the given
functions F1 and F2. The outputs match the expected results from the truth table.
 Ex. 50. ILLUSTRATE A COMBINATIONAL CIRCUIT USING PROM

Aim:

To design and implement a combinational logic circuit using PROM and to verify its
functionality through truth table analysis.

Apparatus Required:

S.NO COMPONENTS QUANTITY

1 PROM IC (74S421,82S12) 1
2 BREAD BOARD 1
3 POWERV SUPPLY(5V) 1
4 LOGIC SWITCHES AS REQ
5 LED AS REQ
6 CONNECTING WIRES AS REQ
7 MULTIMETER 1
8 LOGICAL PROBE(OPTIONAL) 1
9 DATA SHEET FOR PROM 1
10 RESISTORS AS REQ

Theory:

A PROM is a type of memory device that allows a custom combinational logic function to be
implemented. It consists of a fixed AND array followed by a programmable OR array, which
can be programmed to create the desired output based on the input combinations.
Circuit diagram:

Truth Table:
Procedure:
 Understand the Logic Function: Choose a combinational logic function (e.g., XOR
gate, binary-to-Gray converter).
 Create the Truth Table: Construct the truth table showing all possible input
combinations and their corresponding outputs.
 Program the PROM: Based on the truth table, program the PROM so that each input
combination produces the correct output.
 Circuit Setup: Connect the PROM to the breadboard. Wire the input switches to the
input pins of the PROM, connect output pins to LEDs, and power the circuit.
 Verify the Circuit: Test various input combinations using the switches and observe the
output on the LEDs. Verify outputs match the truth table.

Result:
The combinational circuit was successfully designed and implemented using PROM. The
observed outputs matched the expected results according to the function table, verifying the
correct operation of the circuit.