INDIRA GANDHI DELHI

TECHNICAL UNIVERSITY FOR

WOMEN

VLSI DESIGN
BEC-306
LAB FILE

Submitted to
Submitted
Prof. Vandana
by Shristi
Niranjan ECE dept,
Singh
IGDTUW
06901022021
B.tech, ECE
INDEX
S No Experiment Date Signature

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.
 EXPERIMENT-1
Aim: To plot output and transfer characteristics of a n-channel MOSFET.
Apparatus: LT-Spice

Theory: The metal–oxide–semiconductor field-effect transistor (MOSFET) is a

transistor used for amplifying or switching electronic signals. In MOSFETs, a voltage on
the oxide insulated gate electrode can induce a conducting channel between the two other
contacts
called source and drain. The channel can be of n-type or p-type, and is accordingly called an
n MOSFET or a p MOSFET. The characteristics of an nMOS transistor can be explained as
follows. As the voltage on the top electrode increases further, electrons are attracted to the
surface.
At a particular voltage level, which we will shortly define as the threshold voltage, the
electron density at the surface exceeds the hole density. At this voltage, the surface
has
inverted from the p-type polarity of the original substrate to an n-type inversion layer,
or inversion region, directly underneath the top plate. This inversion region is an
extremely
shallow layer, existing as a charge sheet directly below the gate. In the MOS capacitor,
the high density of electrons in the inversion layer is supplied by the electron–hole
generation process within the depletion layer. The positive charge on the gate is balanced
by the
combination of negative charge in the inversion layer plus negative ionic acceptor charge
in the depletion layer. The voltage at which the surface inversion layer just forms play an
extremely important role in field-effect transistors and is called the threshold voltage
Vtn. The region of out.
The transfer characteristic relates drain current (ID) response to the input gate-source driving
voltage (VGS). Since the gate terminal is electrically isolated from the remaining terminals
(drain, source, and bulk), the gate current is essentially zero, so that gate current is not part of
device characteristics. The transfer characteristic curve can locate the gate voltage at which
the transistor passes current and leaves the OFF-state. This is the device threshold voltage
(Vtn).

OUTPUT:
NMOS Output Characteristics
NMOS Transfer Characteristics

Result: The output and transfer characteristics of NMOS are observed .

 EXPERIMENT-2

AIM : To plot the output characteristics of CMOS inverter.

APPARATUS: LT Spice

THEORY:

CMOS inverter definition is a device that is used to generate logic functions is known as
CMOS inverter and is the essential component in all integrated circuits. A CMOS inverter is a
FET (field effect transistor), composed of a metal gate that lies on top of oxygen’s insulating
layer on top of a semiconductor. These inverters are used in most electronic devices which
are accountable for generating data in small circuits.

CIRCUIT DIAGRAM:

OUTPUT:
RESULTS:

The output characteristics of CMOS inverter have been obtained.

 EXPERIMENT- 3

AIM : To design and plot the characteristics of 2-input NAND gate using
CMOS technology.

APPARATUS: LT Spice

THEORY:

The above drawn circuit is a 2-input CMOS NAND gate. Now let’s understand how this
circuit will behave like a NAND gate. The circuit output should follow the same pattern as in
the truth table for different input combinations.

Case-1: VA – Low & VB – Low

As VA and VB both are low, both the pMOS will be ON and both the nMOS will be OFF. So
the output Vout will get two paths through two ON pMOS to get connected with Vdd. The
output will be charged to the Vdd level. The output line will not get any path to the GND as
both the nMOS are off. So, there is no path through which the output line can discharge. The
output line will maintain the voltage level at Vdd; so, High.

Case-2: VA – Low & VB – High

VA – Low: pMOS1 – ON; nMOS1 – OFF

VB – High: pMOS2 – OFF; nMOS2 –

ON

pMOS1 and pMOS2 are in parallel. Though pMOS2 is OFF, still the output line will get a
path through pMOS1 to get connected with Vdd. nMOS1 and nMOS2 are in series. As
nMOS1 is OFF, so Vout will not be able to find a path to GND to get discharged. This in turn
results the Vout to be maintained at the level of Vdd; so, High.
Case-3: VA – High & VB – Low

VA – High: pMOS1 – OFF; nMOS1 –

ON VB – Low: pMOS2 – ON; nMOS2 –

OFF

The explanation is similar as case-2. Vout level will be High.

Case-4: VA – High & VB – High

VA – High: pMOS1 – OFF; nMOS1 –

ON VB – High: pMOS2 – OFF; nMOS2 –

ON

In this case, both the pMOS are OFF. So, Vout will not find any path to get connected with
Vdd. As both the nMOS are ON, the series connected nMOS will create a path from Vout to
GND. Since, the path to ground is established, Vout will be discharged; so, Low.

In all the 4 cases we have observed that Vout is following the exact pattern as in the truth
table for the corresponding input combination.

OUTPUT:
RSEULTS:

The output characteristics of NAND gate are obtained using CMOS technology
 EXPERIMENT- 4

AIM : To design and plot the characteristics of 2-input NOR gate using CMOS technology.

APPARATUS: LT Spice

THEORY:

The above drawn circuit is a 2-input CMOS NOR gate. Now let’s understand how this
circuit will behave like a NOR gate.

Case-1: VA – Low & VB – Low

VA – Low: pMOS1 – ON; nMOS1 –

OFF VB – Low: pMOS2 – ON; nMOS2

– OFF

Path establishes from Vdd to Vout through the series connected ON pMOS transistors and
Vout gets charged to Vdd level. No path from Vout to GND. Therefore, no discharging and
hence Vout will be High.

Case-2: VA – Low & VB – High

VA – Low: pMOS1 – ON; nMOS1 – OFF

VB – High: pMOS2 – OFF; nMOS2 –

ON

In this case path establishes from Vout to GND through nMOS2, but no path to Vdd. So,
Vout would get discharged and will be at level Low.

Case-3: VA – High & VB – Low

VA – High: pMOS1 – OFF; nMOS1 –

ON VB – Low: pMOS2 – ON; nMOS2 –

OFF

The explanation is similar as case-2. Vout will be at level Low.

Case-4: VA – High & VB – High

VA – High: pMOS1 – OFF; nMOS1 –

ON VB – High: pMOS2 – OFF; nMOS2

– ON

No path to Vdd. Path establishes from Vout to GND. So, Vout will be at level Low.In all the
4 cases we have observed that Vout is following the expected value as in 2 input NOR
gate truth table.

OUTPUT:
RESULTS:

The output characteristics of NOR gate are obtained using CMOS technolog
 EXPERIMENT- 5
AIM : To design and plot the characteristics of 2-input AND and OR gate using
CMOS technology.

APPARATUS: LT Spice

THEORY:
In CMOS (Complementary Metal-Oxide-Semiconductor) technology, digital logic circuits
are constructed using a combination of NMOS (N-type Metal-Oxide-Semiconductor) and
PMOS (P-type Metal-Oxide-Semiconductor) transistors. This technology is widely used in
integrated circuits due to its low power consumption, high noise immunity, and scalability.

2- Input CMOS AND Gate:

The 2-input CMOS AND gate is constructed using a combination of NMOS and PMOS
transistors arranged in a specific configuration. The gate consists of two series-connected
NMOS transistors and two parallel-connected PMOS transistors.

● When both inputs are high (logic 1), the NMOS transistors conduct, providing a low
resistance path to ground. This effectively pulls the output node to ground, resulting
in a logic 0 output.
● Conversely, if any input is low (logic 0), at least one of the NMOS transistors will
be turned off, preventing the connection to ground. In this case, the PMOS
transistors
conduct, providing a low resistance path to the supply voltage. This causes the output
node to be pulled up to the supply voltage, resulting in a logic 1 output.

Thus, the 2-input CMOS AND gate produces a high output only when both inputs are
high; otherwise, it produces a low output.

2- Input CMOS OR Gate:

Similarly, the 2-input CMOS OR gate is constructed using a combination of PMOS and
NMOS transistors in a specific arrangement. This gate consists of two series-connected PMOS
transistors and two parallel-connected NMOS transistors.

● When any input is high (logic 1), at least one of the PMOS transistors conducts,
providing a low resistance path to the supply voltage. This pulls the output node up
to the supply voltage, resulting in a logic 1 output.
● If both inputs are low (logic 0), both PMOS transistors will be turned off, preventing
the connection to the supply voltage. In this case, the NMOS transistors conduct,
providing a low resistance path to ground. This effectively pulls the output node to
ground, resulting in a logic 0 output.
Thus, the 2-input CMOS OR gate produces a high output if at least one input is high;
otherwise, it produces a low output.

OUTPUT:
AND gate
 OR gate

RSEULTS:

The output characteristics of AND and OR gates are obtained using CMOS technology
 EXPERIMENT- 6
AIM : To design and plot the characteristics of 2-input XOR gate using CMOS technology.

APPARATUS: LT Spice

THEORY:
The XOR gate is a logical function that produces a high output (logic 1) when the inputs are
different and a low output (logic 0) when the inputs are the same. This gate is fundamental
in digital logic design, used in various applications including arithmetic, data comparison,
and error detection. Implementing the XOR gate using CMOS technology provides
advantages
such as low power consumption, high noise immunity, and scalability.

1. CMOS Technology Overview:

CMOS technology utilizes both NMOS (N-type Metal-Oxide-Semiconductor) and PMOS
(P-type Metal-Oxide-Semiconductor) transistors to construct digital logic circuits. In
CMOS, when one transistor is ON, the other is OFF, resulting in very low static power
consumption. NMOS transistors conduct when the input is high, while PMOS transistors
conduct when the input is low.

2. 2-Input CMOS XOR Gate:

The 2-input CMOS XOR gate can be constructed using a combination of NMOS and
PMOS transistors arranged to achieve the desired logic functionality.

The XOR gate can be implemented using a combination of NMOS and PMOS transistors.
One common implementation involves four transistors: two NMOS and two PMOS.
The NMOS transistors are connected in parallel and serve as the "pull-down" network. They
conduct when the input is high (logic 1), providing a low resistance path to ground when
one input is high.
The PMOS transistors are connected in series and serve as the "pull-up" network. They
conduct when the input is low (logic 0), providing a low resistance path to the supply
voltage when one input is low.
When both inputs are the same, either both high or both low, one of the NMOS or PMOS
paths will be conducting, resulting in a low output. When the inputs are different, neither
NMOS nor PMOS paths are conducting, resulting in a high output.
OUTPUT:

RSEULTS:

The output characteristics of XOR gate are obtained using CMOS technology
 EXPERIMENT- 7
AIM : To design and plot the characteristics of 2-input XNOR gate using
CMOS technology.

APPARATUS: LT Spice

THEORY:
CMOS Technology Overview:
CMOS technology employs both NMOS (N-type Metal-Oxide-Semiconductor) and
PMOS (P-type Metal-Oxide-Semiconductor) transistors to create digital logic circuits. In
CMOS, when one transistor is ON, the other is OFF, leading to very low static power
consumption.
NMOS transistors conduct when the input is high, while PMOS transistors conduct when the
input is low.

2. 2-Input CMOS XNOR Gate:

The 2-input CMOS XNOR gate consists of a combination of NMOS and PMOS transistors
arranged to achieve the desired logic functionality.

•The XNOR gate is essentially an XOR gate followed by an inverter. Therefore, we can
implement it by first designing an XOR gate and then connecting its output to an inverter.
•The XOR gate can be implemented using a combination of NMOS and PMOS transistors,
similar to how it's done for the 2-input XOR gate.

After obtaining the XOR gate output, it is fed into an inverter stage. The inverter stage consists
of a PMOS transistor connected in series with an NMOS transistor, forming a CMOS inverter.

OUTPUT:
RSEULTS:

The output characteristics of XNOR gate are obtained using CMOS technology.