Lecture 10:

Sequential Elements (Latches and Flip Flops)

Mark McDermott
Electrical and Computer Engineering
The University of Texas at Austin

10/2/18 VLSI-1 Class Notes

 Sequencing

§ Combinational logic (CL)

– output depends on current inputs
§ Sequential logic
– output depends on current and previous inputs
– Requires separating previous, current, future
– Called state or tokens
– Ex: FSM, pipeline

clk clk clk clk

in out
CL CL CL

Finite State Machine Pipeline

10/2/18 VLSI-1 Class Notes Page 2

 Sequencing (cont)

§ If tokens moved through pipeline at constant speed, no

sequencing elements would be necessary
§ Ex: fiber-optic cable
– Light pulses (tokens) are sent down cable
– Next pulse sent before first reaches end of cable
– No need for hardware to separate pulses
– But dispersion sets min time between pulses
§ This is called wave pipelining in circuits
§ In most circuits, dispersion is high
– Delay fast tokens so they don’t catch slow ones.

10/2/18 VLSI-1 Class Notes Page 3

 Sequencing Overhead

§ Use flip-flops to delay fast

tokens so they move through
exactly one stage each cycle
§ Inevitably adds some delay
to the slow tokens
§ Makes circuit slower than
just the logic delay
– Called sequencing overhead
§ Some people call this clocking
overhead
– But it applies to asynchronous
circuits too
– Inevitable side effect of
maintaining sequence

10/2/18 VLSI-1 Class Notes Page 4

 Basic LATCH Operation

Dout Dout

Din Din

clock clock
Transparent-low Transparent-high

transparent opaque transparent opaque

clock clock

Din Din

Tdq Tdq
Dout Dout

Tsu Thld Tsu Thld

10/2/18 VLSI-1 Class Notes Page 5

 Building a Flip-Flop with Two Latches
Master Slave

Dout

Din
clock

Transparent Low Transparent High

10/2/18 VLSI-1 Class Notes Page 6

 Difference between a Latch and a Flip-Flop
Latch: Level sensitive Flip-flop: Edge triggered
a.k.a. transparent latch, D latch a.k.a. master-slave flip-flop, D flip-
flop, D register, FLOP

clk
Latch clk

Flop
D Q D Q

clk

Q (latch)

Q (flop)

10/2/18 VLSI-1 Class Notes Page 7

 Static Latch Design

• Static latches are essential for DSM applications

§ Tristate feedback f
+ Static X
D Q
– Backdriving risk
– Susceptible to noise on f
f
D input

f
f
§ Buffered input X
D Q
+ Fixes diffusion input
+ Noninverting f
f

10/2/18 VLSI-1 Class Notes Page 8

 Static Latch Design (cont.)

§ Buffered output
+ No back driving

f Q
§ Widely used in standard cells
+ Very robust (most important) X
D
- Rather large
- Rather slow (1.5 – 2 FO4 delays) f
f
- High clock loading

10/2/18 VLSI-1 Class Notes Page 9

 Static Latch Design (cont.)

§ Datapath latch Q
f
+ Smaller, faster
- un-buffered input -> okay for datapaths X
D
f
f

AGEN - LD / STA
Integer Register

Bypass Cache

Arith Flags
ALU 0

ALU 1
File

10/2/18 VLSI-1 Class Notes Page 10

 AMD K5: Datapath

10/2/18 VLSI-1 Class Notes Page 11

 Flip-Flop Designs

§ Flip-flop is built as pair of back-to-back latches

f f
X
D Q

f f

f f Q

X
D Q
f f
f f

f f
10/2/18 VLSI-1 Class Notes Page 12
 Clock Enable

§ Clock Enable: ignore clock when en = 0

– Mux: increases latch D-Q delay
– Clock Gating: increase enable setup time, skew
Symbol Multiplexer Design Clock Gating Design
f en

f f

D 1
Latch

Latch

Latch
D Q Q D Q
0

en en

f en
f

f D 1
Flop

Q
0
Flop

Flop
D Q D Q
en
en

10/2/18 VLSI-1 Class Notes Page 13

 Reset

§ Force output low when reset asserted

§ Synchronous vs. asynchronous
f f
Symbol

Latch

Flop
D Q D Q

reset reset
Synchronous Reset

f Q f f Q

reset reset
Q
D D
f f
f
f f f

f f
f

Q
Q f
Asynchronous Reset

f f
reset
reset
D
D f
f f
f
f f
reset
reset
f
f
f

10/2/18 VLSI-1 Class Notes Page 14

 Set / Reset

§ Set forces output high when enabled

§ Flip-flop with asynchronous set and reset

f
f
reset
set Q
D
f
f
f
f
set
reset
f
f

10/2/18 VLSI-1 Class Notes Page 15

 Sequencing Methods
Tc

clk

Flip-Flops
§ Flip-flops clk clk

Flop

Flop
Combinational Logic

2-Phase Transparent Latches

f1
tnonoverlap tnonoverlap
Tc/2

§ 2-Phase Latches f2

f1 f2 f1

Combinational Combinational
Latch

Latch

Latch
Logic Logic
Half-Cycle 1 Half-Cycle 1
Pulsed Latches

fp tpw

§ Pulsed Latches fp fp
Latch

Latch
Combinational Logic

10/2/18 VLSI-1 Class Notes Page 16

 Timing Diagrams

Contamination and A tpd

Combinational
Propagation Delays A
Logic
Y
Y tcd

tpd Logic Propagation Delay

tcd Logic Contamination Delay

clk clk tsetup
thold
tpcq Latch/Flop Clk-Q Prop Delay

Flop
D Q D
tccq Latch/Flop Clk-Q Cont. Delay
tpcq
tpdq Latch D-Q Prop Delay Q tccq

tcdq Latch D-Q Cont. Delay

tsetup Latch/Flop Setup Time

clk
clk tsetup thold
tccq tpcq
thold Latch/Flop Hold Time
Latch

D Q D tpdq
tcdq
Q

10/2/18 VLSI-1 Class Notes Page 17

 Master-Slave Flip-Flop
Illustration of delays

I2 T2 I3 I5 T4 I6 Q

QM
D I1 T1 I4 T3

CLK

tsetup =
tpcq =
thold ≥
© Digital Integrated Circuits2nd

10/2/18 VLSI-1 Class Notes Page 18

 Max-Delay: Flip-Flops

Tc ≥ tpd+ (tsetup + tpcq)

sequencing overhead
clk clk

Q1 D2
Combinational Logic
F1

F2
Tc

tsetup
clk
tpcq

Q1 tpd

D2

10/2/18 VLSI-1 Class Notes Page 20

 Max Delay: 2-Phase Latches
Tc ≥ tpd1 + tpd2 + tpdq1+ tpdq2
sequencing overhead
f1 f2 f1

D1 Q1 Combinational D2 Q2 Combinational D3 Q3

L1

L2

L3
Logic 1 Logic 2

f1

f2
Tc

D1 tpdq1

Q1 tpd1

D2 tpdq2

Q2 tpd2

D3

10/2/18 VLSI-1 Class Notes Page 21

 Max Delay: Pulsed Latches
tpd + max(tpdq, tpcq + tsetup - tpw ) ≤ Tc

fp sequencing overhead fp

D1 Q1 D2 Q2
Combinational Logic

L1

L2
Tc

D1 tpdq

(a) tpw > tsetup

Q1 tpd

D2

fp

tpcq Tc tpw
Q1 tpd tsetup
(b) tpw < tsetup
D2

10/2/18 VLSI-1 Class Notes Page 22

 Min-Delay: Flip-Flops

clk

Q1
F1 CL
tcd ³ thold - tccq

clk

D2
F2

clk

Q1 tccq tcd

D2 thold

10/2/18 VLSI-1 Class Notes Page 23

 Min-Delay: 2-Phase Latches

f1

tcd 1,tcd 2 ³ thold - tccq - tnonoverlap Q1

CL

L1
f2
Hold time reduced by D2
non-overlap

L2
tnonoverlap
Paradox: hold applies f1

twice each cycle, vs. only f2

tccq

once for flops.

Q1 tcd

But a flop is made of two D2 thold

latches!

10/2/18 VLSI-1 Class Notes Page 24

 Min-Delay: Pulsed Latches
fp

Q1
CL tcd ³ thold - tccq + t pw
L1

fp Hold time increased by

pulse width
D2
L2

fp
tpw
thold

Q1 tccq tcd

D2

10/2/18 VLSI-1 Class Notes Page 25

 Time Borrowing

§ In a flop-based system:
– Data launches on one rising edge
– Must setup before next rising edge
– If it arrives late, system fails
– If it arrives early, time is wasted
– Flops have hard edges

§ In a latch-based system
– Data can pass through latch while transparent
– Long cycle of logic can borrow time into next
– As long as each loop completes in one cycle

10/2/18 VLSI-1 Class Notes Page 26

 Time Borrowing Example

f1
ϕ1 Delayed

f2
f1 f2 f1

Combinational
Latch

Latch

Latch
(a) Combinational Logic
Logic

Borrowing time across Borrowing time across

half-cycle boundary pipeline stage boundary
f1 f2
Latch

(b) Combinational Logic Latch Combinational

Logic

Loops may borrow time internally but must complete within the cycle

10/2/18 VLSI-1 Class Notes Page 27

 How Much Borrowing?
2-Phase Latches
Tc
tborrow £ - ( tsetup + tnonoverlap )
2
f1 f2

D1 Q1 D2 Q2
Combinational Logic 1
L1

L2
f1

f2 tnonoverlap
Tc

tsetup
Tc/2 tborrow
Nominal Half-Cycle 1 Delay

D2

10/2/18 VLSI-1 Class Notes Page 28

 Clock Skew

§ We have assumed zero clock skew

§ Clocks really have uncertainty in arrival time
– Decreases maximum propagation delay
– Increases minimum contamination delay
– Decreases time borrowing

10/2/18 VLSI-1 Class Notes Page 29

 Clock Skew: Flip-Flops
clk clk

Q1 D2
Combinational Logic

F1

F2
Tc

Tc ≥ tpd + (tpcq + tsetup + tskew)

clk
tpcq
tskew
sequencing overhead Q1 tpdq tsetup

D2

tcd ≥ thold - tccq + tskew clk

Q1
CL

F1 clk

D2 F2

tskew

clk
thold

Q1 tccq

D2 tcd

10/2/18 VLSI-1 Class Notes Page 30

 Clock Skew: Latches

2-Phase Latches
tpd ≤ Tc - (2tpdq)
sequencing overhead

tcd1, tcd2 ≥ thold - tccq - tnonoverlap + tskew f1 f2 f1

D1 Q1 Combinational D2 Q2 Combinational D3 Q3
tborrow ≤ Tc/2 - (tsetup + tnonoverlap + tskew)

L1

L2

L3
Logic 1 Logic 2

f1

Pulsed Latches f2

tpd ≤ Tc - max(tpdq, tpcq + tsetup - tpw + tskew )

sequencing overhead

tcd ≥ thold + tpw - tccq + tskew

tborrow ≤ Tpw - (tsetup + tskew)

10/2/18 VLSI-1 Class Notes 31

 Clocking realities

§ If setup times are violated, reduce clock speed

§ Useful clock skew can be your friend
§ Jitter is NEVER your friend
§ Pulse latches do not scale well from generation to generation
– Use them if you want lot’s of debugging experience J
§ Metastability is very real (and deadly)
§ Lastly, if hold times are violated, chip fails at any speed and PVT
– You have a “brick” for a chip
– You may be out of business if you are a startup

10/2/18 VLSI-1 Class Notes Page 32

 Metastability

Courtesy Altera

10/2/18 VLSI-1 Class Notes Page 33

 Metastability - MTBF

§ The C1 and C2 constants depend on the

device process and operating conditions.
Determined empirically.
§ fCLK is the clock frequency of the clock
domain receiving the asynchronous signal
§ fDATA is the toggling frequency of the
asynchronous input data signal. Faster clock
frequencies and faster-toggling data reduce
(or worsen) the MTBF.
§ The tMET parameter is the available
metastability settling time, or the timing
slack available beyond the register’s tCO, for
a potentially metastable signal to resolve to
a known value.
Courtesy Altera

10/2/18 VLSI-1 Class Notes Page 34

 MTBF vs. TMET

!ln( MTBF )
C2 =
!tMET

e(C2 ´tMET )
C1 =
MTBF ´ fCLOCK ´ f DATA

Time of metastability Courtesy Altera

10/2/18 VLSI-1 Class Notes Page 35

 MTBF: Alternate definition

To avoid synchronizer failure wait long enough

before using a synchronizer’s output. Where “long
enough”, is the mean time between synchronizer
failures and is several orders of magnitude longer
than the designer’s expected length of employment!
John Wakerly

10/2/18 VLSI-1 Class Notes Page 36

 Preventing Metastability

§ The tMET for a synchronization chain is the sum of the output

timing slacks for each register in the chain.

Courtesy Altera

10/2/18 VLSI-1 Class Notes Page 37

 Simulating Metastability

Tsu : input setup time

Thold : input hold time
Tcq : clock to out

Tdata to out = Tsu + Tcq

picoseconds

Din to Dout

10%
Tcq
Tsu Thold
minimum Tcq

-250 -200 -150 -100 -50 0 50 100 150 200 250

Data to Clock (picoseconds)

10/2/18 VLSI-1 Class Notes Page 38

 Simulating Metastability (cont.)

Master internal Slave internal

state node state node

Dout

Din
clock

10/2/18 VLSI-1 Class Notes Page 39

 Functional Pass/Failure vs. Tsu and Th
Master internal node clock
clock

fail

fail

pass
Condition FLOP 1st pass

Input setup time Input hold time

10/2/18 VLSI-1 Class Notes Page 40
 High Speed Flip-Flop for Synchronization

10/2/18 VLSI-1 Class Notes Page 41

 High Speed Flip-Flop for Synchronization (cont.)

10/2/18 VLSI-1 Class Notes Page 42

 Safe Flip-Flop

§ Use flip-flop with non-overlapping clocks

– Very slow – non-overlap adds to setup time
– But no hold times
§ In industry, use a better timing analyzer
– Add buffers to slow signals if hold time is at risk

f2 f1 Q

X
D Q
f2 f1
f2 f1

f2 f1

10/2/18 VLSI-1 Class Notes Page 43

 C2MOS FLOPS slave
clk

CLK CLKB

Din Q
CLKB CLK

master
clk

CLKB CLK

CLK CLKB

CLKB CLKD
CLK Clock slope becomes critical
Low power feedback
Poor driving capability

10/2/18 VLSI-1 Class Notes Page 44

 Hybrid Latch Flip-Flop (HLFF)

Dout
N

Din

Dclk_
Clk

(AMD K-6, Partovi, ISSCC 1996)

10/2/18 VLSI-1 Class Notes Page 45
 Hybrid Latch Flip-Flop Timing
!

Clk

Dclk_

Din

Dout

10/2/18 VLSI-1 Class Notes Page 46

 Pulse Latch

Din

Dout

pclk

Clock

10/2/18 VLSI-1 Class Notes Page 47

 Pulse Latch Waveforms
TIMING:
indow Sampling Window ~ NAND + t
lingw
p Tsu ~ 0 to slightly negative
Sam Th > sampling window
Tcq ~ 2 inverters

Clock

Pclk

Din valid

Dout valid

10/2/18 VLSI-1 Class Notes Page 48

 Merged Function inverting FLOP

Dout’
A
B

clock

10/2/18 VLSI-1 Class Notes Page•49

49
 Flip-Flop Summary

§ Flip-Flops:
– Very easy to use, supported by all tools
§ 2-Phase Transparent Latches:
– Lots of skew tolerance and time borrowing
– Supported by most tools. Can cause timing loops.
§ Pulsed Latches:
– Fast, some skew tol. & borrow, hold time risk

10/2/18 VLSI-1 Class Notes Page 50

 Backup

10/2/18 VLSI-1 Class Notes Page 51

 Dynamic Latch Design

§ Pass Transistor Latch

§ Pros
– Tiny
– Low clock load f
§ Cons
– Vt drop D Q
– Non-restoring
– Back driving Used in the 1970s
– Output noise sensitivity
– Dynamic
– Diffusion input
– Requires capacitance on output to store state.

10/2/18 VLSI-1 Class Notes Page 52

 Dynamic Latch Design (cont.)

f
§ Transmission gate
+ No Vt drop D Q
- Requires inverted clock
f

§ Inverting buffer f
+ Restoring X
D Q
+ No back driving
+ Fixes either f
• Output noise sensitivity f
• Or diffusion input D Q
– Inverted output
f

10/2/18 VLSI-1 Class Notes Page 53