67.27. Semiconductor Devices and Integrated Circuit Formation ‘There are literally thousands of different semiconductor device stmctares, They have been developed to achieve specific perfor ances, either as discrete components arin C=. Accordingly there are many different strctures. However, there are basic strctares required for each of the major device and circuit types. 1. Resistors + Most of the resistors in [Cs are formed by the same processes that are used to form devices (ie. a sequence of ‘oxidation, masking and doping operation). Fig. 67.21 (a) shows a resistor made of a P-type region diffused into an V-type epitaxial ayer. Notice the metallic contacts made at dhe two ends ofthe epi- tnzial layer. The section of the resistor, as dictated by the diffusion, is very nearly rectangular in shape, as shown in Fig. 67.21 (6). The value of aresistor in ols) is given by R= pla or pled we yr Fig. 6720, where pis the resistivity of the layer im obm-cm, 4 the length of the resistive region, and a isthe cross-sectional area of the resistive region. The value of ais equals to wd. where w is the width and di the depth of dhe sesstive region. Fig. 6721Resistance in monolithic ciremits are defined by the term called seer resistance. The sheet ‘resistance isthe resistance of a square region having w = /and has uits of ohms per square. Assum- ing a sheet resistance of 100 to 200 obms per square, practical resistors may have values ranging from 100 to several kilohms. Higher resistance values are obtained by using a meander pattern as shown in Fig. 67.21 (©). The major problem with the resistors of high values is that they tend to ‘occupy a large area on the chip. For example, a resistor of 50 k@ uses up an arca of the wafer that may be occupied by hundreds of the transistors. Jon-implantation instead of diffusion can be used to ‘make resistors with precise values of resistance Fig. 6722 2. Capacitors : One type of capacitor in monolithic ciuits is made by using the capacitance formed between the P and N regions of a reverse-biased diode. Such a capacitor is shown in Fig 6722. These capacitors ate formed by using the same diffusion processes that are used to form devices. Bipolar transistors are made of three regions in which either of the two PXV junctions may be ‘used as capacitors whereby the breakdown voltage of the capacitor may vary considerably from one to the other. The disadvantage of the junction capacitors is the depeudence of the capacitance on the ‘voltage applied to the junction. Capacitors that are voltage-independent can be formed from metal insulator N”((.c. heavily- doped) semiconductor layers as used in MOS structures In dense cireuits, an oxide/nitride/oxide dielectric sendwich is used. The combination film has a ower dielectne constant, allowing a capacstor area smaller than a conventional silicon dioxide ca- pacitor aie Capacitors can also be fabricated by creating a Sieg Sticon dioxide trench etched vertically into the wafer surface (refer N\ to Fig. 67.23). The wenches are etched ether {isotropically with wet etching or anisotropically with dey etching techniques. The wench side walls are oxidised and the centte of the tench is filled wath Txt deposited polysilicon. The final structure is “wired” from the surface, with the silicon and polysilicon serving as two electrodes and silicon dioxide as a dielectric material Fig. 6723, ‘The teenched capacitors are useful when pees ‘ervation of Wafer susfice is main criteria. Another altemative to conserve wafer surface area is ‘build stacked capacitors om the wafer surface. This effort has been driven by the nced for szuall high dielectric capacitors for dynamic random access memory (DRAM) circuits. 3. Diodes = In integrated circuits, where all the interconnections and device terminals are ‘made atthe sucface. a diode is formed in the following two ways: (@) In bipolar circuits from a bipolar transistor by placing a slort-circuit between two of the three terminals ofthe transistor (i¢., collector to base or emitter to base). Thus there are cemutter-base diodes and base-collector diodes. (®) InMOS cireuits, most of the diodes are formed with the source-deain doping step. However. in order to make a discrete PY junction diode. we will discuss the various steps in- ‘volved inthe fabrication.‘The starting material isa heavily doped N-type (N") substrate about 150 pan thick. A layer of Netype silicon (1 to 5 yn) s grown on the substrate by epitaxy as shown in Fig. 67.24 @)- Thea layer of silicon dioxide (Si0,) is deposited by oxidation as shown in Fig, 6724 (2). Next, the sucface is coated with positive photoresist as shown in Fig. 67.24 (e). Then a mask is placed on the surface of silicon, aligned and exposed to ultraviolet light (UV) as shown in Fig. 67-24 (2). Next ‘mask is removed. resist is removed and silicon dioxide lnyer under the exposed resist is etched as shown in Fig. 67.24 (e). Them boron is diffused to form P-type region a shown an Fig, 67.24 (). Note ‘that boron diffuses easily in silicon but notin silicon dioxide. Next thin aluminium film s deposited cover the surface as shown in Fig. 67.24 (). Then the metallized area is covered will esist another mask is used to identify areas where metal isto be preseeved. Wafer surface is etched to semove ‘unwanted metal. Resist is then dissolved and we get a strcture as shown in Fi. 67.24 (i). Finally, contact meta s deposited on the back surface and ohmic contacts are made by heat treatment. 4. Bipolar Transisior + Let us consider the fabsication of an NPN bipolar junction wansistor (BIT) ona silicon wafer. While our discussion will be focussed on the BIT. itis understood that the susface ofthe whole wafer is being processed. “The starting material is» hghtly doped P-type wafer Weill considera small area cn this wafer ‘hese we will form a BJT. The base on which the wansistor is made ss known as the substrate. The function ofthe substrate is to act as a mechanical support forthe device. The reason for the use ofa ‘Paype substrate forthe NPN transistor will be clarified when the term isolation is discussed. The ‘substrate ne a resistivity of $10 0 om with a thickness benween SOD and 100 yam for wafers having iameters aver 100 mm. Sio, ry o Fig. 6724‘Fig. 67.25 shows the fabrication steps up to, and including the metal contac to the the regions (Ge, emitter, base and collector), I 0, ae @ HL Z. +80, x oo Paar . e ~ — Piklaion WML MMM © © Ab, Tet) ® N ¥ Poavbure Fig. 67.25First a layer of silicon dioxide (SiO.). about 0.5 jm thick. is deposited on the surface of the substrate by thennal oxidation as shown in Fig 67.25 (a). Using the first mask and the photolitho- graphic process, windows arc opened in the oxide for the buried layer. The N” (j-e.. heavily doped N- type) buned layer is diffused to a depth of about 3 jun as shown in Fig. 67.25 (4). Thus layer serves +o collect the carriers that have crossed the base on their way tothe collector temninal. Te serves a8 a sub-collector and used toeduce the collector olumic-esistance. After the buried layers diffused, ‘he wafer is stripped of all oxide to permit the next deposition. It is to be noted that daring the subsequent high-temperature processes, the buried layer tends to diffuse out. The next operation isthe deposition ofa phosphorus-doped N-type epitavial Iaver on the whole wafer. This layer has a xesistivity of 0.1 to 1 92 can, The thickness ofthis layer is 0.5 to 3 ya for high-speed digital circuit applications and 10-20 um for linear analog circuits. A layer of silicon dioxide (S:0,) about 0.5 to 1 jum thick i arown thermally on the susface of the epitaxial layer as shown in Fig. 67.25 (c). Since the collector of NPN trnasistar is 1V-type, and so are the collectors ofthe adjacent transis: tors, there isan obvious need to isolate the collectors from each other. The second mask i used 10 ich windows for tis polation segious, which are formed by the subsequent difusion of borou ex- tending from the surface down to the substrate as shown Fig. 67.25 (d). An N-type epitaxial layer separates the isolation regions, thus sewing asthe tb in which each tensietor is formed. The diffi- sion of the isolation region is followed by oxidation of the wafer surface. ‘The rire mask is used to open.a window forthe P-type base of the wansisto. P ype diffusion or ion smplantation is driven to form the base to a depth of about 2-3 ym as shown m Fig. 67.25 (e). This is followed by the deposition of an oxide layer The fourth mask is used to open windows in the oxide for the N” emitter and the collector contacts. The phosphorus or arsenic diffusion is driven to a depth of about 2 jm as shown in Fig. 6725 (f). The need for N” collect isto form a good ohic contact. The ohmic contact permts easy current flow in both directions. To form 2 good obinic contact to an NV material, an N” region is needed between the metal on the top and the N region. Following the N" difusion, an oxidation layer is formed over the entae waler surface Tae ffir mask is used to open windows for the formation of metallic contacts to the bipolar transistor terminals. "Them an aluminium film 0.5 and 1 ym thick is deposited, by evaporation or sputtering, onthe top surface ofthe IC wafer. Assuming tha the complete circuits are to be formed con the susface ofthe water, the svt mashas used to define the interconnection pattern the cincuits ‘These interconnections are etched into the metal that has been deposited on the surface. as shown in Fig. 67.25 (g). Jn order to protect the susface of the wafer from moisture and chemical contamination, a silicon nitride (SiN), called a possivarion layer, is deposited om the surface. Contacts to the integrated circuits are made on pads that are located on the periphery of the JC chip. Since the JC chip will be ‘bonded to an IC package, connections are ta be made fom the package leads to the bonding pads on the IC chi. ‘The seventh mask is used to define the bonding holes over the aliminiim pads for external connections. Following the seven masks, the circuits are tested by a computer-controlled system and al faulty chips are identified and marked. The wafer i thea sawed sno chips, which are bonded on IC packages. Gold wires about 25 yun i diamcter ae used to conicct the package leads to the bonding pads on the chip Fig. 67.26 shows an additional detail om the buried layer. It indicates the path taken by the cavrices on their way from the emuttr tothe hase andio the collector. This path is considerably longer ‘than the path in the discrete BJT shown in Fig. 67.26 (a). Because of this the collector series resis- tance, labelled the parasitic resistance, is quite large ands of the oder of hundreds of obmas. To seduce this sistance, we have placed the low resistivity baried layer in Fig. 67.25 (b) ant the path of|the carriers which acts asa subcollector The wse ofthe buried layer reduces the collector resistance byasmuch ase factor of20. The result ofthis is to improve gain-bandwidth product ofthe ransistor by the same factor 5. MOSFET: Letusconsier the fab- sication of Enhancement mode N-channel seal oxide semiconductor field-effect tan sistor. The starting material ea lightly doped Paaype silicon substrate having a resistivity of about 5 Q.cm_ The doping density is de- teunined by the drain-substate breakdowa voltage of 20-30 V._A thin (shout 20 am) layer of silicon dioxide is formed over the subsuate to provide stess relief to the wa- & er. Next a thin about 20 non) layer of silt connittide (SigNy is deposited by the chemi- ‘cal vapour deposition (CVD) process on top a | P cf the silicon dioxide. The silicon dioxide ey permits selective oxidation so that a thick =m = ‘oxide (about 500 nm) can be formed in the field region. ‘These operations result in Fig. i) 6123 (a), ‘The first mask defines the field-effect Fla 67.26 ‘wansistor areas, so tht the silicon dioxide and the silicon tide are chemically etched out except hese the tansistor i formed. ‘The next step is to diffuse (or ion-implast) boron inthe feld-regions to form P* (:2, heavily doped P type) islands in the substrate. The function of P” islands isto help increase the threshold voltage, V, and prevent the formation of “parasivie™ mansistors (or elecsical exoss talk) between adjacent devices on the wafer. This is followed by the formation of afield oxide Inver (abort 00 sn thick) over the P” implanted region as shown in Fig. 67.27 (6). The field oxide layer also helps 10 increase “The reimining silicon nitride and silicon dioxide are etched away and an lira hin (about 5 to 10 ‘am layer of SiO, is grown over the teansistor area (not above the field oxide). This forms the gnte- oxide ofthe transistor. Refer to Fig. 67.27 (c). Next.a layer of heavily doped (rypically N”) polysilicon is deposited over the entie wafer susface. This is shown in Fig. 6727 (). “The second mask defines the gate region, whcrevpon the polysilicon is etched away except over the gate as shown in Fig. 6727 (@). The heavily doped polysilicon region above the gate behaves lectically ikea meal electrode ‘By son-umplantation and using the polysilicon gate and the fcld oxide, asthe mask, the source and drain N” regions are formed as shovinin Fig. 67 27 (e). The N” layers literally diffasea sufficient distance to ensure proper alignment so thst the channel Length is well defined. The dopants donot penetrate the field oxide. A tia aver of silicon dioxide is then grown, by the CVD process over the wafer ‘The third mask ie ed to open windows forthe metal contacts to the transistor regions as shown in Fig. 6727 (). The thin layer of silicon dioxide is etched away and aluasinium is deposited over the surface of the wafer by evaporation or sputtering. The fourdt mask defines the interconnection pattem that is etched inthe aloniniuns, as show in Fig. 6727 (g). This followed by the deposition of a protective passivation layer of phosphosilicate glass (called P-elas) over the entire surface of| the wae.Fig. 67.27 Just as with the BIT, the fifth mask is used to open windows, so that bonding wires can be ‘connected to the pads on the 7C chip 67.28. Comparison of ICs based on MOS and Bipolar Transistor Technology 1, The JC based on MOS are less costy to fabricate as compared to those using bipolaetransis- tor The rensom for this is that MOS devices are self-isolating Bipolar tenasistors require tubs to isolate devices from each other on one integrated circuit. Isolation in MOS devices is provided by heavy doping and a thick oxide in the regions between adjacent devices. 2. MOS circuits consume less DC power as compared to bipolar transistor circuits. 3. The MOS transistorhas lower value of ransconductance (g,) 88 compared tothe bipolar transis- tor. This fearare makes the bipolar ransistor ICs superior to MOS cireuits for analog circuit applications. 4. For the same channel length and the base width, the limiting cut-off frequency of the MOS transistor is hetter than » bipolar transistor. Therefore the MOS transistor has a higher bandwidth than the bipolar transistor 5, The packing density of MOS JC is atleast 10 times more than that for bipolar ICs. Also, a MOS sessstor occupies less than 1% ofthe area of conventional diffused resisior. This high packing density makes MOS Cs especially suited for LSI, VLSI and ULSI circuits.‘The main disadvantage of MOS ICs is their slower speed as compared to bipolar /Cs. Hence they do not compete wit bipolar [Cs in ultrahigh speed applications. However, due to their () low cost, (i) Jow power consumption and (ii) high packing density. [MOS Cs are widely produced by semiconductor manufacturing industry. The MOS ICé ate avail- able as calculator chips. memory clups, microprocessors (uP). sangle-clup computers etc. 67.29. Popular Applications of ICs “There are plenty of electronic products i the market, which wsed integrated ccs extem- sively: One ofthe widely accepted applications is the digital wath, which cen deplay hours, mn- utes, seconds day and month. Another popular application is electronic calculator which can per form various functions ike addition, subtraction, multiplication and division. There are also 42- vanced scientific calculators that are programmable and can display the graphs. “Modem electronic products ach as pocket PC personal digital assistant (PDA), MPS players, digital cameras, digital camcorders, mobile phones, digital dictionaries and digital translators, CD (compact dik) players, DVD (ctl versatile disk) players et. also make nse of 1 extnsively ‘With PocketPC. you can ead and sende-mail edt Word, Excel and Ourlok fies, stent dicta inmsi, rend electron books (eBooks), rack your finances, and browse the web. The digital camera shown in Fig. 67 28 can tke pictures and store onthe floppy dskers or memory sick A personal digital assistant (PDA) as shown in Fig. 67.29 is a handheld computer which allows the user to organise calender contacts or tasks These litle electronic wonders might po office secretary oxt of job Electronic games have evolve from microelectronics and computer knowhow. Video games that have 1 be hooked upto home TV have become very popular. Handheld PCs and motnle phones also come with games that sequie no TV hook-up Fig. 67.28 Fig. 67.29 (courtesy Sony Corporation, Japan) {courtesy = 300m, USA)