Lecture 3.1.
2 (Concept of pipelining, Pipeline Hazards) CO4
PIPELINING
To grasp the concept of pipelining, let us look at the root level of how the program is
executed. Instruction is the smallest execution packet of a program. Each instruction contains
one or more operations. Simple scalar processors execute one or more instruction per clock
cycle, with each instruction containing only one operation. Instructions are executed in a
sequence of phases to produce the expected results. This sequence is given below:
● IF: Fetches the instruction into the instruction register.
● ID: Instruction Decode, decodes the instruction for the opcode.
● AG: Address Generator, generates the address.
● DF: Data Fetch, fetches the operands into the data register.
● EX: Execution executes the specified operation.
● WB: Write back, writes back the result to the register.
Not all instructions require all the above steps, but most do. These steps use different
hardware functions. In pipelining, these different phases are performed concurrently. In
pipelining, these phases are considered independent between different operations and can be
overlapped. Thus, multiple operations can be performed simultaneously, with each operation
having its own independent phase.
Instruction Pipelining
Let us look at the way instructions are processed in pipelining. This can be easily understood
by the diagram below:
Assume that the instructions are independent. In a simple pipelining processor, at any given
time, there is only one operation in each phase. The initial phase is the IF phase. As a result,
one operation is fetched on the first clock cycle. When the next clock pulse arrives, the first
operation goes into the ID phase, leaving the IF phase empty. Now, this empty phase is
allocated to the next operation. So, during the second clock pulse, the first operation is in the
ID phase, and the second operation is in the IF phase.
For the third cycle, the first operation will be in the AG phase, the second operation will be in
the ID phase, and the third operation will be in the IF phase. In this way, instructions are
executed concurrently, and after six cycles, the processor will output a completely executed
instruction per clock cycle.
Has this instruction executed sequentially, initially the first instruction has to go through all
the phases then the next instruction is fetched? So, for execution of each instruction, the
processor would require six clock cycles. But in a pipelined processor, as the execution of
instructions takes place concurrently, only the initial instruction requires six cycles, and all
the remaining instructions are executed as one per cycle, thereby reducing the time of
execution and increasing the speed of the processor.
Pipelining Architecture
Parallelism can be achieved with hardware, compilers, and software techniques. To exploit
the concept of pipelining in computer architecture, many processor units are interconnected
and are functioned concurrently. In the pipelined processor architecture, there are separate
processing units provided for integers and floating-point instructions. Whereas in sequential
architecture, a single functional unit is provided.
Pipelined Processor Unit [Elprocus.com]
In static pipelining, the processor should pass the instruction through all phases of the
pipeline, regardless of the requirement of the instruction. In a dynamic pipeline processor, an
instruction can bypass the phases depending on its requirement but has to move in sequential
order. In a complex dynamic pipeline processor, the instruction can bypass the phases as well
as choose the phases out of order.
Classification of pipeline processor
Pipeline processors are classified as:
1. Arithmetic pipeline
2. Instruction pipeline
3. Processor pipeline
Arithmetic pipeline
An arithmetic pipeline generally breaks an arithmetic operation into multiple arithmetic steps.
So, in an arithmetic pipeline, an arithmetic operation like multiplication, addition, etc. can be
divided into a series of steps that can be executed one by one in stages in an Arithmetic Logic
Unit (ALU).
Example of Arithmetic pipeline
Listed below are examples of arithmetic pipeline processors:
● 8 stage pipeline used in TI-ASC
● 4 stage pipeline used in Star-100
Instruction pipeline
In an instruction pipeline processor, the execution of a stream of instructions can be pipelined
by overlapping the execution of the current instruction with the fetch, decode, and operand
fetch of subsequent instructions.
Example of an Instruction Pipeline
All high-performance computers nowadays are equipped with an instruction-pipeline
processor.
Processor pipeline
In a processor pipeline, processing of the same data stream is done by a cascade of
processors.
In this, each cascade of processors is assigned and processes a specific task.
There is no practical example found for processor pipelines.
PIPELINE HAZARDS IN COMPUTER ARCHITECTURE
Though using pipeline processors helps improve the efficiency of operations, there are times
when this architecture faces challenges. Those challenges are referred to as pipeline hazards.
Pipeline hazards are encountered in computer architecture in some specific situations that
prevent the next instruction in the instruction stream from being fetched during its designated
clock cycle. The instruction that is prevented from being fetched is said to be stalled.
When an instruction is prevented from being fetched, all the instructions that are to be fetched
later in the pipeline than the stalled one are also stalled. Instructions that have already been
executed before the stall occurred can continue. During the stall, however, new instructions
are not fetched. Depending on the situation that causes a stall state, there are different types
of pipeline hazards.
In most computer programs, the result of one instruction is used as an operand for another
instruction. When such instructions are executed in pipelining, break down occurs as the
result of the first instruction is not available when instruction two starts collecting operands.
So, instruction two must stall until instruction one is executed and the result is generated.
This type of hazard is called the read-after-write pipelining hazard.
Read After Write Pipelining Hazard
Execution of branch instructions also causes a pipelining hazard. Branch instructions in
pipelines have an effect on the fetch stages of the next instructions.
Pipelined Branch Behaviour
Pipeline hazards are classified as follows:
Structural hazards
Data hazards
Control hazards
Dependencies can be addressed in a variety of ways. The easiest is to introduce a bubble into
the pipeline, which stalls it and limits throughput. The bubble forces the next instruction to
wait until the previous one is completed.
Structural Hazards:
Hardware resource conflicts among the instructions in the pipeline cause structural hazards.
Memory, a GPR Register, or an ALU might all be used as resources here. When more than
one instruction in the pipe requires access to the very same resource in the same clock cycle,
a resource conflict is said to arise. In an overlapping pipelined execution, this is a
circumstance where the hardware cannot handle all potential combinations.
Data Hazards:
Data hazards in pipelining emerge when the execution of one instruction is dependent on the
results of another instruction that is still being processed in the pipeline. The order of the
READ or WRITE operations on the register is used to classify data threats into three groups.
Control Hazards:
Branch hazards are caused by branch instructions and are known as control hazards in
computer architecture. The flow of program/instruction execution is controlled by branch
instructions. Remember that conditional statements are used in higher-level languages for
iterative loops and condition testing (correlate with while, for, and if case statements). These
are converted into one of the BRANCH instruction variations. As a result, when the decision
to execute one instruction is reliant on the result of another instruction, such as a conditional
branch, which examines the condition’s consequent value, a conditional hazard develops.
PIPELINE CONFLICTS
There are some factors that cause the pipeline to deviate its normal performance. Some of
these factors are given below:
1. Timing Variations: All stages cannot take the same amount of time. This problem
generally occurs in instruction processing, where different instructions have different
operand requirements and thus different processing time.
2. Data Hazards: When several instructions are in partial execution and they reference
the same data, a problem arises. We must ensure that the next instruction does not
attempt to access data before the current instruction, because this will lead to incorrect
results.
3. Branching: In order to fetch and execute the next instruction, we must know what
that instruction is. If the present instruction is a conditional branch, and its result will
lead us to the next instruction, then the next instruction may not be known until the
current one is processed.
4. Interrupts: Interrupts set unwanted instructions into the instruction stream. Interrupts
affect the execution of instructions.
5. Data Dependency: It arises when an instruction depends on the result of a previous
instruction, but this result is not yet available.
Advantages of Pipelining
Instruction throughput increases.
An increase in the number of pipeline stages increases the number of instructions
executed simultaneously.
Faster ALU can be designed when pipelining is used.
Pipelined CPUs work at higher clock frequencies than the RAM.
Pipelining increases the overall performance of the CPU.
Disadvantages of Pipelining
The design of the pipelined processor is complex.
In pipelined processors, instruction latency increases.
The throughput of a pipelined processor is difficult to predict.
The longer the pipeline, the worse the problem of hazard for branch instructions.
References
Reference Books:
● J.P. Hayes, “Computer Architecture and Organization”, Third Edition.
● Mano, M., “Computer System Architecture”, Third Edition, Prentice Hall.
● Stallings, W., “Computer Organization and Architecture”, Eighth Edition, Pearson
Education.
Text Books:
● Carpinelli J.D,” Computer systems organization &Architecture”, Fourth Edition,
Addison Wesley.
● Patterson and Hennessy, “Computer Architecture”, Fifth Edition Morgaon Kauffman.
Other References:
● https://www.studytonight.com/computer-architecture/pipelining
● https://www.tutorialspoint.com/what-is-pipelining
● https://www.elprocus.com/pipelining-architecture-hazards-advantages-disadvantages/
● https://byjus.com/gate/pipeline-hazards-in-computer-architecture-notes/
Video Links:
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