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The document describes the operation of a single-bus organization for executing the ADD (R3), R1 instruction, detailing the control sequence in four steps: Instruction Fetch, Operand Fetch, Perform the Addition, and Store the Result. Each step involves specific control signals that facilitate data transfer between the ALU, registers, and memory. The entire process emphasizes the reliance on a single bus for data movement, with potential complexities in modern systems not covered in this simplified explanation.

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10 views3 pages

Document

The document describes the operation of a single-bus organization for executing the ADD (R3), R1 instruction, detailing the control sequence in four steps: Instruction Fetch, Operand Fetch, Perform the Addition, and Store the Result. Each step involves specific control signals that facilitate data transfer between the ALU, registers, and memory. The entire process emphasizes the reliance on a single bus for data movement, with potential complexities in modern systems not covered in this simplified explanation.

Uploaded by

hv02062005
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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In a single-bus organization, there is one bus that connects different

components of the system, such as the Arithmetic Logic Unit (ALU), registers,
memory, and the control unit. The execution of an instruction like ADD (R3),
R1 can be broken down into a series of steps. This instruction performs an
addition of the value in memory location pointed to by register R3 to the
value in register R1, and stores the result back into R1.

Here’s the control sequence of operations for the ADD (R3), R1 instruction in
a single-bus organization:

Step 1: Instruction Fetch (IF)

Control Signals:

IR <- M[PC] (Copy the instruction from memory location PC to the instruction
register IR)

PC <- PC + 1 (Increment the program counter)

The instruction is fetched from memory using the program counter (PC), and
then the PC is incremented to point to the next instruction. The instruction
ADD (R3), R1 is stored in the instruction register (IR).

Step 2: Operand Fetch (Load Memory Address)

Control Signals:

MAR <- R3 (Place the address from register R3 into the memory address
register MAR)

MDR <- M[MAR] (Memory read operation, copy the value at memory location
MAR into the memory data register MDR)

The contents of register R3 (which holds the memory address) are copied to
the memory address register (MAR). Then, the value from the memory
address pointed to by R3 is loaded into the memory data register (MDR).

Step 3: Perform the Addition

Control Signals:

A <- R1 (Copy the value from register R1 into the A register)


B <- MDR (Copy the value from the memory data register MDR into the B
register)

ALU(ADD) (Perform the addition in the ALU)

The value in register R1 is copied into the A register, and the value in MDR
(from memory) is copied into the B register. Then, the Arithmetic Logic Unit
(ALU) performs the addition operation on the values in the A and B registers.

Step 4: Store the Result

Control Signals:

R1 <- A (Store the result from register A into register R1)

The result of the addition, which is now in the A register, is stored back into
register R1.

Control Signal Summary:

IR <- M[PC]: Fetch the instruction into the instruction register.

PC <- PC + 1: Increment the program counter.

MAR <- R3: Load the memory address from register R3.

MDR <- M[MAR]: Read the value from memory into the memory data
register.

A <- R1: Load the value from R1 into the A register.

B <- MDR: Load the value from MDR into the B register.

ALU(ADD): Perform the addition operation.

R1 <- A: Store the result from register A into R1.

Explanation:

In this sequence, the operand (value stored in memory) is accessed via


register R3. The ALU then adds the value from memory (retrieved in MDR) to
the value in register R1.

The result of the addition is stored back into register R1.

The entire sequence relies on the use of a single bus for transferring data
between registers, memory, and the ALU.
This is a simplified control sequence. In a more complex or modern system,
additional steps, such as handling flags or managing pipeline stages, might
be added, but the basic flow remains consistent in a single-bus organization.

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