trsf3232
trsf3232
DESCRIPTION/ORDERING INFORMATION
The TRSF3232 consists of two line drivers, two line receivers, and a dual charge-pump circuit with ±15-kV ESD
protection pin-to-pin (serial-port connection pins, including GND). This device provides the electrical interface
between an asynchronous communication controller and the serial-port connector. The charge pump and four
small external capacitors allow operation from a single 3-V to 5.5-V supply. The TRSF3232 operates at typical
data signaling rates up to 1 Mbit/s and a driver output slew rate of 24 V/μs to 150 V/μs.
ORDERING INFORMATION
(1) (2)
TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube of 40 TRSF3232CD
SOIC – D TRSF3232C
Reel of 2500 TRSF3232CDR
Tube of 25 TRSF3232CDW
SOIC – DW TRSF3232C
Reel of 2000 TRSF3232CDWR
0°C to 70°C
Tube of 70 TRSF3232CDB
SSOP – DB RT22C
Reel of 2000 TRSF3232CDBR
Tube of 70 TRSF3232CPW
TSSOP – PW RT22C
Reel of 2000 TRSF3232CPWR
SOIC – D Tube of 40 TRSF3232ID
TRSF3232I
SOIC – DW Reel of 2000 TRSF3232IDR
Tube of 25 TRSF3232IDW
SOIC – DW TRSF3232I
Reel of 2000 TRSF3232IDWR
–40°C to 85°C
Tube of 70 TRSF3232IDB
SSOP – DB RT22I
Reel of 2000 TRSF3232IDBR
Tube of 70 TRSF3232IPW
TSSOP – PW RT22I
Reel of 2000 TRSF3232IPWR
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TRSF3232
3-V TO 5.5-V MULTICHANNEL RS-232 COMPATIBLE
LINE DRIVER/RECEIVER www.ti.com
SLLS858 – AUGUST 2007
FUNCTION TABLES
XXX
10 7
DIN2 DOUT2
12 13
ROUT1 RIN1
9 8
ROUT2 RIN2
(1)
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range (2) –0.3 6 V
V+ Positive-output supply voltage range (2) –0.3 7 V
(2)
V– Negative-output supply voltage range 0.3 –7 V
V+ – V– Supply voltage difference (2) 13 V
Drivers –0.3 6
VI Input voltage range V
Receivers –25 25
Drivers –13.2 13.2
VO Output voltage range V
Receivers –0.3 VCC + 0.3
D package 82
DB package 46
θJA Package thermal impedance (3) (4) °C/W
DW package 57
PW package 108
TJ Operating virtual junction temperature 150 °C
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network GND.
(3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
DRIVER SECTION
abc
(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(3) Short-circuit durations should be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one
output should be shorted at a time.
(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(3) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.
RECEIVER SECTION
abc
(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(3) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.
VOH
3V 3V
Output
−3 V −3 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
SR(tr) + 6V
t or t
THL TLH
A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns.
3V
Input
RS-232 1.5 V 1.5 V
Output 0V
Generator
(see Note B) 50 Ω
CL
RL (see Note A) tTHL tTLH
VOH
3V 3V
Output
−3 V −3 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
SR(tr) + 6V
t or t
THL TLH
A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns.
3V
Input
1.5 V 1.5 V
−3 V
Output
Generator
50 Ω tPHL tPLH
(see Note B)
CL
(see Note A) VOH
Output 50% 50%
VOL
APPLICATION INFORMATION
1 VCC 16
C1+
+ CBYPASS = 0.1 µF
−
+ 2 15
C1 + V+ GND
− †
C3
−
14
3 DOUT1
C1−
13
4 RIN1
C2+
+
C2 5 kΩ
−
5 C2−
12
ROUT1
6
V− 11
−
C4 DIN1
+
7 10
DOUT2 DIN2
8 9
RIN2 ROUT2
5 kΩ
www.ti.com 23-May-2025
PACKAGING INFORMATION
Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)
TRSF3232IDWR Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TRSF3232I
TRSF3232IDWR.A Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TRSF3232I
(1)
Status: For more details on status, see our product life cycle.
(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.
(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Feb-2019
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Feb-2019
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DW 16 SOIC - 2.65 mm max height
7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A SCALE 1.500
SOIC - 2.65 mm max height
SOIC
10.5 2X
10.1 8.89
NOTE 3
8
9
0.51
16X
0.31
7.6
B 0.25 C A B 2.65 MAX
7.4
NOTE 4
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0 -8 0.1
1.27
0.40 DETAIL A
(1.4) TYPICAL
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A SOIC - 2.65 mm max height
SOIC
1 16
16X (0.6)
SYMM
14X (1.27)
8 9
R0.05 TYP
(9.3)
4220721/A 07/2016
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A SOIC - 2.65 mm max height
SOIC
1 16
16X (0.6)
SYMM
14X (1.27)
8 9
R0.05 TYP
(9.3)
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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