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EEE 3103 - Binary Adders & Subtractors

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2 views7 pages

EEE 3103 - Binary Adders & Subtractors

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sabrinatithi235
Copyright
© © All Rights Reserved
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EEE 3103:Digital Electronics-I

Chapter-4: Combinational Logic


Binary Adders & Subtractors

Reference: Digital Design by M. Morris Mano & Michael D. Ciletti [5th Edition]

Prepared by
Baizeed Ahmed Bhuiyan
Lecturer (Grade-I)
Department of Electrical and Electronic Engineering
Ahsanullah University of Science and Technology
❑ Half Adder: It can add 2 bits.
The simplified Boolean functions for the two outputs can be obtained directly from the truth
table. The simplified sum-of-products expressions are
S = x’y + xy’
C = xy
The logic diagram of the half adder implemented in sum of products (SOP) is shown in Fig.
4.5(a) . It can be also implemented with an exclusive-OR and an AND gate as shown in Fig.
4.5(b) . This form is used to show that two half adders can be used to construct a full adder.

000
xyz C0S 001
010 111
011
100
101
110
❑ Implementation of a Full Adder using two Half Adders and basic
Logic Gate(s):
❑ Half Subtractor: It can perform subtraction between two bits and produce
their difference as the result.
❑ Full Subtractor: It can perform subtraction between three bits and produce
their difference as the result.
xyz B0 D
000 110
001 111
010
011
100
101
❑ Implementation of a Full Subtractor using two Half Subtractors and basic
Logic Gate(s):
❑ Implementation of a Full Subtractor using two Half Subtractors and basic
Logic Gate(s) [Another Approach]:

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