STA Basic Concepts
{ Concepts } + { Technique }
Ahmed Abdelazeem
Ahmed Abdelazeem
Ahmed Abdelazeem
Agenda
What is STA? 01 05 Special Timing
Checks
Delay
02 06 Crosstalk & Noise
Calculation
Constraints
Develop
03 07 STA
Methodology
Timing
Verification
04 08 Signoff
Checklist
Ahmed Abdelazeem
Ahmed Abdelazeem
Practice in Mind
1 Establish Key concepts used in STA
2 Correctly constrain ASIC design using SDC
3 Interperate most common timing report
4 Basic timing closure approach
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Ahmed Abdelazeem
Goal of this course
DC/FC and Primetime
We made up some examples for industry standard backend tool
Design/Fusion Compiler and Primetime.
Both has built-in STA engine while DC/FC is more emphasis on
implementation side and PT is more on timing verification side.
28 Special Topics
We go over as many as 28 different special topics to extend the key knowledge
point discussed.
These topics are also made to be easily understood and very practical.
Rules of thumb
We introduce a number of rules to certain knowledge point so it clarifies un-
defined conceptual confusion.
You are welcome to test out these rules in your real-life example.
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Ahmed Abdelazeem
01 What is STA ?
✓ Static Timing Analysis Definition
✓ Limitation of STA
✓ Operation Condition
✓ Library Scaling
✓ Inputs to STA analysis
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Static Timing Analysis (STA)
STA is a technique for digital design verification. It:
• Validates if the design can operate at the set timing constraints
• Is a complete and exhaustive verification of all timing checks of a design
• Is used instead of simulation
Vector-less topological analysis of a circuit.
• The signal at the input is propagated through the gates at each level till it reaches the
output
0 2 4 6
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Ahmed Abdelazeem
Simulation
Simulating (dynamically) circuit response for a specified set of input patterns
Circuit modeled as network of capacitors, resistors and voltage/current sources
010
011
Ahmed Abdelazeem
Ahmed Abdelazeem
Why we need STA?
Timing Problem
Given a circuit design, find if path delay could meet system timing requirement.
SPICE simulation
Accurate, but can be computational expensive and take too much time for today’s million
gate ASIC design.
Static Timing Analysis
We need a fast method that produce relatively accurate timing results compared
to SPICE simulation
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Ahmed Abdelazeem
Features of STA
S E
Static Exhaustive
Fast and large capacity. Use mathematical techniques instead of input vectors.
Does not use dynamic logic simulation. Required timing checks are performed on all possible paths
and scenarios
Collapse whole design into minimal cycle and analyze
once.
Functionality
Does not verify logic functionality.
Need equivalence checking on the side.
F C Conservative
Be pessimistic and conservative in many cases to ensure
there is enough guard band for the design timing
requirement
Synchronous Design Only
Does not verify asynchronous part of the
design
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Ahmed Abdelazeem
Role of STA
Place & Logic
Route Synthes
is
Timing
RTL Power
coding Integrity
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Ahmed Abdelazeem
Limitation of STA
1 Conservative & Pessimistic
2 Flag false paths
3
Not suitable for asynchronous design
Ahmed Abdelazeem
Ahmed Abdelazeem
STA vs. Simulation
Simulation
❑ Advantages • Static Timing Analysis (STA)
Can be very accurate
(Spice-level) • Advantages
❑ Disadvantages - Exhaustive timing coverage
Analysis quality depends on stimulus vectors
- Does not require input vectors
Non-exhaustive, slow
- Faster operation
• Disadvantages
- Less accurate
- Must define timing requirements/exceptions
- Difficulty in handling asynchronous designs, false
paths
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Ahmed Abdelazeem
Problem Variability
Other variables affect circuit timing, thus need to be considered during design
❑ Operating Conditions
Process, Voltage, Temperature variations
❑ Unstable clock frequency (jitter, skew)
Instability of clock frequency requires design margin
❑ On-chip variation (OCV)
Device/Interconnect
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Ahmed Abdelazeem
Components of Circuit Timing
Delay components 𝑇𝑐𝑒𝑙𝑙 𝑇𝑛𝑒𝑡
Cells, Interconnects
Constrained components
Clocked registers require setup/hold, recovery/removal constraints FF
𝑇𝑝𝑎𝑡ℎ = 𝑇𝑐𝑒𝑙𝑙 + 𝑇𝑛𝑒𝑡
For circuit to operate without failure it is required that delay
components at no point violate constraints of other components.
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Ahmed Abdelazeem
Operation Condition
Wafer Process Supply Voltage Junction Temperature
Process: TT, FF, SS, etc.
Voltage: ∓10%
td Temperature: -40 -1250C
CL P:SS
V:0.9
trise T:-40
td ~ Process Variations
td ~ Voltage P:TT
td ~ Temperature V:1.2
T:125
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Ahmed Abdelazeem
Process Variation
Global Process Variation On-Chip Process Variation
Inter-die, systematic Intra-die, random
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Ahmed Abdelazeem
Process Variation (cont’d)
Gaussian Distribution
From Monte Carlo simulation, Process Variation follows
Gaussian Distribution.
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Ahmed Abdelazeem
Process Corners
Process Corners (die-to-die global variation)
Single CMOS device
Due to process variation, CMOS device in different location could have different speed.
{ Slow } | { Typical } | { Fast }
For Transistor Formation
Component of a transistor could have following 4 extreme cases:
{ Typical NMOS and PMOS } +
{ Fast NMOS + Slow PMOS } | { Fast PMOS + Slow NMOS } | { Slow NMOS + Slow PMOS } | { Fast NMOS + Fast PMOS }
For Metallization (interconnection parasitic)
All interconnections and dielectric inter layers are formed
{ Best RC } | { Typical RC } | { Worst RC }
Nominal Distribution
These conditions follow a normal distribution where the center is considered as the typical value.
The best and worst, statistically vary by +/- 3ẟ from the center.
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Ahmed Abdelazeem
Voltage/Temperature Corner
Voltage/Temperature Corners Temperature Inversion
At low power supply the delay of a lightly loaded cell is higher at low temperature
because of increasing of Vth has greater impact than mobility increase.
{ High | Nominal | Low }
voltage/temperature
Standard corners for STA
WCS (worst case slow)
Slowest process + Lowest power supply + Highest / Lowest temperature
BCF (best case fast)
Fastest process + highest power supply + Highest / Lowest temperature
Typical
Typical process + Nominal power supply + Nominal temperature
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Ahmed Abdelazeem
Library Scaling
One-Dimension Scaling Two-Dimension Scaling Three-Dimension Scaling
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Ahmed Abdelazeem
Inputs to STA analysis
Gate-level Netlist Timing Model
Pre-layout: Verilog from logic synthesis tool or PnR tool before the design is detail In the format of Synopsys Liberty file (dotlib) for each standard cell and macro.
routed. Characterized from SPICE simulation
Post-layout: Verilog generated by place and route tool after the design is detail routed.
Timing Constraints OCV Recipe
In the Form of Synopsys Design Constraint (SDC), one SDC for each timing scenario On-chip variation derating factor, OCV/AOCV/POCV table
Parasitic
Post-layout STA only, in the form of Standard Parasitic Exchange Format
(SPEF), generated by layout extraction tool.
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Ahmed Abdelazeem
Topic 1: Netlist
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Ahmed Abdelazeem
Topic 1: Netlist
Cell – Multiple driver and multiple loads
Net – Single driver and multiple loads
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Ahmed Abdelazeem
Topic 2: Hierarchical (cell/pin) v.s. Leaf (cell/pin)
Hierarchical cell/pin/net
A shell/wrapper representing certain logic boundary. In above case, Top/Sub is a hierarchical cell, Top/Sub/Out is a hierarchical pin and
Top/Sub/n1 is a hierarchical net
Leaf cell/pin/net
The deepest level of hierarchy, real physical standard library cell. In above case, Top/Sub/U1 is a leaf cell, Top/Sub/Z is a leaf
pin and Top/Sub/n1 is a leaf net
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Ahmed Abdelazeem
Topic 3: Immediate fanin/fanout
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Ahmed Abdelazeem
Topic 4: Basics query commands
get_cells get_pins / get_nets
➢ Broaden search into all hierarchy with ➢ List same net with different hierarchical net
-hier option name -segment
➢ Refine the results with -filter option ➢ Get top level net name -top_hierarchical_group
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Ahmed Abdelazeem
Topic 4: Basics query commands
list_attribute report_attribute
➢ Find all available attribute of a class ➢ Report active attribute on a cell
get_attribute
➢ Get particular attribute of an object
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Ahmed Abdelazeem
Topic 4: Basics query commands
report_cell
➢ Get a quick look of cell connectivity
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Ahmed Abdelazeem
Topic 5: Basics tracing commands
all_connected [<pin/net object>]
➢ Usually we only care about leaf cell, so get leaf cell with
option –leaf
➢ Argument must be a valid database object, not a plain text
➢ Get immediate fanin/fanout
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Ahmed Abdelazeem
Topic 5: Basics tracing commands
all_fanout -flat -from
➢ Trace entire fanout-cone of particular pin
➢ Refine results with –endpoints_only, -cell_only option
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Ahmed Abdelazeem
Topic 5: Basics tracing commands
all_fanin -flat -to
➢ Trace entire fanin-cone of particular pin
➢ Refine results with –startpoints_only, -cell_only option
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Ahmed Abdelazeem
Topic 6: Synopsys object
query_object
➢ Return the object name rather than internal object
variable _sel*
get_object_name
➢ Translate design object to text sting in a list
Trick: split output into multiple lines
join [lsort -dict -unique [split [get_object_name $arg] "
" ]] "\n“
Trick: [debug feature] proc_body
proc_body shows the content of a procedure. You can use it
to reveal unprotected procedure bodies for debug.
Ahmed Abdelazeem
Ahmed Abdelazeem
Chapter Summary
✓ Static Timing Analysis Definition
✓ Limitation of STA
✓ Operation Condition
✓ Library Scaling
✓ Inputs to STA analysis
Ahmed Abdelazeem
Ahmed Abdelazeem
Thank You ☺
Ahmed Abdelazeem
Ahmed Abdelazeem
