106 Chapter 2 Introduction to VHDL

testing that was done using simulator commands in Figure 2-55. A time-varying signal is
provided to input X using the statement

X <= '0', '1' after 350 ns, '0' after 550ns, '1' after 750 ns, '0'
after 950 ns, '1' after 1350 ns;

Another method to generate the same stimuli is illustrated below:

example_test_seq: process
begin
X <= '0';
wait for 350 ns;
X <= '1';
wait for 200 ns;
X <= '0';
wait for 200 ns;
X <= '1';
wait for 200 ns;
X <= '0';
wait for 400 ns;
X <= '1';
end process example_test_seq;

Yet another method of generating test stimuli is using constant arrays and loops. If there
are several inputs to be fed to the circuit, the input values can be embedded in arrays and
streamed out to the DUV, using loop statements. The same stimuli pattern above is gener-
ated, using an array in a loop below. A better example for the use of arrays and loops can be
found in the next section.

constant N: integer := 6;
type X_arr is array(0 to N) of bit;
constant X_array: X_arr := ('0', '1', '0', '1', '0', '0', '1');
signal X: bit;
begin
process
begin
X <= '0';
wait for 350 ns;
for i in 1 to N loop
X <= X_array(i);
wait for 200 ns;
end loop;

2.20 Tips for Debugging VHDL Code

Students often struggle with testing and debugging code. While this is not a VHDL-specific
issue, understanding specifics about VHDL can help students to minimize the amount of
time spent in debugging. In this section, several code examples are provided with testing and
debugging tips.
 2.20 Tips for Debugging Vhdl Code 107

EXAMPLE
In order to get 2 gates, one student wrote the following code

FIGURE 2-70: Example gates code

entity gates is
port(A, B, C: in bit; D, E: out bit);
end gates;

architecture ckt of gates is

begin
process (A,B,C)
begin
D <= A or B after 5 ns;
E <= not C and A after 5 ns;
end process;
end ckt;

It was tested with the following simulator sequence.

add wave A B C D E
force A 0 0, 1 1 –repeat 2 ns
force B 0
force C 0 0, 1 2 -repeat 4 ns
run 40 ns

It was expected that D would be 1 whenever A is 1 and E would be 1 periodically. But neither D nor E ever turned
1 during simulation. What is wrong with this code?

Answer: Nothing is wrong with this code. The OR and AND gates have an inertial delay of 5 ns. Pulses narrower than
5 ns will get delayed. Hence the test sequence applied should be modified to produce test stimulus that does not get
rejected. For example the following sequence will demonstrate that the code is working as expected.

add wave A B C D E
force A 0 0, 1 10 –repeat 20 ns
force B 0
force C 0 0, 1 20 -repeat 40 ns
run 100 ns

TIP 1: Make sure that your test sequences are appropriately designed considering inertial delay of the circuit elements
so that you do not interpret a working circuit as incorrect.
108 Chapter 2 Introduction to VHDL

EXAMPLE
Design an adder/subtractor unit with a process and when statements. The circuit should be purely combinational, that
is, no latches should be present.
A. The code in Figure 2-71 is incorrect because Output and Cout correspond to previous values of inputs. The signals
tempSum and tempDiff are not in the sensitivity list.

FIGURE 2-71: Preliminary Code for an adder/subtractor unit

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_bit.all;
use IEEE.std_logic_unsigned.all;

entity addsub is
port(A,B: in unsigned(3 downto 0);
opcode: in bit_vector(2 downto 0);
Cin: in bit;
Output: out unsigned(3 downto 0);
Cout: out bit);
end addsub;

architecture Structure of addsub is

signal tempSum: unsigned(4 downto 0);
signal tempDiff: unsigned(4 downto 0);
begin
process(opcode,A,B,Cin)
begin
case opcode is
when "0"=>
tempSum<='0' & A + B + unsigned'(0=>Cin) after 10 ns;
Output<=tempSum(3 downto 0) after 10 ns;
Cout<=tempSum(4) after 10 ns;
when "1"=>
tempDiff<='0' & A - B - unsigned'(0=>Cin) after 10 ns;
Output<=tempDiff(3 downto 0) after 10 ns;
Cout<=tempDiff(4) after 10 ns;
end case;
end process;
end Structure;

B. Figure 2-72 illustrates code with sensitivity list corrected. Two signals tempSum and tempDiff are added to the pro-
cess sensitivity list. The code performs addition and subtraction now, but this code still has problems. It generates
latches for the output. Also, unnecessary libraries still remain in the code. The two std_logic libraries are not required
for this code. Only the numeric_bit library is needed.
 2.20 Tips for Debugging Vhdl Code 109

FIGURE 2-72: Improved Code for the adder/subtractor code

library IEEE;
use IEEE.std_logic_1164.all; --many students add this, but unnecessary here

use IEEE.numeric_bit.all;
use IEEE.std_logic_unsigned.all; --many students add this, but unnecessary here

entity addsub is
port(A,B: in unsigned(3 downto 0);
opcode: in bit_vector(2 downto 0);
Cin: in bit;
Output: out unsigned(3 downto 0);
Cout: out bit);
end addsub;

architecture Structure of addsub is

signal tempSum: unsigned(4 downto 0);
signal tempDiff: unsigned(4 downto 0);
begin
process(opcode,A,B,Cin, tempSum, tempDiff)
begin
case opcode is
when "0"=>
tempSum<='0' & A + B + unsigned'(0=>Cin)after 10 ns;
Output<=tempSum(3 downto 0)after 10 ns;
Cout<=tempSum(4)after 10 ns;
when "1"=>
tempDiff<='0' & A - B - unsigned'(0=>Cin) after 10 ns;
Output<=tempDiff(3 downto 0) after 10 ns;
Cout<=tempDiff(4) after 10 ns;
end case;
end process;
end Structure;

There are two sequential statements dependent on tempSum for case 0 and that results in Output and Cout using
old values of tempSum. While tempSum has correct values, Output and Cout are incorrect.
Basically there is a latch between tempSum and Output and tempSum and Cout which introduces additional delay.
This circuit was intended to be purely combinational and no latches are expected.
Similar problem also exists in case 1 for tempDiff.
TIP 2: If there are multiple statements that need to be executed at the same time, do not put them as sequential state-
ments inside a process.
110 Chapter 2 Introduction to VHDL

C. Figure 2-73 illustrates corrected code with latches removed to eliminate timing problems.

FIGURE 2-73: Corrected code for adder/subtractor

library IEEE;
use IEEE.numeric_bit.all;

entity addsub is
port(A, B: in unsigned(3 downto 0);
opcode: in unsigned(2 downto 0);
Cin: in bit;
Cout: out bit;
Output: out unsigned(3 downto 0));
end addsub;

architecture circuit of addsub is

signal Sum: unsigned (4 downto 0):= "00000";

begin
process(A,B,opcode,Cin)
begin
case opcode is

when "0" =>

Sum <= '0' & A + B + unsigned'(0=>Cin) after 10 ns; -- 5 bits with carry
when "1" =>
Sum <= '0' & A - B - unsigned'(0=>Cin) after 10 ns;
end case;
end process;
Output <= Sum(3 downto 0);
Cout <= Sum(4);
end;

If the statement

tempSum<='0' & A + B + unsigned'(0=>Cin) after 10 ns;

in Figure 2-72 is changed to

Output <= '0' & A + B + unsigned'(0=>Cin) after 10 ns;

Output is correct, but we would like the answer as a 4-bit sum and a 1-bit Cout. Splitting the Sum into Output and Cout is
done outside the process statement, so the operation happens concurrently as opposed to sequentially. Similar changes must
be made in case 1 as well.
TIP 3: If there are multiple statements that should take effect during execution of a case in a case statement, they need to be
independent. If they are dependent (i.e., sequential), see whether a single output vector encompassing all the outputs can be
generated inside the case statement which can be split into multiple outputs outside the process.
 2.20 Tips for Debugging Vhdl Code 111

EXAMPLE

Analyzing code
What is the following code doing?

FIGURE 2-74: Counter Code version 1

library IEEE;
use IEEE.numeric_bit.all;

entity bcd is
port(Load, Clr, Enable, Clk, Up: in bit;
D: in unsigned(3 downto 0);
Cout: out bit; Q: out unsigned(3 downto 0));
end bcd;

architecture counter of bcd is

signal Qout: unsigned(3 downto 0);
begin
Q <= Qout;
process(Clk,Clr)
begin
if Clr = '0' then Qout<="0000";
elsif Clk'event and Clk = '1' then
if Load = '1' and Enable = '1' then Qout <= D after 2 ns;
elsif Load = '0' and Enable = '1' and Up = '1' then
if Qout = "1001" then Cout <= '1'; Qout<="0000" after 2 ns;
else Qout <= Qout + 1 after 2 ns; Cout <= '0';
end if;
elsif Load = '0' and Up = '0' and Enable = '1' then
if Qout = "0000" then Cout <= '1'; Qout<="1001" after 2 ns;
else Qout <= Qout - 1 after 2 ns; Cout <= '0';
end if;
end if;
end if;
end process;
end counter;

Answer: It is implementing a 1-digit BCD up-down counter with parallel load and a carryout. The carryout becomes 1
when the counter counts up from 9 to 0 or counts down from 0 to 9. When load signal is 1, the counter can be parallel
loaded from D. It has an active low clear and an active high enable. The UP signal must be 1 for counting up and 0 for
counting down.
Question: While counting up, when will the carry be generated? When the counter is 9 or when it is 0?
Answer: When it is 0.
Question: What will happen if this counter is asked to load hexadecimal value C (i.e., 1100)?
Answer: It will load it although it is not a legal BCD value.
112 Chapter 2 Introduction to VHDL

Question: How can you prevent the counter from loading non-BCD values?
Change

if Load = '1' and Enable = '1' then Qout <= D after 2 ns;
to
if Load ='1' and Enable = '1' and D <= 1001 then Qout <= D after 2 ns;
Question: Is the carry signal synchronous or asynchronous?
Answer: Synchronous.
Now analyze the following variant of this code.

FIGURE 2-75: Counter code version 2

library IEEE;
use IEEE.numeric_bit.all;

entity bcd is
port(Load, Clr, Enable, Clk, Up: in bit;
D: in unsigned(3 downto 0);
Cout: out bit; Q: out unsigned(3 downto 0));
end bcd;

architecture counter of bcd is

signal Qout: unsigned(3 downto 0);
begin
Q <= Qout;
Cout <= (not Qout(3) and not Qout(2) and not Qout(1) and not Qout(0) and Enable and
not Up) or (Qout(3) and not Qout(2) and not Qout(1) and Qout(0) and Enable and Up);

process(Clk,Clr)
begin
if Clr = '0' then Qout<="0000";
elsif Clk'event and Clk = '1' then
if Load = '1' and Enable = '1' then Qout <= D after 2 ns;
elsif Load = '0' and Enable = '1' and Up = '1' then
if Qout = "1001" then Qout<="0000" after 2 ns;
else Qout <= Qout + 1 after 2 ns;
end if;
elsif Load = '0' and Up = '0' and Enable = '1' then
if Qout = "0000" then Qout<="1001" after 2 ns;
else Qout <= Qout - 1 after 2 ns;
end if;
end if;
end if;
end process;
end counter;
 2.20 Tips for Debugging Vhdl Code 113

Question: What are differences in this code compared to the code in Figure 2-74?
Answer: Cout is a combinational output implemented using a concurrent statement outside the process. Cout is
produced when count is 9 and counter is in the up counting mode or when count 5 0 and the counter is in the down
counting mode.
Question: If a 2-digit BCD counter uses the 1-digit BCD as in code in Figure 2-74 versus the code in Figure 2-75, what are
the differences in the results of the 2 implementations?
Answer: The implementation using Figure 2-74 counts from 69 to 60 to 71.
The implementation using Figure 2-75 counts from 69 to 70 to 71.
Why is there a difference?
The implementation in Figure 2-74 produces Cout inside the process. Hence Cout becomes 1 at the next clock after
count equals 9 and Up signal is there. But Cout has to be present in order for the second digit to increment. Hence the
increment happens 1 clock cycle later.
The code in Figure 2-74 has latches between count value and Cout.
The code for Cout in Figure 2-75 is purely combinational.

EXAMPLE
The following code is used to slow down a fast 50 MHz clock to a 1 Hz clock. The code was tested and found to be not
working. The output simply stays at 0. What is wrong?

FIGURE 2-76: Code for generating a slow clock from a fast clock

library IEEE;
use IEEE.numeric_bit.all;

entity complex is
port(clk50Mhz: in bit;
clk: inout bit);
end complex;

architecture internal of complex is

signal counter_Big: integer range 1 to 5000000;
begin

process(clk50Mhz)
begin
if clk50Mhz = '1' and clk50Mhz'event then
if counter_Big = 50000000 then counter_Big <= 1; clk<=not clk;
else counter_Big<=counter_Big+1;
end if;
end if;
end process;
end internal;
114 Chapter 2 Introduction to VHDL

Answer: The integer range for the counter_Big has a typo. It should be 50 million, not 5 million. It is smaller than the
divider ratio.
Good software engineering practices are important while writing VHDL code. Instead of typing the constant
50 million in each place that it was needed, a constant name such as N could be used. If changes are made to this constant,
it then needs to be changed only in one place.
TIP 4: If the same constant number is used in multiple places, use a constant symbol such as N so the constant is
typed only once.
TIP 5: Check ranges of all signals. They should be at least equal to the highest value computed in the program.
It is important to check the warning signals one obtains during compilation of code. Many students ignore warnings
and only fix errors. Looking at warnings can give hints on the existence of bugs.

In this chapter, we have covered the basics of VHDL. We have shown how to use VHDL
to model combinational logic and sequential machines. Since VHDL is a hardware descrip-
tion language, it differs from an ordinary programming language in several ways. Most
importantly, VHDL statements execute concurrently, since they must model real hardware
in which the components are all in operation at the same time. Statements within a process
execute sequentially, but the processes themselves operate concurrently. VHDL signals
model actual signals in the hardware, but variables may be used for internal computation
that is local to processes, procedures, and functions. We will cover more advanced features
of VHDL in Chapter 8.

Problems
2.1 (a) What do the acronyms VHDL and VHSIC stand for?
(b) How does a hardware description language like VHDL differ from an ordinary programming language?
(c) What are the advantages of using a hardware description language as compared with schematic capture in
the design process?
2.2 (a) Which of the following are legal VHDL identifiers? 123A, A_123, _A123, A123_, c1__c2, and,
and1
(b) Which of the following identifiers are equivalent? aBC, ABC, Abc, abc
2.3 Given the concurrent VHDL statements:

B <= A and C after 3ns;

C <= not B after 2ns;

(a) Draw the circuit the statements represent.

(b) Draw a timing diagram if initially A 5 B 5 '0' and C 5 '1', and A changes to '1' at time 5 ns.
2.4 Write a VHDL description of the following combinational circuit using concurrent statements. Each gate has a
5-ns delay, excluding the inverter, which has a 2-ns delay.

A
B E
C
D
A
F Z
B
C
 Problems 115

2.5 (a) Write VHDL code for a full subtracter using logic equations.
(b) Write VHDL code for a 4-bit subtracter using the module defined in (a) as a component.
2.6 Write VHDL code for the following circuit. Assume that the gate delays are negligible.
(a) Using concurrent statements.
(b) Using a process with sequential statements.

A
E
B
F
C
G
D

2.7 In the following VHDL code, A, B, C, and D are integers that are 0 at time 10 ns. If D changes to 1 at 20 ns, specify
the times at which A, B, and C will change and the values they will take.

process(D)
begin
A <= 1 after 5 ns;
B <= A + 1; -- executes before A changes
C <= B after 10 ns; -- executes before B changes
end process;

2.8 (a) What device does the following VHDL code represent?

process(CLK, Clr, Set)

begin
if Clr = '1' then Q <= '0';
elsif Set = '1' then Q <= '1';
elsif CLK'event and CLK = '0' then
Q <= D;
end if;
end process;

(b) What happens if Clr 5 Set 5 '1' in the device in part a?

2.9 Write a VHDL description of an S-R latch using a process.
2.10 An M-N flip-flop responds to the falling clock edge as follows:

If M = N = '0', the flip-flop changes state.

If M = '0' and N = '1', the flip-flop output is set to '1'.
If M = '1' and N = '0', the flip-flop output is set to '0'.
If M = N = '1', no change of flip-flop state occurs.
The flip-flop is cleared asynchronously if CLRn = '0'.

Write a complete VHDL module that implements an M-N flip-flop.

2.11 A DD flip-flop is similar to a D flip-flop, except that the flip-flop can change state 1 Q1 5 D 2 on both the rising
edge and falling edge of the clock input. The flip-flop has a direct reset input, R, and R 5 '0' resets the flip-flop
to Q 5 '0' independent of the clock. Similarly, it has a direct set input, S, that sets the flip-flop to '1' independent
of the clock. Write a VHDL description of a DD flip-flop.
2.12 An inhibited toggle flip-flop has inputs I0, I1, T, and Reset, and outputs Q and QN. Reset is active high and over-
rides the action of the other inputs. The flip-flop works as follows. If I 0 5 '1', the flip-flop changes state on the
116 Chapter 2 Introduction to VHDL

rising edge of T; if I 1 5 '1', the flip-flop changes state on the falling edge of T. If I 0 5 I 1 5 '0', no state change
occurs (except on reset). Assume the propagation delay from T to output is 8 ns and from reset to output is 5 ns.
(a) Write a complete VHDL description of this flip-flop.
(b) Write a sequence of simulator commands that will test the flip-flop for the input sequence I 1 5 '1', toggle T
twice, I 1 5 '0', I 0 5 '1', toggle T twice.
2.13 In the following VHDL process A, B, C, and D are all integers that have a value of 0 at time 5 10 ns. If E changes
from '0' to '1' at time 5 20 ns, specify the time(s) at which each signal will change and the value to which it will
change. List these changes in chronological order (20, 20 1 D, 20 1 2D, etc.)

p1: process
begin
wait on E;
A <= 1 after 5 ns;
B <= A + 1;
C <= B after 10 ns;
wait for 0 ns;
D <= B after 3 ns;
A <= A + 5 after 15 ns;
B <= B + 7;
end process p1;
2.14 In the following VHDL process A, B, C, and D are all integers that have a value of 0 at time 5 10 ns. If E changes
from '0' to '1' at time 5 20 ns, specify the time(s) at which each signal will change and the value to which it will
change. List these changes in chronological order (20, 20 1 D, 20 1 2D, etc.)
p2: process(E)
begin
A <= 1 after 5 ns;
B <= A + 1;
C <= B after 10 ns;

D <= B after 3 ns;

A <= A + 5 after 15 ns;
B <= B + 7;
end process p2;
2.15 For the following VHDL code, assume that D changes to '1' at time 5 ns. Give the values of A, B, C, D, E, and
F each time a change occurs. That is, give the values at time 5 ns, 5 1 D, 5 1 2D, and so on. Carry this out until
either 20 steps have occurred, until no further change occurs, or until a repetitive pattern emerges.
entity prob is
port(D: inout bit);
end prob;

architecture q1 of prob is
signal A, B, C, E, F: bit;
begin
C <= A;
A <= (B and not E) or D;
P1: process (A)
begin
B <= A;
end process P1;
 Problems 117

P2: process
begin
wait until A = '1';
wait for 0 ns;
E <= B after 5 ns;
D <= '0';
F <= E;
end process P2;
end architecture q1;
2.16 Assuming B is driven by the simulator command:

force B 0 0, 1 10, 0 15, 1 20, 0 30, 1 35

Draw a timing diagram illustrating A, B, and C if the following concurrent statements are executed:

A <= transport B after 5 ns;

C <= B after 8 ns;
2.17 Assuming B is driven by the simulator command:

force B 0 0, 1 4, 0 10, 1 15, 0 20, 1 30, 0 40

Draw a timing diagram illustrating A, B, and C if the following concurrent statements are executed:

A <= transport B after 5 ns;

C <= B after 5 ns;
2.18 In the following VHDL Code, A, B, C, and D are bit signals that are '0' at time 5 4 ns. If A changes to 1 at time
5 ns, make a table showing the values of A, B, C, and D as a function of time until time 5 18 ns. Include deltas.
Indicate the times at which each process begins executing.

P1: process(A)
begin
B <= A after 5 ns;
C <= B after 2 ns;
end process;
P2: process
begin
wait on B;
A <= not B;
D <= not A xor B;
end process;
2.19 If A 5 ''101'', B 5 ''011'', and C 5 ''010'', what are the values of the following statements?
(a) (A & B) or (B & C)
(b) A ror 2
(c) A sla 2
(d) A & not B = "111110"
(e) A or B and C
2.20 Consider the following VHDL code:

entity Q3 is
port(A, B, C, F, Clk: in bit;
E: out bit);
end Q3;
118 Chapter 2 Introduction to VHDL

architecture Qint of Q3 is
signal D, G: bit;
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
D <= A and B and C;
G <= not A and not B;
E <= D or G or F;
end if;
end process;
end Qint;
(a) Draw a block diagram for the circuit (no gates – at block level only)
(b) Give the circuit generated by the above code (at the gate level)
2.21 Implement the following VHDL code using these components: D flip-flops with clock enable, a multiplexer, an
adder, and any necessary gates. Assume that Ad and Ora will never be '1' at the same time, and only enable the
flip-flops when Ad or Ora is '1'.

library IEEE;
use IEEE.numeric_bit.all;

entity module1 is
port(A, B: in unsigned (2 downto 0);
Ad, Ora, clk: in bit;
C: out unsigned (2 downto 0));
end module1;

architecture RT of module1 is
begin
process(clk)
begin
if clk = '1' and clk'event then
if Ad = '1' then C <= A + B; end if;
if Ora = '1' then C <= A or B; end if;
end if;
end process;
end RT;
2.22 Draw the circuit represented by the following VHDL process. Use only two gates.

process(clk, clr)
begin
if clr = '1' then Q <= '0';
elsif clk'event and clk = '0' and CE = '1' then
if C = '0' then Q <= A and B;
else Q <= A or B; end if;
end if;
end process;

Why is clr on the sensitivity list and C is not?

 Problems 119

2.23 (a) Write a selected signal assignment statement to represent the 4-to-1 MUX shown below.
Assume that there is an inherent delay in the MUX that causes the change in output to occur 10 ns after a change
in input.
(b) Repeat (a) using a conditional signal assignment statement.
(c) Repeat (a) using a process and a case statement.

A9 I0
B I1
F
B9 I2
0 I3

C D
2.24 (a) Write a VHDL process that is equivalent to the following concurrent statement:
A <= B1 when C = 1 else B2 when C = 2 else B3 when C = 3 else 0;
(b) Draw a circuit to implement the following VHDL statement,
A <= B1 when C1 = '1' else B2 when C2 = '1' else
B3 when C3 = '1' else '0';
where all signals are of type bit.
2.25 Write a VHDL description of an SR latch.
(a) Use a conditional assignment statement.
(b) Use the characteristic equation.
(c) Use logic gates.
2.26 For the VHDL code of Figure 2-38, what will be the values of S and Co if A 5 ''1101'', B 5 ''111'', and Ci 5 '1'?
2.27 Write VHDL code to add a positive integer B 1 B , 16 2 to a 4-bit bit-vector A to produce a 5-bit bit-vector as a
result. Use an overloaded operator in the IEEE numeric bit package to do the addition. Use calls to conversion
functions as needed. The final result should be a bit-vector, not an unsigned vector.
2.28 The 74HC138 is a 3-to-8 decoder with a logic diagram as shown below.
(a) Write behavioral VHDL model for this circuit using a case statement.
(b) Write dataflow VHDL model for this circuit using the corresponding logical equations (as in Figure 2-57).
(c) Make a structural VHDL model for this circuit (as in Figure 2-58) using AND gates and inverters.

A2 Y7

Y6
A1
Y5
A0
Y4
E1
Y3
E2
Y2
E3
Y1

Y0
120 Chapter 2 Introduction to VHDL

2.29 (a) Using the VHDL model created for the 3-to-8 decoder in Question 2.28 (a), construct a structural VHDL
model of 4-to-16 decoder using portmap statements.
(b) Using the VHDL model created for the 3-to-8 decoder in Question 2.28 (b), construct a structural VHDL
model of 4-to-16 decoder using portmap statements.
(c) Using the VHDL model created for the 3-to-8 decoder in Question 2.28 (c), construct a structural VHDL
model of 4-to-16 decoder using portmap statements.
2.30 The 74LS181 is an ALU chip with the following function table. Input A, input B, and output F are 4-bits each.
(a) Write VHDL code to implement the logic functions of the chip. Use a case statement.
(b) Write VHDL code to implement the arithmetic functions of the chip. Use a case statement.

ACTIVE-LOW DATA

SELECTION M5H M 5 L; ARITHMETIC OPERATIONS

LOGIC Cn 5 L Cn 5 H
S3 S2 S1 S0 FUNCTIONS (no carry) (with carry)
L L L L F5A F 5 A MINUS 1 F5A
L L L H F 5 AB F 5 AB MINUS 1 F 5 AB
L L H L F5A1B F 5 AB MINUS 1 F 5 AB
L L H H F51 F 5 MINUS 1 (2’s COMP) F 5 ZERO
L H L L F5A1B F 5 A PLUS 1 A 1 B 2 F 5 A PLUS 1 A 1 B 2 PLUS 1
L H L H F5B F 5 AB PLUS 1 A 1 B 2 F 5 AB PLUS 1 A 1 B 2 PLUS 1
L H H L F5A!B F 5 A MINUS B MINUS 1 F 5 A MINUS B
L H H H F5A1B F5A1B F 5 1 A 1 B 2 PLUS 1
H L L L F 5 AB F 5 A PLUS 1 A 1 B 2 F 5 A PLUS 1 A 1 B 2 PLUS 1
H L L H F5A!B F 5 A PLUS B F 5 A PLUS B PLUS 1
H L H L F5B F 5 AB PLUS 1 A 1 B 2 F 5 AB PLUS 1 A 1 B 2 PLUS 1
H L H H F5A1B F 5 1A 1 B2 F 5 1 A 1 B 2 PLUS 1
H H L L F50 F 5 A PLUS A ‡
F 5 A PLUS A PLUS 1
H H L H F 5 AB F 5 AB PLUS A F 5 AB PLUS A PLUS 1
H H H L F 5 AB F 5 AB PLUS A F 5 AB PLUS A PLUS 1
H H H H F5A F5A F 5 A PLUS 1
‡
Each bit is shifted to the next more significant position.

2.31 A 4-bit magnitude comparator chip (eg: 74LS85) compares two 4-bit numbers A and B and produces outputs to
indicate whether A , B, A 5 B or A . B. There are 3 output signals to indicate each of the above conditions.
Note that exactly one of the output lines will be high and the other 2 lines will be low at any time. The chip is a
cascadable chip and has 3 inputs, A . B.IN, A 5 B.IN, and A , B.IN, in order to allow cascading the chip to
make 8-bit or bigger magnitude comparators.
(a) Draw block diagram of a 4-bit magnitude comparator
(b) Draw a block diagram to indicate how you can construct an 8-bit magnitude comparator using two 4-bit
magnitude comparators.
 Problems 121

(c) Write behavioral VHDL description for the 4-bit comparator.

(d) Write VHDL code for the 8-bit comparator using two 4-bit comparators as components.
2.32 Write a VHDL module that describes a 16-bit serial-in, serial-out shift register with inputs SI (serial input), EN
(enable), and CK (clock, shifts on rising edge) and a serial output (SO).
2.33 A description of a 74194 4-bit bidirectional shift register follows:
The CLRb input is asynchronous and active low and overrides all the other control inputs. All other state
changes occur following the rising edge of the clock. If the control inputs S 1 5 S 0 5 1, the register is loaded
in parallel. If S 1 5 1 and S 0 5 0, the register is shifted right, and SDR (serial data right) is shifted into Q 3. If
S 1 5 0 and S 0 5 1, the register is shifted left, and SDL is shifted into Q 0. If S 1 5 S 0 5 0, no action occurs.

Q3 Q2 Q1 Q0

SDR SDL
S1 74194 CLRb

S0 CLK

D3 D2 D1 D0

(a) Write a behavioral level VHDL model for the 74194.

(b) Draw a block diagram and write a VHDL description of an 8-bit bidirectional shift register that uses two
74194s as components. The parallel inputs and outputs to the 8-bit register should be X(7 downto 0) and Y(7
downto 0). The serial inputs should be RSD and LSD.
2.34 A synchronous (4-bit) up/down decade counter with output Q works as follows: All state changes occur on the
rising edge of the CLK input, except the asynchronous clear (CLR). When CLR 5 0, the counter is reset regard-
less of the values of the other inputs.
If the LOAD input is 0, the data input D is loaded into the counter.
If LOAD 5 ENT 5 ENP 5 UP 5 1, the counter is incremented.
If LOAD 5 ENT 5 ENP 5 1 and UP 5 0, the counter is decremented.
If ENT 5 UP 5 1, the carry output 1 CO 2 5 1 when the counter is in state 9.
If ENT 5 1 and UP 5 0, the carry output 1 CO 2 5 1 when the counter is in state 0.
(a) Write a VHDL description of the counter.
(b) Draw a block diagram and write a VHDL description of a decimal counter that uses two of the above
counters to form a two-decade decimal up/down counter that counts up from 00 to 99 or down from 99 to 00.
(c) Simulate for the following sequence: load counter with 98, increment 3 times, do nothing for 2 clocks,
decrement 4 times, and clear.
2.35 Write a VHDL model for a 74HC192 synchronous 4-bit up/down counter. Ignore all timing data. Your code
should contain a statement of the form process(DOWN, UP, CLR, LOADB).
2.36 Consider the following 8-bit bi-directional synchronous shift register with parallel load capability. The notation
used to represent the input/output pins is explained below.
CLR Asynchronous Clear, that overrides all other inputs.
Q(7:0) 8-bit output
D(7:0) 8-bit input
S0, S1 mode control inputs
LSI serial input for left shift
RSI serial input for right shift
122 Chapter 2 Introduction to VHDL

The mode control inputs work as follows:

S0 S1 Action
0 0 No action
0 1 Right Shift
1 0 Left Shift
1 1 Load parallel data (i.e. Q 5 D)

(a) Write an entity description for this shift register.

(b) Write an architecture description of this shift register.
(c) Draw a block diagram illustrating how 2 of these can be connected to form a 16-bit cyclic shift register, which
is controlled by signals L and R. If L 5 '1' and R 5 '0', then the 16-bit register is cycled left. If L 5 '0' and
R 5 '1', the register is cycled right. If L 5 R 5 '1', the 16-bit register is loaded from X(15:0). If L 5 R 5 '0',
the register is unchanged.
(d) Write an entity description for the module in part c.
(e) Write an architecture description using the module from parts a and b.
2.37 Complete the following VHDL code to implement a counter that counts in the following sequence: Q 5 1000,
0111, 0110, 0101, 0100, 0011, 1000, 0111, 0110, 0101, 0100, 0011, … (repeats). The counter is synchronously
loaded with 1000 when Ld8 5 '1'. It goes through the prescribed sequence when Enable 5 '1'. The counter out-
puts S5 5 '1' whenever it is in state 0101. Do not change the entity in any way. Your code must be synthesizable.

library IEEE;
use IEEE.numeric_bit.all;

entity countQ1 is
port(clk, Ld8, Enable: in bit; S5: out bit;
Q: out unsigned(3 downto 0));
end countQ1;
2.38 A synchronous 4-bit UP/DOWN binary counter has a synchronous clear signal CLR and a synchronous load
signal LD. CLR has higher priority than LD. Both CLR and LD are active high. D is a 4-bit input to the counter
and Q is the 4-bit output from the counter. UP is a signal that controls the direction of counting. If CLR and LD
are not active and UP 5 1, the counter increments. If CLR and LD are not active and UP 0, the counter decre-
ments. All changes occur on the falling edge of the clock.
(a) Write a behavioral VHDL description of the counter.
(b) Use the above UP/DOWN counter to implement a synchronous modulo 6 counter that counts from 1 to 6.
This modulo 6 counter has an external reset which if applied makes the count 5 1. A count enable signal
CNT makes it count in the sequence 1, 2, 3, 4, 5, 6, 1, 2, … incrementing once for each clock pulse. You should
use any necessary logic to make the counter go to count 5 1 after count 5 6. The modulo 6 counter only
counts in the UP sequence. Provide a textual/pictorial description of your approach.
(c) Write a behavioral VHDL description for the modulo-6 counter in part b.
2.39 Examine the following VHDL code and answer the following questions

entity Problem
port(X, CLK: in bit;
Z1, Z2: out bit);
end Problem;
 Problems 123

architecture Table of Problem is

signal State, Nextstate: integer range 0 to 3 := 0;
begin
process(State, X) --Combinational Circuit
begin
case State is
when 0 =>
if X = '0' then Z1 <= '1'; Z2 <= '0'; Nextstate <= 0;
else Z1 <= '0'; Z2 <= '0'; Nextstate <= 1; end if;
when 1 =>
if X = '0' then Z1 <= '0'; Z2 <= '1'; Nextstate <= 1;
else Z1 <= '0'; Z2 <= '1'; Nextstate <= 2; end if;
when 2 =>
if X = '0' then Z1 <= '0'; Z2 <= '1'; Nextstate <= 2;
else Z1 <= '0'; Z2 <= '1'; Nextstate <= 3; end if;
when 3 =>
if X = '0' then Z1 <= '0'; Z2 <= '0'; Nextstate <= 0;
else Z1 <= '1'; Z2 <= '0'; Nextstate <= 1; end if;
end case;
end process;
process(CLK) --State Register
begin
if CLK'event and CLK = '1' then --rising edge of clock
State <= Nextstate;
end if;
end process;
end Table;
(a) Draw a block diagram of the circuit implemented by this code.
(b) Write the state table that is implemented by this code.
2.40 (a) Write a behavioral VHDL description of the state machine you designed in Problem 1.13.
Assume that state changes occur on the falling edge of the clock pulse. Instead of using if-then-else state-
ments, represent the state table and output table by arrays. Compile and simulate your code using the fol-
lowing test sequence:
X 5 1101 1110 1111
X should change 1/4 clock period after the rising edge of the clock.
(b) Write a data flow VHDL description using the next state and output equations to describe the state machine.
Indicate on your simulation output at which times S and V are to be read.
(c) Write a structural model of the state machine in VHDL that contains the interconnection of the gates and
D flip-flops.
2.41 (a) Write a behavioral VHDL description of the state machine that you designed in Problem 1.14. Assume that
state changes occur on the falling edge of the clock pulse. Use a case statement together with if-then-else
statements to represent the state table. Compile and simulate your code using the following test sequence:
X 5 1011 0111 1000
X should change 1/4 clock period after the falling edge of the clock.
124 Chapter 2 Introduction to VHDL

(b) Write a data flow VHDL description using the next state and output equations to describe the state machine.
Indicate on your simulation output at which times D and B should be read.
(c) Write a structural model of the state machine in VHDL that contains the interconnection of the gates and
J-K flip-flops.
2.42 A Moore sequential machine with two inputs (X1 and X2) and one output (Z) has the following state table:

next state
present
state X1X2 5 00 01 10 11 output (Z)
1 1 2 2 2 0
2 2 1 2 1 1

Write VHDL code that describes the machine at the behavioral level. Assume that state changes occur 10 ns after
the falling edge of the clock, and output changes occur 10 ns after the state changes.
2.43 Write VHDL code to implement the following state table. Use two processes. State changes should occur on the
falling edge of the clock. Implement the Z1 and Z2 outputs using concurrent conditional statements. Assume
that the combinational part of the sequential circuit has a propagation delay of 10 ns, and the propagation delay
between the rising-edge of the clock and the state register output is 5 ns.

next state
present
state X1X2 5 00 01 11 output (Z1Z2)
1 3 2 1 00
2 2 1 3 10
3 1 2 3 01

2.44 In the following code, state and nextstate are integers with a range of 0 to 2.

process(state, X)
begin
case state is
when 0 => if X = '1' then nextstate <= 1;
when 1 => if X = '0' then nextstate <= 2;
when 2 => if X = '1' then nextstate <= 0;
end case;
end process;

(a) Explain why a latch would be created when the code is synthesized.
(b) What signal would appear at the latch output?
(c) Make changes in the code which would eliminate the latch.
2.45 For the process given below, A, B, C, and D are all integers that have a value of 0 at time 5 10 ns. If E changes
from '0' to '1' at time 20 ns, specify all resulting changes. Indicate the time at which each change will occur, the
signal/variable affected and the value to which it will change.

process
variable F: integer:=1; variable A: integer:=0;
 Problems 125

begin
wait on E;
A := 1;
F := A + 5;
B <= F + 1 after 5 ns;
C <= B + 2 after 10 ns;
D <= C + 5 after 15 ns;
A := A + 5;
end process;
2.46 What is wrong with the following model of a 4-to-1 MUX? (It is not a syntax error.)
architecture mux_behavioral of 4to1mux is
signal sel: integer range 0 to 3;
begin
process(A, B, I0, I1, I2, I3)
begin
sel <= 0;
if A = '1' then sel <= sel + 1; end if;
if B = '1' then sel <= sel + 2; end if;
case sel is
when 0 => F <= I0;
when 1 => F <= I1;
when 2 => F <= I2;
when 3 => F <= I3;
end case;
end process;
end mux_behavioral;

2.47 When the following VHDL code is simulated, A is changed to '1' at time 5 ns. Make a table that shows all changes
in A, B, and D and the times at which they occur through time 5 40 ns.

entity Q1F00 is
port(A: inout bit);
end Q1F00;

architecture Q1F00 of Q1F00 is

signal B, D: bit;
begin
D <= A xor B after 10 ns;
process(D)
variable C: bit;
begin
C := not D;
if C = '1' then
A <= not A after 15 ns;
end if;
B <= D;
end process;
end Q1F00;
126 Chapter 2 Introduction to VHDL

2.48 What device does the following VHDL code represent?

process(CLK, RST)
variable Qtmp: bit;
begin
if RST '1' then Qtmp := '0';
elsif CLK'event and CLK = '1' then
if T = '1' then
Qtmp := not Qtmp;
end if;
end if;
Q <= Qtmp;
end process;
2.49 (a) Write a VHDL module for a LUT with four inputs and three outputs. The 3-bit output should be a binary
number equal to the number of 1’s in the LUT input.
(b) Write a VHDL module for a circuit that counts the number of 1’s in a 12-bit number. Use three of the mod-
ules from (a) along with overloaded addition operators.
(c) Simulate your code and test if for the following data inputs:
111111111111, 010110101101, 100001011100
2.50 Implement a 3-to-8 decoder using a LUT. Give the LUT truth table and write the VHDL code. The inputs should
be A, B, and C, and the output should be an 8-bit unsigned vector.
2.51 A(1 to 20) is an array of 20 integers. Write VHDL code that finds the largest integer in the array.
(a) Using a for loop
(b) Using a while loop
2.52 Write VHDL code to test a Mealy sequential circuit with one input (X) and one output (Z). The code should
include the Mealy circuit as a component. Assume the Mealy circuit changes state on the rising edge of CLK.
Your test code should generate a clock with 100 ns period. The code should apply the following test sequence:

X 5 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0

X should change 10 ns after the rising edge of CLK. Your test code should read Z at an appropriate time and
verify that the following output sequence was generated:

Z 5 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0

Report an error if the output sequence from the Mealy circuit is incorrect; otherwise, report “sequence correct.”
Complete the following architecture for the tester:

architecture test1 of tester is

component Mealy
-- sequential circuit to be tested; assume this component
-- is available in your design; do NOT write code for the
-- component
port(X, CLK: in bit; Z: out bit);
end component;
signal XA: bit_vector(0 to 11) := "011011011100";
signal ZA: bit_vector(0 to 11) := "100110110110";
 Problems 127

2.53 Write a VHDL test bench that will test the VHDL code for the sequential circuit of Figure 2-58. Your test bench
should generate all ten possible input sequences (0000, 1000, 0100, 1100, …) and verify that the output sequences
are correct. Remember that the components have a 10 ns delay. The input should be changed 1/4 of a clock period
after the rising edge of the clock, and the output should be read at the appropriate time. Report “Pass” if all
sequences are correct; otherwise, report “Fail.”
2.54 Write a test bench to test the counter of Problem 2.37. The test bench should generate a clock with a 100 ns period.
The counter should be loaded on the first clock; then it should count for five clocks. Then it should do nothing
for two clocks and continue counting for ten clocks. The test bench port should output the current time (in time
units, not the count) whenever S5 5 '1'. Use only concurrent statements in your test bench.
2.55 Complete the following VHDL code to implement a test bench for the sequential circuit SMQ1. Assume that the
VHDL code for the SMQ1 sequential circuit module is already available. Use a clock with a 50 ns half period.
Your test bench should test the circuit for the input sequence X 5 1, 0, 0, 1, 1. Assume that the correct output
sequence for this input sequence is 1, 1, 0, 1, 0. Use a single concurrent statement to generate the X sequence. The
test bench should read the values of output Z at the proper times and compare them with the correct values of
Z. The correct answer is stored as a bit-vector constant:

answer 1 1 to 5 2 5 ''11010'';

The port signal correct should be set to TRUE if the answer is correct; otherwise, it should be set to FALSE.
Make sure that you read Z at the correct time. Use wait statements in your test bench.

entity testSMQ1 is
port(correct: out Boolean);
end testSMQ1;
architecture testSM of test SMQ1 is
component SMQ1 -- the sequential circuit module
port(X, CLK: in bit; Z: out bit);
end component;
constant answer: bit_vector(1 to 5) := "11010";
begin
2.56 Change the code in Figure 2-74 so that if a hex number greater than 9 (eg: hex C) is fed to this counter; it will
parallel load it but convert it to the correct BCD value (i.e., decimal 12). However, it stores only the lower BCD
digit, that is, 2.
2.57 Use constant declaration to correct the error in the code in Figure 2-76.