AN-B039

Chrontel Application Notes

PCB Layout and Design Guide for CH7053A

1.0 INTRODUCTION
Chrontel CH7053A is specifically designed for consumer electronics device and PC markets for which multiple
high definition content display formats are required. With its advanced video encoder and easy-to-configure audio
interface, the CH7053A satisfies manufactures’ products display requirements and reduces their cost of development
and time-to-market.

This application note focuses only on the basic PCB layout and design guidelines for CH7053A
HDTV/VGA/HDMI/DVI encoder. Guidelines in component placement, power supply decoupling, grounding, input
/output signal interface are discussed in this document.

The discussion and figures that follow reflect and describe connections based on the 88-pin QFN package of the
CH7053A. Please refer to the CH7053A datasheet for the details of the pin assignments.

2.0 COMPONENT PLACEMENT AND DESIGN CONSIDERATIONS

Components associated with the CH7053A should be placed as close as possible to the respective pins. The
following discussion will describe guidelines on how to connect critical pins, as well as describe the guidelines for
the placement and layout of components associated with these pins.
2.1 Power Supply Decoupling
The optimum power supply decoupling is accomplished by placing a 0.1μF ceramic capacitor to each of the power
supply pins as shown in Figure 1. These capacitors (C1, C2, C4, C5, C7, C8, C10, C11, C13, C14, C16, C18, C19,
C22) should be connected as close as possible to their respective power and ground pins using short and wide traces
to minimize lead inductance. Whenever possible, a physical connecting trace should connect the ground pins of the
decoupling capacitors to the CH7053A ground pins, in addition to ground vias.
2.1.1 Ground Pins
The analog and digital grounds of the CH7053A should be connected to a common ground plane to provide a low
impedance return path for the supply currents. Whenever possible, each of the CH7053A ground pins should be
connected to its respective decoupling capacitor ground lead directly, then connected to the ground plane through a
ground via. Short and wide traces should be used to minimize the lead inductance. Refer to Table 1 for the Ground
pins assignment.
2.1.2 Power Supply Pins
The power supply include AVDD, AVDD_DAC, VDDH, AVDD_PLL, VDDIO, DVDD. Refer toTable1 for the
Power supply pins assignment. Refer to Figure 1 for Power Supply Decoupling.

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Table 1: Power Supply Pins Assignment of the CH7053A

Pin Assignment #Of Pins Type Symbol Description

30,41 2 Power VDDH DVI Power Supply (3.3V)
10,42 2 Power DVDD Digital Power Supply (1.8V)
9,23,46,53,60,61 6 Power AVDD Analog Power Supply (3.3V)
73, 77 2 Power AVDD_DAC DAC power supply (3.3V)
71 1 Power AVDD_PLL PLL Power Supply (1.8V)
33,38 2 Ground VSSH DVI Ground
83 1 Power VDDIO IO Power Supply (1.2-3.3V)
45 1 Ground DGND Digital Ground
11,22,47,52,59,62 6 Ground AGND Analog Ground
75, 79 2 Ground AGND_DAC DAC Ground
70 1 Ground AGND_PLL PLL Ground
89 1 Ground Thermal Pad Ground

VCC3_3
U1 VCC3_3
47R 100MHz 47R 100MHz
L1 L4
1 2 VDDH 30,41 9,23,46,53,60,61 AVDD 1 2
C1 VDDH AVDD C10
C2 C3 C4 C5 C6 C7 C8 C9
10uF 0.1uF 0.1uF 33,38 11,22,47,52,59,62
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF
VSSH AGND
VCC1_8
47R 100MHz 47R 100MHz
L2 L5
1 2 AVDD_DAC
C11
73,77
AVDD_DAC QFN DVDD
10,42
C16
DVDD 1 2

C12 C13 C14 C15

10uF 0.1uF 0.1uF 75,79 45 0.1uF 0.1uF 10uF
AGND_DAC DGND
47R 100MHz 47R 100MHz
L3 L6
1 2 VDDIO 83 71 AVDD_PLL1 2
C17 VDDIO AVDD_PLL C21
C18 C19 C20
10uF 0.1uF 62 70 0.1uF 0.1uF 10uF
AGND AGND_PLL

89
Thermal Pad

Figure 1: Power Supply Decoupling and Distribution

Note:
1. All the Ferrite Beads described in this document are recommended to have an impedance of less than 0.05 Ω at
DC; 23 Ω at 25MHz & 47 Ω at 100MHz. Please refer to Fair Rite part #2743019447 for details or an equivalent
part can be used for the diagram. .

2.1.3 On chip power-on reset function’s sequence

There are two methods for chip power-on reset.

1. The ResetB signal can be generated by on board Resistor and Capacitor delay which can be refer to Figure 2. For
hard ware circuit, please refer to 2.3 RESETB.

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CHRONTEL AN-B039

AVDD
<9ms

Other
Powers

ResetB

Figure 2: Power-on Reset Function’s Sequence on board

2. ResetB signal is generate by system global reset. In this case, the power supply should be valid and stable for at
least 20ms before the reset signal is valid. The pulse width of valid reset signal should be at least 100us. Otherwise,
the chip can’t work well. The timing is shown in Figure 3.

AVDD
>20ms

Other
Powers
>100
us

ResetB

Figure 3: Power-on Reset Function’s Sequence external global reset

Note:
1. The rising threshold of RESTB is 2.4V.
2. The falling threshold of RESTB is 0.4V.

2.2 Internal Reference Pins

• ISET pin

This pin sets the DAC current. A 1.2K ohm, 1% tolerance resistor should be connected between this pin and
AGND_DAC as shown in Figure 4. This resistor should be placed with short and wide traces as near as possible to
CH7053A.
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CHRONTEL AN-B039

U1
80
ISET

QFN R1
1.2K(1%)

79
AGND_DAC

Figure 4: ISET pin connection

2.3 General Control Pins

• RESETB

This pin is the chip reset pin for CH7053A, which is internally pulled-up, places the device in the power on reset
condition when this pin is low. A power reset switch can be placed on the RESETB pin on the PCB as a hardware
reset for CH7053A or connect to the system’s global reset as shown in Figure 5. When the pin is high, the reset
function can also be controlled through the serial port.

AVDD

U1
R1 SW1
1M
7 ResetB
RESETB
P8058SS-ND
C1
0.1uF

On board reset
AVDD

U2
R2
1M
7 ResetB Global Reset
RESETB

C2
0.1uF

Global reset

Figure 5: RESETB pin connection

• XI/FIN and XO

CH7053A have capability to accept external crystal with frequencies from 2.3 MHz to 64 MHz. However, we
recommend predefined crystal frequency is 27MHz. The crystal must be placed as close as possible to the XI and
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XO/FIN pins, with traces connected from point to point, overlaying the ground plane. Since the crystal generates
timing reference for the CH7053A it is very important that noise should not couple into these input pins. Traces with
fast edge rates should not be routed under or adjacent these pins. In addition, the ground reference of the external
capacitors connected to the crystal pins must be connected very close to the CH7053A.

The crystal load capacitance, CL, is usually specified in the crystal spec from the vendor. As an example to show the
load capacitors Figure 6 gives a reference design for crystal circuit design.

U1 X1
4 3
GND P2
1 2
68 XI/FIN P1 GND
XI/FIN 535-9118-1-ND (27 MHz)

QFN
1

1
C1 C2
67 XO 18pF 18pF
XO

2
Figure 6: Crystal Pins

• Reference Crystal Oscillator

CH7053A integrate an oscillator circuit that allows a predefined-frequency crystal to be connected directly.
Alternatively, an externally generated clock source may be supplied to CH7053A. If an external clock source is used,
it should be of CMOS level specifications. The clock should be connected to the XI pin, and the XO pin should be left
open. The external source must exhibit ±20ppm or better frequency accuracy, and have low jitter characteristics.

If a crystal is used, the designer should ensure that the following conditions are met:

The crystal is specified to be predefined-frequency, ±20 ppm fundamental type and in parallel resonance (NOT series
resonance). The crystal should also have a load capacitance equal to its specified value (CL).

External load capacitors have their ground connection very close to CH7053A (Cext).

To be able to tune, a variable capacitor may be connected from XI to ground.

Note that the XI and XO pins each has approximately 10 PF (Cint) of shunt capacitance internal to the device. To
calculate the proper external load capacitance to be added to the XI and XO pins, the following calculation should be
used:

Cext = (2 x CL) - Cint - 2CS

Where
Cext = external load capacitance required on XI and XO pins.

CL = crystal load capacitance specified by crystal manufacturer.

Cint = capacitance internal to CH7053A (approximately 10-15 pF on each of XI and XO pins).

CS = stray capacitance of the circuit (i.e. routing capacitance on the PCB, associated capacitance of crystal holder
from pin to pin etc.).

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In general,
CintXI = CintXO = Cint
CextXI = CextXO = Cext

Such that
CL = (Cint + Cext) / 2 + CS and Cext = 2 (CL - CS) - Cint=2CL - (2CS + Cint)

Therefore CL must be specified greater than Cint /2 + CS in order to select Cext properly.

After CL (crystal load capacitance) is properly selected, care should be taken to make sure the crystal is not operating
in an excessive drive level specified by the crystal manufacturer. Otherwise, the crystal will age quickly and that in
turn will affect the operating frequency of the crystal.

For detail considerations of crystal oscillator design, please refer to AN-06.

2.4 Serial Port Control for CH7053A

• SPC and SPD

SPD and SPC function as a serial interface where SPD is bi-directional data and SPC is an input only serial clock. In
the reference design, SPD and SPC pins are pulled up to +1.8V ~ +3.3Vwith 6.8 kΩ resistors as shown in Figure 7.

VCC3_3
2

R30 R31
6.8K 6.8K
1

54

QFN
SPC
55
SPD

Figure 7: Serial Port Interface: SPC, SPD pins of CH7053A

2.5 Input Pins

Data Inputs

CH7053A can accept up to 24 data inputs, as shown in Figure 8, from a digital video port of a graphics controller.
The swing is defined by VDDIO (1.2 ~ 3.3V).
Unused Data input pins should be pulled low with 10kΩ resistors or shorted to Ground directly.

H/V Sync Pins

The horizontal/vertical sync pins can be used as inputs as shown in Figure 8.

DE/CSB

The DE/CSB pin is used as a data input indicator (Refer to Figure8). When the pin is high, the input data is active.
When the pin is low, the input data is blanking.
If DE/CSB is not used, it can be left open or pulled down to the Ground.

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GCLK

The GCLK input is the clock signal input to the device for using with the H, V, DE and D [23:0] data.

82
GCLK
29
28 D[0]
27 D[1]
26 D[2]
25 D[3]
21 D[4]
20 D[5]
19 D[6]
18 D[7]
D[8]
Graphics 17
QFN
16 D[9]
15 D[10]
D[11]
Controller 14
13 D[12]
12 D[13]
8 D[14]
6 D[15]
5 D[16]
4 D[17]
3 D[18]
2 D[19]
1 D[20]
88 D[21]
87 D[22]
D[23]
86
85 H/WEB
84 V
DE/CSB

Figure 8: CH7053A Data Input Pins

2.6 SPDIF Interface

SPDIF (pin 56) is an SPDIF audio input pin.

The SPDIF signal to CH7053A is required to be VL<0.4V and VH>2.4V. SPDIF signal has two input ways for
CH7053A. SPDIF signal from audio codec is 0-2.5V, then it can be connected to the CH7053A directly; if through a
RCA connector, the signal on RCA connector is AC coupled signal, signal level of which is 0.5V to 1V. Therefore,
voltage level shifting is strongly recommended. If the current SPDIF circuit is considered too complicated, a simple
circuit can be used (Refer to Figure 9).

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CHRONTEL AN-B039

Audio codec is 0-2.5V

J4
H2

H1 1 SPDIF
2

SPDIF IN

AC coupled signal,simple circuit

J2
H2

C1
H1 1 SPDIF
2

1uF
SPDIF IN

AC coupled signal,strongly recommended circuit

R3 VCC2_5/3_3

10K
U1A U1B R5
14

14
J3 330
H2

C2 R2
H1 1 1 2 3 4 SPDIF
7

100 7
2

R1 0.1uF R4
SPDIF IN 75 74HCU04/SO_0 74HCU04/SO_0
10K

Figure 9: SPDIF pin of CH7053A

2.7 I2S Interface

I2S audio input can be configured through programming CH7053A registers. An I2S bus design consists of three
serial bus lines: a line with data channel [SD], a word select line [WS], and a clock line [SCK]. Data is transmitted
two's complement, MSB first.

U1

56
I2S_D/SPDIF
57
I2S_WS
58
I2S Source
I2S_CK

Figure 10: CH7053A I2S Input Pins

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2.8 DVI/HDMI Outputs

The TLC, TLC*, TDC [2:0], TDC [2:0]* signals are high frequency differential signals that need to be routed with
special precautions. Since those signals are differential, they must be routed in pairs.

2.8.1 Differential Pair Impedance

To match the external cable impedance and maintain the maximal energy efficiency it is important to meet the
impedance target of 100 Ω ± 10% for the differential data/clock traces. The restriction of this impedance target is to
prevent any loss of signal strengths resulting from a reflection of unwanted signals. The impedance can be acquired
by proper design of trace length, trace width, signal layer thickness, board dielectric, etc. The DVI/HDMI differential
pairs should be routed on the top layer directly to the DVI/HDMI connector pads if possible.

2.8.2 Trace Routing Length

To prevent from capacitive and impedance loading, trace lengths should be kept as minimal as possible. Vias and
bends should always be minimized; inductive effects may be introduced, causing spikes in the signals. Trace routing
lengths from CH7053A to the HDMI/DVI connector are limited to a maximum of 2 inches. The CH7053A should be
as close to the HDMI/DVI connector as possible.

2.8.3 Length Matching for Differential Pairs

The HDMI/DVI specifies the intra-pair skew and the inter-pair skew as in Table 2. The intra-pair skew is the
maximum allowable time difference on both low-to-high and high-to-low transitions between the true and
complement signals. The inter-pair skew is the maximum allowable time difference on both low-to-high and high-to-
low transitions between any two single-ended data signals that do not constitute a differential pair.

Table 2: Maximum Skews for the HDMI/DVI Transmitter

Skew Type Maximum at Transmitter

Intra-Pair Skew 0.15 Tbit
Inter-Pair Skew 0.20 TPixel

Where Tbit is defined as the reciprocal of Data Transfer Rate and TPixel is defined as the reciprocal of Clock Rate.
Therefore, TPixel is 10 times Tbit. In other words, the intra-pair length matching is much more stringent than the inter-
pair length matching.

It is recommended that length matching of both signals of a differential pair be within 5 mils. Length matching should
occur on a segment by segment basis. Segments might include the path between vias, resistor pads, capacitor pads, a
pin, an edge-finger pad, or any combinations of them, etc. Length matching from one pair to any other should be
within 100 mils.

Note that lengths should only be counted to the pins or pad edge. Additional etch within the edge-finger pad, for
instance, is electrically considered part of the pad itself.

2.8.4 ESD Protection for HDMI/DVI Interface

In order to minimize the hazard of ESD, a set of protection diodes are highly recommended for each DVI/HDMI
Output (data and clock).

International standard EN 55024:1998 establishes 4kV as the common immunity requirement for contact discharges
in electronic systems. 8kV is also established as the common immunity requirement for air discharges in electronic
systems. International standard EN 61000-4-2:1995 / IEC 1000-4-2:1995 establishes the immunity testing and
measurement techniques.

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CHRONTEL AN-B039
System level ESD testing to International standard EN 61000-4-2:1995 / IEC 1000-4-2:1995 has confirmed that the
proper implementation of Chrontel's recommended diode protection circuitry, using SEMTECH Rclamp0524P diode
array devices, will protect the CH7053A device from DVI/HDMI panel discharges of greater than 8kV (contact) and
16kV (air). The RClamp0524P have a typical capacitance of only 0.30pF between I/O pins. This low capacitance
won’t bring too much bad effect on DVI/HDMI eye diagram test.

Figure11(A) and (B) show the connection of DVI/HDMI connectors, including the recommended design of
SEMTECH Rclamp0524P diode array devices. DVI/HDMI connector is used to connect the CH7053A DVI/HDMI
outputs to the display panels.

TLC*

C1 R1
68

TLC 0.5PF

TDC0*

C2 R2
68

TDC0 0.5PF

TDC1*

U1
C3 R3
31 68
TLC*
32 TDC1 0.5PF
TLC
34 TDC2*
TDC0*

QFN TDC0
35

36
C4 R4
68
TDC1*
37 TDC2 0.5PF
TDC1
39
TDC2*
40
TDC2

81 IRQ
IRQ
51 HPD
HPD

Figure 11(A): The connection of the DVI/HDMI outputs

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CHRONTEL AN-B039
TDC2 1 2
TMDA Data2+ TMDA Data2 Shield
TDC2* 3 4 TDC1
TMDA Data2- TMDA Data1+
5 6 TDC1*
TMDA Data1 Shield TMDA Data1-
TDC0 7 8
TMDA Data0+ TMDA Data0 Shield
TDC0* 9 10 TLC
TMDA Data0- TMDA Clock+
11 12 TLC*
TMDA TMDA Clock Shield TMDA Clock-
13 14 VDD5
CEC Reserv ed
15 16
SCL SDA
17 18
DDC/CEC Ground +5V Power
HPD 19 F1 MINISMDC050CT-ND C1 C2
HPDET 0.1uf 10uf

HDMI Conn
R1
47k

TDC2 1 10 TDC2 1 10
TDC0 1 10 TDC0 I/O 1 I/O 8 I/O 1 I/O 8
I/O 1 I/O 8 TDC2* 2 9 TDC2* 2 9
TDC0* 2 9 TDC0* I/O 2 I/O 7 I/O 2 I/O 7
I/O 2 I/O 7 3 8 3 8
3 8 GND GND GND GND
GND GND TLC 4 7 TLC HPD 4 7 HPD
TDC1 4 7 TDC1 I/O 3 I/O 6 I/O 3 I/O 6
I/O 3 I/O 6 TLC* 5 6 TLC* 5 6
TDC1* 5 6 TDC1* I/O 4 I/O 5 I/O 4 I/O 5
I/O 4 I/O 5 RClamp0524P RClamp0524P
RClamp0524P

Figure 11(B): The connection of the HDMI outputs－CH7053A HDMI connectors

The following is the description for each DVI/HDMI interface pins

• DVI/HDMI Link Data Channel (TDC [2:0] and TDC [2:0]*)

These pins provide DVI/HDMI differential outputs for data channel 0 (blue), data channel 1 (green) and data channel 2 (red). It
is recommended that an impedance compensation circuit be added for each differential pair, including DVI/HDMI Clock
outputs (Refer to Figure 11 (A)).

• DVI/HDMI Link Clock Outputs (TLC and TLC*)

These pins provide the DVI/HDMI differential clock outputs for DVI/HDMI corresponding to data on the TDC [2:0] and TDC
[2:0]* outputs (Refer to Figure 11 (A)).

• HPD (DVI/HDMI Hot Plug Detect)

This input pin determines whether the DVI/HDMI link is connected to a DVI/HDMI panel. When the panel is connected, the
HPD will be given a voltage greater than 2.4 volts. Refer to Figure 11 (B) for the design example.

• IRQ

This pin should be connected with graphic controller directly.

2.9 Video Output

 YPbPr and RGB + Csync output

CH7053A support both RGB+Csync and HDTV YPbPr output format. The resolution is from 480P to 720P 1080i and
1080P. In RGB+Csync output format, the Csync high level is the same with AVDD power supply. Csync pin is a
COMS push-pull output pin, customer can use other circuit to change is high level to 0.7V or other voltage level
according to different Receivers. ( Refer to Figure 12)

 VGA output

VGA standard output signal level of Hsync and Vsync is more than 2.4V. CH7053A Hsync and Vsync output signal
level is same with AVDD power supply. Customer can use 74ACT08 (AND GATE) to pull high this signal level to
5V(recommend to add the diode). It is recommended but not necessary. ( Refer to Figure 12)

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AN-B039

CSYNC
1 CSYNC 1
CSYNC CN1

Note: In order to minimize the hazard of ESD, a set of protection diodes (AZ5125-01H) are highly recommended for each
RCA JACK

2
AZ5125-01H
D1
C34 1pF

2
JP6 1 2
1 RED
1 DAC0 2 L11
3 Y
1 2 1
0.33uH
Y/R
1

1
Y_GREEN C35 CN2

Rev1.2,
1

1
C36 100pF
RCA JACK

2
R38 75 27pF

AZ5125-01H
2
2

D2
2
C37 1pF
1 2
JP7

Figure 12: CH7053A YpbPr, RGB+Csync and VGA output

L12
1 Pb
1 DAC1 Pb/G
2 1 2 1

206-1000-039
0.33uH

1
3 GREEN
C39 CN3

1
C38 100pF 27pF
1

RCA JACK

2
AZ5125-01H
2
Pr_RED
R39 75
2

D3
2
C40 1pF
1 2
JP8
L13
1 Pr
1 DAC2 2 1 2 1
0.33uH
Pr/B CN4

1
3 BLUE
C42

1
C41 100pF 27pF RCA JACK
1

2
Pb_BLUE

AZ5125-01H
2
R40 75
2

D4
It is highly recommend to add the diode in power
supply of 74ACT08, it can prevent the back drive

2
from TV or Monitor
U5A
74ACT08
A
1 Y
B 3
1 HSO 2

AZ5125-01H
U5B
74ACT08
A

D5
4 Y
B 6
1 VSO

2
5

AZ5125-01H

17
D6

17
2
L15
L14 6
MONRED
6

2
1
1 11
47R 100MHz 47R 100MHz 11 7

1
MONGREEN
7 2
C43 C44 C45 2 12
10pF 22pF 10pF

AZ5125-01H
12 8

2
MONBLUE
8 3
3 13
L16 150-220R 100MHz MONHSYNC
13

2
9

D7
9 4
L17 L18 L19 150-220R 100MHz MONVSYNC
4

2
14

2
14

2
10
10 5
47R 100MHz 47R 100MHz 5 15

1
15
CHRONTEL

DAC and Sync Output.

C46 C48 C49

1
10pF 22pF 10pF C47 C50

AZ5125-01H

16
2

2
22pF 22pF P1

16
L20 L21 VGA

D8
1 2 1 2

2
47R 100MHz 47R 100MHz

1
C51 C52 C53
10pF 22pF 10pF

AZ5125-01H
2

D9
2

12
CHRONTEL AN-B039

2.10 Thermal Exposed Pad Package

The CH7053A are available in 88-pin QFN package with thermal exposed pad package. The advantage of the thermal
exposed pad package is that the heat can be dissipated through the ground layer of the PCB more efficiently. When
properly implemented, the exposed pad package provides a means of reducing the thermal resistance of the CH7053A.

Careful attention to the design of the PCB layout is required for good thermal performance. For maximum heat
dissipation, the exposed pad of the package should be soldered to the PCB as shown in Figure 14.

Figure 14: Cross-section of exposed pad package

Thermal pad dimension is from 6.6mm to 6.9mm (min to max), 6.6mm x 6.6mm is the minimum size recommended
for the thermal pad, and 6.9mm x 6.9mm is the maximum size. The thermal land pattern should have a 5x5 grid array
of 1.0 mm pitch thermal vias connected to the ground layer of the PCB. These vias should be 0.3mm in diameter with
1 oz copper via barrel plating. Please refer to Figure 15.
6.6 mm

Thermal Via Array

Exposed Pad
(5x5) 1 mm Pitch 6.6 mm
land pattern
0.3 mm diameter

Figure 15: Thermal Land Pattern

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When applying solder paste to the thermal land pattern, the recommended stencil thickness is from 5 to 8 mils. Thermal
resistance was calculated using the thermal simulation program called ANSYS.

2.11 FN Package Assembly

For the assembly process, it is important to limit the amount of solder paste that is put under the thermal pad. If too much paste
is put on the PCB, the package may float during assembly. Compared with the solder mask of thermal pad, the paste mask
should be shrank to70%~80%. Figure 16 shows a paste mask pattern in gray for the thermal pad.

Figure16: Thermal Pad Paste Mask Pattern

14 206-1000-039 Rev1.2, 11/29/2023

 VDDIO voltage should be the same as the input data high voltage

VCC3_3 VCC3_3 AVDD_DAC VCC3_3

VCC3_3 VDDIO AVDD
L2 L7
L1 1 2 AVDD 1 2 AVDD_DAC

2
2
1 2 VDDIO C22 XI/FIN
FB C4 C5 C9 FB
C3 C10 C11 C20 C21 0.1uF D10 SM5817 R15 R16
FB 0.1uF 0.1uF 0.1uF VDD5 VDD5_DDC
C7 C1 C2 0.1uF 0.1uF 0.1uF
0.1uF 0.1uF 10uF 10u XO 6.8K 6.8K
JP3
SPC

1
1
10uF X1 1 SPD
4 3
GND P2 2
3 C29 C30
1 2
P1 GND 4

206-1000-039
VCC1_8 535-9118-1-ND (27 MHz) HEADER 4 10pF 10pF

1
1
L6 C26 C27
1 2 AVDD_PLL VCC5_0

2
2
18pF 18pF
VDD5 VCC3_3 VDD5_DDC
FB L3
L8 1 2 L9
C15 C16
1 2 DVDD 0.1uF 1 2 VDDH
FB
10uF C6 C8 AVDD
FB FB C13 C12 C14 C25
0.1uF C17 C18 C19
0.1uF 0.1uF 0.1uF
C23 C24 10uF 0.1uF 0.1uF
10uF
CHRONTEL

0.1uF 10uF
10uF
R19
1M SW1
Global reset

Rev1.2,
R17 0 ResetB

P8058SS-ND
C31
0.1uF
2.12 Reference Schematic

TLC*
TLC* 4
VCC3_3
C33 R21
68

2
2
R27 R28 DAC0 TLC 0.5PF TLC
DAC0 3 TLC 4

11/29/2023
10K 10K
DAC1

1
1
DAC1 3 TDC0* TDC0*
TDC0* 4
DAC2
DAC2 3 C34
JP2 R23
D16 D17 68
D18 1 2 DGND VSO
3 4 VSO 3 TDC0 TDC0
0.5PF
TDC0 4

D22
D23
H/WEB
V
DE/CSB
VDDIO
GCLK
IRQ
ISET
AGND_DAC
DAC0
AVDD_DAC
DAC1
AGND_DAC
DAC2
AVDD_DAC
AVDD_PLL
AGND_PLL
XI/FIN
XO
D19 5 6 VDD5_DDC
D20 7 8 D21
DE/CSB 9 10 DGND AVDD
AVDD
D7 11 12 D6 TDC1* TDC1*

88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
2
2
D5 13 14 D4 TDC1* 4
15 16 AVDD_DAC

V
D3 D2 R18 R26 AVDD_DAC

XO
D1 17 18 D0 C36

D22
D23
IRQ
R25

ISET
19 20

GCLK
DAC0
DAC1
DAC2
DGND D15 89 66 R24 10K 1.8K 1.8K 68

XI/FIN

VDDIO

H/WEB
21 22 Thermal pad NC HPD

DE/CSB
D14 D13 D21 1 65

1
1
HPD 4

Reserved
Reserved
D12 23 24 D11 D20 2 D21 Reserv ed 64 TDC1

AVDD_PLL
0.5PF

AGND_PLL

AVDD_DAC
AVDD_DAC

AGND_DAC
AGND_DAC
D10 25 26 D9 D19 3 D20 Reserv ed 63 TDC1 4
D8 27 28 DGND D18 4 D19 Reserv ed 62 AGND VDD5_DDC
29 30 5 D18 AGND 61 VDD5_DDC
V H/WEB D17 AVDD
DGND 31 32 GCLK D16 6 D17 AVDD 60 AVDD TDC2* TDC2*
DGND 33 34 SPC ResetB 7 D16 AVDD 59 AGND TDC2* 4
D22 35 36 SPD D15 8 ResetB AGND 58 I2S_CK IRQ
D23 37 38 DGND AVDD 9 D15 I2S_CK 57 I2S_WS IRQ C37 R30
39 40 DVDD 10 AVDD I2S_WS 56 I2S/SPDIF 68
HEADER 20X2 AGND 11 DVDD I2S_D/SPDIF 55 SPD
Reserved interrupt pin
D14 12 AGND SPD 54 SPC TDC2 0.5PF TDC2
D14 SPC TDC2 4
CH7053A
D13 13 53 AVDD
D12 14 D13 AVDD 52 AGND
D11 15 D12 AGND 51 HPD R29 10K
D10 16 D11 HPD 50
D9 17 D10 Reserv ed 49 VSO
D8 18 D9 VSO 48 HSO/CSY NC
D7 19 D8 HSO/CSY NC 47 AGND
D6 20 D7 AGND 46 AVDD
D5 21 D6 AVDD 45 DGND
AGND 22 D5 DGND
AGND

(a) QFN connection

Audio codec is 0-2.5V

AVDD
NC
D4
D3
D2
D1
D0
VDDH
TLC*
TLC
VSSH
TDC0*
TDC0
TDC1*
TDC1
VSSH
TDC2*
TDC2
VDDH
DVDD
Reserved
Reserved

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
CH7053A
J5

H2
JP1
H1 1
Reference Design Example

SPDIF HSO
HSO/CSY NC 1 HSO 3
2 CSY NC

2
3 CSY NC 3

AVDD
D4
D3
D2
D1
D0
VDDH
TLC*
TLC
VSSH
TDC0*
TDC0
TDC1*
TDC1
VSSH
TDC2*
TDC2
VDDH
DVDD
SPDIF IN HEADER 3

AC coupled signal,simple circuit

J4

H2
C65 JP5
H1 1 SPDIF I2S_D R22
I2S/SPDIF 1 AGND_PLL DGND ISET
2 SPDIF

2
1uF 3 1.2K (1%)
SPDIF IN HEADER 3

VSSH

AC coupled signal,strongly recommended circuit

JP4
I2S_D
I2S_WS 1 AGND AGND_DAC
R40 VCC2_5/3_3 I2S_CK 2
3
4
10K HEADER 4
U17C U17B R36

14
14
J6 330

H2
C66 R39 L10
H1 1 5 6 3 4 SPDIF 1 2
I2S is for Audio input
7 7 FB

2
100
R37 0.1uF R38
SPDIF IN 75 74HCU04/SO_10 74HCU04/SO_10
10K
contact Chrontel Applications group if necessary. Table 3 provides the BOM list for the reference schematic.
AN-B039

15
The figures below are the reference schematic of CH7053A, which is provided here for design reference only. Please
16
CN1
RCA JACK

CSY NC 1
2 CSY NC

1
CSYNC
2

D3

AZ5125-01H
C38

2
1pF CN2
1 2
JP6 RCA JACK
RED
1 L11
2 DAC0 2 1 2 1
Y
3 0.33uH

1
1

1
1
Y _GREEN C40 Y/R
R31
CHRONTEL

C39 27pF

2
2

D4

2
75 100pF

2
AZ5125-01H
2

C41
1pF
1 2 CN3
RCA JACK
JP7 L12
Pb 1 2 1
1 0.33uH
2 DAC1 2 GREEN 1 Pb/G

1
1

3 C43

1
C42 27pF
2
2

Pr_RED D5

2
R32 100pF

75 AZ5125-01H

2
2

C44
1pF
1 2 CN4
RCA JACK
JP8 L13
Pr 1 2 1
1 0.33uH
1

2 DAC2 2 BLUE
1
1

3 C46 Pr/B

1
C45 27pF
2
2

Pb_BLUE D6
2

R33 100pF

75 AZ5125-01H

2
2

It is highly recommended to use VDD5_DDC, the diode

can prevent the back driver from TV or Monitor

VDD5_DDC
U12
1 14
2 A0 VCC 13
3 B0 A2 12
2 HSO 4 O0 B2 11
5 A1 O2 10
6 B1 A3 9
7 O1 B3 8
GND O3
74ACT08

2 VSO
17

P1

(b) YpbPr, RGB+Csync and VGA output

17

L15 L14 6
1 2 1 2 MONRED 1 6
47R_100MHz 47R_100MHz 11 1

206-1000-039
7 11

1
1
1
1

MONGREEN 2 7
AVDD C47 C48 C49 12 2
D7
AVDD 2 22pF 10pF 8 12

2
2
2

10pF
MONBLUE 3 8
13 3
AZ5125-01H 13
150-220R 100MHz 1 2 L16 MONHSY NC 9
AVDD_DAC 4 9
AVDD_DAC 2 1 MONVSY NC 14 4
2

L18 L19 150-220R 100MHz 2 L17

1 2 1 2 10 14
47R_100MHz 47R_100MHz 5 10
15 5
1
1
1
1

VDD5_DDC 15
VDD5_DDC 2,4 C50 C52 C53
D8
22pF 10pF
2

10pF
2
2
16

C51 C54
AZ5125-01H 22pF 22pF VGA
16

L20 L21

Rev1.2,
1 2 1 2
2

47R_100MHz 47R_100MHz
1
1
1
1

C55 C56 C57

D9
22pF 10pF
2
2
2

10pF

AZ5125-01H
2
AN-B039

11/29/2023
CHRONTEL AN-B039
U6 HDMI TYPE A Connector
U6

1 2
2,4 TDC2 TMDA Data2+ TMDA Data2 Shield
3 4
2,4 TDC2* TMDA Data2- TMDA Data1+ TDC1 2,4
5 6
TMDA Data1 Shield TMDA Data1- TDC1* 2,4
7 8
2,4 TDC0 TMDA Data0+ TMDA Data0 Shield
9 10
2,4 TDC0* TMDA Data0- TMDA Clock+ TLC 2,4
11 12
TMDA TMDA Clock Shield TMDA Clock- TLC* 2,4
13 14
CEC Reserv ed
15 16
VDD5_DDC SCL SDA
VDD5_DDC
17 18
DDC/CEC Ground +5V Power
19 F1 MINISMDC050CT-ND
HPDET VDD5_DDC

HDMI Conn TY PE A

C58 C59
0.1uF 10uF

It is highly recommended to use VDD5_DDC, the diode can prevent the back
driver from TV or Monitor
HPD 2,4

R34
47K

1 10
1 10 1 10 I/O 1 I/O 8
2,4 TDC1 I/O 1 I/O 8 TDC1 2,4 2,4 TDC2 I/O 1 I/O 8 TDC2 2,4 2 9
2 9 2 9 I/O 2 I/O 7
2,4 TDC1* I/O 2 I/O 7 TDC1* 2,4 2,4 TDC2* I/O 2 I/O 7 TDC2* 2,4 3 8
3 8 3 8 GND GND
GND GND GND GND 4 7
4 7 4 7 2,4 HPD I/O 3 I/O 6 HPD 2,4
2,4 TLC I/O 3 I/O 6 TLC 2,4 2,4 TDC0 I/O 3 I/O 6 TDC0 2,4 5 6
5 6 5 6 I/O 4 I/O 5
2,4 TLC* I/O 4 I/O 5 TLC* 2,4 2,4 TDC0* I/O 4 I/O 5 TDC0* 2,4
RClamp0524P
RClamp0524P RClamp0524P

U9 HDMI TYPE C Connector

U9

1 2
TMDS Data2 Shield TMDS Data2+ TDC2 2,4
3 4
2,4 TDC2* TMDS Data2- TMDS Data1 Shield
5 6
2,4 TDC1 TMDS Data1+ TMDS Data1- TDC1* 2,4
7 8
TMDS Data0 Shield TMDS Data0+ TDC0* 2,4
9 10
2,4 TDC0* TMDS Data0- TMDS Clock Shield
11 12
2,4 TLC TMDS Clock+ TMDS Clock- TLC* 2,4
13 14
DDC/CEC Ground CEC
15 16
SCL SDA
17 18
N.C +5V Power
19 F2 MINISMDC050CT-ND VDD5_DDC
HPDET

HDMI Conn TY PE C

C60 C61
0.1uF 10uF

It is highly recommended to use VDD5_DDC, the

diode can prevent the back driver from TV or
HPD 2,4 Monitor
R35
47K

Reserved, please don't solder

(c) HDMI output

206-1000-039 Rev1.2, 11/29/2023 17

CHRONTEL AN-B039

2.13 Reference Board Preliminary BOM

Table 3: CH7053A Reference Design BOM List
Item Quantity Reference Part
1 7 D3, D4, D5, D6, D7, D8, D9 AZ5125-01H
2 1 D10 SM5817
3 21 C1, C2, C4, C5, C8, C9,C10, C11, C12, C14, C16, C18, 0.1uF
C19, C21, C22, C24, C25, C31, C58, C60,C66
4 10 C3, C6, C7, C13, C15, C17, C20,C23,C59,C61 10uF
5 3 C38, C41, C44 1PF
6 8 C29, C30, C47, C49, C50, C53, C55, C57 10pF
7 2 C26, C27 18pF
8 5 C48, C51, C52, C54, C56 22pF
9 3 C39, C42, C45 100pF
10 3 C40, C43, C46 27pF
11 1 C65 1uF
12 4 C33, C34, C36, C37 0.5PF
13 2 F1, F2 MINISMDC050CT-ND
14 2 JP3, JP4 Header 4
15 1 JP2 Header 20x2
16 5 JP1,JP5, JP6, JP7, JP8 Header 3
17 8 L1, L2, L3, L6, L7, L8, L9, L10 FB
18 7 J4, J5, J6, CN1, CN2, CN3, CN4 RCA
19 3 L11, L12, L13 0.33uH
20 6 L14, L15, L18, L19, L20, L21 47 Ω_100M
21 2 L16,L17 150-220R_100M
22 1 P1 VGA
23 2 R15,R16 6.8 k Ω
24 1 R17 0Ω
25 1 R19 1MΩ
26 4 R21, R23, R25, R30, 68 Ω
27 1 R22 1.2 k Ω (1%)
28 6 R24, R27, R28, R29, R38, R40 10 k Ω
29 2 R18, R26 1.8 k Ω
30 1 R36 330 Ω
31 1 R39 100 Ω
32 4 R31,R32,R33,R37 75 Ω
33 2 R34, R35 47k Ω
34 1 SW1 P8058SS-ND
35 1 U2 CH7053A
36 1 1 HDMI connector TYPEA
37 1 U9 HDMI connector TYPEC
38 3 U7, U8, U16 Rclamp0524P
39 1 U12 74ACT08
40 1 U17 74HCU04/SO_10
41 1 X1 535-9118-1-ND (27MHz)

18 206-1000-039 Rev1.2, 11/29/2023

CHRONTEL AN-B039
3.0 REVISION HISTORY
Table 4: Revisions
Rev. # Date Section Description
1.0 09/23/2014 All Initial release
1.1 06/30/2020 2.11 Update QFN Package Assembly
1.2 11/29/2023 2.1.2 Correct the DVDD power pins connection

206-1000-039 Rev1.2, 11/29/2023 19

CHRONTEL AN-B039

Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at any time
without notice to improve and supply the best possible product and is not responsible and does not assume any
liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of
our products and assume no liability for errors contained in this document. The customer should make sure that they
have the most recent data sheet version. Customers should take appropriate action to ensure their use of the products
does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe
upon or assist others to infringe upon such rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT
SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF
Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used
as directed can reasonably expect to result in personal injury or death.

Chrontel
Chrontel International Limited
129 Front Street, 5th floor,
Hamilton, Bermuda HM12
www.chrontel.com
E-mail: [email protected]

2012 Chrontel - All Rights Reserved.

20 206-1000-039 Rev1.2, 11/29/2023