8086 Memory Banks
Dept. of Computer Science and Engineering
BRAC University
CSE 341 Team
Lecture References:
? Book:
? Microprocessors and Interfacing: Programming and Hardware,
Author: Douglas V. Hall
? The 8086/8088 Family: Design, Programming, And Interfacing,
Author: John Uffenbeck.
CSE – 341: Microprocessors
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8086 Memory Organisation
?
CSE – 341: Microprocessors
BRAC University
8086 Memory Organisation
?
CSE – 341: Microprocessors
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8086 Memory Organisation
? Addresses are consecutively numbered
? All even numbers end with a 0 and all
odd numbers end with a 1
Even Odd
6= 110 5= 101
14 = 1110 13 = 1101
20 = 10100 27 = 11011
42 = 101010 35 = 100011
eve od
CSE – 341: Microprocessors n d
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8086 Memory Organisation
? Even addresses are considered as the even/low bank, which
holds the content of the low byte while
? Odd addresses are considered as the odd/high bank, which
holds the content of the high byte
CSE – 341: Microprocessors
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Why EVEN Bank = Low Bank
When 2 byte of data is stored inside the memory.
Low byte is stored in the low bank which has the even
address .
High byte is stored in the High bank which has the odd
address .
CSE – 341: Microprocessors
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A0 : Starting address EVEN → 0
Starting address ODD → 1
BHE’: Odd bank deactivated → 1
Odd bank activated → 0
1 bank can hold 1 byte of data at EACH bus cycle.
CSE – 341: Microprocessors
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8086 Memory Banks
?
The memory for an 8086 is
set up in to 2 banks of up to
524,288 bytes or 512kB each
This makes it possible to
read/write a word with one
machine cycle
CSE – 341: Microprocessors
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8086 Memory Addressing
Data can be accessed from the memory in 4 different ways:
?8 - bit data from Even Bank e.g. from address 00002
?8 - bit data from Odd Bank e.g. from address 00003
?16 - bit data starting from Even Address e.g. from 00002 and 00003
?16 - bit data starting from Odd Address. e.g. from 00003 and 00004
Type of Transfer Data Lines
0 0 Word i.e.
a byte from each bank
0 1 Byte from odd bank
1 0 Byte from even bank
1 1 None -
CSE – 341: Microprocessors
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A byte from Low/Even bank
?
Not accessed Accessed
Type of Transfer Data Lines
1 0 Byte from even bank
Notice the dots (inverse operation)
CSE – 341: Microprocessors
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Explanation
A0 is 0, since the starting address is EVEN.
Since we are working with 8 bit (1 byte) of data
hence we do not need the odd bank. We are
keeping our data in even bank. So BHE’ is set to
1, deactivating the odd bank.
CSE – 341: Microprocessors
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A byte from High/Odd bank
Accessed Not accessed
Type of Transfer Data Lines
0 1 Byte from odd bank
CSE – 341: Microprocessors
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Explanation
A0 is 1, since the starting address is ODD.
We are working with 8 bit (1 byte) of data. We are
keeping our data in odd bank. So BHE’ is set to
0, activating the odd bank. One thing to note,
here the even bank is not used.
CSE – 341: Microprocessors
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An aligned word
starting from an even address
Accessed Accessed
Type of Transfer Data Lines
0 0 Word i.e.
a byte from each bank
CSE – 341: Microprocessors
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Explanation
A0 is 0, since the starting address is EVEN.
We are working with 16 bit (2 byte) of data. We
are keeping our data both in odd and even
banks. So BHE’ is set to 0, activating the odd
bank.
CSE – 341: Microprocessors
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Why A0 = 1 & BHE’ = 1 is NOT a valid option
A0 = 1 means starting address is odd address,
hence it MUST use the odd bank.
But here BHE’ = 1 means we are not using the odd
bank here, i.e it is deactivated.
So there is a CONFLICT. So this combination
impossible.
CSE – 341: Microprocessors
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An unaligned word
starting from an odd address
1 2
CSE – 341: Microprocessors
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An unaligned word
starting from an odd address
2 bus-cycles required
Accessed Not accessed Not accessed Accessed
CSE – 341: Microprocessors
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Points to the note:
1) 8 bit data always require 1 bus cycle
2) 16 bit data sometimes require 1 bus cycle
CSE – 341: Microprocessors
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Aligned vs Unaligned
Unaligned Word → 16 bit (2 bytes) of data is stored at
ODD address. Requires 2 Bus cycles to fetch. Lower
byte is on ODD address, higher byte is on Even
address.
Aligned Word → 16 bit (2 bytes) of data is stored at
EVEN address. Requires 1 Bus cycles to fetch. Lower
byte is on EVEN address, higher byte is on ODD
address.
CSE – 341: Microprocessors
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Practice
Instruction A0 BHE’ No. of Bus Cycle
MOV AH, [1234h] 0 1 1
1 0
MOV [2135h], BX 2
0 1
MOV CX, [4122h] 0 0 1
MOV [4123h] , DL 1 0 1
CSE – 341: Microprocessors
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Worked Example
Address 10600h 10601h 10610h 10611h 20200h 20201h 20202h 20600h 20601h
Data 91h 24h 12h 34h 31h 72h 66h 56h 78h
DS = 2000h SS = 1000h BP = 0409h SI = 0201h
MOV BX, [SI + BP]
Target address = DS*10 + BP + SI = 20160Ah (even address)
A0 = 0 BHE’ = 0 (1 bus cycle)
System : 40 Mhz. Clock Pulse = ns.
Time required for bus cycle = 4 * 200 = 800ns
Time required for one instruction cycle = 800ns
CSE – 341: Microprocessors
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Worked Example
Address 10600h 10601h 10610h 10611h 20200h 20201h 20202h 20600h 20601h
Data 91h 24h 12h 34h 31h 72h 66h 56h 78h
DS = 2000h SS = 1000h BP = 0409h SI = 0201h
MOV BX, [SI]
Target address = DS*10 + SI = 20201h (odd address)
A0 = 1 BHE’ = 0 (1st bus cycle)
A0 = 0 BHE’ = 1 (2nd bus cycle)
Time required for bus cycle = 4 * 200 = 800ns
Time required for one instruction cycle = 800 * 2 = 1600ns
CSE – 341: Microprocessors
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Duty Cycle
Duty Cycle = 25%
Instruction MOV BH, [BP + SI] MOV BX, [SI]
TON for one clock cycle 50ns 50ns
TON for one bus cycle 50 * 4 = 200ns 50 * 4 = 200ns
TON for one instruction 200ns 200 * 2 = 400ns
cycle
CSE – 341: Microprocessors
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Worked Example
Address 10600h 10601h 10610h 10611h 20200h 20201h 20202h 20600h 20601h
Data 91h 24h 12h 34h 31h 72h 66h 56h 78h
DS = 2000h SS = 1000h BP = 0409h SI = 0201h
MOV BH, [BP + SI]
Target address = SS*10 + BP + SI = 0160Ah (even address)
A0 = 0 BHE’ = 1 (1 bus cycle)
System : 5 Mhz. Clock Pulse = 200ns.
Time required for bus cycle = 4 * 200 = 800ns
Time required for one instruction cycle = 800ns
CSE – 341: Microprocessors
BRAC University
Worked Example
Address 10600h 10601h 10610h 10611h 20200h 20201h 20202h 20600h 20601h
Data 91h 24h 12h 34h 31h 72h 66h 56h 78h
DS = 2000h SS = 1000h BP = 0409h SI = 0201h
MOV BL, [SI]
Target address = DS*10 + SI = 20201h (odd address)
A0 = 1 BHE’ = 0 (1 bus cycle)
Time required for bus cycle = 4 * 200 = 800ns
Time required for one instruction cycle = 800ns
CSE – 341: Microprocessors
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Duty Cycle
Duty Cycle = 25%
Instruction MOV BH, [BP + SI] MOV BL, [SI]
TON for one clock cycle 50ns 50ns
TON for one bus cycle 50 * 4 = 200ns 50 * 4 = 200ns
TON for one instruction 200ns 200ns
cycle
CSE – 341: Microprocessors
BRAC University
Worked Example
Address 10600h 10601h 10610h 10611h 20200h 20201h 20202h 20600h 20601h
Data 91h 24h 12h 34h 31h 72h 66h 56h 78h
DS = 2000h SS = 1000h BP = 0409h SI = 0201h
MOV BL, [600h]
Target address = DS*10 + 600h = 20600h (odd address)
A0 = 1 BHE’ = 0 (1 bus cycle)
Time required for bus cycle = 4 * 200 = 800ns
Time required for one instruction cycle = 800ns
CSE – 341: Microprocessors
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MOV BL, [1234h]
MOV BH, [1234h]
A0 and BHE’ =
CSE – 341: Microprocessors
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CSE – 341: Microprocessors
BRAC University
Thank
You
CSE – 341: Microprocessors
BRAC University
