Khulna University of Engineering & Technology B. Sc. Engineering 4th Year 1° Term Examination, 2015 Department of Electrical and Electronic Engineering EE 4121 VLSI Design and Technology Time: 3 hours Full Marks: 210 N.B.: (i) Answer ANY THREE questions from each section in separate scripts a. @ “oO @ % @ (ii) Figures in the right margin indicate full marks section A ‘What are the importances’s of two-phase clocking in VLSI memory design? Describe the principle of the D- flip flop based two-phase clock generator circuit Derive the expression for drain to source current of nMOSFET and hence show that the ceurrent depends on its geometry. Explain the PLA based approach of VLSI design and hence design a three line priority encoder. Draw your design in MOS form, Why are the design rules necessary for VLSI design? Write down the advantages of A= based design rules. Define stick diagram and mask layout. Design an nMOS logic circuit to realize the following function and draw the corresponding stick diagram and mask layout. 2=R+B+O What are pass transistor and transmission gate? Discuss on their importance in VLSI design. ‘What do you mean by C#MOS logic? Construct the diagram of 2-input NOR gate using C2MOS log ‘What factors need to be considered to assess different storage elements? Design a four transistor dynamic memory cell for storing one bit What is RAM? Explain the basic principle of RAM to read from and write to one bit within 2" memory cells using necessary diagrams. What is pseudo-static RAM cell? Draw the circuit diagram of nMOS pseudo-static RAM cell and estimate its area and power dissipation considering 4 = 2.5 um. Define semi custom and full custom design. Briefly explain the top down hierarchy of full custom VLSI system design, What do you mean by structured design approach? Design an n-line bus arbitration logic circuit using structured design approach and explain its operation. Draw the block diagram of basic digital microprocessor structure. Also discuss on the communication strategy for data path in the context of VLSI design. Section B Deseribe the evolution of microelectronics. Does Moore's law still hold it true? Justify ‘your answer: ‘Write the major processing steps of bipolar manufacturing technology. Why Silicon is suitable asa substrate? Why (111) plane is suitable for crystal growth? Write down the commonly used techniques of bulk growth with their merits and demerits. eine epitaxy, Why it is important in fabrication of modern.devices? isiefly explain MOVPE and MBE growth process. px What do you mean by photolithography? Draw different types of photolithography ‘exposure system with brief explanation. What are the purposes of metallization in IC fabrication? Briefly explain the metallization process Page 1 of 2 (19) ey) 2) (08) (13) 07) on (ao) 3) a2 (12) 3) (10) (08) (08) (06) (as) on (10) (08) (10)7 a @ 8. (a) b) i} What do you mean by selfaligned gate? What are the differences between my and silicon gate? 8 and What is mean by lat jscuss on the latch-up susceptibility: of ives. Explain the silicon gat nMOS fabrication process with necessary diagram. ‘What do you mean by oxide-isolation and silicon-on-sapphire CMOS processes? What are the effects of sub-mieron down scaling of Si devices? Why GaAs is suitable (09) for faster system? Explain using energy band concept. Compare different features of CMOS, bipolar and GaAs technologies. (09) Briefly explain the self-aligned processing steps for Gas E-/D-MESFET. a7 , ! Page 2 of 2ot Khulna University of Engineering & Technology M. Sc. Engineering Examination, 2017 (July Semester) Department of Electrical and Electronic Engineering EE 6801 Digital Circuit Design Time: 4 hours Full Marks: 210 NB: (i) Answer ANY SIX questions, ii) Figures in the right margin indicate full marks. : Ql. (@ What do you mean by di computer. (b) Define and explain PUN and PDN. Either NAND gates or NOR gates can be used for (I) implementing Boolean functions. Discuss which one of the two is better regarding the ital circuit? Draw and explain the block diagram of a digital (10) area to be implemented in complementary CMOS logic, explain in a few sentences 4 # with the schematiC diagram, (©) Write doysrthe logic equation and logic diagram for the following Gates & (10) i Aol AD 2 <= 2, (i) OallI2. = pet | ‘ (i). AON) = (iv) AON(12) = aM 0: TED a wt. iv a yar 1m (6) Whats the intended fonction OMe Ufeut shown below? What isthe output voltage (04) range for this circuit? q y ~ XN @2. CMOS Leaf Cell Design: For the CMOS logic gate Y=A¥B.CD, do the following: (35) Draw the logic diagram draw the transistor-level schematic size the transistors to have the same resistance as a unit inverter find the Euler path for both the p and n-MOS networks Xd 2 a draw the stick diagram layout using the standard colour estimate the total area in units of 4? and for 180-nm technology estimate the gate and diffusion capacitances for the gate, Label them om your layout Page | of 4@. (@) Consider the following stick diagram. Draw electrically equivalent trans storey schematic, What logic equation does the circuit implement? Draw the logie diagrens = (b) Draw the Elmore RC model diagram. Write down the delay equation for the Elmore (10) RC model. (c) Inyour answers to this question you may assume: (15) ‘All delays are in units of ¢ An inverter gate has g=1, p ‘A nsinput NAND gate has g = (n+ 2)/3, p =n A neinput NOR gaté has = 2n + 1)/3, p A n-input MUX gate has g = 3, p = 3 ‘A 2-input XOR ot XNOR gate has ‘© A 3-input XOR or XNOR gate has g Use the principle of logical effort to estimate the delay along the path from input A to output OUT in the figure below. our e.. ‘What is PLD? Classify PLD. Write short notes on PAL and GAL. (08) /(b) What is OPALjr? How to write a program in OPLAje? The GALI6VS is a popular (06) PLD. What do the “16” and “8” in GAL16V8 respectively mean? (©) What are the basic differences between combinational and sequential circuits? Design (10) a four bits bidirectional shift register. (@) Design a Mod-S synchronous counter using D flip-flops. Draw the logic circuit and (11) write the equations for Q2.Q, QID and Q0.D. How you can add hold, enable and reset signals in Mod-5 synchronous counter design?” Page 2 of 4Khulna University of Engineering & Technology M. Sc. Engineering Examination, 2019 (July Semester) Department of Electrical and Electronic Engineering EE 6801 Digital Circuit Design Time: 4hours Full Marks: 210 NB. () Answer ANY SIX questions. . . (ii) Figures in the right margin indicate full marks. Se ee digital circuit in ou real life? Explain abasic digital (15) computer system with necessary block diagram. (06+05) (©) Define and explain PUN and PDN. Either NAND gates or NOR gates can be used for (15) implementing Boolean functions. Discuss which one ofthe two is better regarding the (0408-403) area to be implemented in complementary CMOS logic explain in a few sentences withthe schematic diagram, Als, write down the practical significances of Euler path ben for designing the stick diagram layout. (6) Weite dovn the logic equation for the following gates: © () OABI, (i) AOII2, (ii) AON (12), (iv) AOTI(13)), and (¥) OAT (xt) af CMOS Leaf Cell Design: For the CMOS logic gate F= T+D), do the (35) following (draw the transistor level schematic (05) (i) size the transistors to have the same resistance as a unit inverter (04) (Gi) find the Buler path for both the p and n-MOS networks (02) ~ (Gs) draw the stick cliagram layout using the standard colour (08) c (¥) estimate the total area in units of 1? and for 90.nm technology (06) (vi) estimate the gate and difusion capacitances forthe above gate. Label them ) cn your layout (10) i @3. a} Explain the Elmore RC model diagram with necessary diagrams and also write down (10) i the delay equation forthe Elmore RC model. (#5) { (©) In your answers to this question you may assume: All delays are in units of an (15) inverter gate has g=1, p= 1s A n-input NAND gate has g = (n-+2)3, p = mA ne put NOR gate has ¢™ Qn + 1Y3,p = nA minput MUX ghte has apt XOR o¢ XNOR gas hag =, p= A apt NOR oF XNOR gates = Use the principe of logical effort to estimate the delay slong te pth from input A fo ‘output OUT in the figure below. ee : ipo Fig. Q3(b) Page | of 3(by °y @ () © 6. @ @ © Design a four bits bidirectional shift register with necessary diagrams, Describe PLD? How you can distinguish PLD from basic logic gates? Write short notes on PAL, GAL, PLA, CPLD, and FPGA. What is OPALjr? How to write a program in OPALje? Why GALI6V8 is a popular PLD? What do the “16” and “8” in GALI6V8, respectively mean? Design a synchronous counter for 12 hours-based clocks using D flip-flops. Draw the logic circuit and write the equations for Q3.D, Q2.D, QU.D, and Q0.D. Write down a synthesizable VHDL code for a traffic-light controller based on Q4, (a). Write shor notes on AMD and AM2900. Explain how digital printer interface works? Describe microprogramming for designing a digital circuit. Draw the block diagram ‘of Am 2909 micro sequencer. What are the advantages and disadvantages of a data acquisition system? What are the differences between ROM and RAM? Briefly explain on SRAM, EPROM, and Flash Memory with their practical applications. Describe DMA? Distinguish between DMA and No DMA for a CPU operation, Explain different types of DMA. Why we need FPGA-based cesign instead of ASIC-based design for a prototype complex digital circuit? Draw the comparison diagram of different technologies? Write down the design flow of VLSI Give four of the data types used in VHDL with examples. Write down the synthesizable VHDL code for 4x 1 MUX. VEIDL code below is a standard description of working on the rising edge of a clock. Iwiodify the below code so that the flip-flop hasan asytichronous reset input with falling edge clock. process (CLK) begin IFCLKYevent and CLK =‘I’then Q<=D;_ endif, end process; List the three data objects used in VHDL, also give an example for each data object. Write down the VHDL “for generate” statement and why itis important? Complete the comments in the VHDL code below: entity numeric is \ port (A: in std_logie_vector (1 downto 0); B: in Std_logic_vecior (1 downto 0); Cr out std_logic_vector (7 downie 0); Dzout std_logic_vector (1 downto 0); end numeric; initialize A= 10" and B=“10": architecture numeric operation of mumerie is signal B : sid_togie begin rector(i dovento 0) = po000000", downto 0) downs (7 downto 4) CE D< A()KE(O); end numeric_operatio to (08) as) G2H0) (08) (4x2) (1) (10) (10) i) (44645) (a3) (449) (12) (24347) (io) (446) (05) (10) G6) (05) (10) 4) (05) (x1) ie Page 3 of 3 a O‘Time: 4 hours NB. (i Answer ANY SIX question, ee igares in the right margin indiGate full marks. aon: 2 ¢ Goer oe awe a Ante a Describe the oe of the di layout. Either NANOS gates or NOR gates can be used for implementing Boolean functions, Discuss which one of the two is better regarding the area t i Impl CMOS lope exh in etal Wah be nessa dram ‘ements op SMOS-bed design rbot NAND and NO ats pore 4" Khulna University of Engineering & Technology M, Se. Enginesring Examination, 2018 (uly Department of Electrical and Electronic Engineering smester) 801 Digital Cireuit Design Full Marks: 210 Greil in ur real life? Explain abasic digital (10) aay (©) WATEaoW the loge equation and logic diagram forthe following gt 0) Saran an a a Awe bat) FaoeD) i @ “cmos fllowing Da foe Hos tc tate Y= TEACHD), do the G5) VIE ‘AYO: SO. sew Ga igi ea (05) Ci) siete transistors to have the sane resistance a unit inverter (04) Gi) find he Euler path for bath the pandn-MOS networks (02) ab (i) _ dew thes diagram you using the anand olor (8) 22 bin (v) estimate the total area in units of 2? and for 90-nm technology (06) aA = er (i) estimate the gate and diffusion capacitances forthe above gat, Label them 6 your layout (10) B. @ Explain the Elmore RC model diagram with necessary diagrams and also write down (10) the delay equations forthe Elmore RC model © Show the critical path and estimate delay using logical eet fo the folowing circuit 25) as depicted in Fig. Q3b) Ry Rik ane get Fog Gt Pa OS Nia tata te Riferenses + cn) + Re Geter oat D+ % Gre terestetaryy of, t= CR ten. (Ar Alt (Hehehe ¥