MALLA REDDY ENGINEERING COLLEGE (AUTONOMOUS)

II B.Tech I Semester (MR 22) I Mid Question Bank 2023-24 (Objective)

Subject: Digital Electronics (C0403) Branch: ECE

Name of the Faculty: Mrs. NVK Maha Lakshmi & Mrs.L.Sailaja

S.No Questions Ans

MODULE-I
1 Convert the following decimal number to 8-bit binary.187
a) 101110112 b)110111012 c)101111012 d)101111002 A
2 Convert binary 111111110010 to hexadecimal.
a)EE216 b)FF216 c)2FE16 d)FD216 A
3 Convert the binary number 1001.00102 to decimal.
a)90.125 b)9.125 c)125 d)12.5 B
4 Convert 59.7210 to BCD.
a)111011 b)01011001.01110010 c)1110.11 d)0101100101110010 B
5 Convert 8B3F16 to binary.
a)35647 b)011010 c)1011001111100011 d)1000101100111111 D
6 Which is typically the longest: bit, byte, nibble, word?
a)Bit b)Byte c)Nibble D
d)Word
7 If a typical PC uses a 20-bit address code, how much memory can the CPU address?
a)20 MB b)10 MB c)1 MB d)580 MB C
8 Which of the following is the most widely used alphanumeric code for computer input
and output? B
a) Gray b)ASCII c)Parity d)EBCDIC
9 Assign the proper odd parity bit to the code 111001.
a)1111011 b)1111001 c)0111111 d)0011111 B
10 Convert decimal 64 to binary.
a)01010010 b)01000000 c)00110110 d)01001000 B
11 Convert hexadecimal value C1 to binary.
a)11000001 b)1000111 c)111000100 d)111000001 A
12 Convert the following octal number to decimal.
a)51 b)82 c)57 d)15 D
13 Convert the following binary number to octal.
0101111002 D
a)1728 b)2728 c)1748 d)2748
14 The sum of 11101 + 10111 equals ________.
a)110011 b)100001 c)110100 d)100100 C
15 The decimal number 188 is equal to the binary number
a)10111100 b)0111000 c)1100011 d)1111000 A
16 How many bits are in an ASCII character?
a)16 b)10 c)8 d)7 D
17 Convert 11001010001101012 to hexadecimal
a)121035 b)CA35 c)53AC1 d)530121 B
18 Convert the following decimal number to octal.281
a)1348 b)4318 c)3318 d)1338 B
19 When using even parity, where is the parity bit placed?
a) Before the MSB
b) After the LSB A
c) In the parity word
d) After the odd parity bit
20 An analog signal has a range from 0 V to 5 V. What is the total number of analog
possibilities within this range? D
a)100 b)5 c)200 d)Infinite
21 Hexadecimal letters A through F are used for decimal equivalent values from
a)1 through 6 b)9 through 14 c)10 through 15 d)11 through 17 C
22 A decimal 11 in BCD is ________
a)00001011 b)00001100 c)00010001 d)00010010 C
23 What is the resultant binary of the decimal problem 49 + 01 =?
a)01010101 b)00110101 c)00110010 d)00110001 C
24 The difference of 111 – 001 equals ________.
a)100 b)111 c)110 d)101 C
25 Convert the binary number 1100 to Gray code
a)0011 b)1010 c)1100 d)1001 B
26 The binary number 11101011000111010 can be written in hexadecimal as _______
a)DD63A16 b)1D63A16 c)1D33A16 d)1D63116 C
27 Which of the following is an invalid BCD code?
a)0011 b)1101 c)0101 d)1001 B

28 What decimal number does 25 represent?

a)10 b)31 c)64 d)32 D
29 Convert the Gray code 1011 to binary
a)1011 b)1010 c)0100 d)1101 D

30 The 1's complement of 10011101 is ________.

a)01100010 b)10011110 c)01100001 d)01100011 A
31 Convert the decimal number 151.75 to binary.
a)10000111.11 b)11010011.01 c)00111100.00 d)10010111.11 D
32 3428 is the decimal value for which of the following binary-coded decimal (BCD)
groupings? B
a)11010001001000 b)11010000101000 c)011010010000010 d)110100001101010
33 The binary-coded decimal (BCD) system can be used to represent each of the 10
decimal digits as a(n): A
a)4-bit binary code b)8-bit binary code c)16-bit binary code d)None
34 The 2's complement of 11100111 is ________
a)11100110 b)00011001 c)00011000 d)00011010 B
35 Express the decimal number –37 as an 8-bit number in sign-magnitude. A
a)10100101 b)00100101 c)11011000 d)11010001
36 The American Standard Code for Information Interchange (ASCII) uses how many
individual pulses for any given character? C
a)1 b)2 c)7 d)8
37 The weight of the LSB as a binary number is A
a)1 b)2 c)3 d)4
38 The base of the hexadecimal system is C
a)1 b)8 c)6 d)32
39 Assign the proper even parity bit to the code 1100001 A
a)11100001 b)1100001 c)01100001 d)01110101
40 Which of the following is the primary advantage of using the BCD code instead of
straight binary coding?
a) Fewer bits are required to represent a decimal number with the BCD code. B
b) The relative ease of converting to and from decimal.
c) BCD codes are easily converted to hexadecimal codes.
d) BCD codes are easily converted to straight binary codes.
41 What is the decimal value of the hexadecimal number 777? B
a) 191 b)1911 c)19 d)19111
42 Convert the following BCD number to decimal.
010101101001bcd C
a)539 b)2551 c)569 d)1552
43 What is the result when a decimal 5238 is converted to base 16?
a)327.375 b)12.166 c)1388 d)1476 D
44 Digital electronics is based on the ________ numbering system
a)decimal b)Octal c)Binary d)hexadecimal C
45 An informational signal that makes use of binary digits is considered to be
a)solid state b)Digital c)Analog d)non-oscillating B
46 The binary number 101110101111010 can be written in octal as ________ D
a)515628 b)565778 c)656278 d)565728
47 Convert 45710 to hexadecimal D
a)711 b)2C7 c)811 d)1C9
48 Determine the decimal equivalent of the signed binary number 11110100 in 1's
complement. C
a)116 b)–12 c)11 d)128
49 What is the base value in octal code B
a)2 b)8 c)16 d)10
50 What is the base value in decimal code D
a)2 b)8 c)16 d)10
MODULE-II
51 An n variable K-map can have B
a)n2 cells b)2n cells c) nn cells d) n2n cells
52 Each term in the standard SOP form is called a A
a) minterm b) maxterm c)don’t care d)Literal
53 Each term in the standard POS form is called a B
a) minterm b) maxterm c)don’t care d)Literal
54 The binary number designations of the rows and columns of the K-map are in C
a)binary code b)BCD code c)Gray code d)Excess 3 code
55 An 8-square eliminates B
a)2 variables b)3 variables c) 4 variables d)8 variables
56 The terms which cannot be combined further in the tabular method are called
a)Implicants b)prime implicants B
c)essential prime implicants d)selective prime implicants
57 The implicants which will definitely occur in the final expression are called
a)Implicants b)prime implicants B
c)essential prime implicants d)selective prime implicants
58 The number of cells in a 6 variable K-map is D
a) 6 b) 12 c)36 d)64
59 The Quine-McClusky method of minimization of a logic expression is a
(i)Graphical method (ii) Algebraic method (iii) Tabular method (iv) A computer- A
oriented method
a) (iii) and (iv) b) (ii) and (iv) c) (i) and (iii) d) (i) and (ii)
60 In simplification of a Boolean function of n variables, a group of 2m adjacent 1s leads
to a term with
a) m-1 literals less than the total number of variables D
b) m+1 literals less than the total number of variables
c) n+m literals d)n-m literals
61 The number of adjacent cells each cell in an n variable K-map can have is B
a)n-1 b)N c)n+1 d)2n
62 A 16-square eliminates
a)2 variables b)3 variables c) 4 variables d)8 variable B
63 In K-map simplification, a group of four adjacent 1s leads to a term with
a) One literal less than the total number of variables
b) Two literals less than the total number of variables B
c) Three literals less than the total number of variables
d) Four literals less than the total number of variables
64 The NAND-NAND realization is equivalent to
a)AND-NOT realization b)AND-OR realization B
c)OR-AND realization d)NOT-OR realization
65 The NOR-NOR realization is equivalent to
a)AND-OR realization b)NOT-AND realization D
c)OR-NOT realization d)OR-AND realization
66 AND-OR realization of a combinational circuit is equivalent to
a)NAND-NOR realization b)NAND-NAND realization B
c)NOR-NOR realization d)NOR-NAND realization
67 OR- AND realization of a combinational circuit is equivalent to
a)NAND-NOR realization b)NAND-NAND realization D
c)NOR-NOR realization d)NOR-NAND realization
68 A combinational circuit can be designed using only
 a)AND gates b)OR gates c)OR and X-NOR gates d)NOR D
gates
69 A combinational circuit can be designed using only
a)AND gates b)OR gates c)OR and X-NOR gates d)NOR D
gates
70 The NAND gate can function as a NOT gate if
a)All inputs are connected together b)Inputs are left open A
c)One input is set to 0 d)One input is set to 1
71 The NOR gate can function as a NOT gate if
a)All inputs are connected together b)Inputs are left open A
c)One input is set to 0 d)One input is set to 1
72 An Exclusive-NOR gate is logically equivalent to
a)Inverter followed by an X-OR gate b)X-OR gate followed by an inverter B
c)NOT gate followed by an X-OR gate d)Complement of a NOR gate
73 Which of the following is known as a mod-2 adder?
a)X-OR gate b)X-NOR gate c)NAND gate d)NOR A
gate
74 What is the minimum number of two-input NAND gates used to perform the function
of 2-input OR gate? C
a)One b)Two c)Three d )Four
75 NOT gates are to be added to the inputs of which gate to convert it to a NAND gate? A
a)OR b)AND c)NOT d)X-OR
76 NOT gates are to be added to the inputs of which gate to convert it to a NOR gate? B
a)OR b)AND c)NOT d)X-OR
77 What logic function is produced by adding inverters to the inputs of an AND gate? B
a)OR b)AND c )NOT d)X-OR
78 What logic function is produced by adding inverters to the inputs of an OR gate? B
a)NOR b)NAND c)AND d)X-NOR
79 What logic function is produced by adding an inverter to each input and output of an
AND gate? D
a)NOR b)NAND c)AND d)X-NOR
80 What logic function is produced by adding an inverter to each input and output of an
OR gate? C
a)NAND b)NOR c)AND d)X-OR
81 How many NOR gates are required to obtain AND operation? B
a)2 b)3 c)4 d)1
82 What is the minimum number of NAND gates required to realize an X-OR gate? B
a)3 b) 4 c) 5 d) 6
83 What is the minimum number of NOR gates required to realize an X-OR gate? C
a)3 b) 4 c) 5 d) 6
84 A bubbled AND gate is equivalent to C
a)OR gate b)NAND gate c)NOR gate d)X-OR gate
85 A bubbled OR gate is equivalent to B
a)AND gate b)NAND gate c)NOR gate d)X-OR gate
86 A bubbled NAND gate is equivalent to A
a)OR gate b)NAND gate c)NOR gate d)X-OR gate
87 A bubbled NOR gate is equivalent to A
a)AND gate b)NAND gate c)NOR gate d)X-OR gate
88 The output of logic gate is LOW when atleast one of its inputs is HIGH. This is true for C
a)AND b)NAND c)NOR d)OR
89 The output of logic gate is HIGH when atleast one of its inputs is LOW. This is true for B
a) X-OR b)NAND c)NOR d)OR
90 The output of logic gate is LOW if and only if all its inputs are HIGH. This is true for D
a)AND b)X-NOR c)NOR d) NAND
91 The output of logic gate is HIGH if and only if all its inputs are LOW. This is true for A
a)NOR b)X-OR c)NAND d)X-NOR
92 The most suitable gate for comparing two bits is D
a)AND b)OR c)NAND d)X-OR
93 Which of the following gates cannot be used as an inverter? B
a)NAND b)AND c)NOR d)X-NOR
94 The output of a logic gate is 1 when all its inputs are at logic 1. The gate is either
a) a NAND or a NOR b)an AND or an OR B
c)an OR or an X-OR d)an AND or a NOR
95 The output of a logic gate is 1 when all its inputs are at logic 0. The gate is either
a)a NAND or a NOR b)an AND or an X-NOR A
c)an OR or a NAND d)an X-OR or an X-NOR
96 For checking the parity of a digital word, it is preferable to use C
a)AND gates b)NAND gates c)X-OR gates d)NOR gates
97 The most suitable gate to check whether the number of 1s in a digital word is even or
odd is A
a)X-OR b)NAND c)NOR d)AND, OR and NOT
98 A+AB+ABC+ABCD+ABCDE+………… = B
a)1 b)A c)A+AB d)AB
99 The dual of a Boolean expression is obtained by
a)Interchanging all 0s and 1s B
b)Interchanging all 0s and 1s, all + and ‘.’ signs
c) Interchanging all 0s and 1s, all + and ‘.’ signs and complementing all the variables
d) Interchanging all + and ‘.’ Signs and complementing all the variables
100 The complement of a Boolean expression is obtained by
a)Interchanging all 0s and 1s
b)Interchanging all 0s and 1s, all + and ‘.’ signs C
c)Interchanging all 0s and 1s, all + and ‘.’ signs and complementing all the variables
d).Interchanging all + and ‘.’ Signs and complementing all the variables
MODULE-III
101 The difference output in a full-subtractor is the same as the
a)Difference output of a half-subtractor b)Sum output of a half-adder C
c)Sum output of a full-adder d)Carry output of a full-adder
102 on inputs, and produces two binary digits, a sum bit and a carry bit on its outputs?
a)Full-adder b)Half-adder c)Serial adder d)Parallel B
 adder
103 How many inputs and outputs does a full-adder have?
a)Two inputs, two outputs b)Two inputs, one output C
c)Three inputs, two outputs d)Two inputs, three outputs
104 How many inputs and outputs does a full-subtractor have?
a)Two inputs, two outputs b)Two inputs, one output D
c)Three inputs, two outputs d)Two inputs, three outputs
105 A full-adder can be realized using
a)One half-adder, two OR gates b)Two half-adders, one OR gate B
c)Two half-adders, two OR gates d)Two half-adders, one AND gate
106 The minimum number of 2-input NAND/NOR gates required to realize a half-adder is C
a)3 b) 4 c) 5 d)6
107 The minimum number of 2-input NAND/NOR gates required to realize a half-
subtractor is C
a)3 b) 4 c) 5 d)6
108 The minimum number of 2-input NAND gates required to realize a full-adder/full-
subtractor is B
a)8 b)9 c)10 d)12
109 The minimum number of 2-input NOR gates required to realize a full-sbtractor is D
a)8 b)9 c)10 d)12
110 How many full-adders are required to construct an m-bit parallel adder? B
a)m/2 b)m-1 c)M d)m+1
111 Parallel adders are
a)Combinational logic circuits b)Sequential logic circuits A
c)Both of the above d)None of the above
112 In which of the following adder circuits is the carry ripple delay eliminated? D
a)Half-adder b) Full-adder c)Parallel adder d)Carry-look-ahead-adder
113 To secure a higher speed of addition, which of the following is the preferred solution? C
a)serial-adder b)parallel-adder c)Adder with a look-ahead-carry d)Full-adder
114 A parallel adder in which the carry-out of each full-adder is the carry-in to the next
significant digital adder is called a A
a)Ripple carry adder b)Look-ahead-carry adder
c)Serial-carry adder d)Parallel carry adder
115 A serial adder requires only one B
a)Half-adder b)Full-adder c)Counter d)Multiplier
116 In digital systems subtraction is performed
a) Using half-adders C
b) Using half-subtractors
c) Using adders with 1’s complement representation of negative numbers
d) None of the above
117 In BCD addition, 0110 is required to be added to the sum for getting the correct result if
a) The sum of two BCD numbers is not a valid BCD number B
b) The sum of two BCD numbers is not a valid BCD number or a carry is produced
c) A carry is produced
d) None of the above
118 BCD subtraction is performed by using
 a)1’s complement representation b)2’s complement representation D
c)5’s complement representation d)9’s complement representation
119 Which logic gate is a basic comparator D
a)NOR b)NAND c)X-OR d)X-NOR
120 The logic gate used in parity checkers is C
a)NAND b)NOR c)X-OR d)X-NOR
121 Which of the following statements accurately represents the two BEST methods of
logic circuit simplification?
a) Boolean algebra and Karnaugh mapping A
b) Karnaugh mapping and circuit waveform analysis
c) Actual circuit trial and error evaluation and waveform analysis
d) Boolean algebra and actual circuit trial and error evaluation
122 The binary numbers A =1100 and B = 1001 are applied to the inputs of a comparator.
What are the output levels? C
a)A > B = 1, A < B = 0, A < B = 1 b)A > B = 0, A < B = 1, A = B = 0
c) > B = 1, A < B = 0, A = B = 0 d)A > B = 0, A < B = 1, A = B = 1
123 Two 4-bit binary numbers (1011 and 1111) are applied to a 4-bit parallel adder. The
carry input is 1. What are the values for the sum and carry output?
a) 4 3 2 1 = 0111, Cout = 0 C
b) 4 3 2 1 = 1111, Cout = 1
c) 4 3 2 1 = 1011, Cout = 1
d) 4 3 2 1 = 1100, Cout = 1
124 The carry propagation can be expressed as B
a)Cp = AB b)Cp = A + B c) d)
125 How many 4-bit parallel adders would be required to add two binary numbers each
representing decimal numbers up through 30010? C
a)1 b)2 c)3 d)4

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