132 IEEE TRANSACTIONS

ON CIRCUITTHEORY,FEBRUARY1970
resistance, whereas that of the grounded-base stage is high. A TABLE I
shunt-feedback stage can, of course, be designed to have unity APPLICATIONOF CURRENT CONVEYORSTOACTIVE NETWORK
current gain; one merely chooses RL = Rp when SYNTHESIS
~,,~:W.CICKILHI ION REALIZATION USING CURRENT. CONVEY07

Similarly, if one chooses RL for a grounded-base stage equal to

RF, the stage transfer resistance becomes
RT= -A,XR,--++R,.
However, these two special cases do not constitute equivalence
of the circuits.
E. M. CHERRY
Dept. of Elec. Engrg. 2
Monash University
SOURCE T
Clayton, Victoria, Australia 3168

A Second-Generation Current Conveyor and Its

Applications
A recent publication [l] introduced the concept of current
conveying and an implementation in the form of a circuit
building block termed the current conveyor (CC). This block
has proven to be useful in many inst.rumentation applications,
some of which have already been test)ed and reported [2], [3],
while others are still under investigation. This correspondence
introduces another new building block embodying the current
conveying concept, but with different and more versatile terminal
characteristics. This new block is considered to be a second-
generation current conveyor,1 and h.ence is termed CC II.2
Application of CC II to the areas of active network synthesis
and analog computation will be considered.. 7 GYRATOR

TERMINAL CHARACTE~RISTICS
The current conveyor is a grounded three-port network
represented by the black box at the tsop right of Table I with
in the applications, the symbolic representation of the current
the three ports denoted by x, y, and x. Its terminal characteristics
conveyor will include a @ or 0 sign to correspond with the
can be represented best by a Ihybrid matrix giving the outputs
of the three ports in terms of their corresponding inputs. For sign of ha2 in (1) and (2).
CC I this relationship can be stated as APPLICATION TO ACTIVE NETWORK SYNTHESIS
Table I shows the use of the current conveyor to realize a
few of the generating elements commonly used in active network
synthesis. All designs are obtained by a direct implementation
of the network-defining equations as given in column 2 of Table
I. Although the table is self explanatory, we note the following.
while for CC II 1) Two different realizations are given for the NIC. In both
realizations port 1 is short-circuit stable (SCS), while port 2
is open-circuit stable (OCS). Although in the realization using
CC I, terminal z is assumed to be grounded, this is not a neces-
sary condition. Since z carries an equal current as that through
x and y, it can be used to monitor the current flowing in the
negative impedance without causing any disturbance to the
It should be noted that all currents and voltages in (1) and NIC. This unique three-port NIC has some interesting ap-
(2) are total instantaneous quantities rather than incremedtal plications [4].
values. This property requires that any implementation of the 2) In the gyrator realization, the gyration conductance g
current conveyor should be direct-cloupled, should have no is explicity available through two grounded resistances. This
offset, and should exhibit linear ideal operation over a wide makes possible the realization of time-variable gyrators [5]
signal range. Circuit implementations for CC I have been by simple electronic variation of both of the conductances g.
previously reported [l], [3], while various implementations of The same general remark applies for the NIV.
CC II are under investigation. Details of circuit design are THE CURRENT CONVEYORASAN ANALOG COMPUTER
considered beyond the scope of this correspondence. Note that ELEMENT
If current is made to correspond to the computation variable
ManuscriptreceivedAugust5, 1968;revisedOctober28, 1968and April 7, 1969.
This work w&ssupportedin part by the Natiom,l ResearchCouncil of Canads. in an analog computer, it is possible to use the current conveyor
under Grant A-3148. as the fundamental unit of such a computer. Table II illustrates
1Patent appliedfor.
1We will refer to the current conveyorpreviouslyreported8s CC I. the use of CC II to obtain the basic analog computation func-

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 CORRESPONDENCE 133

.m, .mp .m,

io= 1, i, ---- In

trj =‘(R /R)

Iq + m,+---t %.’ I

Fig. 1. A generalizedfunction generator.

TABLE II Another powerful analog computation block is shown in

APPLICATIONOF CURRENT CONVEYORSTOANALOG Fig. 1. Fundamentally it is a generalized function generator
COMPUTATION with inputs 11, 12, * * . , I,,, and output lo. Using the terminal
iEALlZATlON USING CURRENT CONVEYOR characteristics of CC II given in (2) and assuming ideal matched
logarithmic characteristics for all diodes, it can be shown that
FUNCTIONAL
--q-p
FUNCTION
ELEMENT
(3)
7
where
CURRENT -

AMPLIFIER
R
0
mi = f Ri
CURRENT -
dI1 with the sign corresponding to that of the jth conveyor.
2 10: CR r
Many useful functions can be obtained from this generalized
DIFFERENTIATOR function generator by the choice of the number of conveyors
I I and appropriate values for the powers mi. As an example, an
analog multiplier-divider requires that n = 3, ml = i-1,
CURRENT -
mz = f 1, and m3 = - 1 and provides the relation
3
INTEGRATOR
I,,=+R
J I,dt
IO = LLp
I I - a
CURRENT - where Iz and I3 may be considered, alternatively, as variables
or constants. Although one quadrant operation is implied by
4
SUMMER -
the diagram of Fig. 1, four quadrant operations can be provided
I
by some additions.
CONCLUSIONS
The second-generation current conveyor introduced is a
convenient building block that provides a simplified approach
SUMMER
to the design of linear analog systems. Although its circuit
implementation is not considered in this correspondence, it
seems that the versatility of the device warrants its production
in integrated form.
tions. Note that all passive elements have a grounded terminal.
It is relatively easy then to provide direct digital control of the A. SEDRA
gain and time constants by switching some resistors in a binary- K. C. SMITH
weighted fashion. Also the fact that the integrator capacitor Dept. of Elec. Engrg.
has a grounded terminal simplifies the application of initial University of Toronto
conditions. Toronto 5, Ont., Canada

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 134 IEEE TR4NSACTION.8
ON CIRCUITTHEORY,FEBRUARY1970
REFERENCES included in a, block (of a realizable partition of S) corresponding
PI K. C. Smith and A. Sedra,“The cwrent conveyor-A new circuit building to that IR.
block,” Proc. IEEE (Letters), vol. 56, pp. 136B-1369,August 1968.
PI A. Sedraand K. C. Smith, “Design of computercontrollableinstrumentation.”
presentedat the 6th Nstl. Conf. of the ComputerSot. of Canada,June 1968. DeJinition 4
131K. C. Smithand A. Sedra.“A newsimplewide-b:mdcurrentmeasuringdevice.” A subset s of a circuit S is an IR-compatibility class if there-
IEEE Trans. Instrumentation and Mcasuremenf vol. IM-18, pp. 126-128.
June 1969. exists a realizable partition of S having s among its blocks.
141I-, “Realization of the Chua family of new nonlinear network elements
using the current conveyor.” this issue,pp. 137-139.
[51 R. W. Newcomb. Active Integratea! Network Synthesis. Englewood Cliffs, DeJinition 6
N. J.: Prentice-Hall,1968.
A maximal IR-compatibility class is a class that is not in-
cluded in any other IR-compatibility class.

In the set of the blocks of all realizable partitions of a circuit,

the maximum blocks correspond to the maximal IR-compati-
On the Selection of Isolated Regions in Computer-Aided bility classes (Definition 4). We can therefore state the following
Design of Integrated Circuits theorem.

I. INTRODUCTION Theorem 1
Bipolar integrated circuits cannot be fabricated if electrical A partition of a circuit is realizable if and only if its blocks
isolation is not provided between some groups of components are included in the maximal IR-compatibility classes of the
[I]. The determination of these groups is one of the initial tasks circuit.
in integrated-circuit design. Since the increasing complexity By Theorem 1, any realizable partition can be derived very
of circuits that can be integrated makes the use of computers easily from maximal classes. According to the main design
more and more necessary to the designer [2], [3], the problem objective, that is the minimization of circuit size, a maximum
of selecting isolated regions (IR’s) by computer has been in- partition should be selected,’ since the area required by such
vestigated. a partition to separate the IR’s from one another is minimum [5]
In a preceding paper [4], an algorithm has been presented To show that many maximum partitions may exist, let us
that determines the so-called “maximal IR-compatibility” limit, for the sake of simplicity, our discussion to integrated
classes of components, from which all allowable partitions of circuits with a reverse-biased p-n junction isolation and a
the circuit can be derived. This is the first step toward the p-type substrate.* We shall state the requirements for IR
solution. To minimize the circuit area, a maximum partition, compatibility in terms of conditions to be satisfied by component
i.e., a partition with the minimum number of IR’s, should be terminals. The terminal of an n-type region that constitutes
selected. However, there are generally several maximum par- an IR corresponds to a node in the circuit schematic only if
titions. The problem of selecting one of them is discussed in the region is used also as a part of one or more components
this correspondence. In Section II the theoretical background (e.g., as the collector of an n-p-n transistor).
of the algorithm for maximal classes i,s summarized. A design Dejinition 6
criterion for defining the optimum partition and the problems
encountered in its implementation are illustrated in Section The terminal of an IR is said to be its fundamental termina1.s
III. Section IV finally describes an algorithm based on the re- Dejkition 7
sults of the ‘investigation performed in Section III.
For each component the terminal indicated in Table I is
II. BACKGROUN:D called the prim&y terminal.
In this section we shall recall the ‘definition of a maximal There are two types of components in Table I: the topo-
IR-compatibility class and show that generally these classes logical-constraint components (TC-components) and the elec-
are not disjoint, i.e., many maximum partitions do exist. The trical-constraint components (EC-components) ; EC-components
algorithm for determining maximal classes will not be described are indicated in Table I by a star. The differences between
here; the interested reader can find it and a more detailed de- these two types are explained in the statement of the following
scription of its theoretical basis in a preceding paper [4]. theorem.
A list of preliminary definitions will now be given.
Theorem .%?
Definition 1
A component can be included in an IR-compatibility class
A partition P = (B1; Bz; . . 1 ; B,} of a set S is a collection if and only if its primary terminal:
of n disjoint and exhaustive subsets of S. Subsets B1, Bz, . . .,
B,, are said to be the blocks of P. a) is connected to the fundamental terminal of the class
(condition for a TC-component) ; or
Dejinition d b) has a voltage not greater than the voltage of the fundamen-
A partition P of a circuit S (considered as the set of its com- tal terminal (condition for an EC-component).
ponents) is said to be reaZi&le (with respect to the problem As shown by this theorem, the constraint for EC-components
of IR’s) if the components of each block of P can be fabricated is such that they may often be included’ in more than one
together without isolation. A maximuwt partition is a realizable maximal IR-compatibility class. Because of the existence of
partition with the minimum number of blocks. multiclass components, i.e., of EC-components belonging to
several maximal classes, these classes are generally not disjoint.
DeJinition 3
Two or more components of a circuit S, are said to be com-
1Note that sometimesthere ~lre8om18 constraintsto be taken into account,
patible with respect to an IR (IR-compatible) if they can be for example,the area of the IR’s containing transistorswhoseperformanceis
highly sensitiveto capacitiveloading should be minimized. Thesecasescan be
easily dealt with by the algorithm describedin the paper cited above [4].
* Extending what will be said to other isolation techniquesox-to the c&seof
ManuscriptreceivedAugust3, 1968;revisedNovember11, 1968.This work w&s n-type substrateis straightforward.
supported in part by the Comitsto di Ingegneria,Consiglio Nrtsionaledelle 8 Note that eachIR-compatibility classis an IR in somerealizablepartitions.
Ricerche,Rome, Italy. henceits fundamentalterminal is alwaysperfectly defined.

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