Mostafa Essam Abdelhamid Abdelhai

Electronics and Communication Engineer

Mobile: (+20)1159660640 E-mail: [email protected]
Address: Fifth Settlement / Cairo / Egypt
LinkedIn: linkedin.com/in/mostafa-essam-abd-el-hamid
GitHub: https://github.com/MostafaEssamAbdelhameed

Summary:
Dedicated Core Network and IMS Engineer with a strong passion for mobile core architecture,
IP multimedia systems, signaling protocols, and next-generation voice services. Equipped with
a solid foundation in telecommunications from Ain Shams University and hands-on experience
in core switching, VoLTE/IMS systems.
Education:
Ain Shams University Faculty of engineering 2019 – 2024
Electronics and communication department (GPA 3.14).
Last Term GPA 3.671.

Personal Information:
Military status: Exempted.
Date of Birth: 31 / 8 / 2001.
Graduation Project:
Under the Supervision of: Dr.DiaaEldin S Khalil, and STMicroelectronics
Grade: A+
Title: Digital Design of 5G-NR Physical Uplink-Shared Channel (PUSCH) Chain.
Role in GP:
• Understanding OFDM/SC-FDMA systems
• Understanding 3GPP TS 38.211/212 Docs.
• Determining of the PUSCH Blocks Specs.
• Floating Point MATLAB Modeling for the PUSCH Chain.
• Fixed Point MATLAB Modeling for 2048-IFFT & Re-Configurable DFT-Precoding Mixed radix (2, 3, 5)] using Single-
path delay feedback (SDF) Architecture to achieve required performance (SQNR).
• Fixed Point MATLAB Modeling for Hardware Friendly implementation of Reference signal generation using
Zadoff-chu sequence.
• Preparing Hardware Architecture.
• RTL using System Verilog [Mainly SDF DFT-Precoding Mixed radix (2, 3, and 5) & Reference signal generation].
• Integrating Whole system blocks and apply system verification.
Experience:
Lead Core Switching & IMS Engineer (Jan 2025 – Present)
Orange Egypt — Smart Village
 Lead the deployment, optimization, and maintenance of CS core network and IMS infrastructure.
 Manage VoLTE, VoWIFI provisioning and delivery with a focus on network reliability and scalability.
 Automate routine tasks and reporting using SQL where applicable.
 Collaborate cross-functionally with operations, planning, and vendor teams to ensure seamless integration and service uptime.
 Perform traffic analysis, troubleshooting for network nodes.
 Courses:
Self-Study Data Analyst Program: (April 2025 – Present)
comprehensive self-paced course covering core data analysis tools and techniques. Gained hands-on experience in:
 SQL: Data querying, joins, CTEs, and data cleaning.
 Excel: Pivot tables, formulas, XLOOKUP, and data visualization.
 Tableau & Power BI: Built interactive dashboards and reports.
 Python: Data analysis with Pandas, web scraping, and automation.
 Projects: Completed end-to-end projects using real-world datasets.

Mobile CS/IMS Voice Core: (Feb 2025 – April 2025)

CS Voice Core Concepts:

◦ High Level view about CS Core Nodes, & used Protocols, Split Architecture From MSC to MSC-S and MGW,
Access/Radio RF Network Structure, MSCS, MGW, HLR, SMSC, EIR, IMSI, IMEI, IMEI check call flow, ,MSRN ,
Location Identities in CS Core, Basic Procedures in CS Circuit Switching Core Network, IMSI Attach Signaling
Procedures, Authentication Procedures, Purge MS, Location update & what is its types ,Normal Location Update
Procedures, IMSI Attach Signaling Procedures, IMSI Detach Signaling Procedures, Call Flow MO/MT Signaling
Procedures, SMS call flow, MSC in Pool.

IMS Core Concepts:

◦ Essential Protocol in VoLTE Network, SIP Basics, SIP elements, SIP flow Diagram, SIP Architecture, SIP Call flow
detailed, SIP Messages, SDP protocol & its Headers, IMS Network Architecture, IMS Nodes, VoLTE interaction with CS
Networks, VoLTE identities, VoLTE registration procedures, VoLTE call procedures, VoLTE Breakout & Breakin
Scenarios, SRVCC.

CCNA Networking Fundamentals: (Oct 2024 – Nov 2024)

◦ Network Topologies and models, Network components, IP addressing and subnetting, VLAN’s, spanning tree protocol
(STP), static and dynamic routing protocols, DHCP and DNS, Virtual Private Network (VPN), access control lists
(ACLs), network address translation (NAT), Port address translation (PAT), WAN technologies, network security basics,
troubleshooting network connectivity, IPv6 configuration.
4G Radio Optimization: (August 2024 – Sept 2024)
◦ Idle & Active Mode parameters, PLMN and Cell selection Criteria (PCI Planning / S-criteria), Cell Re-selection
Criteria, LTE Control Channels, Tracking Area update, Paging, RACH (RSI planning), Measurement Quantities,
Handover, CSFB Optimization, Power control technique, Radio link supervision, LTE Capacity management, LTE
QOS and Scheduler, LTE KPI's analysis.
4G-LTE Drive Test: (August 2024)
◦ LTE-Drive Test parameters, TEMS Discovery 22.x, TEMS investigation 22.x (Real time guide + Cell File Reading),
Benchmarking Analysis, Carrier aggregation, Heavy DL&UL analysis, Benchmarking Analysis, Cross Sector, Cross
Feeder, CSFB, CSFB Events Analysis, CSFB L3 Messages Analysis, VOLTE Log File Analysis, VOLTE SRVCC, Site
Acceptance (All DT-Activities).
Mobile Communication: (July 2024 – August 2024)
◦ Mobile technology Features, Cell Type, Interference in Mobile system, Handover & Power Control, 2G/3G/4G
Network Architecture, Duplex Technique, Multipath Fading, Location area/ Tracking area , Handover Cases, Radio
Frequency Planning ( Cluster Concept & Frequency Reuse ), Cell sectorization, Access techniques, FreqBands,
Channels classification, Call Flow, Time Advance,2G/3G RF Problems, CMDA Full Concept, Scrambling Codes, Soft
Handover, Control Channels, Spreading Factor, LTE Frame Structure, Cyclic prefix, ( OFDM & SC-FDMA ).

RTL Verification Diploma using System Verilog and UVM: (September 2023 – Nov 2023)

Under supervision of Eng. Sherif Hosny.

Digital IC Design Diploma: (July 2023 – September 2023)

Under supervision of Eng. Ali El-Temsah.

Najah Now FPGA Digital Design Diploma: (January 2023 – June 2023)
Projects:

 Automating the routine tasks that handles Provisioning of VoLTE/VoWIFI … etc and
reporting the network nodes behavior. (SQL)
Digital:
 Greatest Common Divisor (GCD) (Verilog) (1 March –6 March)
 RSA cryptosystem Implementation on Spartan-6 FPGA (Verilog) (29 April – 7 May)
 AES Implementation on Zynq Kit (Verilog) (7 July – 13 July)
 Linear Feedback Shift Register (CRC) (Verilog) (2 August – 6 August)
 UART TX & RX (Verilog) (22 Aug – 5 Sep)
 Asynchronous FIFO (Verilog) (9 Sep – 11 Sep)
 RTL to GDS Implementation of Low Power Configurable Multi Clock Digital System (12 Sep – 18 Sep)
 TCL Scripts For writing Test Benches (TCL)
 I2C Master Controller (Verilog) (3 Oct – 5 Oct)
 Full UVM Environment for testing and verifying 16-bit memory

Technical Skills:
o SQL o Excel
o Tableau o Power BI
o TEMS Discovery 22.x o TEMS investigation 22.x
o Verilog / System Verilog o Formality
o ISE / Vivado o MATLAB
o ModelSim and Questasim. o Cadence Virtuoso
o TCL o Embedded C
o Synopsys Design Compiler o Multisim
o DFT Insertion o Proteus