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Appendix-‘D’ Refer/WI/ACAD/18

SHRI RAMSWAROOP MEMORIAL COLLEGE OF ENGINEERING & MANAGEMENT

PRE-END SEMESTER EXAMINATION

[Session: 2024-25 (Odd)]

B. Tech. III Sem. (AM, DS, CY & IO)

BOE-310: DIGITAL ELECTRONICS
Duration: 03 Hours Maximum Marks: 100

Section A M
A1(a) 19316  (623) x  1162  9 161  3 160  6  x 2  2  x  3 [2]

 256  144  3  6 x 2  2 x  3  6 x 2  2 x  400  0

 x 8
A1(b) The complement of the result of ANDing variables is the same as ORing the complements of [2]
the individual variables: ( A.B)  A  B
The complement of the result of ORing variables is the same as ANDing the complements of
the individual variables:  A  B   A.B
A1(c) Half Adder using NAND gates: [2]

A1(d) Gate level diagram of 2:1 MUX: [2]

A1(e) Universal shift register is a register which has both the right shift, left shift with parallel load [2]
and hold capabilities.
A1(f) The key difference between a latch and a flip-flop is that a latch is "level-triggered," meaning its [2]
output changes whenever the input changes at a certain logic level, while a flip-flop is "edge-
triggered," meaning its output changes only at the transition (rising or falling edge) of a clock
signal, making it more precise for timing-critical applications; essentially, a latch is constantly
monitoring input changes while a flip-flop only updates its state at specific clock edges.
A1(g) [2]

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A1(h) Asynchronous circuits, also known as self-timed circuits, are a type of digital circuit design in [2]
which the components operate independently of a global clock signal. Unlike synchronous
circuits, where all operations are synchronized to a central clock signal, asynchronous circuits
rely on local signals to control the timing of individual components.
A1(i) Fan-in: A logic gate's fan-in is the maximum number of inputs it can handle. For example, a [2]
two-input AND gate has a fan-in of 2.
Fan-out: Fan-out is the maximum number of output signals that a logic gate can produce.
A1(j) [2]

Section B M
A2(a) [10]

[1+1+1.5+1.5= 5 Marks]
[1+1+1.5+1.5= 5 Marks]
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A2(b) (ii) Full subtractor using NAND gate only: [10]

[5 Marks]
(ii) 16:1 mux using 8:1 mux and 2:1 mux only:

[5 Marks]
A2(c) The register which is used to shift the data on the right side or left side based on the selected [10]
mode is known as the bidirectional shift register.

This register can be implemented through a D flip flop and logic gates which allow the data bit
to transfer from one stage to the next stage to any side either right or left based on an input

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 signal. Here, the direction of data shifting is selected by the mode control.
The bidirectional shift register mainly includes two serial inputs like the data input with serial
right shift (DR) and the data input with serial left shift (DL) with a select mode input (M).
Whenever the data needs to shift on the right side then input is given to the DR. Similarly, if the
data needs to shift on the left side then input is given from DL.
If the mode select input, M = 1, then 1st, 3rd, 5th & 7th AND logic gates are enabled & the
remaining 2nd, 4th, 6th & 8th AND gates are not enabled. The binary data on serial right shift
data input (DR) can be moved to the right bit side through a bit from flip flop3 to flip flop0 on
the CLK pulses application. So for M = 1 condition, we can attain the serial shift right
operation.
If the mode select input, M = 0, then then 2nd, 4th, 6th & 8th AND gates are enabled and 1st,
3rd, 5th & 7th AND gates are disabled. The data on the serial left shift data input (DL) is moved
left bit side through a bit from Flip Flop0 to Flip Flop3 on the CLK pulses application. So for M
= 0 conditions, we can obtain the serial shift left operation. [2+4+4 =10]
A2(d) [10]

Logic Diagram [4 Marks] [2 Marks]

[2 Marks] Flow table [2 Marks]

A2(e) (i) A CMOS IC can easily drive any low power schottky TTL IC directly. But to interface [10]
standard TTL IC, buffer is provided in between CMOS and TTL ICs. This is shown in
following figures-
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 TTL to CMOS interfacing CMOS to TTL interfacing
[2.5 Marks] [2.5 Marks]
(ii) Even though there are various logic families, the general characteristics, definitions,
nomenclature, and terminologies used for all of them have been standardized. some of the most
important general characteristics are:

1. Voltage Parameters (Threshold Levels): Ideally, the input voltage levels of 0V and +5V
(for TTL) are called logic 0 and 1 levels respectively.

However, practically we will not always obtain voltage levels matching exactly to these values.
Therefore it is necessary to define the worst-case input voltages.

VIL(max) – worst case low level input voltage: This is the maximum value of input voltage
which will be considered as a logic 0 level. If the input voltage is higher than VIL(max), then it
will not be treated as a low (0) input level.

VIH(min) – worst-case high-level input voltage: This is the minimum value of input voltage
which will be considered as a logic 1 level. If the input voltage is lower than VIH(min), then it
will not be treated as a high (1) input level.

VOH(min) – worst-case high-level output voltage: This is the minimum value of output voltage
which will be considered as a logic 1 level. If the output voltage is lower than VOH(min), then
it will not be treated as a high (1) output level.

VOL(max) – worst-case low-level output voltage: This is the maximum value of output voltage
which will be considered as a logic 0 level. If the input voltage is higher than VOL(max), then it
will not be treated as a low (0) output level.
[2.5 Marks]

2. Current Parameters:
IIL – Low-level input Current: It is the current that flows into the input when a low-level input
voltage in the specified range is applied.
IIH – High-level input Current: It is the current that flows into the input when a high-level
input voltage in the specified range is applied.
IOL – Low-level output Current: It is the current that flows from the output when the output
voltage is in the specified low voltage range and the specified load is applied.
IOH – High-level Output Current: It is the current that flows from the output when the output
voltage is in the specified high voltage range and the specified load is applied.
[2.5 Marks]

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 Section C M
A3(a) [10]

[3+3+4 = 10 Marks]

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A3(b) This Question has two possible solutions as shown below, Students have to provide anyone of [10]
the solutions:

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A4(a) [10]

[5 +5 =10 Marks]
A4(b) (i)Implementation with 16:1 MUX [10]
 In the given Boolean expression, there are 4 variables.
 Hence, use 2n = 24 : 1 = 16:1 multiplexer.

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  So, the mux has 16 input lines, 4 selection lines, and 1 output.
 The inputs, corresponding to the min-terms (2,3,4,5,8,9,12) are
connected to logic 1 and the remaining terms to logic 0 (Grounded).
 The given input variables are connected as 4 selection lines.
 The 16:1 multiplexer can be drawn as follows:

[4 Marks]
(ii)Implementation with 8:1 MUX
 In the given boolean expression, there are 4 variables.
 Hence, we should use 24 : 1 = 16:1 multiplexer.
 But as per the question, it is to be implemented with 8:1 mux.
 For the 8:1 multiplexer, there should be 3 selection lines.
 So from the given 4 variables, the 3 least significant variables(B, C, D) are used as
selection line inputs.
 Let us derive the eight inputs of the 8:1 multiplexer using the Implementation Table.
 The eight inputs are listed column-wise and all the minterms are written under the eight
inputs in rows as shown below the implementation table:

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 [6 Marks]
A5(a) [10]

[ 5 Marks]

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 [ 5 Marks]
A5(b) The twisted ring counter is the modification of ring counter; complemented [10]
output of last stage serves as the input to the first stage flip-flop. The
modulus of the twisted ring counter is 2n, where n is the number of flip-
flops are used in the design. Figure () shows the logic diagram of 4-bit
twisted ring counter using D flip-flops.

Initially, the contents of flip-flops (Q0Q1Q2Q3) are assumed as (0000), at

the first rising edge of the clock pulse 𝐷0 = 𝑄3 ̅̅̅ and hence, 𝑄0 = 𝐷0,𝑄1 =
𝐷1,𝑄2 = 𝐷2,𝑄3 = 𝐷3 this data shift position wise at the flip-flops at every
rising edge of the clock pulse, The twisted ring counter generates the eight
sequence and the sequence repeats after every eight clock pulses, hence the
mod of this counter is eight. The twisted ring counter is also called
Johnson counter and switch tail counter.
[5 Marks]

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 [5 Marks]
A6(a) [10]

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 This circuit represent a Serial Adder.
[2+4+3+1= 10 Marks]
A6(b) [10]

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 The sequence of internal states Y1Y2 for the input sequence x1x2: 00, 10,
11, 01, 11, 10, 00 will be 00, 00, 01, 11, 11, 01, 00. (This can be
explained using above transition table).
[2+2+4+2 =10 Marks]
A7(a) [10]

Simplified expressions of E0, E1, E2, E3 can be obtained using K-map as:

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 [2+2+2+4 = 10 Marks]

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A7(b) [10]

[6 Marks]

[4 Marks]

____________X____________

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