S.D.

M Jainmatt Trust®
A. G. M RURAL COLLEGE OF ENGINEERING AND
TECHNOLOGY, VARUR
Navagraha Teerth, NH-4 Road, VARUR-581 207, Hubli, Dist. Dharwad,
Karnataka
(APPROVED BY AICTE, NEW DELHI, AFFILIATED TO VTU,
BELGAUM AND RECOGNIZED BY STATE GOVT.)
Accredited by NAAC with grade B++
Phone: 0836-2312071, Fax: 0836-2312061, E-mail:[email protected],
Web: www.agmrcet.ac.in

Department of

Electronics & Communication Engineering

VLSI Design & Testing

BEC602

Course project
“Design and testing of 4:1 Multiplexer”

Submitted by:
Sl.No. Name USN Signature
1 Rahul Halageri 2AV22EC034
submitted for the partial fulfillment of the course

Mentored by:
Dr. Kunjan D. Shinde
Associate Professor,
Dept. of E&CE,
AGMR College of Engineering and Technology, Varur.

Academic Year 2024-25

 2:1 MUX

Contents
1. Problem Statement
2. Introduction
3. Logic Diagram
4. Design, Truth table & Equations
5. Explanation
6. Results and Discussions (Photos)
a. Simulation Results
7. Advantages and Applications
8. Conclusion
9. References

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1. Problem Statement:

Design a 4:1 multiplexer using CMOS logic that selects one of the four input signals (D0,
D1, D2, D3) based on the values of two select lines (S0, S1) and routes the selected input to
a single output (Y).

2. Introduction:
A multiplexer (MUX) is a fundamental digital circuit used to select one of several input
signals and forward it to a single output line. It acts as a data selector and is widely used in
digital systems such as communication devices, processors, and memory units to control the
flow of data.

A 4:1 multiplexer has four data inputs (D0–D3), two select lines (S0, S1), and one output (Y).
The select lines determine which input is connected to the output. This functionality is crucial
in building data paths, implementing logic functions, and routing signals in integrated circuits.

In modern VLSI systems, designing logic circuits using CMOS (Complementary Metal-
Oxide-Semiconductor) technology is preferred due to its advantages such as low static power
dissipation, high noise margins, and scalability. CMOS-based multiplexers are not only
reliable but also power-efficient and capable of high-speed operation.

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3. Block Diagram:

4.Design:
A 4:1 multiplexer using CMOS transmission gates can be designed by extending the concept
used in a 2:1 MUX. In this design, four transmission gates (TGs) are used—each
corresponding to one of the four data inputs: D0, D1, D2, and D3. Each transmission gate is
constructed using one NMOS and one PMOS transistor connected in parallel. The gates of
these transistors are driven by complementary control signals derived from the two select
lines S1 and S0.
The working principle is simple: based on the values of S1 and S0, only one transmission gate
is enabled at any given time, allowing the corresponding data input to pass through to the
output Y, while the other transmission gates remain OFF, isolating their respective inputs.
For example, when S1 = 0 and S0 = 0, the control logic enables the transmission gate
connected to D0, making Y = D0. When S1 = 0 and S0 = 1, only the TG connected to D1 is
enabled, so Y = D1, and so on. To generate the correct enable signals, logic gates (AND,
NOT) are used to derive the four control combinations: S1'S0', S1'S0, S1S0', and S1S0. This

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ensures reliable selection of one input at a time.

Logic Equation:
The logic equation for a 4:1 multiplexer using inputs D0, D1, D2, D3 and select lines S1
and S0 is:
Y=S1‾⋅S0‾⋅D0+S1‾⋅S0⋅D1+S1⋅S0‾⋅D2+S1⋅S0⋅D3
4.Explaination:

A 4:1 multiplexer selects one of four input signals (D0, D1, D2, or D3) based on the
values of two select lines (S1 and S0) and directs the selected input to the output (Y). Only
one data input is passed to the output at a time, depending on the select-line combination.

S1 S0 D0 D1 D2 D3 Y
0 0 0 X X X 0
0 0 1 X X X 1
0 1 X 0 X X 0
0 1 X 1 X X 1
1 0 X X 0 X 0
1 0 X X 1 X 1
1 1 X X X 0 0
1 1 X X X 1 1

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5. Schematic:4:1 MUX using 2:1mux

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1. CMOS 4:1 MUX Logic

Logic Equation:

Y=S1‾⋅S0‾⋅D0+S1‾⋅S0⋅D1+S1⋅S0‾⋅D2+S1⋅S0⋅D3

Where:

• D0, D1, D2, D3 = Data inputs

• S1, S0 = Select signals
• Y = Output

This can be implemented using:

• CMOS static logic (NAND, NOR, and inverters), or

• Transmission gates controlled by select-line combinations (with complementary
logic).

2. Power Consumption

CMOS power is split into two primary components:

a. Dynamic Power (dominant during switching)

Pdyn=α×CL×VDD2×f

Where:

• α = Activity factor (worst-case: 1)

• CL = Load capacitance
• VDD = Supply voltage
• f = Clock/switching frequency

Dynamic power increases with:

• More gates (4 data channels instead of 2)

• More switching nodes (internal select decoding logic)

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b. Static Power (due to leakage)

Pstatic=Ileak×VDD
Occurs even when no switching is happening

• Very low for CMOS unless heavily scaled or high temp

3. Delay Measurement

Measure delay with cross() function in simulation:

• Propagation delay (High-to-Low):

tpHL=cross(V(S),0.5)−cross(V(Y),0.5)

• Propagation delay (Low-to-High):

tpLH=cross(V(S),0.5)−cross(V(Y),0.5)

• Average delay:

tp=tpHL+tpLH2

Note: In 4:1 MUX, internal logic complexity (select decoding) slightly increases delay
compared to 2:1 MUX.

4. Power Measurement (Simulation)

• Plot current through VDD supply: I(VDD)

• Compute average power:

Pavg=average(I(VDD)×VDD)P_{\text{avg}} = \text{average}(I(VDD) \times

VDD)Pavg=average(I(VDD)×VDD)

Typical Example Values for 4:1 CMOS MUX

Parameter Example Value

VDD 1.8 V
CL 20 fF (higher due to more TGs and logic)
Frequency 100 MHz

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Parameter Example Value

Delay (tp) 120 ps (due to extra decoding logic)
Dynamic Power ~6.4 µW
Static Power < 200 nW

6. Simulation results:

Power Consumption :
Static Power
Pseudo‑NMOS uses a single always‑ON PMOS as pull‑up. When the PDN is active
(output = 0), there's direct DC current between VDD and ground:
𝑃𝑠𝑡𝑎𝑡𝑖𝑐=𝐼𝑐𝑜𝑛𝑡×V𝐷𝐷

Advantages:
1. Low Power Consumption: CMOS circuits consume power only when switching between
logic states.
2. High Noise Immunity: CMOS circuits have high noise immunity due to the
complementary nature of the transistors.
Applications

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• Digital Multiplexing:
A 4:1 MUX is commonly used in digital systems to select one of four input signals
and route it to a single output line, reducing the number of data lines required.
• Data Routing and Bus Control:
In microprocessors and communication systems, 4:1 multiplexers are used to route
data from multiple sources to a shared data bus based on control signals.

Pseudo-NMOS Logic4:1 mux :

LOGIC DIAGRAM:

Power Consumption
Static Power

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Pseudo‑NMOS uses a single always‑ON PMOS as pull‑up. When the PDN is active (output = 0), there's
direct DC current between VDD and ground:
𝑃𝑠𝑡𝑎𝑡𝑖𝑐=𝐼𝑐𝑜𝑛𝑡×V𝐷𝐷

Design Style Power (nW) Delay (ps)

Static CMOS 6.1226 316.66

Pseudo‑NMOS 22.464 318.24

Metric Pseudo‑NMOS MUX Static CMOS MUX

Avg Power ~411 μW ~55 μW
Delay (τ\_pd) ~4.56 ns ~4.57 ns
PDP ~1.87 pJ ~0.25 pJ

Practical Implications
Use pseudo‑NMOS when area and transistor count are critical, and the static power can be
tolerated (e.g., small logic blocks in non-battery-powered applications).
Avoid if power-sensitive (especially low-power or battery contexts) or if the output is often
low for long periods.
Optimization tip: scale down the pull-up PMOS to reduce static power, but keep it strong
enough to meet noise margins
Conclusion:
The design of a 4:1 multiplexer using CMOS logic demonstrates the effective use of
complementary pull-up (PMOS) and pull-down (NMOS) networks to achieve low-power,
high-speed digital switching. By using transmission gates or complementary CMOS logic,
the circuit ensures correct logic level transmission with minimal static power dissipation. This
approach offers advantages in terms of noise margin, power efficiency, and scalability,
making it well-suited for integration in modern digital VLSI systems.

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References:
• Textbooks:
Introductory VLSI design books often cover 2:1 MUX designs using static CMOS, pass transistor logic,
and complementary pass transistor logic.
• Online Resources:
Websites like Virtual Labs provide simplified explanations and examples of 2:1 MUX design using basic
logic gates and GeeksforGeeks offers a general overview of multiplexers.
• Research Papers:
Publications on ResearchGate and IEEE Xplore analyze and compare different logic styles (static CMOS,
pass transistor, TGL, etc.) for 2:1 MUX implementations, often including simulation results and
performance metrics.

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