Cambridge University Press & Assessment

978-1-009-60223-5 — Analysis and Design of Data Converters

Behzad Razavi
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Analysis and Design of Data Converters

Master the art of data converter design with this definitive textbook, a detailed and accessible guide ideal for
students and practicing engineers.

Key Features
• Razavi’s distinctive and intuitive pedagogical approach, building up from elementary components to
complex systems.
• Step-by-step transistor-level designs and simulations offer a practical, hands-on understanding of key
design concepts.
• Comprehensive coverage of essential topics including sampling circuits, comparator design, digital-to-
analog converters, flash topologies, SAR and pipelined architectures, time-interleaved converters, and
oversampling systems.
• Over 250 examples pose thought-provoking questions, reinforcing core concepts and helping students
develop confidence.
• Over 350 end-of-chapter homework problems to test student understanding, with solutions available for
course instructors.
Developed by leading author Behzad Razavi, and addressing all the principles and design concepts essential
to today’s engineers, this is the ideal text for senior undergraduate and graduate-level students and profes-
sional engineers who aspire to excel in data converter analysis and design.

Behzad Razavi is a Professor of Electrical Engineering at the University of California, Los Angeles. He has
received numerous teaching and education awards, has served as an IEEE Distinguished Lecturer, and is
a member of the US National Academy of Engineering and a Fellow of the IEEE. His previous text-
books include Fundamentals of Microelectronics, RF Microelectronics, Design of Analog CMOS Integrated
Circuits, and Design of CMOS Phase-Locked Loops.

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Behzad Razavi
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“It is always a great pleasure to read Professor Razavi’s books. This one is no exception. It is a timely update of
his prior book on data converters. It is a must-read for anyone who is interested in data converter design.”
Nan Sun, Tsinghua University
“Writing a book on data converters that covers all fundamental principles, provides practical design insights, and
can remain relevant in this ever changing field is very difficult. Professor Razavi did it.”
Dante Muratore, Delft University of Technology
“This book stands out as a definitive resource on data converters. Professor Razavi strikes the perfect balance
between intuitive explanations of complex concepts and the mathematical rigor necessary for a deep technical
understanding. Whether you are a student seeking clarity or a professional looking for a reliable reference, this
book is an indispensable guide.”
Pavan Kumar Hanumolu, University of Illinois Urbana–Champaign

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978-1-009-60223-5 — Analysis and Design of Data Converters
Behzad Razavi
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Analysis and Design of Data Converters

B E H Z A D R A Z AV I
University of California, Los Angeles

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Cambridge University Press & Assessment
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Behzad Razavi
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Shaftesbury Road, Cambridge CB2 8EA, United Kingdom

One Liberty Plaza, 20th Floor, New York, NY 10006, USA
477 Williamstown Road, Port Melbourne, VIC 3207, Australia
314–321, 3rd Floor, Plot 3, Splendor Forum, Jasola District Centre,
New Delhi – 110025, India
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Cambridge University Press is part of Cambridge University Press & Assessment,

a department of the University of Cambridge.
We share the University’s mission to contribute to society through the pursuit of
education, learning and research at the highest international levels of excellence.

www.cambridge.org
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DOI: 10.1017/9781009602266
© Behzad Razavi 2025
This publication is in copyright. Subject to statutory exception and to the provisions
of relevant collective licensing agreements, no reproduction of any part may take
place without the written permission of Cambridge University Press & Assessment.
When citing this work, please include a reference to the DOI 10.1017/9781009602266
First published 2025
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To the memory of my brother Hojjat

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Contents
Preface xv

Acknowledgments xvi

About the Author xviii

1 Introduction to Data Conversion 1

1.1 Analog-to-Digital Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Digital-to-Analog Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Basic Circuit Concepts 6

2.1 Charge Conservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Charge Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Integrated Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Offset, Gain Error, and Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Sampling Circuits 20
3.1 Basic Sampling Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.1 Ideal Sampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.2 Zero-Order-Hold Sampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.3 Track-and-Hold Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.4 Choice of Sampler Time Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2 Basic Sampling Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 Distortion Due to Switch Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4 Complementary Sampling Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5 Other Switch Imperfections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5.1 Review of MOS Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5.2 Clock Feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5.3 Channel Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.5.4 kT /C Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.6 Differential Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.7 Use of Dummy Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.8 Bootstrapped Sampling Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.8.1 Preliminary Ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.8.2 Complete Bootstrapped Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.8.3 Bootstrapping Imperfections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.9 Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.9.1 Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.9.2 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.9.3 Static and Dynamic Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.10 Effect of Clock Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4 Design Study of a Sampling Circuit 60

4.1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.2 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.3 Simulation Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.4 Track-Mode Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.5 Basic Sampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.6 Sampler with MOS Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.7 Device Stress Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
vii

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4.8 Input Current Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5 Comparator Design Principles 70

5.1 A Brief Note on Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.2 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.3 Amplification by Positive Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.4 Controlled Positive Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.5 A Simple Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.6 A Better Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.7 Comparator Design Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.7.1 Input Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.7.2 Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.7.3 Electronic Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.7.4 Kickback Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.8 The StrongArm Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.8.1 Differential Pairs with Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.8.2 Addition of Positive Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.8.3 Complete StrongArm Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.8.4 Basic Properties of StrongArm Comparator . . . . . . . . . . . . . . . . . . . . . . . . 96
5.8.5 The Need for an RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

6 Advanced Comparator Concepts 102

6.1 Analysis of Transistor Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.1.1 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.1.2 Dependence of Mismatches on Channel Area . . . . . . . . . . . . . . . . . . . . . . . 105
6.2 Metastability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.2.1 Metastability in Current-Steering Comparators . . . . . . . . . . . . . . . . . . . . . . 107
6.2.2 Metastability in StrongArm Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3 Noise in StrongArm Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.1 Noise in Time Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.3.2 Noise in Amplification Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.4 Simulation of Comparator Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.5 Offset Cancelation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.5.1 Analog Offset Cancelation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.5.2 Digital Offset Cancelation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.5.3 Offset Cancelation in StrongArm Comparator . . . . . . . . . . . . . . . . . . . . . . . 125

7 Design Study of a Comparator 129

7.1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7.2 Choice of Device Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7.3 Basic Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.4 Offset and Speed Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.5 Addition of RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.6 Metastability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7.7 Input-Referred Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.8 Kickback Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

8 General DAC Concepts 142

8.1 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
8.2 DAC Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
8.2.1 Static Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
8.2.2 Dynamic Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

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Contents ix

8.3 Digital Codes in DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

8.4 Clocking in DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

9 Resistor-Ladder DACs 158

9.1 Basic Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
9.2 Speed Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
9.3 Differential RDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
9.4 Effect of Gradients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
9.5 Effect of Random Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
9.6 Problem of Reference Bounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

10 Current-Steering DACs 174

10.1 Basic Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
10.2 Basic Matching Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
10.2.1 Deterministic Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
10.2.2 Random Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
10.3 Binary-Weighted and Thermometric IDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
10.4 R-2R IDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
10.5 Segmented IDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
10.6 Nonlinearity Due to Output Impedance of Current Sources . . . . . . . . . . . . . . . . . . . . 186
10.7 Transistor Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
10.8 Matrix Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
10.8.1 Basic Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
10.8.2 Effect of Gradients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
10.8.3 Signal and Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
10.9 Speed and Reference Bounce Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
10.10 Dynamic Errors in IDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
10.10.1 Output Impedance at High Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . 202
10.10.2 Nonlinear Memory Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

11 Capacitor DACs 210

11.1 Basic Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
11.2 Binary-Weighted and Thermometric CDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
11.3 Speed Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
11.4 Effect of Random Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
11.5 Capacitor Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
11.6 Problem of Reference Bounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
11.7 Split CDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
11.8 Choice of Unit Capacitance Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
11.9 Matrix Architecture for CDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

12 Introduction to Nyquist-Rate ADCs 236

12.1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
12.2 A First Look at Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
12.2.1 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
12.2.2 Formulation of Quantization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
12.3 ADC Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
12.3.1 Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
12.3.2 Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
12.3.3 Differential Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
12.3.4 Integral Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
12.3.5 SNDR and ENOB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

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12.3.6 SFDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

12.3.7 Static and Dynamic Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
12.3.8 Figure of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
12.4 Nyquist-Rate ADC Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

13 Flash ADCs 251

13.1 Basic Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
13.2 Sampling in Flash ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
13.3 Thermometer-to-Binary Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
13.3.1 ROM Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
13.3.2 MUX Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
13.3.3 ONEs-Counter Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
13.4 Nonidealities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
13.4.1 Comparator Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
13.4.2 Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
13.4.3 Comparator Metastability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
13.4.4 Kickback Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
13.4.5 Input-Dependent Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
13.5 Bubble Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
13.6 Fully-Differential Flash ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
13.6.1 Fully-Differential Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
13.6.2 U-Shaped Flash Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
13.7 Flash ADC Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

14 SAR ADC Fundamentals 284

14.1 General Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
14.1.1 Quantization by Binary Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
14.1.2 Basic SAR Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
14.1.3 Concept of Time Trellis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
14.1.4 Simple SAR Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
14.1.5 Computing Vin from Dout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
14.2 Charge Redistribution SAR ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
14.2.1 SAR ADCs with CDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
14.2.2 Basic Top-Plate Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
14.2.3 Single-Ended Top-Plate-Sampling ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 293
14.2.4 Differential Top-Plate-Sampling ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
14.2.5 Bottom-Plate-Sampling ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
14.2.6 Differential Bottom-Plate-Sampling ADC . . . . . . . . . . . . . . . . . . . . . . . . . 303
14.3 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

15 SAR ADC Nonidealities 310

15.1 Sampling Nonidealities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
15.1.1 Switch Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
15.1.2 Switch Junction Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
15.2 DAC Nonidealities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
15.2.1 DAC kT /C Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
15.2.2 DAC Offset and Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
15.2.3 DAC Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
15.2.4 Reference Bounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
15.2.5 Reference Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
15.3 Comparator Nonidealities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
15.4 Speed Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

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15.4.1 Comparator Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

15.4.2 DAC Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
15.4.3 Tapering and Minimum Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

16 Advanced SAR ADCs 330

16.1 Speed Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
16.1.1 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
16.1.2 SAR ADCs with Multibit Quantizers . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
16.1.3 Hybrid Flash/SAR ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
16.2 DAC Complexity Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
16.2.1 Monotonic Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
16.2.2 Three-Level Bottom-Plate Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

17 Fundamentals of Pipelined ADCs 353

17.1 Binary Search Revisited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
17.2 Basic Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
17.3 Brief Review of Op Amp Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
17.4 Precision Multiply-by-2 Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
17.4.1 Non-Flip-Around Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
17.4.2 Flip-Around Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
17.5 Multiplying DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
17.5.1 Non-Flip-Around MDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
17.5.2 Flip-Around MDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
17.6 Basic Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
17.7 Concept of Residue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
17.8 Multibit Pipelined Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
17.9 Comparison of SAR and Pipelined ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

18 Nonidealities in Pipelined ADCs 383

18.1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
18.1.1 MDAC Nonidealities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
18.1.2 Residue Manipulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
18.2 Effect of Comparator Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
18.2.1 Offset in the First Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
18.2.2 Offset in Second Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
18.3 Effect of Op-Amp Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
18.4 Effect of Switch Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
18.4.1 Charge Injection in Non-Flip-Around MDAC . . . . . . . . . . . . . . . . . . . . . . . 393
18.4.2 Charge Injection in Flip-Around MDAC . . . . . . . . . . . . . . . . . . . . . . . . . . 394
18.5 kT/C Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
18.5.1 Non-Flip-Around MDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
18.5.2 Flip-Around MDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
18.6 Effect of Op-Amp Nonidealities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
18.6.1 Finite Output Impedance and Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . 396
18.6.2 Finite Op-Amp Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
18.6.3 Op-Amp Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
18.7 Effect of Capacitor Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
18.8 Effect of the Reference Bounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
18.9 Timing Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

19 Advanced SAR and Pipelining Techniques 418

19.1 Overlap in Hybrid Flash/SAR ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
19.1.1 Comparator Offset Revisited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

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19.1.2 Overlap and Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

19.1.3 Effect of Timing Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
19.1.4 Residue in Hybrid Flash/SAR ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
19.1.5 Effect of SAR Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
19.2 1.5-Bit/Stage Pipelined ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
19.2.1 Basic Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
19.2.2 Residue Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
19.2.3 Cascade Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
19.2.4 Omission of Resistor Ladder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
19.3 Open-Loop Residue Amplification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
19.4 Hybrid SAR/Pipelined ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
19.4.1 Hybrid Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
19.4.2 Hybrid Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
19.4.3 Hybrid Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
19.4.4 Hybrid Example 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

20 Interleaved ADCs 439

20.1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
20.1.1 Basic Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
20.1.2 Advantages of Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
20.1.3 Disadvantages of Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
20.2 Effect of Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
20.2.1 Offset Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
20.2.2 Gain Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
20.2.3 Phase Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
20.2.4 Bandwidth Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
20.3 Charge Sharing and Interchannel Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
20.4 Interleaving Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
20.4.1 Two-Rank Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
20.4.2 Reduction of Interchannel Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
20.5 Interchannel Mismatch Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
20.5.1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
20.5.2 Foreground and Background Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 460
20.5.3 Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
20.5.4 Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
20.5.5 Phase Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
20.6 Clock Generation for Interleaved ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

21 Introduction to Oversampling ADCs 479

21.1 Quantization Noise Revisited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
21.2 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
21.2.1 Q-Noise Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
21.2.2 Noise in a Feedback System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
21.2.3 Simple Noise-Shaping ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
21.2.4 Noise Shaping in Time Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
21.3 Discrete-Time ∆Σ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
21.3.1 Discrete-Time Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
21.3.2 First-Order ∆Σ Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
21.3.3 Q-Noise Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
21.4 Continuous-Time First-Order ∆Σ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
21.5 Second-Order ∆Σ Modulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
21.5.1 Basic Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

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21.5.2 Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

21.5.3 Total Quantization Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
21.6 Advantages of Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
21.6.1 General Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
21.6.2 CT Modulator Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
21.7 Disadvantages of Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
21.8 Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
21.9 Properties of 1-Bit Quantizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

22 Basic Design of ∆Σ Modulators 509

22.1 First-Order DT Loop Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
22.1.1 Improved DT Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
22.1.2 First-Order Loop with 1-Bit Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
22.2 Second-Order DT Loop with 1-Bit Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
22.2.1 SNR Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
22.2.2 Additional Insights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
22.3 First-Order Continuous-Time Loop Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
22.3.1 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
22.3.2 Loop Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
22.3.3 SNR Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
22.4 Second-Order Continuous-Time Loop Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
22.4.1 SNR Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
22.4.2 Integrator Output Swings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
22.5 Generation of Nonoverlapping Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

23 Nonidealities in ∆Σ Modulators 534

23.1 DT Modulator Nonidealities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
23.1.1 Capacitor Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
23.1.2 kT /C Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
23.1.3 Op-Amp Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
23.1.4 Op-Amp Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
23.1.5 Op-Amp Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
23.1.6 Op-Amp Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
23.1.7 Comparator Offset and Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
23.1.8 Reference Settling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
23.1.9 Clock Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
23.2 Problem of Idle Tones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
23.3 Noise Folding Due to Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
23.4 CT Modulator Nonidealities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
23.4.1 Slewing at Op Amp Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
23.4.2 Noise Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
23.4.3 Resistive Load at Op Amp Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
23.4.4 Clock Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
23.4.5 Comparator Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
23.5 Stability Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

24 Advanced Oversampling ADCs 559

24.1 Cascaded Modulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
24.1.1 Basic Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
24.1.2 Higher-Order Cascades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
24.1.3 Problem of Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
24.1.4 Remedies for Gain Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565

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24.2 ∆Σ Modulators with Multibit Quantizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567

24.2.1 Basic Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
24.2.2 Problem of DAC Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
24.2.3 Data-Weighted Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
24.3 Modulators with Feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
24.4 Decimation Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
24.4.1 Basic Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
24.4.2 Counter-Based Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

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Preface

Data converters are an integral part of most electronic systems and play a key role in communications and
signal processing. Examples include wireless and wireline transceivers, imaging applications, audio and video
processing, and instrumentation. Despite decades of development, data converters continue to present new
challenges as we push for higher speeds and lower power consumption.
Since I published my first book, Principles of Data Conversion System Design, in 1995, the field of data
converters has grown and evolved dramatically. Owing to extensive work by industry and academia over the
past 30 years, many new design techniques have been introduced at both the circuit level and the architecture
level. Moreover, new analysis techniques have been developed that offer deeper insights. A completely new
book was therefore due.
This textbook addresses the need for a detailed, accessible treatment of data converters that can serve both
students and practicing engineers. Aiming for classroom adoption and/or self-study, the book offers hundreds
of analysis examples and end-of-chapter problems. In addition, it advocates a bottom-up synthesis mentality
by (a) describing how to build a complex system from elementary components such that the role of each
component is appreciated and (b) providing step-by-step transistor-level designs and simulations.
We begin with fundamental building blocks such as sampling circuits, comparators, and digital-to-
analog converters. Next, we deal with Nyquist-rate analog-to-digital converters (ADCs), focusing on flash,
successive-approximation, pipelined, and interleaved architectures. We then turn to oversampling converters,
introduce the concept of noise shaping, study the basic design of such architectures, and analyze their imper-
fections. We also present more advanced topics such as cascaded topologies and data-weighted averaging.
As with my previous books, I follow four pedagogical principles in writing. (1) I explain why the reader
needs to know the concepts to be studied. (2) I place myself in the reader’s shoes and predict the questions
and confusions that the reader may face while seeing these concepts for the first time. (3) I pretend to know
only as much as the reader and begin with the core of the concept so that I can hook the reader - even at the
cost of rigor. (4) I then add the necessary details so as to create a complete and rigorous picture.
This book is accompanied by a set of slides and a solutions manual.
Behzad Razavi

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Acknowledgments

I am indebted to numerous individuals who have assisted with the publication of this book. First, a band of
reviewers:

Pietro Andreani, Lund University Leonardo Papale, Eindhoven University of

Mostafa Ayesh, University of Southern California Technology
Ivor Chan, University of Macau Sharvil Patil, Analog Devices
Dong-Jin Chang, Chungnam National University Kevin Pelzers, Pelzers Integrated Circuits
Yujie Chen, UCLA Michael Pietzko, Universitat Ulm
Wood Chiang, Brigham Young University Chithira Ravi, Synopsys
Delong Cui, Broadcom Vishnu Ravinuthula, Texas Instruments
Denis Daly, Apple Stijn Ringeling, Eindhoven University of
Mohamed Darwish, Apple Technology
Manar El-Chammas, Omni Design Technologies Seung-Tak Ryu, KAIST
Ahmed Elshater, Mediatek Bibhu Sahoo, University at Buffalo
Brett Forejt, Texas Instruments Vineeth Sarma, Analog Devices
Miguel Gandara, Mediatek Remco Schalk, Eindhoven University of
Manideep Gande, Nvidia Technology
Yuji Gendai, THine Electronics Yuting Shen, NXP
Pieter Harpe, Eindhoven University of Hajime Shibata, Analog Devices
Technology Hyun Woo Shin, KAIST
Xiyu He, Tsinghua University Kwan Hoon Song, KAIST
Benjamin Hershberg, Intel Shiyu Su, University of Waterloo
Matias Jara, Broadcom Nan Sun, Tsinghua University
Paul Josef Kaesser, Universitat Ulm Charlie Tahar, KAIST
John Kauffman, Universitat Ulm Yunsong Tao, Tsinghua University
Guansheng Li, Broadcom Jonathan Ungethum, Universitat Ulm
Hanyue Li, IMEC Frank Van der Goes, Broadcom
Juzheng Liu, University of Southern California Stan van der Ven, IMEC
Kent Edrian Lozada, KAIST Hongrui Wang, Tsinghua University
Yanquan Luo, Tsinghua University Yujie Wang, UCLA
Raymond Mabilangan, KAIST Jan Westra, Broadcom
Ahmed Mahmoud, Universitat Ulm David-Peter Wiens, Universitat Ulm
Jan Mulder, Broadcom Haoming Xin, IMEC
Ali Nazemi, Broadcom Bishoy Zaky, Universitat Ulm
Dong-Ryeol Oh, Jeju National University Minglei Zhang, University of Macau
Kyle van Oosterhout, Eindhoven University of Qiaochu Zhang, University of Virginia
Technology Meiyi Zhou, IMEC
Henry Park, Mediatek Yan Zhu, University of Macau
Kun Woo Park, KAIST

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Acknowledgments xvii

My special thanks go to Pietro Andreani, who heroically reviewed the entire book and caught many mis-
takes. Grazie, Piero! In addition, Mike Chen, Pieter Harpe, Harry Lee, Rui Martins, Afshin Momtaz, Maurits
Ortmanns, Richard Schreier, and Nan Sun have contributed to this book.
I also wish to thank the staff at Cambridge University Press for their support during the production of the
book, particularly, Elizabeth Horne, Sarah Lewis, and Rachel Norridge.
My wife, Angelina, typed the entire book. I am very grateful to her.

Behzad Razavi

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About the Author

Behzad Razavi received the BSEE degree from Sharif University of Technology in 1985 and the MSEE and
PhDEE degrees from Stanford University in 1988 and 1992, respectively. He was with AT&T Bell Labora-
tories and Hewlett-Packard Laboratories until 1996. Since 1996, he has been Associate Professor and sub-
sequently Professor of electrical engineering at University of California, Los Angeles. His current research
includes wireless and wireline transceivers and data converters.
Professor Razavi was an Adjunct Professor at Princeton University from 1992 to 1994, and at Stanford
University in 1995. He served on the Technical Program Committees of the International Solid-State Circuits
Conference (ISSCC) from 1993 to 2002 and VLSI Circuits Symposium from 1998 to 2002. He has also
served as Guest Editor and Associate Editor of the IEEE Journal of Solid-State Circuits, IEEE Transactions
on Circuits and Systems, and International Journal of High Speed Electronics. He presently serves as the
Editor-in-Chief of the IEEE Solid-State Circuits Letters.
Professor Razavi received the Beatrice Winner Award for Editorial Excellence at the 1994 ISSCC, the
best paper award at the 1994 European Solid-State Circuits Conference, the best panel award at the 1995
and 1997 ISSCC, the TRW Innovative Teaching Award in 1997, the best paper award at the IEEE Custom
Integrated Circuits Conference in 1998, and the McGraw-Hill First Edition of the Year Award in 2001. He
was the co-recipient of both the Jack Kilby Outstanding Student Paper Award and the Beatrice Winner Award
for Editorial Excellence at the 2001 ISSCC. He received the Lockheed Martin Excellence in Teaching Award
in 2006, the UCLA Faculty Senate Teaching Award in 2007, and the CICC Best Invited Paper Award in 2009
and in 2012. He was the co-recipient of the 2012 and the 2015 VLSI Circuits Symposium Best Student Paper
Awards and the 2013 CICC Best Paper Award. He was also recognized as a top author in the 50-year and
75-year history of ISSCC. He received the 2012 Donald Pederson Award in Solid-State Circuits. He was also
the recipient of the American Society for Engineering Education PSW Teaching Award in 2014. Professor
Razavi is a member of the US National Academy of Engineering and a fellow of the National Academy of
Inventors. He received the 2017 IEEE CAS John Choma Education Award.
Professor Razavi has served as an IEEE Distinguished Lecturer and is a Fellow of IEEE. He is the author
of Principles of Data Conversion System Design (IEEE Press, 1995), RF Microelectronics (Prentice Hall,
1998, 2012) (translated to Chinese, Japanese, and Korean), Design of Analog CMOS Integrated Circuits
(McGraw-Hill, 2001, 2016) (translated to Chinese, Japanese, and Korean), Design of Integrated Circuits
for Optical Communications (McGraw-Hill, 2003, Wiley, 2012), Fundamentals of Microelectronics (Wiley,
2006) (translated to Korean, Portuguese, and Turkish), Design of CMOS Phase-Locked Loops (Cambridge,
2020), and the editor of Monolithic Phase-Locked Loops and Clock Recovery Circuits (IEEE Press, 1996),
and Phase-Locking in High-Performance Systems (IEEE Press, 2003).

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