SHRI G. S.

INSTITUTE OF TECHNOLOGY & SCIENCE

(An Autonomous Institute Affiliated to RGPV, Bhopal)

DEPT. OF ELECTRONICS & INSTRUMENTATION ENGG.

Session: -July-December-2024

LAB MANUAL-
VLSI DESIGN
(EI-47055)

SUBMITTED BY:- SUBMITTED TO:-

Ankit Lakra MS. NEHA ARYA
0801EI211010 (Ass. Prof. , Dept. of E & I.)
Electronics and Instrumentation
B. Tech IV Year ( 7th semester )
 SHRI G. S. INSTITUTE OF TECHNOLOGY & SCIENCE
(An Autonomous Institute Affiliated to RGPV, Bhopal)
DEPT. OF ELECTRONICS & INSTRUMENTATION ENGG.

Session: - July-December -2024

CERTIFICATE

Ankit Lakra
This is to certify that Mr. /Ms………………………………………
0801EI211010
Enrolment no………………………………………. studying in
B.Tech. VII semester in Electronics & Instrumentation
Engineering department of this institute has completed
practical course based on the syllabus and given a satisfactory
account of it in the notebook containing a record of the
laboratory work.

MS. NEHA ARYA

 INDEX
S. Date Date of Remarks &
Name of the Experiment Page No.
No. Submission Signature
24/07/24 Introduction to VHDL 1-5 31/07/24

Combinational Circuit Design Exercise

Write and simulate the VHDL
1 24/07/24 6-12 31/07/24
code for Logic Gates.
Implimentation of Half Adder
2 31/07/24 13-17 07/08/24
and Half Subtractor using VHDL.

07/08/24
Implimentation of Full Adder 18-29
3 14/08/24
using VHDL.
Implimentation of Full
4 14/08/24 30-38 28/08/24
Subtractor using VHDL.
Implimentation of Full Adder
5 28/08/24 39-42 04/09/24
using two Half Adder.
Implimentation of 2x4 and 3x8
6 04/09/24 43-60 11/09/24
Decoders using VHDL.
Implimentation of 8x3 and
7 11/09/24 61-70 25/09/24
Encoders using VHDL.
Implimentation of 4x1
8 25/09/24 71-79 09/10/24
multiplexer and using VHDL.

9 Implimentation of 1x4 18/10/24

09/10/24 80-81
Demultiplexer and using VHDL.

10

Sequential Circuit Design Exercise

Implimentation of various Flip-
1 18/10/24 82-93 18/10/24
Flops using VHDL.
Implement design of synchronous
2 18/10/24 94-96 18/10/24
8 – bit Johnson Counter.

3 18/10/24 Design of MOD 16 up counter. 97-99 18/10/24

Design of MOD 16 up-down

4 18/10/24 counter.
100-102 18/10/24

APPENDIX A BASYS3 FPGA Board Reference Manual

103-104
APPENDIX B
Introduction to VHDL
What is VHDL?

• VHDL is a short form of VHSlC Hardware Description Language where VHSIC stands for
Very High Speed Integrated Circuits
It’s a hardware description language – means it describes the behavior of a digital circuit, and
•
also it can be used to derive or implement a digital circuit/system hardware
It can be used for digital circuit synthesis as well as simulation.
•
It is used to build digital system/circuit using Programmable Logic Device like CPLD (
•
Complex Programmable Logic Device) or FPGA (Field Programmable Gate Array)
VHDL program (code) is used to implement digital circuit inside CPLD / FPGA, or it can be
•
used to fabricate ASIC (Application Specific Integrated Circuit)
It is very useful in developing high end, sophisticated microprocessor or micro-controller like
• ASIP (Application Specific Instruction Processor) or PSoC (Programmable System on Chip)

Now before going into more details about VHDL, let us first see how and why there was a need for
VHDL.
Why VHDL?
• In 1980’s US DoD (Department of Defence) initiated the VHSIC program
• Different hardware designing companies started developing their ICs with their own HDL. All
companies had their own and different HDL
So the problem was all these different companies cannot exchange their code and designs with
•
another.
Also, all companies provide their chip design to DoD with different HDL
•
So there was a requirement to standardized hardware description language for digital
• circuit/system design, documentation, and verification.

Advantages of VHDL
• Its vendor-independent
• It is portable
• It is reusable
• It supports hierarchical design – whole big and complex system can be modelled as an
interconnection of small components, and again components can be further modelled as an
interconnection of subcomponents

• All statements of VHDL program are executed concurrently (unless and until the statements
are placed inside procedure, function or process)
• It is human-readable as well as machine-readable

• It is IEEE and ANSI standard

• Supports different design methodologies like top-down, bottom-up, mix, etc

 • Can be used to design combinational, sequential or mixed digital circuits using three different
methods 1) dataflow 2) behavioural 3) structural
Brief history of VHDL origin

• In 1985 the first version of VHDL 7.2 was developed by IBM, TEXAS INST. and Intermatrix
under a contract of DoD
• In 1987 it was standardized by IEEE with IEEE 1076 standard. After then new standard IEEE
1164 was given to VHDL that is now a day’s used everywhere
• ANSI also recognizes VHDL, and standard VHDL reference manual is made available by IEEE
that has an official description of this VHDL

Now after getting enough information about VHDL, let us move ahead with designing digital circuits
using VHDL.
Here once again, before moving further, I advice all of you to go through two very good books on
VHDL.

• Circuits design using VHDL by V A Pedroni

• A VHDL Primer by J Bhaskar
These books will give you complete information about VHDL and serves as a companion in

your
journey
advise to learn VHDL. The information given above was also taken from these two books. I also
you to continuously refer these books as you move further with this VHDL tutorial series. So I
think, now you all are very excited to learn VHDL. Let us first see how to design a digital circuit
using VHDL means, “What is the flow of VHDL design?”
VHDL Design Flow
 1. VHDL design flow starts with writing the VHDL program. Various manufacturing
companies like XILINX, Altera, etc. provide their own software development tools like
XILINX ISE, Altera Quartus, etc. to edit, compile, and simulate VHDL code. In this VHDL
code, the circuit is described in RTL (Resister Transfer Level)
2. This VHDL code is compiled, and it generates Netlist at Gate level. The compiler converts
high-level VHDL code in RTL to Gate Level
3. This Netlist is further optimized to get optimized Netlist again at Gate Level. Optimization is
done for better speed and less space. The simulation of design is done at this stage
4. Finally, a physical device is implemented on CPLD / FPGA, or final MASK is prepared for
ASIC from this optimize Netlist by place and route software (fitter). once again the final device
can be simulated and verified
This is the digital circuit design flow using VHDL. Now because VHDL is also one kind of
programming language, it also has its program structure (similar to other programming languages like
C program structure). So as a next step, let us learn what the VHDL program structure is?
VHDL Program Structure

• All the VHDL programs consist of at least two components: Entity and Architecture
• It may have additional components like configuration, package declaration, body, etc. as per
requirements

The structure of the VHDL program is like:

Library declaration:

• The library contains all the piece of code that is used frequently. It will allow us to reuse them
again and again. Also, this can be shared with other designs
• It starts with keyword LIBRARY followed by library name

• There are three libraries usually used in all VHDL codes

1. IEEE – specifies multilevel logic system

 2. std – resource library for VHDL design environment
3. work – used for saving our project work and program file (.vhd)

• However, in program code, we need to declare only the IEEE library because the other two
libraries are default libraries
Now to add library packages and its part USE keyword is used with library name, library
•
packages, and package parts. For example in the IEEE library, the package is std_logic_1164
and to add all its part we can write

LIBRARY ieee
USE ieee.std_logic_1164.all
• So all VHDL programs start with above two statements for library declaration
Entity declaration:

• Entity defines input-output connections of the digital circuit with which it can interact
with other components/circuits
• It declares the number of inputs given to the circuit and the number of outputs taken

out form
•
the circuit.
• Also, it declares any intermediate signals that are used within the circuit itself.
Entity declaration starts with the keyword ENTITY. The user has to give desire name to
entity
often related to a circuit that is being designed like ‘mux,’ ‘decoder,’ ‘adder,’ ‘counter’
• etc.
(the rule of thumb for any VHDL program is the program file name must be same as
•
entity
name)
Inside entity, input-output pins of a circuit are declared using keyword PORT
PORT (means interfacing pins) are declared with port_name, port_mode, and port_type

1. port_name – it’s a user-defined name of the input-output pin

2. port_mode – there are four types of port mode IN, OUT, INOUT and BUFFER. IN
indicates an input pin, that can be read-only. OUT indicates an output pin and its
write-
only. Both these pins are unidirectional. INOUT pin is bidirectional that can be read as
well as write. BUFFER is used for the intermediate output
3. port_type – it can be BIT, BIT_VECTOR, STD_LOGIC, etc
• After declaring all interfaces, the entity declaration ends with keyword END followed by entity
name
• Let us see an entity example for two-input AND gate.

• Similarly, we can write an entity for half adder as

Architecture:
• Architecture declares the functionalities of the digital circuit
• It gives internal details of an entity that means how input-output are interconnected
• It describes behaviour of the circuit means how the circuit generates required output from given
inputs
The architecture declaration starts with keyword ARCHITECTURE followed by
•
architecture_name and entity_name
The BEGIN keyword indicates the starting of the architecture body. The body includes
•
sequential or concurrent statements that describe circuit functionality
The architecture body ends with keyword END followed by architecture_name
•
Here is the architecture of 2 input AND gate (the entity is as given above).
•

• Similarly, let us write architecture for half adder.

• There are three different modelling styles for architecture body

1. Data flow style – in this modelling style the circuit is described using concurrent
statements
2. Behavioral style – in this modelling style the circuit is described using sequential
statements
3. Structural style – in this modelling style the circuit is described using different
interconnected components
• There can be one more modelling style also that is mix modelling style – a combination of any
two or all three styles given above.
Combinational Circuit Design Exercise
Experiment-1
Aim: Write and simulate the VHDL code for Logic Gates
i) AND Gate
Code: -

Simulation: -

RTL Schematic: -
 ii) OR Gate

Code: -

Simulation: -

RTL Schematic: -
 iii) NAND Gate

Code: -

Simulation: -

RTL Schematic: -
 iv) NOR Gate
Code: -

Simulation: -

RTL Schematic: -
 v) XOR Gate
Code: -

Simulation: -

RTL Schematic: -
 vi) XNOR Gate
Code: -

Simulation: -

RTL Schematic: -
 vii) NOT Gate
Code: -

Simulation: -

RTL Schematic: -
 Experiment-2
Aim: Implimentation of Half Adder and Half Subtractor using
VHDL
i) Half Adder
Code:-

Simulation: -
RTL Schematic: -

Project Summary-
ii) Half Subtractor
Code: -
Simulation: -

RTL Schematic: -
Project Summary-
 Experiment -3
Aim: Implimentation of Full Adder using VHDL
i) Data Flow Model

Code:-

Simulation: -
RTL Schematic: -

Project Summary-
ii) Behavioural Modelling

Code:-
Simulation:-

RTL Schematic:-
Project Summary-
 iii) Sturctural Modeling
Code:-
Simulation:-

RTL Schematic:-
Project Summary:-
 iv) FPGA Board Implimentation

Code:-

Basys-3-Master.xdc:-
Project Summary:-
Board:-
 Experiment-4
Aim: Implimentation of Full Subtractor using VHDL
i) Data Flow Model
Code:-

Simulation:-
RTL Schematic:-

Project Summary:-
 ii) Behavioural
Code:-
Simulation:-

RTL Schematic:-
Project Summary:-
 iii) Structural Modelling
Code:-
Simulation:-

RTL Schematic:-
Project Summary:-
 Experiment-5
Aim: Implimentation of Full Adder using two Half Adder
i) OR28.vhd
Code:-

ii) HalfAdder.vhd
 iii) fullAdder_using_halfAdder.vhd

Simulation:-
RTL Schematic:-

Project Summary:-
 Experiment-6
Aim: Implimentation of 2x4 and 3x8 Decoders using VHDL (Structural,
Dataflow, Behavioural Modelling)

i) 2x4 Decoder

i) Data Flow Model

Code:-

Simulation:-
RTL Schematic:-

Project Summary:-
 ii) Behavioural Model

Code:-
Simulation:-

RTL Schematic:-
Project Summary:-
 iii) Structural Modelling

Code:-
Simulation:-

RTL Schematic:-
Project Summary:-
 ii) 3x8 Decoder

i) Data Flow Model

Code:-
Simulation:-

RTL Schematic:-
Project Summary:-
 ii) Behavioural Model
Code:-
Simulation:-

RTL Schematic:-
Project Summary:-
 iii) Structural Model
Code:-
Simulation:-

RTL Schematic:-
Project Summary:-
 Experiment-7
Aim: Implimentation of 8x3 and Encoders using VHDL (Structural, Dataflow,
Behavioural Modelling)

i) Data Flow Model

Code:-
Simulation:-

RTL Schematic:-
Project Summary:-
 ii) Behavioural Model
Code:-
Simulation:-
RTL Schematic:-
Project Summary:-
 iii) Structural Model
Code:-
Simulation:-

RTL Schematic:-
Project Summary:-
 Experiment-8
Aim: Implimentation of 4x1 multiplexer and using VHDL (Structural, Dataflow,
Behavioural Modelling)

i) Data Flow Model

Code:-

Simulation:-
RTL Schematic:-

Project Summary:-
 ii) Behavioural Model
Code:-

Simulation:-
RTL Schematic:-

Project Summary:-
 iii) Structural Model
Code:-
Simulation:-

RTL Schematic:-
Project Summary:-
 Experiment-9
Aim: Implimentation of 1x4 Demultiplexer and using VHDL(Dataflow
modelling)

i) Data Flow Model

Code:- library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity demux_tb is
end entity;
architecture tb of demux_tb is
component DEMUX_SOURCE is
Port ( I,S : in STD_LOGIC;
O1, O2 : out STD_LOGIC);
end component;

signal I, S, O1, O2 : STD_LOGIC;

begin
uut: DEMUX_SOURCE port map(
I => I, S => S,
O1 => O1, O2 => O2);
stim: process
begin
I <= '0';
S <= '0';
wait for 20 ns;
S <= '1';
wait for 20 ns;
I <= '1';
S <= '0';
wait for 20 ns;
S <= '1';
wait for 20 ns;
wait;
end process;
end tb;

Simulation:-
RTL Schematic:-

Project Summary:-
Sequential Circuit Design Exercise
Experiment-1
Aim: Implimentation of various Flip-Flops using VHDL (if-then-else) Sequential
constructs.

i) SR Flip-Flop
Code:-
Simulation:-

RTL Schematic:-
Project Summary:-
 ii) JK Flip-Flop
Code:-
Simulation:-

RTL Schematic:-
Project Summary:-
 iii) D Flip-Flop
Code:-

Simulation:-
RTL Schematic: -

Project Summary: -
 iv) T Flip-Flop
Code: -

Simulation: -
RTL Schematic: -

Project Summary: -
 Experiment-2
Aim: Implement design of synchronous 8 – bit Johnson Counter.

Code:-
Simulation:-

RTL Schematic:-
Project Summary: -
 Experiment-3
Aim: Design of MOD 16 up counter.

Code:-
Simulation: -

RTL Schematic: -
Project Summary: -
 Experiment-4
Aim: Design of MOD 16 up-down counter.

Code:-
Simulation: -

RTL Schematic: -
Project Summary: -
 ## This file is a general .xdc for the Basys3 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

## Clock signal
#set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk]
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

## Switches
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {sw[0]}]
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {sw[1]}]
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}]
#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}]
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}]
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {sw[5]}]
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports {sw[6]}]
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {sw[7]}]
#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {sw[8]}]
#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}]
#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}]
#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}]
#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {sw[12]}]
#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {sw[13]}]
#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}]
#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {sw[15]}]

## LEDs
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {led[0]}]
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports {led[1]}]
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports {led[2]}]
#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports {led[3]}]
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports {led[4]}]
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports {led[5]}]
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports {led[6]}]
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports {led[7]}]
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports {led[8]}]
#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports {led[9]}]
#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports {led[10]}]
#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports {led[11]}]
#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports {led[12]}]
#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports {led[13]}]
#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports {led[14]}]
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {led[15]}]

##7 Segment Display

#set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {seg[0]}]
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {seg[1]}]
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {seg[2]}]
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {seg[3]}]
#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {seg[4]}]
#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {seg[5]}]
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {seg[6]}]

#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports dp]

#set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {an[0]}]

#set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {an[1]}]
#set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {an[2]}]
#set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {an[3]}]

##Buttons
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC]
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU]
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL]
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports btnR]
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports btnD]

##Pmod Header JA
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports {JA[0]}];#Sch name = JA1
#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports {JA[1]}];#Sch name = JA2
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports {JA[2]}];#Sch name = JA3
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports {JA[3]}];#Sch name = JA4
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports {JA[4]}];#Sch name = JA7
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {JA[5]}];#Sch name = JA8
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports {JA[6]}];#Sch name = JA9
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports {JA[7]}];#Sch name = JA10
 ##Pmod Header JB
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports {JB[0]}];#Sch name = JB1
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports {JB[1]}];#Sch name = JB2
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports {JB[2]}];#Sch name = JB3
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {JB[3]}];#Sch name = JB4
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports {JB[4]}];#Sch name = JB7
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports {JB[5]}];#Sch name = JB8
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports {JB[6]}];#Sch name = JB9
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {JB[7]}];#Sch name = JB10

##Pmod Header JC
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {JC[0]}];#Sch name = JC1
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {JC[1]}];#Sch name = JC2
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports {JC[2]}];#Sch name = JC3
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports {JC[3]}];#Sch name = JC4
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports {JC[4]}];#Sch name = JC7
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports {JC[5]}];#Sch name = JC8
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports {JC[6]}];#Sch name = JC9
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports {JC[7]}];#Sch name = JC10

##Pmod Header JXADC

#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[0]}];#Sch name = XA1_P
#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[1]}];#Sch name = XA2_P
#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[2]}];#Sch name = XA3_P
#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[3]}];#Sch name = XA4_P
#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[4]}];#Sch name = XA1_N
#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[5]}];#Sch name = XA2_N
#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[6]}];#Sch name = XA3_N
#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[7]}];#Sch name = XA4_N

##VGA Connector
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}]
#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}]
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}]
#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}]
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}]
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}]
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}]
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}]
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}]
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}]
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}]
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}]
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports Hsync]
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports Vsync]

##USB-RS232 Interface
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports RsRx]
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports RsTx]

##USB HID (PS/2)

#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Clk]
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Data]

##Quad SPI Flash

##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
##STARTUPE2 primitive.
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[0]}]
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[1]}]
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[2]}]
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[3]}]
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports QspiCSn]

## Configuration options, can be used for all designs

set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

## SPI configuration mode options for QSPI boot, can be used for all designs
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]