Lecture 19,20,21 - Digital Logic Design (DLD)
Functions of Combinational Logic
Fall 2022
3
Course Instructor: Engr.
InamNabeeha
Junejo Ehsan
Digital Fundamentals by Floyd - Chapter 6: Topic 6-1, 6-2, 6-3, 6-4, 6-5, 6-6, 6-7, 6-8, 6-9
Outline
• Combinational Logic
• Adders (Half and Full)
• Parallel Binary adders
• Ripple Carry Adder
• Look-ahead Carry Adder
• Subtractor (Half and Full)
• Comparator
• Decoder
• Encoder
• Multiplexer
• DeMultiplexer
Combinational Logic
• A combinational circuit consists of logic gates whose outputs at any time are
determined by logic operations on current input values.
• A combinational circuit performs an operation that can be specified logically by a
set of Boolean equations.
• In contrast the other type of circuits which uses Sequential logic, is the function
of the inputs and the bit values in the storage elements (Stored elements are
those which are processed earlier).
• Means the output of a sequential circuit depends not only on the current input
values but also on past inputs.
• We will study Sequential Logic in detail in coming lectures.
• A Combinational circuit consists of input variables, output variables, logic gates
and interconnections. The interconnected logic gates accept signals from the
inputs and generate signals at the outputs.
• There are several functions of Combinational circuits, such as Adding the
numbers together (Adders), Comparing the numbers together (Comparators),
Converting the numbers from one system into other (Decoders and Encoders),
Selection and deselection of data into serial and parallel lines (Multiplexers and
Demultiplexers).
Adders
• Every digital system uses addition and multiplication to process basic arithmetic
operation.
• A combinational circuit that performs the addition of two or three or more bits
are called adders (Using additive laws that we have studied earlier).
• A two bit adder is called a half adder, sometimes a half adder leaves a carry
behind, which adds to other two bits in the next half adder.
• One that performs the addition of three bits (two significant bits and a previous
carry) is a full adder.
Half Adder
• A half adder is constructed of two binary inputs and two binary outputs. The
input variables are designate as “the augend” and “the addend” bits. The output
variables produces the “sum – S” and “carry – C”.
From truth table, we can determine the Boolean expressions of SUM and CARRY and also can
design the logic circuit for half adder.
ҧ + 𝐴𝐵ത
= 𝐴𝐵
=𝐴 ⊕ 𝐵
𝐶𝑜𝑢𝑡 = 𝐴𝐵
Full Adder
• A full adder adds three bits together (two significant bits and a previous carry).
Implementation of Full Adder in Sum of Product form can be formed using truth table.
𝐴ҧ𝐵𝐶
ത
𝐴
= 𝐴ҧ𝐵𝐶 ҧ 𝐶ҧ + 𝐴𝐵ത 𝐶ҧ + 𝐴𝐵𝐶
ത + 𝐴𝐵
𝐴ҧ ҧ 𝐶ҧ
𝐴𝐵
𝐶𝑜𝑢𝑡 = 𝐴𝐵𝐶ҧ ത + 𝐴𝐵 𝐶ҧ + 𝐴𝐵𝐶
+ 𝐴𝐵𝐶
𝐵 Σ
ҧ ത + 𝐴𝐵 𝐶ҧ 𝐵ത
𝐶𝑜𝑢𝑡 = 𝐴𝐵𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶
𝐴𝐵ത 𝐶ҧ
𝐶𝑜𝑢𝑡 = 𝐵𝐶 𝐴ҧ + 𝐴 + 𝐴𝐵𝐶 ത + 𝐴𝐵𝐶ҧ 𝐶
𝐶𝑜𝑢𝑡 = 𝐵𝐶 + 𝐴𝐵𝐶ത + 𝐴𝐵𝐶ҧ
𝐶ҧ 𝐴𝐵𝐶
𝐶𝑜𝑢𝑡 = 𝐶 𝐵 + 𝐴𝐵ത + 𝐴𝐵𝐶ҧ
𝐶𝑜𝑢𝑡 = 𝐶 𝐴 + 𝐵 + 𝐴𝐵 𝐶ҧ
𝐶𝑜𝑢𝑡 = 𝐴𝐶 + 𝐵𝐶 + 𝐴𝐵 𝐶ҧ
𝐶𝑜𝑢𝑡 = 𝐴𝐶 + 𝐵 𝐶 + 𝐴𝐶ҧ 𝐴 𝐴𝐵
𝐶𝑜𝑢𝑡 = 𝐴𝐶 + 𝐵(𝐴 + 𝐶) 𝐵
𝐶𝑜𝑢𝑡 = 𝐴𝐶 + 𝐴𝐵 + 𝐵𝐶 𝐶𝑜𝑢𝑡
𝐶 𝐴𝐶
𝐵𝐶
Logic required to form a Full Adder
= (𝐴 ⊕ 𝐵) ⊕ 𝐶𝑖𝑛
Complete Logic Circuit for a Full Adder
In other words
two half adders
form a full adder
𝑪𝒐𝒖𝒕 = 𝑨𝑩 + (𝑨 ⊕ 𝑩)𝑪𝒊𝒏
Full Adder Logic Symbol
Parallel Binary Adders
Two or more full adders are connected to form a Parallel Binary Adders.
2nd FA for 2nd Column
1st FA for 1st Column
Four bit Parallel Adder: Two Nibbles adder
C4 C3 C2 C1 C0
A4 A3 A2 A 1
B4 B3B2 B1
Σ4 Σ3 Σ2 Σ1
Parallel Adder IC
74LS283 4-Bit Parallel Adder
Ripple Carry Adder
A Ripple Carry Adder is one in which the carry output of each full adder is connected to
the carry input of the next higher order stage (a stage is one full adder).
The sum and the output of any stage
cannot be produced until the input carry
occurs, which causes a time delay in the
addition process.
The carry propagation delay for each
full-adder is the time from the application
of the input carry to the output carry
occurs.
Look Ahead Carry Adder
• To eliminate ripple carry delay, full adders use Look-ahead Carry. This logic anticipates
the output carry of each stage by its inputs.
• There are two ways that Look-ahead Carry adder produces the output carry:
1) Carry Generation 2) Carry Propagation.
Carry Generation: Occurs when an output carry is produced (generated) internally by the
full-adder, when both of its input bits are 1s. The generated carry, CG, is expressed as the
AND function of the two input bits A and B.
CG = AB
Carry Propagation occurs when the input carry is rippled to become the output carry.
An input carry may be propagated by the full adder when either or both of the input
bits are 1s. The propagated carry, Cp, is expressed as the OR function of the input bits.
Cp = A+B
Comparator
• The basic function of comparator is to compare the magnitude of two binary
quantities to determine the relationship between them.
• If A and B are to be compared together, the outcome of the comparison is
specified by three binary variables that indicates whether A>B, A=B, or A<B.
• One of the gate which is able to compare two values and give output accordingly
is the exclusive-OR gate, whose output is 0 when both inputs are same and 1
when both are inverted to eachother.
The expression for XOR is
ҧ + 𝐴𝐵ത
𝐴𝐵
A<B A>B
XOR can give us information whether A>B or A<B but for A=B, we will have to complement
the whole equation, which will be XNOR gate, as it outputs high when both the inputs are
equal:
ҧ + 𝐴𝐵ത
𝐴𝐵 A=B
Lets design the Circuit and analyze it by placing input combinations in above equation
ҧ (A<B)
A B 𝐴𝐵 𝐴𝐵ത (A>B) ҧ + 𝐴𝐵ത
𝐴𝐵 ҧ + 𝐴𝐵ത (A=B)
𝐴𝐵
0 0 0 0 0 1
0 1 1 0 1 0
1 0 0 1 1 0
1 1 0 0 0 1
Example related to Equal or Not Equal Condition
A1 A0
B1 B0
XNOR XNOR
2 1
AND
4 bits (Nibble) Magnitude Comparator 8 bits (Word) Magnitude Comparator
74LS85
74LS85 Pin Layout
Pin 2-4 Cascading Inputs
Comparator IC
74HC85 4-Bit Magnitude Comparator
Decoder
• Decoder is a digital combinational circuit that detects the presence of a specified
combinations of bits (code) on its input and indicates the presence of that code by a
specified output level.
• A binary code of ‘n’ bits is capable of representing up to ‘2n’ distinct elements of
coded information.
• A decoder has n-bit binary code applied to its inputs and a m-bit binary code
appearing at the outputs and the functional blocks which implements decoding are
classed n-to-m-line decoders.
1-2 Line Decoder
Basic Binary Decoder
Suppose we need to determine when a binary 1001 occurs on the input of a digital circuit.
We need to design a logic which detects 1001 and give the output 1, otherwise 0.
AND gate is used in the
end to make sure the Positive
20
output is 1 when all the Logic
21
inputs are 1.
For negative logic we can use
22
NAND gate at the end, which will
23 output 0 when detects the specific
binary code, 1 otherwise.
Similarly if we need to detect the 0101 binary code, then the logic circuit will become:
1 1
1 0
0 1 1 0
1 1
1 1
0 0
𝑋 = 𝐴4. 𝐴3. 𝐴2. 𝐴1. 𝐴0
3 to 8 line Decoder
D0 0
D1 1
D2 2
D3 3
D4 4
D5 5
D6 6
D7 7
4 to 16 line Decoder
(Home Work – Truth Table & Logic Circuit)
Binary Coded Decimal (BCD) Number System
In BCD Number System, each decimal digit 0 through 9, is represented by a binary code
of 4 bits. This system is also known as 8421 code system, which is the weight of each bit
in the combination.
Binary Coded Decimal (BCD) to Decimal Decoder
BCD code is always a 4 bit code and Decimal number system is 0-9, which means this logic has to be 4-10
lines or 4-16 according to the 2n rule.
K-map for BCD to Decimal System
LSB
CD (𝐶ҧ 𝐷
ഥ) ҧ
(𝐶𝐷) (𝐶𝐷) ഥ)
(C𝐷
MSB AB 00 01 11 10
(𝐴ҧ𝐵)
ത 00 1 1 1 1
𝐴ҧ 𝐵ത 𝐶ҧ 𝐷
ഥ 0 𝐴ҧ𝐵ത 𝐶𝐷
ҧ 1 𝐴ҧ𝐵𝐶𝐷
ത 3 𝐴ҧ𝐵𝐶
ത 𝐷ഥ 2
ҧ
(𝐴𝐵) 01 1 1 1 1
ҧ 𝐶ҧ 𝐷
𝐴𝐵 ഥ ҧ 𝐶𝐷
4 𝐴𝐵 ҧ ҧ
5 𝐴𝐵𝐶𝐷 ҧ 𝐷
7 𝐴𝐵𝐶 ഥ 6
(𝐴𝐵) 11 X X X X
𝐴𝐵 𝐶ҧ 𝐷
ഥ ҧ
12 𝐴𝐵 𝐶𝐷 13 𝐴𝐵𝐶𝐷 ഥ
15 𝐴𝐵𝐶 𝐷 14
ത
(A𝐵) 10 1 1 X X
𝐴𝐵ത 𝐶ҧ 𝐷
ഥ ҧ
8 𝐴𝐵ത 𝐶𝐷 ത
9 𝐴𝐵𝐶𝐷 ത 𝐷
11 𝐴𝐵𝐶 ഥ 10
ഥ 𝑨 𝑩
𝑨 ഥ 𝑪 𝑫
ഥ 𝑩 𝑪 ഥ 𝑫
ഥ𝑩
𝑨 ഥ𝑪ഥ𝑫
ഥ
D0 0
ഥ𝑩
𝑨 ഥ𝑫
ഥ𝑪
D1 1
ഥ
𝑨
ഥ𝑩
𝑨 ഥ 𝑪𝑫
ഥ
𝑨 D2 2
ഥ
𝑩
ഥ𝑩
𝑨 ഥ 𝑪𝑫
D3 3
𝑩
ഥ
𝑪 ഥ 𝑩𝑪
𝑨 ഥ𝑫
ഥ
D4 4
𝑪
ഥ
𝑫 𝑨 ഥ
ഥ 𝑩𝑪𝑫
D5 5
𝑫 ഥ 𝑩𝑪𝑫ഥ
𝑨
D6 6
ഥ 𝑩𝑪𝑫
𝑨
D7 7
D7
ഥ𝑪
𝑨𝑩 ഥ𝑫
ഥ
D8 8
ഥ
ഥ 𝑪𝑫
𝑨𝑩
D9 9
Decoding a Combinational Logic Expression/Truth Table/minterms/maxterms
Similarly we can decode the given logic expression into a decoder circuit
𝑋 = 𝐴ҧ𝐵ത 𝐶ҧ 𝐷
ഥ + 𝐴ҧ𝐵𝐶𝐷
ത ത
+ 𝐴𝐵𝐶𝐷 ҧ 𝐷
+ 𝐴𝐵𝐶 ഥ + 𝐴𝐵𝐶ҧ 𝐷
ഥ
We can also decode any Truth Table into a decoder circuits
A B C D O/P
0 0 0 1 𝐴ҧ𝐵ത 𝐶𝐷
ҧ
0 1 0 0 ҧ 𝐶ҧ 𝐷
𝐴𝐵 ഥ
0 1 0 1 𝐴𝐵ҧ 𝐶𝐷
ҧ
0 1 1 0 ҧ 𝐷
𝐴𝐵𝐶 ഥ
We can also decode any minterms and maxterms expressions into a decoder circuit.
𝑋 = 𝑚 (0,1,2,5,6,8) 𝑋 = ෑ 𝑀 (3,4,7)
Example: Implement a full adder circuit with a decoder by decoding Sum and Carry outputs.
𝑆𝑢𝑚 𝐴, 𝐵, 𝐶𝑖𝑛 = න(1,2,4,7)
𝐶𝑎𝑟𝑟𝑦 𝐴, 𝐵, 𝐶𝑖𝑛 = න(3,5,6,7)
As there are three inputs and total of minterms, therefore we need a 3-to-8
line decoder
𝐶𝑖𝑛
Port Address Decoder
74HC1541
4-to-16
decoder
IC forms of difference Combinations Circuits
74H154 1-of-16 Decoder
IC forms of difference Combinations Circuits
IC forms of difference Combinations Circuits
𝐿𝑇 = Lamp Test = When its low and 𝐵𝐼/𝑅𝐵𝑂 is high, all the segments will be
High. So it should be high to verify that all the segments are in working
condition.
𝑅𝐵𝐼 (Ripple Blank Input), 𝐵𝐼 (𝐵𝑙𝑎𝑛𝑘 𝐼𝑛𝑝𝑢𝑡)/𝑅𝐵𝑂(Ripple Blank Output) are
used to suppress the unnecessary zero’s in multi-digits display.
74LS47 BCD-to-7-Segment Decoder
Illustration of Leading Zero Suppression
IC forms of difference Combinations Circuits
𝐿𝑇 = Lamp Test = When its low and 𝐵𝐼/𝑅𝐵𝑂 is high, all the segments will be
High. So it should be high to verify that all the segments are in working
condition.
𝑅𝐵𝐼 (Ripple Blank Input), 𝐵𝐼 (𝐵𝑙𝑎𝑛𝑘 𝐼𝑛𝑝𝑢𝑡)/𝑅𝐵𝑂(Ripple Blank Output) are
used to suppress the unnecessary zero’s in multi-digits display.
74LS47 BCD-to-7-Segment Decoder
Illustration of Trailing Zero Suppression
Encoder
• An Encoder is a combinational logic circuit that performs a “reverse” decoder function.
• An encoder accepts an active level (HIGH or LOW) on one of its inputs, representing a
digit, such as a decimal or octal digit, and converts it to a coded output, such as BCD,
or binary.
• An encoder has 2n input lines and n output lines.
𝑨𝟎 = 𝑫𝟏 + 𝑫𝟑 + 𝑫𝟓 + 𝑫7
𝑨𝟏 = 𝑫𝟐 + 𝑫𝟑 + 𝑫𝟔 + 𝑫7
𝑨𝟐 = 𝑫𝟒 + 𝑫𝟓 + 𝑫𝟔 + 𝑫7
Truth Table for Octal-to-Binary Encoder
𝑨𝟐 = 𝑫𝟒 + 𝑫𝟓 + 𝑫𝟔 + 𝑫7
𝑨𝟏 = 𝑫𝟐 + 𝑫𝟑 + 𝑫𝟔 + 𝑫7
𝑨𝟎 = 𝑫𝟏 + 𝑫𝟑 + 𝑫𝟓 + 𝑫7
Logic Circuit for Octal-to-Binary Encoder
Decimal to BCD Encoder
Inputs Outputs
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Decimal A3 A2 A1 A0
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
0 0 0 0 0 0 0 0 1 0 1 0 0 0 1
0 0 0 0 0 0 0 1 0 0 2 0 0 1 0
0 0 0 0 0 0 1 0 0 0 3 0 0 1 1
0 0 0 0 0 1 0 0 0 0 4 0 1 0 0
0 0 0 0 1 0 0 0 0 0 5 0 1 0 1 𝑨𝟎 = 𝑫𝟏 + 𝑫𝟑 + 𝑫𝟓 + 𝑫7+ 𝑫9
0 0 0 1 0 0 0 0 0 0 6 0 1 1 0 𝑨𝟏 = 𝑫𝟐 + 𝑫𝟑 + 𝑫𝟔 + 𝑫7
0 0 1 0 0 0 0 0 0 0 7 0 1 1 1 𝑨𝟐 = 𝑫𝟒 + 𝑫𝟓 + 𝑫𝟔 + 𝑫7
0 1 0 0 0 0 0 0 0 0 8 1 0 0 0 𝑨𝟑 = 𝑫𝟖 + 𝑫𝟗
1 0 0 0 0 0 0 0 0 0 9 1 0 0 1
𝑫𝟏
𝑨𝟎 = 𝑫𝟏 + 𝑫𝟑 + 𝑫𝟓 + 𝑫𝟕 + 𝑫𝟗
𝑫𝟐
𝑫𝟑
𝑨𝟏 = 𝑫𝟐 + 𝑫𝟑 + 𝑫𝟔 + 𝑫7
𝑫𝟒
𝑫𝟓
𝑫𝟔 𝑨𝟐 = 𝑫𝟒 + 𝑫𝟓 + 𝑫𝟔 + 𝑫7
𝑫7
𝑫𝟖
𝑨𝟑 = 𝑫𝟖 + 𝑫𝟗
𝑫𝟗
Logic Circuit for Decimal-to-BCD Encoder
Encoder IC
74HC147 Decimal to BCD
Encoder
Multiplexers
• Multiplexer (date selectors) is a device that allows digital information from several
sources to be routed onto a single line for transmission over that line to a common
destination.
• Normally there are 2n input lines and n selection inputs (input variables) whose bit
combination determine which input is selected.
• A ‘4-line to 1-line multiplexer’ will have 4 input
lines, 1 output and 2 data select lines as
(𝑆1𝑎𝑛𝑑 𝑆0). The 2 bit code on 𝑆1𝑎𝑛𝑑 𝑆0 will allow
on the selected data input to pass through to the
data output.
𝑫𝒂𝒕𝒂 𝑺𝒆𝒍𝒆𝒄𝒕 𝑰𝒏𝒑𝒖𝒕𝒔
𝑰𝒏𝒑𝒖𝒕 𝑺𝒆𝒍𝒆𝒄𝒕𝒆𝒅 𝑶𝒖𝒕𝒑𝒖𝒕 (𝒀)
𝑺𝟏 𝑺𝟎
0 0 D0 𝐷0𝑆1 . 𝑆0
0 1 D1 𝐷1𝑆1 𝑆0
1 0 D2 𝐷2𝑆1𝑆0
1 1 D3 𝐷3𝑆1𝑆0
Upon ORing these terms, the total expression for
that data output would be:
Y = 𝐷0𝑆1 . 𝑆0 + 𝐷1𝑆1 𝑆0 + 𝐷2𝑆1𝑆0 + 𝐷3𝑆1𝑆0
The logic circuit will be comprised of four 3-input
AND gates, one 4-input OR gate, and two
inverters for data select lines.
𝑫𝒂𝒕𝒂 𝑺𝒆𝒍𝒆𝒄𝒕 𝑰𝒏𝒑𝒖𝒕𝒔 𝑰𝒏𝒑𝒖𝒕
𝑶𝒖𝒕𝒑𝒖𝒕 (𝒀)
𝑺𝟏 𝑺𝟎 𝑺𝒆𝒍𝒆𝒄𝒕𝒆𝒅
0 0 D0 𝐷0𝑆1 . 𝑆0
0 1 D1 𝐷0𝑆1 𝑆0
1 0 D2 𝐷0𝑆1𝑆0
1 1 D3 𝐷0𝑆1𝑆0
Multiplexer IC
74LS151 8 input Data
Selector/Multiplexer
DeMultiplexers
A DeMultiplexers (DEMUX) reverses the multiplexing function. It takes information
from one line and distribute it to a given number of output lines.
𝑫𝒂𝒕𝒂 𝑺𝒆𝒍𝒆𝒄𝒕 𝑰𝒏𝒑𝒖𝒕𝒔
𝑰𝒏𝒑𝒖𝒕 𝑪𝒐𝒎𝒑𝒃𝒊𝒏𝒂𝒕𝒊𝒐𝒏 𝑶𝒖𝒕𝒑𝒖𝒕
𝑺𝟏 𝑺𝟎
0 0 𝐷𝑖 𝑆1 . 𝑆0 D0
0 1 𝐷𝑖 𝑆1 𝑆0 D1
1 0 𝐷𝑖 𝑆1 𝑆0 D2
1 1 𝐷𝑖 𝑆1 𝑆0 D3
𝑫𝒂𝒕𝒂 𝑺𝒆𝒍𝒆𝒄𝒕 𝑰𝒏𝒑𝒖𝒕𝒔
𝑰𝒏𝒑𝒖𝒕 𝑪𝒐𝒎𝒑𝒃𝒊𝒏𝒂𝒕𝒊𝒐𝒏 𝑶𝒖𝒕𝒑𝒖𝒕
𝑺𝟏 𝑺𝟎
0 0 𝐷𝑖 𝑆1 . 𝑆0 D0
0 1 𝐷𝑖 𝑆1 𝑆0 D1
1 0 𝐷𝑖 𝑆1 𝑆0 D2
1 1 𝐷𝑖 𝑆1 𝑆0 D3
DeMultiplexer IC
74H154 4-to-16 input
Data DeMultiplexers
